1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _X86_APICVAR_H_ 31 #define _X86_APICVAR_H_ 32 33 /* 34 * Local && I/O APIC variable definitions. 35 */ 36 37 /* 38 * Layout of local APIC interrupt vectors: 39 * 40 * 0xff (255) +-------------+ 41 * | | 15 (Spurious / IPIs / Local Interrupts) 42 * 0xf0 (240) +-------------+ 43 * | | 14 (I/O Interrupts / Timer) 44 * 0xe0 (224) +-------------+ 45 * | | 13 (I/O Interrupts) 46 * 0xd0 (208) +-------------+ 47 * | | 12 (I/O Interrupts) 48 * 0xc0 (192) +-------------+ 49 * | | 11 (I/O Interrupts) 50 * 0xb0 (176) +-------------+ 51 * | | 10 (I/O Interrupts) 52 * 0xa0 (160) +-------------+ 53 * | | 9 (I/O Interrupts) 54 * 0x90 (144) +-------------+ 55 * | | 8 (I/O Interrupts / System Calls) 56 * 0x80 (128) +-------------+ 57 * | | 7 (I/O Interrupts) 58 * 0x70 (112) +-------------+ 59 * | | 6 (I/O Interrupts) 60 * 0x60 (96) +-------------+ 61 * | | 5 (I/O Interrupts) 62 * 0x50 (80) +-------------+ 63 * | | 4 (I/O Interrupts) 64 * 0x40 (64) +-------------+ 65 * | | 3 (I/O Interrupts) 66 * 0x30 (48) +-------------+ 67 * | | 2 (ATPIC Interrupts) 68 * 0x20 (32) +-------------+ 69 * | | 1 (Exceptions, traps, faults, etc.) 70 * 0x10 (16) +-------------+ 71 * | | 0 (Exceptions, traps, faults, etc.) 72 * 0x00 (0) +-------------+ 73 * 74 * Note: 0x80 needs to be handled specially and not allocated to an 75 * I/O device! 76 */ 77 78 #define xAPIC_MAX_APIC_ID 0xfe 79 #define xAPIC_ID_ALL 0xff 80 #define MAX_APIC_ID 0x800 81 #define APIC_ID_ALL 0xffffffff 82 83 #define IOAPIC_MAX_ID xAPIC_MAX_APIC_ID 84 85 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 86 #define APIC_IO_INTS (IDT_IO_INTS + 16) 87 #define APIC_NUM_IOINTS 191 88 89 /* The timer interrupt is used for clock handling and drives hardclock, etc. */ 90 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 91 92 /* 93 ********************* !!! WARNING !!! ****************************** 94 * Each local apic has an interrupt receive fifo that is two entries deep 95 * for each interrupt priority class (higher 4 bits of interrupt vector). 96 * Once the fifo is full the APIC can no longer receive interrupts for this 97 * class and sending IPIs from other CPUs will be blocked. 98 * To avoid deadlocks there should be no more than two IPI interrupts 99 * pending at the same time. 100 * Currently this is guaranteed by dividing the IPIs in two groups that have 101 * each at most one IPI interrupt pending. The first group is protected by the 102 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 103 * at a time) The second group uses a single interrupt and a bitmap to avoid 104 * redundant IPI interrupts. 105 */ 106 107 /* Interrupts for local APIC LVT entries other than the timer. */ 108 #define APIC_LOCAL_INTS 240 109 #define APIC_ERROR_INT APIC_LOCAL_INTS 110 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 111 #define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 112 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 113 114 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 115 #define IPI_INVLOP (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, amd64 */ 116 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs, i386 */ 117 #define IPI_INVLPG (APIC_IPI_INTS + 2) 118 #define IPI_INVLRNG (APIC_IPI_INTS + 3) 119 #define IPI_INVLCACHE (APIC_IPI_INTS + 4) 120 /* Vector to handle bitmap based IPIs */ 121 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5) 122 123 /* IPIs handled by IPI_BITMAP_VECTOR */ 124 #define IPI_AST 0 /* Generate software trap. */ 125 #define IPI_PREEMPT 1 126 #define IPI_HARDCLOCK 2 127 #define IPI_TRACE 3 /* Collect stack trace. */ 128 #define IPI_BITMAP_LAST IPI_TRACE 129 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 130 131 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */ 132 #define IPI_SUSPEND (APIC_IPI_INTS + 7) /* Suspend CPU until restarted. */ 133 #define IPI_SWI (APIC_IPI_INTS + 8) /* Run clk_intr_event. */ 134 #define IPI_DYN_FIRST (APIC_IPI_INTS + 9) 135 #define IPI_DYN_LAST (254) /* IPIs allocated at runtime */ 136 137 /* 138 * IPI_STOP_HARD does not need to occupy a slot in the IPI vector space since 139 * it is delivered using an NMI anyways. 140 */ 141 #define IPI_NMI_FIRST 255 142 #define IPI_STOP_HARD 255 /* Stop CPU with a NMI. */ 143 144 /* 145 * The spurious interrupt can share the priority class with the IPIs since 146 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 147 */ 148 #define APIC_SPURIOUS_INT 255 149 150 #ifndef LOCORE 151 152 #define APIC_IPI_DEST_SELF -1 153 #define APIC_IPI_DEST_ALL -2 154 #define APIC_IPI_DEST_OTHERS -3 155 156 #define APIC_BUS_UNKNOWN -1 157 #define APIC_BUS_ISA 0 158 #define APIC_BUS_EISA 1 159 #define APIC_BUS_PCI 2 160 #define APIC_BUS_MAX APIC_BUS_PCI 161 162 #define IRQ_EXTINT -1 163 #define IRQ_NMI -2 164 #define IRQ_SMI -3 165 #define IRQ_DISABLED -4 166 167 /* 168 * An APIC enumerator is a pseudo bus driver that enumerates APIC's including 169 * CPU's and I/O APIC's. 170 */ 171 struct apic_enumerator { 172 const char *apic_name; 173 int (*apic_probe)(void); 174 int (*apic_probe_cpus)(void); 175 int (*apic_setup_local)(void); 176 int (*apic_setup_io)(void); 177 SLIST_ENTRY(apic_enumerator) apic_next; 178 }; 179 180 inthand_t 181 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 182 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 183 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 184 IDTVEC(spuriousint), IDTVEC(timerint), 185 IDTVEC(apic_isr1_pti), IDTVEC(apic_isr2_pti), IDTVEC(apic_isr3_pti), 186 IDTVEC(apic_isr4_pti), IDTVEC(apic_isr5_pti), IDTVEC(apic_isr6_pti), 187 IDTVEC(apic_isr7_pti), IDTVEC(cmcint_pti), IDTVEC(errorint_pti), 188 IDTVEC(spuriousint_pti), IDTVEC(timerint_pti); 189 190 extern vm_paddr_t lapic_paddr; 191 extern int *apic_cpuids; 192 193 /* Allow to replace the lapic_ipi_vectored implementation. */ 194 extern void (*ipi_vectored)(u_int, int); 195 196 void apic_register_enumerator(struct apic_enumerator *enumerator); 197 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 198 int ioapic_disable_pin(void *cookie, u_int pin); 199 int ioapic_get_vector(void *cookie, u_int pin); 200 void ioapic_register(void *cookie); 201 int ioapic_remap_vector(void *cookie, u_int pin, int vector); 202 int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 203 int ioapic_set_extint(void *cookie, u_int pin); 204 int ioapic_set_nmi(void *cookie, u_int pin); 205 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 206 int ioapic_set_triggermode(void *cookie, u_int pin, 207 enum intr_trigger trigger); 208 int ioapic_set_smi(void *cookie, u_int pin); 209 210 void lapic_create(u_int apic_id, int boot_cpu); 211 void lapic_init(vm_paddr_t addr); 212 void lapic_xapic_mode(void); 213 bool lapic_is_x2apic(void); 214 void lapic_setup(int boot); 215 void lapic_dump(const char *str); 216 void lapic_disable(void); 217 void lapic_eoi(void); 218 int lapic_id(void); 219 int lapic_intr_pending(u_int vector); 220 /* XXX: UNUSED */ 221 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id); 222 u_int apic_cpuid(u_int apic_id); 223 u_int apic_alloc_vector(u_int apic_id, u_int irq); 224 u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align); 225 void apic_enable_vector(u_int apic_id, u_int vector); 226 void apic_disable_vector(u_int apic_id, u_int vector); 227 void apic_free_vector(u_int apic_id, u_int vector, u_int irq); 228 void lapic_calibrate_timer(void); 229 int lapic_enable_pmc(void); 230 void lapic_disable_pmc(void); 231 void lapic_reenable_pmc(void); 232 void lapic_enable_cmc(void); 233 int lapic_enable_mca_elvt(void); 234 void lapic_ipi_raw(register_t icrlo, u_int dest); 235 236 static inline void 237 lapic_ipi_vectored(u_int vector, int dest) 238 { 239 240 ipi_vectored(vector, dest); 241 } 242 243 int lapic_ipi_wait(int delay); 244 int lapic_ipi_alloc(inthand_t *ipifunc); 245 void lapic_ipi_free(int vector); 246 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked); 247 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode); 248 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt, 249 enum intr_polarity pol); 250 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, 251 enum intr_trigger trigger); 252 void lapic_handle_cmc(void); 253 void lapic_handle_error(void); 254 void lapic_handle_intr(int vector, struct trapframe *frame); 255 void lapic_handle_timer(struct trapframe *frame); 256 257 int ioapic_get_rid(u_int apic_id, uint16_t *ridp); 258 259 extern int x2apic_mode; 260 extern int lapic_eoi_suppression; 261 262 #ifdef _SYS_SYSCTL_H_ 263 SYSCTL_DECL(_hw_apic); 264 #endif 265 266 #endif /* !LOCORE */ 267 #endif /* _X86_APICVAR_H_ */ 268