1 /*- 2 * Copyright (c) 1992 Terrence R. Lambert. 3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 4 * Copyright (c) 1997 KATO Takenori. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_cpu.h" 45 46 #include <sys/param.h> 47 #include <sys/bus.h> 48 #include <sys/cpu.h> 49 #include <sys/eventhandler.h> 50 #include <sys/limits.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/sysctl.h> 54 #include <sys/power.h> 55 56 #include <vm/vm.h> 57 #include <vm/pmap.h> 58 59 #include <machine/asmacros.h> 60 #include <machine/clock.h> 61 #include <machine/cputypes.h> 62 #include <machine/frame.h> 63 #include <machine/intr_machdep.h> 64 #include <machine/md_var.h> 65 #include <machine/segments.h> 66 #include <machine/specialreg.h> 67 68 #include <amd64/vmm/intel/vmx_controls.h> 69 #include <x86/isa/icu.h> 70 #include <x86/vmware.h> 71 72 #ifdef __i386__ 73 #define IDENTBLUE_CYRIX486 0 74 #define IDENTBLUE_IBMCPU 1 75 #define IDENTBLUE_CYRIXM2 2 76 77 static void identifycyrix(void); 78 static void print_transmeta_info(void); 79 #endif 80 static u_int find_cpu_vendor_id(void); 81 static void print_AMD_info(void); 82 static void print_INTEL_info(void); 83 static void print_INTEL_TLB(u_int data); 84 static void print_hypervisor_info(void); 85 static void print_svm_info(void); 86 static void print_via_padlock_info(void); 87 static void print_vmx_info(void); 88 89 #ifdef __i386__ 90 int cpu; /* Are we 386, 386sx, 486, etc? */ 91 int cpu_class; 92 #endif 93 u_int cpu_feature; /* Feature flags */ 94 u_int cpu_feature2; /* Feature flags */ 95 u_int amd_feature; /* AMD feature flags */ 96 u_int amd_feature2; /* AMD feature flags */ 97 u_int amd_rascap; /* AMD RAS capabilities */ 98 u_int amd_pminfo; /* AMD advanced power management info */ 99 u_int amd_extended_feature_extensions; 100 u_int via_feature_rng; /* VIA RNG features */ 101 u_int via_feature_xcrypt; /* VIA ACE features */ 102 u_int cpu_high; /* Highest arg to CPUID */ 103 u_int cpu_exthigh; /* Highest arg to extended CPUID */ 104 u_int cpu_id; /* Stepping ID */ 105 u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 106 u_int cpu_procinfo2; /* Multicore info */ 107 char cpu_vendor[20]; /* CPU Origin code */ 108 u_int cpu_vendor_id; /* CPU vendor ID */ 109 u_int cpu_fxsr; /* SSE enabled */ 110 u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 111 u_int cpu_clflush_line_size = 32; 112 u_int cpu_stdext_feature; /* %ebx */ 113 u_int cpu_stdext_feature2; /* %ecx */ 114 u_int cpu_stdext_feature3; /* %edx */ 115 uint64_t cpu_ia32_arch_caps; 116 u_int cpu_max_ext_state_size; 117 u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 118 u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 119 u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 120 u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 121 u_int cpu_power_eax; /* 06H: Power management leaf, %eax */ 122 u_int cpu_power_ebx; /* 06H: Power management leaf, %ebx */ 123 u_int cpu_power_ecx; /* 06H: Power management leaf, %ecx */ 124 u_int cpu_power_edx; /* 06H: Power management leaf, %edx */ 125 char machine[] = MACHINE; 126 127 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 128 &via_feature_rng, 0, 129 "VIA RNG feature available in CPU"); 130 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 131 &via_feature_xcrypt, 0, 132 "VIA xcrypt feature available in CPU"); 133 134 #ifdef __amd64__ 135 #ifdef SCTL_MASK32 136 extern int adaptive_machine_arch; 137 #endif 138 139 static int 140 sysctl_hw_machine(SYSCTL_HANDLER_ARGS) 141 { 142 #ifdef SCTL_MASK32 143 static const char machine32[] = "i386"; 144 #endif 145 int error; 146 147 #ifdef SCTL_MASK32 148 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) 149 error = SYSCTL_OUT(req, machine32, sizeof(machine32)); 150 else 151 #endif 152 error = SYSCTL_OUT(req, machine, sizeof(machine)); 153 return (error); 154 155 } 156 SYSCTL_PROC(_hw, HW_MACHINE, machine, CTLTYPE_STRING | CTLFLAG_RD | 157 CTLFLAG_MPSAFE, NULL, 0, sysctl_hw_machine, "A", "Machine class"); 158 #else 159 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 160 machine, 0, "Machine class"); 161 #endif 162 163 static char cpu_model[128]; 164 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD | CTLFLAG_MPSAFE, 165 cpu_model, 0, "Machine model"); 166 167 static int hw_clockrate; 168 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 169 &hw_clockrate, 0, "CPU instruction clock rate"); 170 171 u_int hv_base; 172 u_int hv_high; 173 char hv_vendor[16]; 174 SYSCTL_STRING(_hw, OID_AUTO, hv_vendor, CTLFLAG_RD | CTLFLAG_MPSAFE, hv_vendor, 175 0, "Hypervisor vendor"); 176 177 static eventhandler_tag tsc_post_tag; 178 179 static char cpu_brand[48]; 180 181 #ifdef __i386__ 182 #define MAX_BRAND_INDEX 8 183 184 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = { 185 NULL, /* No brand */ 186 "Intel Celeron", 187 "Intel Pentium III", 188 "Intel Pentium III Xeon", 189 NULL, 190 NULL, 191 NULL, 192 NULL, 193 "Intel Pentium 4" 194 }; 195 196 static struct { 197 char *cpu_name; 198 int cpu_class; 199 } cpus[] = { 200 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */ 201 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */ 202 { "i386DX", CPUCLASS_386 }, /* CPU_386 */ 203 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */ 204 { "i486DX", CPUCLASS_486 }, /* CPU_486 */ 205 { "Pentium", CPUCLASS_586 }, /* CPU_586 */ 206 { "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */ 207 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */ 208 { "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */ 209 { "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */ 210 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */ 211 { "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */ 212 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */ 213 { "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */ 214 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */ 215 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */ 216 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */ 217 }; 218 #endif 219 220 static struct { 221 char *vendor; 222 u_int vendor_id; 223 } cpu_vendors[] = { 224 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */ 225 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */ 226 { HYGON_VENDOR_ID, CPU_VENDOR_HYGON }, /* HygonGenuine */ 227 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */ 228 #ifdef __i386__ 229 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */ 230 { CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */ 231 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */ 232 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */ 233 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */ 234 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */ 235 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */ 236 #if 0 237 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */ 238 { "TransmetaCPU", CPU_VENDOR_TRANSMETA }, 239 #endif 240 #endif 241 }; 242 243 void 244 printcpuinfo(void) 245 { 246 u_int regs[4], i; 247 char *brand; 248 249 printf("CPU: "); 250 #ifdef __i386__ 251 cpu_class = cpus[cpu].cpu_class; 252 strncpy(cpu_model, cpus[cpu].cpu_name, sizeof (cpu_model)); 253 #else 254 strncpy(cpu_model, "Hammer", sizeof (cpu_model)); 255 #endif 256 257 /* Check for extended CPUID information and a processor name. */ 258 if (cpu_exthigh >= 0x80000004) { 259 brand = cpu_brand; 260 for (i = 0x80000002; i < 0x80000005; i++) { 261 do_cpuid(i, regs); 262 memcpy(brand, regs, sizeof(regs)); 263 brand += sizeof(regs); 264 } 265 } 266 267 switch (cpu_vendor_id) { 268 case CPU_VENDOR_INTEL: 269 #ifdef __i386__ 270 if ((cpu_id & 0xf00) > 0x300) { 271 u_int brand_index; 272 273 cpu_model[0] = '\0'; 274 275 switch (cpu_id & 0x3000) { 276 case 0x1000: 277 strcpy(cpu_model, "Overdrive "); 278 break; 279 case 0x2000: 280 strcpy(cpu_model, "Dual "); 281 break; 282 } 283 284 switch (cpu_id & 0xf00) { 285 case 0x400: 286 strcat(cpu_model, "i486 "); 287 /* Check the particular flavor of 486 */ 288 switch (cpu_id & 0xf0) { 289 case 0x00: 290 case 0x10: 291 strcat(cpu_model, "DX"); 292 break; 293 case 0x20: 294 strcat(cpu_model, "SX"); 295 break; 296 case 0x30: 297 strcat(cpu_model, "DX2"); 298 break; 299 case 0x40: 300 strcat(cpu_model, "SL"); 301 break; 302 case 0x50: 303 strcat(cpu_model, "SX2"); 304 break; 305 case 0x70: 306 strcat(cpu_model, 307 "DX2 Write-Back Enhanced"); 308 break; 309 case 0x80: 310 strcat(cpu_model, "DX4"); 311 break; 312 } 313 break; 314 case 0x500: 315 /* Check the particular flavor of 586 */ 316 strcat(cpu_model, "Pentium"); 317 switch (cpu_id & 0xf0) { 318 case 0x00: 319 strcat(cpu_model, " A-step"); 320 break; 321 case 0x10: 322 strcat(cpu_model, "/P5"); 323 break; 324 case 0x20: 325 strcat(cpu_model, "/P54C"); 326 break; 327 case 0x30: 328 strcat(cpu_model, "/P24T"); 329 break; 330 case 0x40: 331 strcat(cpu_model, "/P55C"); 332 break; 333 case 0x70: 334 strcat(cpu_model, "/P54C"); 335 break; 336 case 0x80: 337 strcat(cpu_model, "/P55C (quarter-micron)"); 338 break; 339 default: 340 /* nothing */ 341 break; 342 } 343 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 344 /* 345 * XXX - If/when Intel fixes the bug, this 346 * should also check the version of the 347 * CPU, not just that it's a Pentium. 348 */ 349 has_f00f_bug = 1; 350 #endif 351 break; 352 case 0x600: 353 /* Check the particular flavor of 686 */ 354 switch (cpu_id & 0xf0) { 355 case 0x00: 356 strcat(cpu_model, "Pentium Pro A-step"); 357 break; 358 case 0x10: 359 strcat(cpu_model, "Pentium Pro"); 360 break; 361 case 0x30: 362 case 0x50: 363 case 0x60: 364 strcat(cpu_model, 365 "Pentium II/Pentium II Xeon/Celeron"); 366 cpu = CPU_PII; 367 break; 368 case 0x70: 369 case 0x80: 370 case 0xa0: 371 case 0xb0: 372 strcat(cpu_model, 373 "Pentium III/Pentium III Xeon/Celeron"); 374 cpu = CPU_PIII; 375 break; 376 default: 377 strcat(cpu_model, "Unknown 80686"); 378 break; 379 } 380 break; 381 case 0xf00: 382 strcat(cpu_model, "Pentium 4"); 383 cpu = CPU_P4; 384 break; 385 default: 386 strcat(cpu_model, "unknown"); 387 break; 388 } 389 390 /* 391 * If we didn't get a brand name from the extended 392 * CPUID, try to look it up in the brand table. 393 */ 394 if (cpu_high > 0 && *cpu_brand == '\0') { 395 brand_index = cpu_procinfo & CPUID_BRAND_INDEX; 396 if (brand_index <= MAX_BRAND_INDEX && 397 cpu_brandtable[brand_index] != NULL) 398 strcpy(cpu_brand, 399 cpu_brandtable[brand_index]); 400 } 401 } 402 #else 403 /* Please make up your mind folks! */ 404 strcat(cpu_model, "EM64T"); 405 #endif 406 break; 407 case CPU_VENDOR_AMD: 408 /* 409 * Values taken from AMD Processor Recognition 410 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf 411 * (also describes ``Features'' encodings. 412 */ 413 strcpy(cpu_model, "AMD "); 414 #ifdef __i386__ 415 switch (cpu_id & 0xFF0) { 416 case 0x410: 417 strcat(cpu_model, "Standard Am486DX"); 418 break; 419 case 0x430: 420 strcat(cpu_model, "Enhanced Am486DX2 Write-Through"); 421 break; 422 case 0x470: 423 strcat(cpu_model, "Enhanced Am486DX2 Write-Back"); 424 break; 425 case 0x480: 426 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through"); 427 break; 428 case 0x490: 429 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back"); 430 break; 431 case 0x4E0: 432 strcat(cpu_model, "Am5x86 Write-Through"); 433 break; 434 case 0x4F0: 435 strcat(cpu_model, "Am5x86 Write-Back"); 436 break; 437 case 0x500: 438 strcat(cpu_model, "K5 model 0"); 439 break; 440 case 0x510: 441 strcat(cpu_model, "K5 model 1"); 442 break; 443 case 0x520: 444 strcat(cpu_model, "K5 PR166 (model 2)"); 445 break; 446 case 0x530: 447 strcat(cpu_model, "K5 PR200 (model 3)"); 448 break; 449 case 0x560: 450 strcat(cpu_model, "K6"); 451 break; 452 case 0x570: 453 strcat(cpu_model, "K6 266 (model 1)"); 454 break; 455 case 0x580: 456 strcat(cpu_model, "K6-2"); 457 break; 458 case 0x590: 459 strcat(cpu_model, "K6-III"); 460 break; 461 case 0x5a0: 462 strcat(cpu_model, "Geode LX"); 463 break; 464 default: 465 strcat(cpu_model, "Unknown"); 466 break; 467 } 468 #else 469 if ((cpu_id & 0xf00) == 0xf00) 470 strcat(cpu_model, "AMD64 Processor"); 471 else 472 strcat(cpu_model, "Unknown"); 473 #endif 474 break; 475 #ifdef __i386__ 476 case CPU_VENDOR_CYRIX: 477 strcpy(cpu_model, "Cyrix "); 478 switch (cpu_id & 0xff0) { 479 case 0x440: 480 strcat(cpu_model, "MediaGX"); 481 break; 482 case 0x520: 483 strcat(cpu_model, "6x86"); 484 break; 485 case 0x540: 486 cpu_class = CPUCLASS_586; 487 strcat(cpu_model, "GXm"); 488 break; 489 case 0x600: 490 strcat(cpu_model, "6x86MX"); 491 break; 492 default: 493 /* 494 * Even though CPU supports the cpuid 495 * instruction, it can be disabled. 496 * Therefore, this routine supports all Cyrix 497 * CPUs. 498 */ 499 switch (cyrix_did & 0xf0) { 500 case 0x00: 501 switch (cyrix_did & 0x0f) { 502 case 0x00: 503 strcat(cpu_model, "486SLC"); 504 break; 505 case 0x01: 506 strcat(cpu_model, "486DLC"); 507 break; 508 case 0x02: 509 strcat(cpu_model, "486SLC2"); 510 break; 511 case 0x03: 512 strcat(cpu_model, "486DLC2"); 513 break; 514 case 0x04: 515 strcat(cpu_model, "486SRx"); 516 break; 517 case 0x05: 518 strcat(cpu_model, "486DRx"); 519 break; 520 case 0x06: 521 strcat(cpu_model, "486SRx2"); 522 break; 523 case 0x07: 524 strcat(cpu_model, "486DRx2"); 525 break; 526 case 0x08: 527 strcat(cpu_model, "486SRu"); 528 break; 529 case 0x09: 530 strcat(cpu_model, "486DRu"); 531 break; 532 case 0x0a: 533 strcat(cpu_model, "486SRu2"); 534 break; 535 case 0x0b: 536 strcat(cpu_model, "486DRu2"); 537 break; 538 default: 539 strcat(cpu_model, "Unknown"); 540 break; 541 } 542 break; 543 case 0x10: 544 switch (cyrix_did & 0x0f) { 545 case 0x00: 546 strcat(cpu_model, "486S"); 547 break; 548 case 0x01: 549 strcat(cpu_model, "486S2"); 550 break; 551 case 0x02: 552 strcat(cpu_model, "486Se"); 553 break; 554 case 0x03: 555 strcat(cpu_model, "486S2e"); 556 break; 557 case 0x0a: 558 strcat(cpu_model, "486DX"); 559 break; 560 case 0x0b: 561 strcat(cpu_model, "486DX2"); 562 break; 563 case 0x0f: 564 strcat(cpu_model, "486DX4"); 565 break; 566 default: 567 strcat(cpu_model, "Unknown"); 568 break; 569 } 570 break; 571 case 0x20: 572 if ((cyrix_did & 0x0f) < 8) 573 strcat(cpu_model, "6x86"); /* Where did you get it? */ 574 else 575 strcat(cpu_model, "5x86"); 576 break; 577 case 0x30: 578 strcat(cpu_model, "6x86"); 579 break; 580 case 0x40: 581 if ((cyrix_did & 0xf000) == 0x3000) { 582 cpu_class = CPUCLASS_586; 583 strcat(cpu_model, "GXm"); 584 } else 585 strcat(cpu_model, "MediaGX"); 586 break; 587 case 0x50: 588 strcat(cpu_model, "6x86MX"); 589 break; 590 case 0xf0: 591 switch (cyrix_did & 0x0f) { 592 case 0x0d: 593 strcat(cpu_model, "Overdrive CPU"); 594 break; 595 case 0x0e: 596 strcpy(cpu_model, "Texas Instruments 486SXL"); 597 break; 598 case 0x0f: 599 strcat(cpu_model, "486SLC/DLC"); 600 break; 601 default: 602 strcat(cpu_model, "Unknown"); 603 break; 604 } 605 break; 606 default: 607 strcat(cpu_model, "Unknown"); 608 break; 609 } 610 break; 611 } 612 break; 613 case CPU_VENDOR_RISE: 614 strcpy(cpu_model, "Rise "); 615 switch (cpu_id & 0xff0) { 616 case 0x500: /* 6401 and 6441 (Kirin) */ 617 case 0x520: /* 6510 (Lynx) */ 618 strcat(cpu_model, "mP6"); 619 break; 620 default: 621 strcat(cpu_model, "Unknown"); 622 } 623 break; 624 #endif 625 case CPU_VENDOR_CENTAUR: 626 #ifdef __i386__ 627 switch (cpu_id & 0xff0) { 628 case 0x540: 629 strcpy(cpu_model, "IDT WinChip C6"); 630 break; 631 case 0x580: 632 strcpy(cpu_model, "IDT WinChip 2"); 633 break; 634 case 0x590: 635 strcpy(cpu_model, "IDT WinChip 3"); 636 break; 637 case 0x660: 638 strcpy(cpu_model, "VIA C3 Samuel"); 639 break; 640 case 0x670: 641 if (cpu_id & 0x8) 642 strcpy(cpu_model, "VIA C3 Ezra"); 643 else 644 strcpy(cpu_model, "VIA C3 Samuel 2"); 645 break; 646 case 0x680: 647 strcpy(cpu_model, "VIA C3 Ezra-T"); 648 break; 649 case 0x690: 650 strcpy(cpu_model, "VIA C3 Nehemiah"); 651 break; 652 case 0x6a0: 653 case 0x6d0: 654 strcpy(cpu_model, "VIA C7 Esther"); 655 break; 656 case 0x6f0: 657 strcpy(cpu_model, "VIA Nano"); 658 break; 659 default: 660 strcpy(cpu_model, "VIA/IDT Unknown"); 661 } 662 #else 663 strcpy(cpu_model, "VIA "); 664 if ((cpu_id & 0xff0) == 0x6f0) 665 strcat(cpu_model, "Nano Processor"); 666 else 667 strcat(cpu_model, "Unknown"); 668 #endif 669 break; 670 #ifdef __i386__ 671 case CPU_VENDOR_IBM: 672 strcpy(cpu_model, "Blue Lightning CPU"); 673 break; 674 case CPU_VENDOR_NSC: 675 switch (cpu_id & 0xff0) { 676 case 0x540: 677 strcpy(cpu_model, "Geode SC1100"); 678 cpu = CPU_GEODE1100; 679 break; 680 default: 681 strcpy(cpu_model, "Geode/NSC unknown"); 682 break; 683 } 684 break; 685 #endif 686 case CPU_VENDOR_HYGON: 687 strcpy(cpu_model, "Hygon "); 688 #ifdef __i386__ 689 strcat(cpu_model, "Unknown"); 690 #else 691 if ((cpu_id & 0xf00) == 0xf00) 692 strcat(cpu_model, "AMD64 Processor"); 693 else 694 strcat(cpu_model, "Unknown"); 695 #endif 696 break; 697 698 default: 699 strcat(cpu_model, "Unknown"); 700 break; 701 } 702 703 /* 704 * Replace cpu_model with cpu_brand minus leading spaces if 705 * we have one. 706 */ 707 brand = cpu_brand; 708 while (*brand == ' ') 709 ++brand; 710 if (*brand != '\0') 711 strcpy(cpu_model, brand); 712 713 printf("%s (", cpu_model); 714 if (tsc_freq != 0) { 715 hw_clockrate = (tsc_freq + 5000) / 1000000; 716 printf("%jd.%02d-MHz ", 717 (intmax_t)(tsc_freq + 4999) / 1000000, 718 (u_int)((tsc_freq + 4999) / 10000) % 100); 719 } 720 #ifdef __i386__ 721 switch(cpu_class) { 722 case CPUCLASS_286: 723 printf("286"); 724 break; 725 case CPUCLASS_386: 726 printf("386"); 727 break; 728 #if defined(I486_CPU) 729 case CPUCLASS_486: 730 printf("486"); 731 break; 732 #endif 733 #if defined(I586_CPU) 734 case CPUCLASS_586: 735 printf("586"); 736 break; 737 #endif 738 #if defined(I686_CPU) 739 case CPUCLASS_686: 740 printf("686"); 741 break; 742 #endif 743 default: 744 printf("Unknown"); /* will panic below... */ 745 } 746 #else 747 printf("K8"); 748 #endif 749 printf("-class CPU)\n"); 750 if (*cpu_vendor) 751 printf(" Origin=\"%s\"", cpu_vendor); 752 if (cpu_id) 753 printf(" Id=0x%x", cpu_id); 754 755 if (cpu_vendor_id == CPU_VENDOR_INTEL || 756 cpu_vendor_id == CPU_VENDOR_AMD || 757 cpu_vendor_id == CPU_VENDOR_HYGON || 758 cpu_vendor_id == CPU_VENDOR_CENTAUR || 759 #ifdef __i386__ 760 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 761 cpu_vendor_id == CPU_VENDOR_RISE || 762 cpu_vendor_id == CPU_VENDOR_NSC || 763 (cpu_vendor_id == CPU_VENDOR_CYRIX && ((cpu_id & 0xf00) > 0x500)) || 764 #endif 765 0) { 766 printf(" Family=0x%x", CPUID_TO_FAMILY(cpu_id)); 767 printf(" Model=0x%x", CPUID_TO_MODEL(cpu_id)); 768 printf(" Stepping=%u", cpu_id & CPUID_STEPPING); 769 #ifdef __i386__ 770 if (cpu_vendor_id == CPU_VENDOR_CYRIX) 771 printf("\n DIR=0x%04x", cyrix_did); 772 #endif 773 774 /* 775 * AMD CPUID Specification 776 * http://support.amd.com/us/Embedded_TechDocs/25481.pdf 777 * 778 * Intel Processor Identification and CPUID Instruction 779 * http://www.intel.com/assets/pdf/appnote/241618.pdf 780 */ 781 if (cpu_high > 0) { 782 /* 783 * Here we should probably set up flags indicating 784 * whether or not various features are available. 785 * The interesting ones are probably VME, PSE, PAE, 786 * and PGE. The code already assumes without bothering 787 * to check that all CPUs >= Pentium have a TSC and 788 * MSRs. 789 */ 790 printf("\n Features=0x%b", cpu_feature, 791 "\020" 792 "\001FPU" /* Integral FPU */ 793 "\002VME" /* Extended VM86 mode support */ 794 "\003DE" /* Debugging Extensions (CR4.DE) */ 795 "\004PSE" /* 4MByte page tables */ 796 "\005TSC" /* Timestamp counter */ 797 "\006MSR" /* Machine specific registers */ 798 "\007PAE" /* Physical address extension */ 799 "\010MCE" /* Machine Check support */ 800 "\011CX8" /* CMPEXCH8 instruction */ 801 "\012APIC" /* SMP local APIC */ 802 "\013oldMTRR" /* Previous implementation of MTRR */ 803 "\014SEP" /* Fast System Call */ 804 "\015MTRR" /* Memory Type Range Registers */ 805 "\016PGE" /* PG_G (global bit) support */ 806 "\017MCA" /* Machine Check Architecture */ 807 "\020CMOV" /* CMOV instruction */ 808 "\021PAT" /* Page attributes table */ 809 "\022PSE36" /* 36 bit address space support */ 810 "\023PN" /* Processor Serial number */ 811 "\024CLFLUSH" /* Has the CLFLUSH instruction */ 812 "\025<b20>" 813 "\026DTS" /* Debug Trace Store */ 814 "\027ACPI" /* ACPI support */ 815 "\030MMX" /* MMX instructions */ 816 "\031FXSR" /* FXSAVE/FXRSTOR */ 817 "\032SSE" /* Streaming SIMD Extensions */ 818 "\033SSE2" /* Streaming SIMD Extensions #2 */ 819 "\034SS" /* Self snoop */ 820 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */ 821 "\036TM" /* Thermal Monitor clock slowdown */ 822 "\037IA64" /* CPU can execute IA64 instructions */ 823 "\040PBE" /* Pending Break Enable */ 824 ); 825 826 if (cpu_feature2 != 0) { 827 printf("\n Features2=0x%b", cpu_feature2, 828 "\020" 829 "\001SSE3" /* SSE3 */ 830 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */ 831 "\003DTES64" /* 64-bit Debug Trace */ 832 "\004MON" /* MONITOR/MWAIT Instructions */ 833 "\005DS_CPL" /* CPL Qualified Debug Store */ 834 "\006VMX" /* Virtual Machine Extensions */ 835 "\007SMX" /* Safer Mode Extensions */ 836 "\010EST" /* Enhanced SpeedStep */ 837 "\011TM2" /* Thermal Monitor 2 */ 838 "\012SSSE3" /* SSSE3 */ 839 "\013CNXT-ID" /* L1 context ID available */ 840 "\014SDBG" /* IA32 silicon debug */ 841 "\015FMA" /* Fused Multiply Add */ 842 "\016CX16" /* CMPXCHG16B Instruction */ 843 "\017xTPR" /* Send Task Priority Messages*/ 844 "\020PDCM" /* Perf/Debug Capability MSR */ 845 "\021<b16>" 846 "\022PCID" /* Process-context Identifiers*/ 847 "\023DCA" /* Direct Cache Access */ 848 "\024SSE4.1" /* SSE 4.1 */ 849 "\025SSE4.2" /* SSE 4.2 */ 850 "\026x2APIC" /* xAPIC Extensions */ 851 "\027MOVBE" /* MOVBE Instruction */ 852 "\030POPCNT" /* POPCNT Instruction */ 853 "\031TSCDLT" /* TSC-Deadline Timer */ 854 "\032AESNI" /* AES Crypto */ 855 "\033XSAVE" /* XSAVE/XRSTOR States */ 856 "\034OSXSAVE" /* OS-Enabled State Management*/ 857 "\035AVX" /* Advanced Vector Extensions */ 858 "\036F16C" /* Half-precision conversions */ 859 "\037RDRAND" /* RDRAND Instruction */ 860 "\040HV" /* Hypervisor */ 861 ); 862 } 863 864 if (amd_feature != 0) { 865 printf("\n AMD Features=0x%b", amd_feature, 866 "\020" /* in hex */ 867 "\001<s0>" /* Same */ 868 "\002<s1>" /* Same */ 869 "\003<s2>" /* Same */ 870 "\004<s3>" /* Same */ 871 "\005<s4>" /* Same */ 872 "\006<s5>" /* Same */ 873 "\007<s6>" /* Same */ 874 "\010<s7>" /* Same */ 875 "\011<s8>" /* Same */ 876 "\012<s9>" /* Same */ 877 "\013<b10>" /* Undefined */ 878 "\014SYSCALL" /* Have SYSCALL/SYSRET */ 879 "\015<s12>" /* Same */ 880 "\016<s13>" /* Same */ 881 "\017<s14>" /* Same */ 882 "\020<s15>" /* Same */ 883 "\021<s16>" /* Same */ 884 "\022<s17>" /* Same */ 885 "\023<b18>" /* Reserved, unknown */ 886 "\024MP" /* Multiprocessor Capable */ 887 "\025NX" /* Has EFER.NXE, NX */ 888 "\026<b21>" /* Undefined */ 889 "\027MMX+" /* AMD MMX Extensions */ 890 "\030<s23>" /* Same */ 891 "\031<s24>" /* Same */ 892 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */ 893 "\033Page1GB" /* 1-GB large page support */ 894 "\034RDTSCP" /* RDTSCP */ 895 "\035<b28>" /* Undefined */ 896 "\036LM" /* 64 bit long mode */ 897 "\0373DNow!+" /* AMD 3DNow! Extensions */ 898 "\0403DNow!" /* AMD 3DNow! */ 899 ); 900 } 901 902 if (amd_feature2 != 0) { 903 printf("\n AMD Features2=0x%b", amd_feature2, 904 "\020" 905 "\001LAHF" /* LAHF/SAHF in long mode */ 906 "\002CMP" /* CMP legacy */ 907 "\003SVM" /* Secure Virtual Mode */ 908 "\004ExtAPIC" /* Extended APIC register */ 909 "\005CR8" /* CR8 in legacy mode */ 910 "\006ABM" /* LZCNT instruction */ 911 "\007SSE4A" /* SSE4A */ 912 "\010MAS" /* Misaligned SSE mode */ 913 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ 914 "\012OSVW" /* OS visible workaround */ 915 "\013IBS" /* Instruction based sampling */ 916 "\014XOP" /* XOP extended instructions */ 917 "\015SKINIT" /* SKINIT/STGI */ 918 "\016WDT" /* Watchdog timer */ 919 "\017<b14>" 920 "\020LWP" /* Lightweight Profiling */ 921 "\021FMA4" /* 4-operand FMA instructions */ 922 "\022TCE" /* Translation Cache Extension */ 923 "\023<b18>" 924 "\024NodeId" /* NodeId MSR support */ 925 "\025<b20>" 926 "\026TBM" /* Trailing Bit Manipulation */ 927 "\027Topology" /* Topology Extensions */ 928 "\030PCXC" /* Core perf count */ 929 "\031PNXC" /* NB perf count */ 930 "\032<b25>" 931 "\033DBE" /* Data Breakpoint extension */ 932 "\034PTSC" /* Performance TSC */ 933 "\035PL2I" /* L2I perf count */ 934 "\036MWAITX" /* MONITORX/MWAITX instructions */ 935 "\037ADMSKX" /* Address mask extension */ 936 "\040<b31>" 937 ); 938 } 939 940 if (cpu_stdext_feature != 0) { 941 printf("\n Structured Extended Features=0x%b", 942 cpu_stdext_feature, 943 "\020" 944 /* RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */ 945 "\001FSGSBASE" 946 "\002TSCADJ" 947 "\003SGX" 948 /* Bit Manipulation Instructions */ 949 "\004BMI1" 950 /* Hardware Lock Elision */ 951 "\005HLE" 952 /* Advanced Vector Instructions 2 */ 953 "\006AVX2" 954 /* FDP_EXCPTN_ONLY */ 955 "\007FDPEXC" 956 /* Supervisor Mode Execution Prot. */ 957 "\010SMEP" 958 /* Bit Manipulation Instructions */ 959 "\011BMI2" 960 "\012ERMS" 961 /* Invalidate Processor Context ID */ 962 "\013INVPCID" 963 /* Restricted Transactional Memory */ 964 "\014RTM" 965 "\015PQM" 966 "\016NFPUSG" 967 /* Intel Memory Protection Extensions */ 968 "\017MPX" 969 "\020PQE" 970 /* AVX512 Foundation */ 971 "\021AVX512F" 972 "\022AVX512DQ" 973 /* Enhanced NRBG */ 974 "\023RDSEED" 975 /* ADCX + ADOX */ 976 "\024ADX" 977 /* Supervisor Mode Access Prevention */ 978 "\025SMAP" 979 "\026AVX512IFMA" 980 /* Formerly PCOMMIT */ 981 "\027<b22>" 982 "\030CLFLUSHOPT" 983 "\031CLWB" 984 "\032PROCTRACE" 985 "\033AVX512PF" 986 "\034AVX512ER" 987 "\035AVX512CD" 988 "\036SHA" 989 "\037AVX512BW" 990 "\040AVX512VL" 991 ); 992 } 993 994 if (cpu_stdext_feature2 != 0) { 995 printf("\n Structured Extended Features2=0x%b", 996 cpu_stdext_feature2, 997 "\020" 998 "\001PREFETCHWT1" 999 "\002AVX512VBMI" 1000 "\003UMIP" 1001 "\004PKU" 1002 "\005OSPKE" 1003 "\006WAITPKG" 1004 "\007AVX512VBMI2" 1005 "\011GFNI" 1006 "\012VAES" 1007 "\013VPCLMULQDQ" 1008 "\014AVX512VNNI" 1009 "\015AVX512BITALG" 1010 "\016TME" 1011 "\017AVX512VPOPCNTDQ" 1012 "\021LA57" 1013 "\027RDPID" 1014 "\032CLDEMOTE" 1015 "\034MOVDIRI" 1016 "\035MOVDIR64B" 1017 "\036ENQCMD" 1018 "\037SGXLC" 1019 ); 1020 } 1021 1022 if (cpu_stdext_feature3 != 0) { 1023 printf("\n Structured Extended Features3=0x%b", 1024 cpu_stdext_feature3, 1025 "\020" 1026 "\003AVX512_4VNNIW" 1027 "\004AVX512_4FMAPS" 1028 "\005FSRM" 1029 "\011AVX512VP2INTERSECT" 1030 "\012MCUOPT" 1031 "\013MD_CLEAR" 1032 "\016TSXFA" 1033 "\023PCONFIG" 1034 "\025IBT" 1035 "\033IBPB" 1036 "\034STIBP" 1037 "\035L1DFL" 1038 "\036ARCH_CAP" 1039 "\037CORE_CAP" 1040 "\040SSBD" 1041 ); 1042 } 1043 1044 if ((cpu_feature2 & CPUID2_XSAVE) != 0) { 1045 cpuid_count(0xd, 0x1, regs); 1046 if (regs[0] != 0) { 1047 printf("\n XSAVE Features=0x%b", 1048 regs[0], 1049 "\020" 1050 "\001XSAVEOPT" 1051 "\002XSAVEC" 1052 "\003XINUSE" 1053 "\004XSAVES"); 1054 } 1055 } 1056 1057 if (cpu_ia32_arch_caps != 0) { 1058 printf("\n IA32_ARCH_CAPS=0x%b", 1059 (u_int)cpu_ia32_arch_caps, 1060 "\020" 1061 "\001RDCL_NO" 1062 "\002IBRS_ALL" 1063 "\003RSBA" 1064 "\004SKIP_L1DFL_VME" 1065 "\005SSB_NO" 1066 "\006MDS_NO" 1067 "\010TSX_CTRL" 1068 "\011TAA_NO" 1069 ); 1070 } 1071 1072 if (amd_extended_feature_extensions != 0) { 1073 u_int amd_fe_masked; 1074 1075 amd_fe_masked = amd_extended_feature_extensions; 1076 if ((amd_fe_masked & AMDFEID_IBRS) == 0) 1077 amd_fe_masked &= 1078 ~(AMDFEID_IBRS_ALWAYSON | 1079 AMDFEID_PREFER_IBRS); 1080 if ((amd_fe_masked & AMDFEID_STIBP) == 0) 1081 amd_fe_masked &= 1082 ~AMDFEID_STIBP_ALWAYSON; 1083 1084 printf("\n " 1085 "AMD Extended Feature Extensions ID EBX=" 1086 "0x%b", amd_fe_masked, 1087 "\020" 1088 "\001CLZERO" 1089 "\002IRPerf" 1090 "\003XSaveErPtr" 1091 "\005RDPRU" 1092 "\011MCOMMIT" 1093 "\012WBNOINVD" 1094 "\015IBPB" 1095 "\017IBRS" 1096 "\020STIBP" 1097 "\021IBRS_ALWAYSON" 1098 "\022STIBP_ALWAYSON" 1099 "\023PREFER_IBRS" 1100 "\030PPIN" 1101 "\031SSBD" 1102 "\032VIRT_SSBD" 1103 "\033SSB_NO" 1104 ); 1105 } 1106 1107 if (via_feature_rng != 0 || via_feature_xcrypt != 0) 1108 print_via_padlock_info(); 1109 1110 if (cpu_feature2 & CPUID2_VMX) 1111 print_vmx_info(); 1112 1113 if (amd_feature2 & AMDID2_SVM) 1114 print_svm_info(); 1115 1116 if ((cpu_feature & CPUID_HTT) && 1117 (cpu_vendor_id == CPU_VENDOR_AMD || 1118 cpu_vendor_id == CPU_VENDOR_HYGON)) 1119 cpu_feature &= ~CPUID_HTT; 1120 1121 /* 1122 * If this CPU supports P-state invariant TSC then 1123 * mention the capability. 1124 */ 1125 if (tsc_is_invariant) { 1126 printf("\n TSC: P-state invariant"); 1127 if (tsc_perf_stat) 1128 printf(", performance statistics"); 1129 } 1130 } 1131 #ifdef __i386__ 1132 } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1133 printf(" DIR=0x%04x", cyrix_did); 1134 printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12); 1135 printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8); 1136 #ifndef CYRIX_CACHE_REALLY_WORKS 1137 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700) 1138 printf("\n CPU cache: write-through mode"); 1139 #endif 1140 #endif 1141 } 1142 1143 /* Avoid ugly blank lines: only print newline when we have to. */ 1144 if (*cpu_vendor || cpu_id) 1145 printf("\n"); 1146 1147 if (bootverbose) { 1148 if (cpu_vendor_id == CPU_VENDOR_AMD || 1149 cpu_vendor_id == CPU_VENDOR_HYGON) 1150 print_AMD_info(); 1151 else if (cpu_vendor_id == CPU_VENDOR_INTEL) 1152 print_INTEL_info(); 1153 #ifdef __i386__ 1154 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA) 1155 print_transmeta_info(); 1156 #endif 1157 } 1158 1159 print_hypervisor_info(); 1160 } 1161 1162 #ifdef __i386__ 1163 void 1164 panicifcpuunsupported(void) 1165 { 1166 1167 #if !defined(lint) 1168 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU) 1169 #error This kernel is not configured for one of the supported CPUs 1170 #endif 1171 #else /* lint */ 1172 #endif /* lint */ 1173 /* 1174 * Now that we have told the user what they have, 1175 * let them know if that machine type isn't configured. 1176 */ 1177 switch (cpu_class) { 1178 case CPUCLASS_286: /* a 286 should not make it this far, anyway */ 1179 case CPUCLASS_386: 1180 #if !defined(I486_CPU) 1181 case CPUCLASS_486: 1182 #endif 1183 #if !defined(I586_CPU) 1184 case CPUCLASS_586: 1185 #endif 1186 #if !defined(I686_CPU) 1187 case CPUCLASS_686: 1188 #endif 1189 panic("CPU class not configured"); 1190 default: 1191 break; 1192 } 1193 } 1194 1195 static volatile u_int trap_by_rdmsr; 1196 1197 /* 1198 * Special exception 6 handler. 1199 * The rdmsr instruction generates invalid opcodes fault on 486-class 1200 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the 1201 * function identblue() when this handler is called. Stacked eip should 1202 * be advanced. 1203 */ 1204 inthand_t bluetrap6; 1205 #ifdef __GNUCLIKE_ASM 1206 __asm 1207 (" \n\ 1208 .text \n\ 1209 .p2align 2,0x90 \n\ 1210 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\ 1211 " __XSTRING(CNAME(bluetrap6)) ": \n\ 1212 ss \n\ 1213 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1214 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1215 iret \n\ 1216 "); 1217 #endif 1218 1219 /* 1220 * Special exception 13 handler. 1221 * Accessing non-existent MSR generates general protection fault. 1222 */ 1223 inthand_t bluetrap13; 1224 #ifdef __GNUCLIKE_ASM 1225 __asm 1226 (" \n\ 1227 .text \n\ 1228 .p2align 2,0x90 \n\ 1229 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\ 1230 " __XSTRING(CNAME(bluetrap13)) ": \n\ 1231 ss \n\ 1232 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\ 1233 popl %eax /* discard error code */ \n\ 1234 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\ 1235 iret \n\ 1236 "); 1237 #endif 1238 1239 /* 1240 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not 1241 * support cpuid instruction. This function should be called after 1242 * loading interrupt descriptor table register. 1243 * 1244 * I don't like this method that handles fault, but I couldn't get 1245 * information for any other methods. Does blue giant know? 1246 */ 1247 static int 1248 identblue(void) 1249 { 1250 1251 trap_by_rdmsr = 0; 1252 1253 /* 1254 * Cyrix 486-class CPU does not support rdmsr instruction. 1255 * The rdmsr instruction generates invalid opcode fault, and exception 1256 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The 1257 * bluetrap6() set the magic number to trap_by_rdmsr. 1258 */ 1259 setidt(IDT_UD, bluetrap6, SDT_SYS386TGT, SEL_KPL, 1260 GSEL(GCODE_SEL, SEL_KPL)); 1261 1262 /* 1263 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU. 1264 * In this case, rdmsr generates general protection fault, and 1265 * exception will be trapped by bluetrap13(). 1266 */ 1267 setidt(IDT_GP, bluetrap13, SDT_SYS386TGT, SEL_KPL, 1268 GSEL(GCODE_SEL, SEL_KPL)); 1269 1270 rdmsr(0x1002); /* Cyrix CPU generates fault. */ 1271 1272 if (trap_by_rdmsr == 0xa8c1d) 1273 return IDENTBLUE_CYRIX486; 1274 else if (trap_by_rdmsr == 0xa89c4) 1275 return IDENTBLUE_CYRIXM2; 1276 return IDENTBLUE_IBMCPU; 1277 } 1278 1279 /* 1280 * identifycyrix() set lower 16 bits of cyrix_did as follows: 1281 * 1282 * F E D C B A 9 8 7 6 5 4 3 2 1 0 1283 * +-------+-------+---------------+ 1284 * | SID | RID | Device ID | 1285 * | (DIR 1) | (DIR 0) | 1286 * +-------+-------+---------------+ 1287 */ 1288 static void 1289 identifycyrix(void) 1290 { 1291 register_t saveintr; 1292 int ccr2_test = 0, dir_test = 0; 1293 u_char ccr2, ccr3; 1294 1295 saveintr = intr_disable(); 1296 1297 ccr2 = read_cyrix_reg(CCR2); 1298 write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW); 1299 read_cyrix_reg(CCR2); 1300 if (read_cyrix_reg(CCR2) != ccr2) 1301 ccr2_test = 1; 1302 write_cyrix_reg(CCR2, ccr2); 1303 1304 ccr3 = read_cyrix_reg(CCR3); 1305 write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3); 1306 read_cyrix_reg(CCR3); 1307 if (read_cyrix_reg(CCR3) != ccr3) 1308 dir_test = 1; /* CPU supports DIRs. */ 1309 write_cyrix_reg(CCR3, ccr3); 1310 1311 if (dir_test) { 1312 /* Device ID registers are available. */ 1313 cyrix_did = read_cyrix_reg(DIR1) << 8; 1314 cyrix_did += read_cyrix_reg(DIR0); 1315 } else if (ccr2_test) 1316 cyrix_did = 0x0010; /* 486S A-step */ 1317 else 1318 cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */ 1319 1320 intr_restore(saveintr); 1321 } 1322 #endif 1323 1324 /* Update TSC freq with the value indicated by the caller. */ 1325 static void 1326 tsc_freq_changed(void *arg __unused, const struct cf_level *level, int status) 1327 { 1328 1329 /* If there was an error during the transition, don't do anything. */ 1330 if (status != 0) 1331 return; 1332 1333 /* Total setting for this level gives the new frequency in MHz. */ 1334 hw_clockrate = level->total_set.freq; 1335 } 1336 1337 static void 1338 hook_tsc_freq(void *arg __unused) 1339 { 1340 1341 if (tsc_is_invariant) 1342 return; 1343 1344 tsc_post_tag = EVENTHANDLER_REGISTER(cpufreq_post_change, 1345 tsc_freq_changed, NULL, EVENTHANDLER_PRI_ANY); 1346 } 1347 1348 SYSINIT(hook_tsc_freq, SI_SUB_CONFIGURE, SI_ORDER_ANY, hook_tsc_freq, NULL); 1349 1350 static const struct { 1351 const char * vm_bname; 1352 int vm_guest; 1353 } vm_bnames[] = { 1354 { "QEMU", VM_GUEST_VM }, /* QEMU */ 1355 { "Plex86", VM_GUEST_VM }, /* Plex86 */ 1356 { "Bochs", VM_GUEST_VM }, /* Bochs */ 1357 { "Xen", VM_GUEST_XEN }, /* Xen */ 1358 { "BHYVE", VM_GUEST_BHYVE }, /* bhyve */ 1359 { "Seabios", VM_GUEST_KVM }, /* KVM */ 1360 }; 1361 1362 static const struct { 1363 const char * vm_pname; 1364 int vm_guest; 1365 } vm_pnames[] = { 1366 { "VMware Virtual Platform", VM_GUEST_VMWARE }, 1367 { "Virtual Machine", VM_GUEST_VM }, /* Microsoft VirtualPC */ 1368 { "VirtualBox", VM_GUEST_VBOX }, 1369 { "Parallels Virtual Platform", VM_GUEST_PARALLELS }, 1370 { "KVM", VM_GUEST_KVM }, 1371 }; 1372 1373 static struct { 1374 const char *vm_cpuid; 1375 int vm_guest; 1376 } vm_cpuids[] = { 1377 { "XENXENXEN", VM_GUEST_XEN }, /* XEN */ 1378 { "Microsoft Hv", VM_GUEST_HV }, /* Microsoft Hyper-V */ 1379 { "VMwareVMware", VM_GUEST_VMWARE }, /* VMware VM */ 1380 { "KVMKVMKVM", VM_GUEST_KVM }, /* KVM */ 1381 { "bhyve bhyve ", VM_GUEST_BHYVE }, /* bhyve */ 1382 { "VBoxVBoxVBox", VM_GUEST_VBOX }, /* VirtualBox */ 1383 }; 1384 1385 static void 1386 identify_hypervisor_cpuid_base(void) 1387 { 1388 u_int leaf, regs[4]; 1389 int i; 1390 1391 /* 1392 * [RFC] CPUID usage for interaction between Hypervisors and Linux. 1393 * http://lkml.org/lkml/2008/10/1/246 1394 * 1395 * KB1009458: Mechanisms to determine if software is running in 1396 * a VMware virtual machine 1397 * http://kb.vmware.com/kb/1009458 1398 * 1399 * Search for a hypervisor that we recognize. If we cannot find 1400 * a specific hypervisor, return the first information about the 1401 * hypervisor that we found, as others may be able to use. 1402 */ 1403 for (leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) { 1404 do_cpuid(leaf, regs); 1405 1406 /* 1407 * KVM from Linux kernels prior to commit 1408 * 57c22e5f35aa4b9b2fe11f73f3e62bbf9ef36190 set %eax 1409 * to 0 rather than a valid hv_high value. Check for 1410 * the KVM signature bytes and fixup %eax to the 1411 * highest supported leaf in that case. 1412 */ 1413 if (regs[0] == 0 && regs[1] == 0x4b4d564b && 1414 regs[2] == 0x564b4d56 && regs[3] == 0x0000004d) 1415 regs[0] = leaf + 1; 1416 1417 if (regs[0] >= leaf) { 1418 for (i = 0; i < nitems(vm_cpuids); i++) 1419 if (strncmp((const char *)®s[1], 1420 vm_cpuids[i].vm_cpuid, 12) == 0) { 1421 vm_guest = vm_cpuids[i].vm_guest; 1422 break; 1423 } 1424 1425 /* 1426 * If this is the first entry or we found a 1427 * specific hypervisor, record the base, high value, 1428 * and vendor identifier. 1429 */ 1430 if (vm_guest != VM_GUEST_VM || leaf == 0x40000000) { 1431 hv_base = leaf; 1432 hv_high = regs[0]; 1433 ((u_int *)&hv_vendor)[0] = regs[1]; 1434 ((u_int *)&hv_vendor)[1] = regs[2]; 1435 ((u_int *)&hv_vendor)[2] = regs[3]; 1436 hv_vendor[12] = '\0'; 1437 1438 /* 1439 * If we found a specific hypervisor, then 1440 * we are finished. 1441 */ 1442 if (vm_guest != VM_GUEST_VM) 1443 return; 1444 } 1445 } 1446 } 1447 } 1448 1449 void 1450 identify_hypervisor(void) 1451 { 1452 u_int regs[4]; 1453 char *p; 1454 int i; 1455 1456 /* 1457 * If CPUID2_HV is set, we are running in a hypervisor environment. 1458 */ 1459 if (cpu_feature2 & CPUID2_HV) { 1460 vm_guest = VM_GUEST_VM; 1461 identify_hypervisor_cpuid_base(); 1462 1463 /* If we have a definitive vendor, we can return now. */ 1464 if (*hv_vendor != '\0') 1465 return; 1466 } 1467 1468 /* 1469 * Examine SMBIOS strings for older hypervisors. 1470 */ 1471 p = kern_getenv("smbios.system.serial"); 1472 if (p != NULL) { 1473 if (strncmp(p, "VMware-", 7) == 0 || strncmp(p, "VMW", 3) == 0) { 1474 vmware_hvcall(VMW_HVCMD_GETVERSION, regs); 1475 if (regs[1] == VMW_HVMAGIC) { 1476 vm_guest = VM_GUEST_VMWARE; 1477 freeenv(p); 1478 return; 1479 } 1480 } 1481 freeenv(p); 1482 } 1483 1484 /* 1485 * XXX: Some of these entries may not be needed since they were 1486 * added to FreeBSD before the checks above. 1487 */ 1488 p = kern_getenv("smbios.bios.vendor"); 1489 if (p != NULL) { 1490 for (i = 0; i < nitems(vm_bnames); i++) 1491 if (strcmp(p, vm_bnames[i].vm_bname) == 0) { 1492 vm_guest = vm_bnames[i].vm_guest; 1493 /* If we have a specific match, return */ 1494 if (vm_guest != VM_GUEST_VM) { 1495 freeenv(p); 1496 return; 1497 } 1498 /* 1499 * We are done with bnames, but there might be 1500 * a more specific match in the pnames 1501 */ 1502 break; 1503 } 1504 freeenv(p); 1505 } 1506 p = kern_getenv("smbios.system.product"); 1507 if (p != NULL) { 1508 for (i = 0; i < nitems(vm_pnames); i++) 1509 if (strcmp(p, vm_pnames[i].vm_pname) == 0) { 1510 vm_guest = vm_pnames[i].vm_guest; 1511 freeenv(p); 1512 return; 1513 } 1514 freeenv(p); 1515 } 1516 } 1517 1518 bool 1519 fix_cpuid(void) 1520 { 1521 uint64_t msr; 1522 1523 /* 1524 * Clear "Limit CPUID Maxval" bit and return true if the caller should 1525 * get the largest standard CPUID function number again if it is set 1526 * from BIOS. It is necessary for probing correct CPU topology later 1527 * and for the correct operation of the AVX-aware userspace. 1528 */ 1529 if (cpu_vendor_id == CPU_VENDOR_INTEL && 1530 ((CPUID_TO_FAMILY(cpu_id) == 0xf && 1531 CPUID_TO_MODEL(cpu_id) >= 0x3) || 1532 (CPUID_TO_FAMILY(cpu_id) == 0x6 && 1533 CPUID_TO_MODEL(cpu_id) >= 0xe))) { 1534 msr = rdmsr(MSR_IA32_MISC_ENABLE); 1535 if ((msr & IA32_MISC_EN_LIMCPUID) != 0) { 1536 msr &= ~IA32_MISC_EN_LIMCPUID; 1537 wrmsr(MSR_IA32_MISC_ENABLE, msr); 1538 return (true); 1539 } 1540 } 1541 1542 /* 1543 * Re-enable AMD Topology Extension that could be disabled by BIOS 1544 * on some notebook processors. Without the extension it's really 1545 * hard to determine the correct CPU cache topology. 1546 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h 1547 * Models 60h-6Fh Processors, Publication # 50742. 1548 */ 1549 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD && 1550 CPUID_TO_FAMILY(cpu_id) == 0x15) { 1551 msr = rdmsr(MSR_EXTFEATURES); 1552 if ((msr & ((uint64_t)1 << 54)) == 0) { 1553 msr |= (uint64_t)1 << 54; 1554 wrmsr(MSR_EXTFEATURES, msr); 1555 return (true); 1556 } 1557 } 1558 return (false); 1559 } 1560 1561 void 1562 identify_cpu1(void) 1563 { 1564 u_int regs[4]; 1565 1566 do_cpuid(0, regs); 1567 cpu_high = regs[0]; 1568 ((u_int *)&cpu_vendor)[0] = regs[1]; 1569 ((u_int *)&cpu_vendor)[1] = regs[3]; 1570 ((u_int *)&cpu_vendor)[2] = regs[2]; 1571 cpu_vendor[12] = '\0'; 1572 1573 do_cpuid(1, regs); 1574 cpu_id = regs[0]; 1575 cpu_procinfo = regs[1]; 1576 cpu_feature = regs[3]; 1577 cpu_feature2 = regs[2]; 1578 } 1579 1580 void 1581 identify_cpu2(void) 1582 { 1583 u_int regs[4], cpu_stdext_disable; 1584 1585 if (cpu_high >= 6) { 1586 cpuid_count(6, 0, regs); 1587 cpu_power_eax = regs[0]; 1588 cpu_power_ebx = regs[1]; 1589 cpu_power_ecx = regs[2]; 1590 cpu_power_edx = regs[3]; 1591 } 1592 1593 if (cpu_high >= 7) { 1594 cpuid_count(7, 0, regs); 1595 cpu_stdext_feature = regs[1]; 1596 1597 /* 1598 * Some hypervisors failed to filter out unsupported 1599 * extended features. Allow to disable the 1600 * extensions, activation of which requires setting a 1601 * bit in CR4, and which VM monitors do not support. 1602 */ 1603 cpu_stdext_disable = 0; 1604 TUNABLE_INT_FETCH("hw.cpu_stdext_disable", &cpu_stdext_disable); 1605 cpu_stdext_feature &= ~cpu_stdext_disable; 1606 1607 cpu_stdext_feature2 = regs[2]; 1608 cpu_stdext_feature3 = regs[3]; 1609 1610 if ((cpu_stdext_feature3 & CPUID_STDEXT3_ARCH_CAP) != 0) 1611 cpu_ia32_arch_caps = rdmsr(MSR_IA32_ARCH_CAP); 1612 } 1613 } 1614 1615 void 1616 identify_cpu_fixup_bsp(void) 1617 { 1618 u_int regs[4]; 1619 1620 cpu_vendor_id = find_cpu_vendor_id(); 1621 1622 if (fix_cpuid()) { 1623 do_cpuid(0, regs); 1624 cpu_high = regs[0]; 1625 } 1626 } 1627 1628 /* 1629 * Final stage of CPU identification. 1630 */ 1631 void 1632 finishidentcpu(void) 1633 { 1634 u_int regs[4]; 1635 #ifdef __i386__ 1636 u_char ccr3; 1637 #endif 1638 1639 identify_cpu_fixup_bsp(); 1640 1641 if (cpu_high >= 5 && (cpu_feature2 & CPUID2_MON) != 0) { 1642 do_cpuid(5, regs); 1643 cpu_mon_mwait_flags = regs[2]; 1644 cpu_mon_min_size = regs[0] & CPUID5_MON_MIN_SIZE; 1645 cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; 1646 } 1647 1648 identify_cpu2(); 1649 1650 #ifdef __i386__ 1651 if (cpu_high > 0 && 1652 (cpu_vendor_id == CPU_VENDOR_INTEL || 1653 cpu_vendor_id == CPU_VENDOR_AMD || 1654 cpu_vendor_id == CPU_VENDOR_HYGON || 1655 cpu_vendor_id == CPU_VENDOR_TRANSMETA || 1656 cpu_vendor_id == CPU_VENDOR_CENTAUR || 1657 cpu_vendor_id == CPU_VENDOR_NSC)) { 1658 do_cpuid(0x80000000, regs); 1659 if (regs[0] >= 0x80000000) 1660 cpu_exthigh = regs[0]; 1661 } 1662 #else 1663 if (cpu_vendor_id == CPU_VENDOR_INTEL || 1664 cpu_vendor_id == CPU_VENDOR_AMD || 1665 cpu_vendor_id == CPU_VENDOR_HYGON || 1666 cpu_vendor_id == CPU_VENDOR_CENTAUR) { 1667 do_cpuid(0x80000000, regs); 1668 cpu_exthigh = regs[0]; 1669 } 1670 #endif 1671 if (cpu_exthigh >= 0x80000001) { 1672 do_cpuid(0x80000001, regs); 1673 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); 1674 amd_feature2 = regs[2]; 1675 } 1676 if (cpu_exthigh >= 0x80000007) { 1677 do_cpuid(0x80000007, regs); 1678 amd_rascap = regs[1]; 1679 amd_pminfo = regs[3]; 1680 } 1681 if (cpu_exthigh >= 0x80000008) { 1682 do_cpuid(0x80000008, regs); 1683 cpu_maxphyaddr = regs[0] & 0xff; 1684 amd_extended_feature_extensions = regs[1]; 1685 cpu_procinfo2 = regs[2]; 1686 } else { 1687 cpu_maxphyaddr = (cpu_feature & CPUID_PAE) != 0 ? 36 : 32; 1688 } 1689 1690 #ifdef __i386__ 1691 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1692 if (cpu == CPU_486) { 1693 /* 1694 * These conditions are equivalent to: 1695 * - CPU does not support cpuid instruction. 1696 * - Cyrix/IBM CPU is detected. 1697 */ 1698 if (identblue() == IDENTBLUE_IBMCPU) { 1699 strcpy(cpu_vendor, "IBM"); 1700 cpu_vendor_id = CPU_VENDOR_IBM; 1701 cpu = CPU_BLUE; 1702 return; 1703 } 1704 } 1705 switch (cpu_id & 0xf00) { 1706 case 0x600: 1707 /* 1708 * Cyrix's datasheet does not describe DIRs. 1709 * Therefor, I assume it does not have them 1710 * and use the result of the cpuid instruction. 1711 * XXX they seem to have it for now at least. -Peter 1712 */ 1713 identifycyrix(); 1714 cpu = CPU_M2; 1715 break; 1716 default: 1717 identifycyrix(); 1718 /* 1719 * This routine contains a trick. 1720 * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now. 1721 */ 1722 switch (cyrix_did & 0x00f0) { 1723 case 0x00: 1724 case 0xf0: 1725 cpu = CPU_486DLC; 1726 break; 1727 case 0x10: 1728 cpu = CPU_CY486DX; 1729 break; 1730 case 0x20: 1731 if ((cyrix_did & 0x000f) < 8) 1732 cpu = CPU_M1; 1733 else 1734 cpu = CPU_M1SC; 1735 break; 1736 case 0x30: 1737 cpu = CPU_M1; 1738 break; 1739 case 0x40: 1740 /* MediaGX CPU */ 1741 cpu = CPU_M1SC; 1742 break; 1743 default: 1744 /* M2 and later CPUs are treated as M2. */ 1745 cpu = CPU_M2; 1746 1747 /* 1748 * enable cpuid instruction. 1749 */ 1750 ccr3 = read_cyrix_reg(CCR3); 1751 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1752 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID); 1753 write_cyrix_reg(CCR3, ccr3); 1754 1755 do_cpuid(0, regs); 1756 cpu_high = regs[0]; /* eax */ 1757 do_cpuid(1, regs); 1758 cpu_id = regs[0]; /* eax */ 1759 cpu_feature = regs[3]; /* edx */ 1760 break; 1761 } 1762 } 1763 } else if (cpu == CPU_486 && *cpu_vendor == '\0') { 1764 /* 1765 * There are BlueLightning CPUs that do not change 1766 * undefined flags by dividing 5 by 2. In this case, 1767 * the CPU identification routine in locore.s leaves 1768 * cpu_vendor null string and puts CPU_486 into the 1769 * cpu. 1770 */ 1771 if (identblue() == IDENTBLUE_IBMCPU) { 1772 strcpy(cpu_vendor, "IBM"); 1773 cpu_vendor_id = CPU_VENDOR_IBM; 1774 cpu = CPU_BLUE; 1775 return; 1776 } 1777 } 1778 #endif 1779 } 1780 1781 int 1782 pti_get_default(void) 1783 { 1784 1785 if (strcmp(cpu_vendor, AMD_VENDOR_ID) == 0 || 1786 strcmp(cpu_vendor, HYGON_VENDOR_ID) == 0) 1787 return (0); 1788 if ((cpu_ia32_arch_caps & IA32_ARCH_CAP_RDCL_NO) != 0) 1789 return (0); 1790 return (1); 1791 } 1792 1793 static u_int 1794 find_cpu_vendor_id(void) 1795 { 1796 int i; 1797 1798 for (i = 0; i < nitems(cpu_vendors); i++) 1799 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0) 1800 return (cpu_vendors[i].vendor_id); 1801 return (0); 1802 } 1803 1804 static void 1805 print_AMD_assoc(int i) 1806 { 1807 if (i == 255) 1808 printf(", fully associative\n"); 1809 else 1810 printf(", %d-way associative\n", i); 1811 } 1812 1813 static void 1814 print_AMD_l2_assoc(int i) 1815 { 1816 switch (i & 0x0f) { 1817 case 0: printf(", disabled/not present\n"); break; 1818 case 1: printf(", direct mapped\n"); break; 1819 case 2: printf(", 2-way associative\n"); break; 1820 case 4: printf(", 4-way associative\n"); break; 1821 case 6: printf(", 8-way associative\n"); break; 1822 case 8: printf(", 16-way associative\n"); break; 1823 case 15: printf(", fully associative\n"); break; 1824 default: printf(", reserved configuration\n"); break; 1825 } 1826 } 1827 1828 static void 1829 print_AMD_info(void) 1830 { 1831 #ifdef __i386__ 1832 uint64_t amd_whcr; 1833 #endif 1834 u_int regs[4]; 1835 1836 if (cpu_exthigh >= 0x80000005) { 1837 do_cpuid(0x80000005, regs); 1838 printf("L1 2MB data TLB: %d entries", (regs[0] >> 16) & 0xff); 1839 print_AMD_assoc(regs[0] >> 24); 1840 1841 printf("L1 2MB instruction TLB: %d entries", regs[0] & 0xff); 1842 print_AMD_assoc((regs[0] >> 8) & 0xff); 1843 1844 printf("L1 4KB data TLB: %d entries", (regs[1] >> 16) & 0xff); 1845 print_AMD_assoc(regs[1] >> 24); 1846 1847 printf("L1 4KB instruction TLB: %d entries", regs[1] & 0xff); 1848 print_AMD_assoc((regs[1] >> 8) & 0xff); 1849 1850 printf("L1 data cache: %d kbytes", regs[2] >> 24); 1851 printf(", %d bytes/line", regs[2] & 0xff); 1852 printf(", %d lines/tag", (regs[2] >> 8) & 0xff); 1853 print_AMD_assoc((regs[2] >> 16) & 0xff); 1854 1855 printf("L1 instruction cache: %d kbytes", regs[3] >> 24); 1856 printf(", %d bytes/line", regs[3] & 0xff); 1857 printf(", %d lines/tag", (regs[3] >> 8) & 0xff); 1858 print_AMD_assoc((regs[3] >> 16) & 0xff); 1859 } 1860 1861 if (cpu_exthigh >= 0x80000006) { 1862 do_cpuid(0x80000006, regs); 1863 if ((regs[0] >> 16) != 0) { 1864 printf("L2 2MB data TLB: %d entries", 1865 (regs[0] >> 16) & 0xfff); 1866 print_AMD_l2_assoc(regs[0] >> 28); 1867 printf("L2 2MB instruction TLB: %d entries", 1868 regs[0] & 0xfff); 1869 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1870 } else { 1871 printf("L2 2MB unified TLB: %d entries", 1872 regs[0] & 0xfff); 1873 print_AMD_l2_assoc((regs[0] >> 28) & 0xf); 1874 } 1875 if ((regs[1] >> 16) != 0) { 1876 printf("L2 4KB data TLB: %d entries", 1877 (regs[1] >> 16) & 0xfff); 1878 print_AMD_l2_assoc(regs[1] >> 28); 1879 1880 printf("L2 4KB instruction TLB: %d entries", 1881 (regs[1] >> 16) & 0xfff); 1882 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1883 } else { 1884 printf("L2 4KB unified TLB: %d entries", 1885 (regs[1] >> 16) & 0xfff); 1886 print_AMD_l2_assoc((regs[1] >> 28) & 0xf); 1887 } 1888 printf("L2 unified cache: %d kbytes", regs[2] >> 16); 1889 printf(", %d bytes/line", regs[2] & 0xff); 1890 printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); 1891 print_AMD_l2_assoc((regs[2] >> 12) & 0x0f); 1892 } 1893 1894 #ifdef __i386__ 1895 if (((cpu_id & 0xf00) == 0x500) 1896 && (((cpu_id & 0x0f0) > 0x80) 1897 || (((cpu_id & 0x0f0) == 0x80) 1898 && (cpu_id & 0x00f) > 0x07))) { 1899 /* K6-2(new core [Stepping 8-F]), K6-III or later */ 1900 amd_whcr = rdmsr(0xc0000082); 1901 if (!(amd_whcr & (0x3ff << 22))) { 1902 printf("Write Allocate Disable\n"); 1903 } else { 1904 printf("Write Allocate Enable Limit: %dM bytes\n", 1905 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4); 1906 printf("Write Allocate 15-16M bytes: %s\n", 1907 (amd_whcr & (1 << 16)) ? "Enable" : "Disable"); 1908 } 1909 } else if (((cpu_id & 0xf00) == 0x500) 1910 && ((cpu_id & 0x0f0) > 0x50)) { 1911 /* K6, K6-2(old core) */ 1912 amd_whcr = rdmsr(0xc0000082); 1913 if (!(amd_whcr & (0x7f << 1))) { 1914 printf("Write Allocate Disable\n"); 1915 } else { 1916 printf("Write Allocate Enable Limit: %dM bytes\n", 1917 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4); 1918 printf("Write Allocate 15-16M bytes: %s\n", 1919 (amd_whcr & 0x0001) ? "Enable" : "Disable"); 1920 printf("Hardware Write Allocate Control: %s\n", 1921 (amd_whcr & 0x0100) ? "Enable" : "Disable"); 1922 } 1923 } 1924 #endif 1925 /* 1926 * Opteron Rev E shows a bug as in very rare occasions a read memory 1927 * barrier is not performed as expected if it is followed by a 1928 * non-atomic read-modify-write instruction. 1929 * As long as that bug pops up very rarely (intensive machine usage 1930 * on other operating systems generally generates one unexplainable 1931 * crash any 2 months) and as long as a model specific fix would be 1932 * impractical at this stage, print out a warning string if the broken 1933 * model and family are identified. 1934 */ 1935 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 && 1936 CPUID_TO_MODEL(cpu_id) <= 0x3f) 1937 printf("WARNING: This architecture revision has known SMP " 1938 "hardware bugs which may cause random instability\n"); 1939 } 1940 1941 static void 1942 print_INTEL_info(void) 1943 { 1944 u_int regs[4]; 1945 u_int rounds, regnum; 1946 u_int nwaycode, nway; 1947 1948 if (cpu_high >= 2) { 1949 rounds = 0; 1950 do { 1951 do_cpuid(0x2, regs); 1952 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0) 1953 break; /* we have a buggy CPU */ 1954 1955 for (regnum = 0; regnum <= 3; ++regnum) { 1956 if (regs[regnum] & (1<<31)) 1957 continue; 1958 if (regnum != 0) 1959 print_INTEL_TLB(regs[regnum] & 0xff); 1960 print_INTEL_TLB((regs[regnum] >> 8) & 0xff); 1961 print_INTEL_TLB((regs[regnum] >> 16) & 0xff); 1962 print_INTEL_TLB((regs[regnum] >> 24) & 0xff); 1963 } 1964 } while (--rounds > 0); 1965 } 1966 1967 if (cpu_exthigh >= 0x80000006) { 1968 do_cpuid(0x80000006, regs); 1969 nwaycode = (regs[2] >> 12) & 0x0f; 1970 if (nwaycode >= 0x02 && nwaycode <= 0x08) 1971 nway = 1 << (nwaycode / 2); 1972 else 1973 nway = 0; 1974 printf("L2 cache: %u kbytes, %u-way associative, %u bytes/line\n", 1975 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff); 1976 } 1977 } 1978 1979 static void 1980 print_INTEL_TLB(u_int data) 1981 { 1982 switch (data) { 1983 case 0x0: 1984 case 0x40: 1985 default: 1986 break; 1987 case 0x1: 1988 printf("Instruction TLB: 4 KB pages, 4-way set associative, 32 entries\n"); 1989 break; 1990 case 0x2: 1991 printf("Instruction TLB: 4 MB pages, fully associative, 2 entries\n"); 1992 break; 1993 case 0x3: 1994 printf("Data TLB: 4 KB pages, 4-way set associative, 64 entries\n"); 1995 break; 1996 case 0x4: 1997 printf("Data TLB: 4 MB Pages, 4-way set associative, 8 entries\n"); 1998 break; 1999 case 0x6: 2000 printf("1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size\n"); 2001 break; 2002 case 0x8: 2003 printf("1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2004 break; 2005 case 0x9: 2006 printf("1st-level instruction cache: 32 KB, 4-way set associative, 64 byte line size\n"); 2007 break; 2008 case 0xa: 2009 printf("1st-level data cache: 8 KB, 2-way set associative, 32 byte line size\n"); 2010 break; 2011 case 0xb: 2012 printf("Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries\n"); 2013 break; 2014 case 0xc: 2015 printf("1st-level data cache: 16 KB, 4-way set associative, 32 byte line size\n"); 2016 break; 2017 case 0xd: 2018 printf("1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"); 2019 break; 2020 case 0xe: 2021 printf("1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size\n"); 2022 break; 2023 case 0x1d: 2024 printf("2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size\n"); 2025 break; 2026 case 0x21: 2027 printf("2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size\n"); 2028 break; 2029 case 0x22: 2030 printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2031 break; 2032 case 0x23: 2033 printf("3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2034 break; 2035 case 0x24: 2036 printf("2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size\n"); 2037 break; 2038 case 0x25: 2039 printf("3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2040 break; 2041 case 0x29: 2042 printf("3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2043 break; 2044 case 0x2c: 2045 printf("1st-level data cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2046 break; 2047 case 0x30: 2048 printf("1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size\n"); 2049 break; 2050 case 0x39: /* De-listed in SDM rev. 54 */ 2051 printf("2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2052 break; 2053 case 0x3b: /* De-listed in SDM rev. 54 */ 2054 printf("2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size\n"); 2055 break; 2056 case 0x3c: /* De-listed in SDM rev. 54 */ 2057 printf("2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2058 break; 2059 case 0x41: 2060 printf("2nd-level cache: 128 KB, 4-way set associative, 32 byte line size\n"); 2061 break; 2062 case 0x42: 2063 printf("2nd-level cache: 256 KB, 4-way set associative, 32 byte line size\n"); 2064 break; 2065 case 0x43: 2066 printf("2nd-level cache: 512 KB, 4-way set associative, 32 byte line size\n"); 2067 break; 2068 case 0x44: 2069 printf("2nd-level cache: 1 MB, 4-way set associative, 32 byte line size\n"); 2070 break; 2071 case 0x45: 2072 printf("2nd-level cache: 2 MB, 4-way set associative, 32 byte line size\n"); 2073 break; 2074 case 0x46: 2075 printf("3rd-level cache: 4 MB, 4-way set associative, 64 byte line size\n"); 2076 break; 2077 case 0x47: 2078 printf("3rd-level cache: 8 MB, 8-way set associative, 64 byte line size\n"); 2079 break; 2080 case 0x48: 2081 printf("2nd-level cache: 3MByte, 12-way set associative, 64 byte line size\n"); 2082 break; 2083 case 0x49: 2084 if (CPUID_TO_FAMILY(cpu_id) == 0xf && 2085 CPUID_TO_MODEL(cpu_id) == 0x6) 2086 printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n"); 2087 else 2088 printf("2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size"); 2089 break; 2090 case 0x4a: 2091 printf("3rd-level cache: 6MByte, 12-way set associative, 64 byte line size\n"); 2092 break; 2093 case 0x4b: 2094 printf("3rd-level cache: 8MByte, 16-way set associative, 64 byte line size\n"); 2095 break; 2096 case 0x4c: 2097 printf("3rd-level cache: 12MByte, 12-way set associative, 64 byte line size\n"); 2098 break; 2099 case 0x4d: 2100 printf("3rd-level cache: 16MByte, 16-way set associative, 64 byte line size\n"); 2101 break; 2102 case 0x4e: 2103 printf("2nd-level cache: 6MByte, 24-way set associative, 64 byte line size\n"); 2104 break; 2105 case 0x4f: 2106 printf("Instruction TLB: 4 KByte pages, 32 entries\n"); 2107 break; 2108 case 0x50: 2109 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries\n"); 2110 break; 2111 case 0x51: 2112 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries\n"); 2113 break; 2114 case 0x52: 2115 printf("Instruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries\n"); 2116 break; 2117 case 0x55: 2118 printf("Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries\n"); 2119 break; 2120 case 0x56: 2121 printf("Data TLB0: 4 MByte pages, 4-way set associative, 16 entries\n"); 2122 break; 2123 case 0x57: 2124 printf("Data TLB0: 4 KByte pages, 4-way associative, 16 entries\n"); 2125 break; 2126 case 0x59: 2127 printf("Data TLB0: 4 KByte pages, fully associative, 16 entries\n"); 2128 break; 2129 case 0x5a: 2130 printf("Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries\n"); 2131 break; 2132 case 0x5b: 2133 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 64 entries\n"); 2134 break; 2135 case 0x5c: 2136 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 128 entries\n"); 2137 break; 2138 case 0x5d: 2139 printf("Data TLB: 4 KB or 4 MB pages, fully associative, 256 entries\n"); 2140 break; 2141 case 0x60: 2142 printf("1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2143 break; 2144 case 0x61: 2145 printf("Instruction TLB: 4 KByte pages, fully associative, 48 entries\n"); 2146 break; 2147 case 0x63: 2148 printf("Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries\n"); 2149 break; 2150 case 0x64: 2151 printf("Data TLB: 4 KBytes pages, 4-way set associative, 512 entries\n"); 2152 break; 2153 case 0x66: 2154 printf("1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2155 break; 2156 case 0x67: 2157 printf("1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size\n"); 2158 break; 2159 case 0x68: 2160 printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n"); 2161 break; 2162 case 0x6a: 2163 printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2164 break; 2165 case 0x6b: 2166 printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n"); 2167 break; 2168 case 0x6c: 2169 printf("DTLB: 2M/4M pages, 8-way set associative, 128 entries\n"); 2170 break; 2171 case 0x6d: 2172 printf("DTLB: 1 GByte pages, fully associative, 16 entries\n"); 2173 break; 2174 case 0x70: 2175 printf("Trace cache: 12K-uops, 8-way set associative\n"); 2176 break; 2177 case 0x71: 2178 printf("Trace cache: 16K-uops, 8-way set associative\n"); 2179 break; 2180 case 0x72: 2181 printf("Trace cache: 32K-uops, 8-way set associative\n"); 2182 break; 2183 case 0x76: 2184 printf("Instruction TLB: 2M/4M pages, fully associative, 8 entries\n"); 2185 break; 2186 case 0x78: 2187 printf("2nd-level cache: 1 MB, 4-way set associative, 64-byte line size\n"); 2188 break; 2189 case 0x79: 2190 printf("2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2191 break; 2192 case 0x7a: 2193 printf("2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2194 break; 2195 case 0x7b: 2196 printf("2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size\n"); 2197 break; 2198 case 0x7c: 2199 printf("2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size\n"); 2200 break; 2201 case 0x7d: 2202 printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n"); 2203 break; 2204 case 0x7f: 2205 printf("2nd-level cache: 512-KB, 2-way set associative, 64-byte line size\n"); 2206 break; 2207 case 0x80: 2208 printf("2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size\n"); 2209 break; 2210 case 0x82: 2211 printf("2nd-level cache: 256 KB, 8-way set associative, 32 byte line size\n"); 2212 break; 2213 case 0x83: 2214 printf("2nd-level cache: 512 KB, 8-way set associative, 32 byte line size\n"); 2215 break; 2216 case 0x84: 2217 printf("2nd-level cache: 1 MB, 8-way set associative, 32 byte line size\n"); 2218 break; 2219 case 0x85: 2220 printf("2nd-level cache: 2 MB, 8-way set associative, 32 byte line size\n"); 2221 break; 2222 case 0x86: 2223 printf("2nd-level cache: 512 KB, 4-way set associative, 64 byte line size\n"); 2224 break; 2225 case 0x87: 2226 printf("2nd-level cache: 1 MB, 8-way set associative, 64 byte line size\n"); 2227 break; 2228 case 0xa0: 2229 printf("DTLB: 4k pages, fully associative, 32 entries\n"); 2230 break; 2231 case 0xb0: 2232 printf("Instruction TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2233 break; 2234 case 0xb1: 2235 printf("Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries\n"); 2236 break; 2237 case 0xb2: 2238 printf("Instruction TLB: 4KByte pages, 4-way set associative, 64 entries\n"); 2239 break; 2240 case 0xb3: 2241 printf("Data TLB: 4 KB Pages, 4-way set associative, 128 entries\n"); 2242 break; 2243 case 0xb4: 2244 printf("Data TLB1: 4 KByte pages, 4-way associative, 256 entries\n"); 2245 break; 2246 case 0xb5: 2247 printf("Instruction TLB: 4KByte pages, 8-way set associative, 64 entries\n"); 2248 break; 2249 case 0xb6: 2250 printf("Instruction TLB: 4KByte pages, 8-way set associative, 128 entries\n"); 2251 break; 2252 case 0xba: 2253 printf("Data TLB1: 4 KByte pages, 4-way associative, 64 entries\n"); 2254 break; 2255 case 0xc0: 2256 printf("Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries\n"); 2257 break; 2258 case 0xc1: 2259 printf("Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries\n"); 2260 break; 2261 case 0xc2: 2262 printf("DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries\n"); 2263 break; 2264 case 0xc3: 2265 printf("Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries\n"); 2266 break; 2267 case 0xc4: 2268 printf("DTLB: 2M/4M Byte pages, 4-way associative, 32 entries\n"); 2269 break; 2270 case 0xca: 2271 printf("Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries\n"); 2272 break; 2273 case 0xd0: 2274 printf("3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size\n"); 2275 break; 2276 case 0xd1: 2277 printf("3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size\n"); 2278 break; 2279 case 0xd2: 2280 printf("3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size\n"); 2281 break; 2282 case 0xd6: 2283 printf("3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size\n"); 2284 break; 2285 case 0xd7: 2286 printf("3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size\n"); 2287 break; 2288 case 0xd8: 2289 printf("3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size\n"); 2290 break; 2291 case 0xdc: 2292 printf("3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size\n"); 2293 break; 2294 case 0xdd: 2295 printf("3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size\n"); 2296 break; 2297 case 0xde: 2298 printf("3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size\n"); 2299 break; 2300 case 0xe2: 2301 printf("3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size\n"); 2302 break; 2303 case 0xe3: 2304 printf("3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size\n"); 2305 break; 2306 case 0xe4: 2307 printf("3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size\n"); 2308 break; 2309 case 0xea: 2310 printf("3rd-level cache: 12MByte, 24-way set associative, 64 byte line size\n"); 2311 break; 2312 case 0xeb: 2313 printf("3rd-level cache: 18MByte, 24-way set associative, 64 byte line size\n"); 2314 break; 2315 case 0xec: 2316 printf("3rd-level cache: 24MByte, 24-way set associative, 64 byte line size\n"); 2317 break; 2318 case 0xf0: 2319 printf("64-Byte prefetching\n"); 2320 break; 2321 case 0xf1: 2322 printf("128-Byte prefetching\n"); 2323 break; 2324 } 2325 } 2326 2327 static void 2328 print_svm_info(void) 2329 { 2330 u_int features, regs[4]; 2331 uint64_t msr; 2332 int comma; 2333 2334 printf("\n SVM: "); 2335 do_cpuid(0x8000000A, regs); 2336 features = regs[3]; 2337 2338 msr = rdmsr(MSR_VM_CR); 2339 if ((msr & VM_CR_SVMDIS) == VM_CR_SVMDIS) 2340 printf("(disabled in BIOS) "); 2341 2342 if (!bootverbose) { 2343 comma = 0; 2344 if (features & (1 << 0)) { 2345 printf("%sNP", comma ? "," : ""); 2346 comma = 1; 2347 } 2348 if (features & (1 << 3)) { 2349 printf("%sNRIP", comma ? "," : ""); 2350 comma = 1; 2351 } 2352 if (features & (1 << 5)) { 2353 printf("%sVClean", comma ? "," : ""); 2354 comma = 1; 2355 } 2356 if (features & (1 << 6)) { 2357 printf("%sAFlush", comma ? "," : ""); 2358 comma = 1; 2359 } 2360 if (features & (1 << 7)) { 2361 printf("%sDAssist", comma ? "," : ""); 2362 comma = 1; 2363 } 2364 printf("%sNAsids=%d", comma ? "," : "", regs[1]); 2365 return; 2366 } 2367 2368 printf("Features=0x%b", features, 2369 "\020" 2370 "\001NP" /* Nested paging */ 2371 "\002LbrVirt" /* LBR virtualization */ 2372 "\003SVML" /* SVM lock */ 2373 "\004NRIPS" /* NRIP save */ 2374 "\005TscRateMsr" /* MSR based TSC rate control */ 2375 "\006VmcbClean" /* VMCB clean bits */ 2376 "\007FlushByAsid" /* Flush by ASID */ 2377 "\010DecodeAssist" /* Decode assist */ 2378 "\011<b8>" 2379 "\012<b9>" 2380 "\013PauseFilter" /* PAUSE intercept filter */ 2381 "\014EncryptedMcodePatch" 2382 "\015PauseFilterThreshold" /* PAUSE filter threshold */ 2383 "\016AVIC" /* virtual interrupt controller */ 2384 "\017<b14>" 2385 "\020V_VMSAVE_VMLOAD" 2386 "\021vGIF" 2387 "\022GMET" /* Guest Mode Execute Trap */ 2388 "\023<b18>" 2389 "\024<b19>" 2390 "\025GuesSpecCtl" /* Guest Spec_ctl */ 2391 "\026<b21>" 2392 "\027<b22>" 2393 "\030<b23>" 2394 "\031<b24>" 2395 "\032<b25>" 2396 "\033<b26>" 2397 "\034<b27>" 2398 "\035<b28>" 2399 "\036<b29>" 2400 "\037<b30>" 2401 "\040<b31>" 2402 ); 2403 printf("\nRevision=%d, ASIDs=%d", regs[0] & 0xff, regs[1]); 2404 } 2405 2406 #ifdef __i386__ 2407 static void 2408 print_transmeta_info(void) 2409 { 2410 u_int regs[4], nreg = 0; 2411 2412 do_cpuid(0x80860000, regs); 2413 nreg = regs[0]; 2414 if (nreg >= 0x80860001) { 2415 do_cpuid(0x80860001, regs); 2416 printf(" Processor revision %u.%u.%u.%u\n", 2417 (regs[1] >> 24) & 0xff, 2418 (regs[1] >> 16) & 0xff, 2419 (regs[1] >> 8) & 0xff, 2420 regs[1] & 0xff); 2421 } 2422 if (nreg >= 0x80860002) { 2423 do_cpuid(0x80860002, regs); 2424 printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n", 2425 (regs[1] >> 24) & 0xff, 2426 (regs[1] >> 16) & 0xff, 2427 (regs[1] >> 8) & 0xff, 2428 regs[1] & 0xff, 2429 regs[2]); 2430 } 2431 if (nreg >= 0x80860006) { 2432 char info[65]; 2433 do_cpuid(0x80860003, (u_int*) &info[0]); 2434 do_cpuid(0x80860004, (u_int*) &info[16]); 2435 do_cpuid(0x80860005, (u_int*) &info[32]); 2436 do_cpuid(0x80860006, (u_int*) &info[48]); 2437 info[64] = 0; 2438 printf(" %s\n", info); 2439 } 2440 } 2441 #endif 2442 2443 static void 2444 print_via_padlock_info(void) 2445 { 2446 u_int regs[4]; 2447 2448 do_cpuid(0xc0000001, regs); 2449 printf("\n VIA Padlock Features=0x%b", regs[3], 2450 "\020" 2451 "\003RNG" /* RNG */ 2452 "\007AES" /* ACE */ 2453 "\011AES-CTR" /* ACE2 */ 2454 "\013SHA1,SHA256" /* PHE */ 2455 "\015RSA" /* PMM */ 2456 ); 2457 } 2458 2459 static uint32_t 2460 vmx_settable(uint64_t basic, int msr, int true_msr) 2461 { 2462 uint64_t val; 2463 2464 if (basic & (1ULL << 55)) 2465 val = rdmsr(true_msr); 2466 else 2467 val = rdmsr(msr); 2468 2469 /* Just report the controls that can be set to 1. */ 2470 return (val >> 32); 2471 } 2472 2473 static void 2474 print_vmx_info(void) 2475 { 2476 uint64_t basic, msr; 2477 uint32_t entry, exit, mask, pin, proc, proc2; 2478 int comma; 2479 2480 printf("\n VT-x: "); 2481 msr = rdmsr(MSR_IA32_FEATURE_CONTROL); 2482 if (!(msr & IA32_FEATURE_CONTROL_VMX_EN)) 2483 printf("(disabled in BIOS) "); 2484 basic = rdmsr(MSR_VMX_BASIC); 2485 pin = vmx_settable(basic, MSR_VMX_PINBASED_CTLS, 2486 MSR_VMX_TRUE_PINBASED_CTLS); 2487 proc = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS, 2488 MSR_VMX_TRUE_PROCBASED_CTLS); 2489 if (proc & PROCBASED_SECONDARY_CONTROLS) 2490 proc2 = vmx_settable(basic, MSR_VMX_PROCBASED_CTLS2, 2491 MSR_VMX_PROCBASED_CTLS2); 2492 else 2493 proc2 = 0; 2494 exit = vmx_settable(basic, MSR_VMX_EXIT_CTLS, MSR_VMX_TRUE_EXIT_CTLS); 2495 entry = vmx_settable(basic, MSR_VMX_ENTRY_CTLS, MSR_VMX_TRUE_ENTRY_CTLS); 2496 2497 if (!bootverbose) { 2498 comma = 0; 2499 if (exit & VM_EXIT_SAVE_PAT && exit & VM_EXIT_LOAD_PAT && 2500 entry & VM_ENTRY_LOAD_PAT) { 2501 printf("%sPAT", comma ? "," : ""); 2502 comma = 1; 2503 } 2504 if (proc & PROCBASED_HLT_EXITING) { 2505 printf("%sHLT", comma ? "," : ""); 2506 comma = 1; 2507 } 2508 if (proc & PROCBASED_MTF) { 2509 printf("%sMTF", comma ? "," : ""); 2510 comma = 1; 2511 } 2512 if (proc & PROCBASED_PAUSE_EXITING) { 2513 printf("%sPAUSE", comma ? "," : ""); 2514 comma = 1; 2515 } 2516 if (proc2 & PROCBASED2_ENABLE_EPT) { 2517 printf("%sEPT", comma ? "," : ""); 2518 comma = 1; 2519 } 2520 if (proc2 & PROCBASED2_UNRESTRICTED_GUEST) { 2521 printf("%sUG", comma ? "," : ""); 2522 comma = 1; 2523 } 2524 if (proc2 & PROCBASED2_ENABLE_VPID) { 2525 printf("%sVPID", comma ? "," : ""); 2526 comma = 1; 2527 } 2528 if (proc & PROCBASED_USE_TPR_SHADOW && 2529 proc2 & PROCBASED2_VIRTUALIZE_APIC_ACCESSES && 2530 proc2 & PROCBASED2_VIRTUALIZE_X2APIC_MODE && 2531 proc2 & PROCBASED2_APIC_REGISTER_VIRTUALIZATION && 2532 proc2 & PROCBASED2_VIRTUAL_INTERRUPT_DELIVERY) { 2533 printf("%sVID", comma ? "," : ""); 2534 comma = 1; 2535 if (pin & PINBASED_POSTED_INTERRUPT) 2536 printf(",PostIntr"); 2537 } 2538 return; 2539 } 2540 2541 mask = basic >> 32; 2542 printf("Basic Features=0x%b", mask, 2543 "\020" 2544 "\02132PA" /* 32-bit physical addresses */ 2545 "\022SMM" /* SMM dual-monitor */ 2546 "\027INS/OUTS" /* VM-exit info for INS and OUTS */ 2547 "\030TRUE" /* TRUE_CTLS MSRs */ 2548 ); 2549 printf("\n Pin-Based Controls=0x%b", pin, 2550 "\020" 2551 "\001ExtINT" /* External-interrupt exiting */ 2552 "\004NMI" /* NMI exiting */ 2553 "\006VNMI" /* Virtual NMIs */ 2554 "\007PreTmr" /* Activate VMX-preemption timer */ 2555 "\010PostIntr" /* Process posted interrupts */ 2556 ); 2557 printf("\n Primary Processor Controls=0x%b", proc, 2558 "\020" 2559 "\003INTWIN" /* Interrupt-window exiting */ 2560 "\004TSCOff" /* Use TSC offsetting */ 2561 "\010HLT" /* HLT exiting */ 2562 "\012INVLPG" /* INVLPG exiting */ 2563 "\013MWAIT" /* MWAIT exiting */ 2564 "\014RDPMC" /* RDPMC exiting */ 2565 "\015RDTSC" /* RDTSC exiting */ 2566 "\020CR3-LD" /* CR3-load exiting */ 2567 "\021CR3-ST" /* CR3-store exiting */ 2568 "\024CR8-LD" /* CR8-load exiting */ 2569 "\025CR8-ST" /* CR8-store exiting */ 2570 "\026TPR" /* Use TPR shadow */ 2571 "\027NMIWIN" /* NMI-window exiting */ 2572 "\030MOV-DR" /* MOV-DR exiting */ 2573 "\031IO" /* Unconditional I/O exiting */ 2574 "\032IOmap" /* Use I/O bitmaps */ 2575 "\034MTF" /* Monitor trap flag */ 2576 "\035MSRmap" /* Use MSR bitmaps */ 2577 "\036MONITOR" /* MONITOR exiting */ 2578 "\037PAUSE" /* PAUSE exiting */ 2579 ); 2580 if (proc & PROCBASED_SECONDARY_CONTROLS) 2581 printf("\n Secondary Processor Controls=0x%b", proc2, 2582 "\020" 2583 "\001APIC" /* Virtualize APIC accesses */ 2584 "\002EPT" /* Enable EPT */ 2585 "\003DT" /* Descriptor-table exiting */ 2586 "\004RDTSCP" /* Enable RDTSCP */ 2587 "\005x2APIC" /* Virtualize x2APIC mode */ 2588 "\006VPID" /* Enable VPID */ 2589 "\007WBINVD" /* WBINVD exiting */ 2590 "\010UG" /* Unrestricted guest */ 2591 "\011APIC-reg" /* APIC-register virtualization */ 2592 "\012VID" /* Virtual-interrupt delivery */ 2593 "\013PAUSE-loop" /* PAUSE-loop exiting */ 2594 "\014RDRAND" /* RDRAND exiting */ 2595 "\015INVPCID" /* Enable INVPCID */ 2596 "\016VMFUNC" /* Enable VM functions */ 2597 "\017VMCS" /* VMCS shadowing */ 2598 "\020EPT#VE" /* EPT-violation #VE */ 2599 "\021XSAVES" /* Enable XSAVES/XRSTORS */ 2600 ); 2601 printf("\n Exit Controls=0x%b", mask, 2602 "\020" 2603 "\003DR" /* Save debug controls */ 2604 /* Ignore Host address-space size */ 2605 "\015PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2606 "\020AckInt" /* Acknowledge interrupt on exit */ 2607 "\023PAT-SV" /* Save MSR_PAT */ 2608 "\024PAT-LD" /* Load MSR_PAT */ 2609 "\025EFER-SV" /* Save MSR_EFER */ 2610 "\026EFER-LD" /* Load MSR_EFER */ 2611 "\027PTMR-SV" /* Save VMX-preemption timer value */ 2612 ); 2613 printf("\n Entry Controls=0x%b", mask, 2614 "\020" 2615 "\003DR" /* Save debug controls */ 2616 /* Ignore IA-32e mode guest */ 2617 /* Ignore Entry to SMM */ 2618 /* Ignore Deactivate dual-monitor treatment */ 2619 "\016PERF" /* Load MSR_PERF_GLOBAL_CTRL */ 2620 "\017PAT" /* Load MSR_PAT */ 2621 "\020EFER" /* Load MSR_EFER */ 2622 ); 2623 if (proc & PROCBASED_SECONDARY_CONTROLS && 2624 (proc2 & (PROCBASED2_ENABLE_EPT | PROCBASED2_ENABLE_VPID)) != 0) { 2625 msr = rdmsr(MSR_VMX_EPT_VPID_CAP); 2626 mask = msr; 2627 printf("\n EPT Features=0x%b", mask, 2628 "\020" 2629 "\001XO" /* Execute-only translations */ 2630 "\007PW4" /* Page-walk length of 4 */ 2631 "\011UC" /* EPT paging-structure mem can be UC */ 2632 "\017WB" /* EPT paging-structure mem can be WB */ 2633 "\0212M" /* EPT PDE can map a 2-Mbyte page */ 2634 "\0221G" /* EPT PDPTE can map a 1-Gbyte page */ 2635 "\025INVEPT" /* INVEPT is supported */ 2636 "\026AD" /* Accessed and dirty flags for EPT */ 2637 "\032single" /* INVEPT single-context type */ 2638 "\033all" /* INVEPT all-context type */ 2639 ); 2640 mask = msr >> 32; 2641 printf("\n VPID Features=0x%b", mask, 2642 "\020" 2643 "\001INVVPID" /* INVVPID is supported */ 2644 "\011individual" /* INVVPID individual-address type */ 2645 "\012single" /* INVVPID single-context type */ 2646 "\013all" /* INVVPID all-context type */ 2647 /* INVVPID single-context-retaining-globals type */ 2648 "\014single-globals" 2649 ); 2650 } 2651 } 2652 2653 static void 2654 print_hypervisor_info(void) 2655 { 2656 2657 if (*hv_vendor != '\0') 2658 printf("Hypervisor: Origin = \"%s\"\n", hv_vendor); 2659 } 2660 2661 /* 2662 * Returns the maximum physical address that can be used with the 2663 * current system. 2664 */ 2665 vm_paddr_t 2666 cpu_getmaxphyaddr(void) 2667 { 2668 2669 #if defined(__i386__) 2670 if (!pae_mode) 2671 return (0xffffffff); 2672 #endif 2673 return ((1ULL << cpu_maxphyaddr) - 1); 2674 } 2675