1 /*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef lint 32 static const char rcsid[] = 33 "$FreeBSD$"; 34 #endif /* not lint */ 35 36 #include <sys/types.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <strings.h> 41 #include <sys/agpio.h> 42 #include <sys/pciio.h> 43 44 #include <dev/agp/agpreg.h> 45 #include <dev/pci/pcireg.h> 46 47 #include "pciconf.h" 48 49 static void list_ecaps(int fd, struct pci_conf *p); 50 51 static void 52 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 53 { 54 uint16_t cap, status; 55 56 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 57 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 58 printf("powerspec %d supports D0%s%s D3 current D%d", 59 cap & PCIM_PCAP_SPEC, 60 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 61 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 62 status & PCIM_PSTAT_DMASK); 63 } 64 65 static void 66 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 67 { 68 uint32_t status, command; 69 70 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 71 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 72 printf("AGP "); 73 if (AGP_MODE_GET_MODE_3(status)) { 74 printf("v3 "); 75 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 76 printf("8x "); 77 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 78 printf("4x "); 79 } else { 80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 81 printf("4x "); 82 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 83 printf("2x "); 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 85 printf("1x "); 86 } 87 if (AGP_MODE_GET_SBA(status)) 88 printf("SBA "); 89 if (AGP_MODE_GET_AGP(command)) { 90 printf("enabled at "); 91 if (AGP_MODE_GET_MODE_3(command)) { 92 printf("v3 "); 93 switch (AGP_MODE_GET_RATE(command)) { 94 case AGP_MODE_V3_RATE_8x: 95 printf("8x "); 96 break; 97 case AGP_MODE_V3_RATE_4x: 98 printf("4x "); 99 break; 100 } 101 } else 102 switch (AGP_MODE_GET_RATE(command)) { 103 case AGP_MODE_V2_RATE_4x: 104 printf("4x "); 105 break; 106 case AGP_MODE_V2_RATE_2x: 107 printf("2x "); 108 break; 109 case AGP_MODE_V2_RATE_1x: 110 printf("1x "); 111 break; 112 } 113 if (AGP_MODE_GET_SBA(command)) 114 printf("SBA "); 115 } else 116 printf("disabled"); 117 } 118 119 static void 120 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 121 { 122 123 printf("VPD"); 124 } 125 126 static void 127 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 128 { 129 uint16_t ctrl; 130 int msgnum; 131 132 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 133 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 134 printf("MSI supports %d message%s%s%s ", msgnum, 135 (msgnum == 1) ? "" : "s", 136 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 137 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 138 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 139 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 140 printf("enabled with %d message%s", msgnum, 141 (msgnum == 1) ? "" : "s"); 142 } 143 } 144 145 static void 146 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 147 { 148 uint32_t status; 149 int comma, max_splits, max_burst_read; 150 151 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 152 printf("PCI-X "); 153 if (status & PCIXM_STATUS_64BIT) 154 printf("64-bit "); 155 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 156 printf("bridge "); 157 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 158 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 159 printf("supports"); 160 comma = 0; 161 if (status & PCIXM_STATUS_133CAP) { 162 printf("%s 133MHz", comma ? "," : ""); 163 comma = 1; 164 } 165 if (status & PCIXM_STATUS_266CAP) { 166 printf("%s 266MHz", comma ? "," : ""); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_533CAP) { 170 printf("%s 533MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 174 return; 175 max_burst_read = 0; 176 switch (status & PCIXM_STATUS_MAX_READ) { 177 case PCIXM_STATUS_MAX_READ_512: 178 max_burst_read = 512; 179 break; 180 case PCIXM_STATUS_MAX_READ_1024: 181 max_burst_read = 1024; 182 break; 183 case PCIXM_STATUS_MAX_READ_2048: 184 max_burst_read = 2048; 185 break; 186 case PCIXM_STATUS_MAX_READ_4096: 187 max_burst_read = 4096; 188 break; 189 } 190 max_splits = 0; 191 switch (status & PCIXM_STATUS_MAX_SPLITS) { 192 case PCIXM_STATUS_MAX_SPLITS_1: 193 max_splits = 1; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_2: 196 max_splits = 2; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_3: 199 max_splits = 3; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_4: 202 max_splits = 4; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_8: 205 max_splits = 8; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_12: 208 max_splits = 12; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_16: 211 max_splits = 16; 212 break; 213 case PCIXM_STATUS_MAX_SPLITS_32: 214 max_splits = 32; 215 break; 216 } 217 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 218 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 219 } 220 221 static void 222 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 223 { 224 uint32_t reg; 225 uint16_t command; 226 227 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 228 printf("HT "); 229 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 230 printf("slave"); 231 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 232 printf("host"); 233 else 234 switch (command & PCIM_HTCMD_CAP_MASK) { 235 case PCIM_HTCAP_SWITCH: 236 printf("switch"); 237 break; 238 case PCIM_HTCAP_INTERRUPT: 239 printf("interrupt"); 240 break; 241 case PCIM_HTCAP_REVISION_ID: 242 printf("revision ID"); 243 break; 244 case PCIM_HTCAP_UNITID_CLUMPING: 245 printf("unit ID clumping"); 246 break; 247 case PCIM_HTCAP_EXT_CONFIG_SPACE: 248 printf("extended config space"); 249 break; 250 case PCIM_HTCAP_ADDRESS_MAPPING: 251 printf("address mapping"); 252 break; 253 case PCIM_HTCAP_MSI_MAPPING: 254 printf("MSI %saddress window %s at 0x", 255 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 256 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 257 "disabled"); 258 if (command & PCIM_HTCMD_MSI_FIXED) 259 printf("fee00000"); 260 else { 261 reg = read_config(fd, &p->pc_sel, 262 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 263 if (reg != 0) 264 printf("%08x", reg); 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 267 printf("%08x", reg); 268 } 269 break; 270 case PCIM_HTCAP_DIRECT_ROUTE: 271 printf("direct route"); 272 break; 273 case PCIM_HTCAP_VCSET: 274 printf("VC set"); 275 break; 276 case PCIM_HTCAP_RETRY_MODE: 277 printf("retry mode"); 278 break; 279 case PCIM_HTCAP_X86_ENCODING: 280 printf("X86 encoding"); 281 break; 282 case PCIM_HTCAP_GEN3: 283 printf("Gen3"); 284 break; 285 case PCIM_HTCAP_FLE: 286 printf("function-level extension"); 287 break; 288 case PCIM_HTCAP_PM: 289 printf("power management"); 290 break; 291 case PCIM_HTCAP_HIGH_NODE_COUNT: 292 printf("high node count"); 293 break; 294 default: 295 printf("unknown %02x", command); 296 break; 297 } 298 } 299 300 static void 301 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 302 { 303 uint8_t length; 304 305 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 306 printf("vendor (length %d)", length); 307 if (p->pc_vendor == 0x8086) { 308 /* Intel */ 309 uint8_t version; 310 311 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 312 1); 313 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 314 if (version >> 4 == 1 && length == 12) { 315 /* Feature Detection */ 316 uint32_t fvec; 317 int comma; 318 319 comma = 0; 320 fvec = read_config(fd, &p->pc_sel, ptr + 321 PCIR_VENDOR_DATA + 5, 4); 322 printf("\n\t\t features:"); 323 if (fvec & (1 << 0)) { 324 printf(" AMT"); 325 comma = 1; 326 } 327 fvec = read_config(fd, &p->pc_sel, ptr + 328 PCIR_VENDOR_DATA + 1, 4); 329 if (fvec & (1 << 21)) { 330 printf("%s Quick Resume", comma ? "," : ""); 331 comma = 1; 332 } 333 if (fvec & (1 << 18)) { 334 printf("%s SATA RAID-5", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 9)) { 338 printf("%s Mobile", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 7)) { 342 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } else { 345 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 346 comma = 1; 347 } 348 if (fvec & (1 << 5)) { 349 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 3)) { 353 printf("%s SATA AHCI", comma ? "," : ""); 354 comma = 1; 355 } 356 } 357 } 358 } 359 360 static void 361 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 362 { 363 uint16_t debug_port; 364 365 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 366 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 367 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 368 } 369 370 static void 371 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 372 { 373 uint32_t id; 374 375 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 376 printf("PCI Bridge card=0x%08x", id); 377 } 378 379 #define MAX_PAYLOAD(field) (128 << (field)) 380 381 static const char * 382 link_speed_string(uint8_t speed) 383 { 384 385 switch (speed) { 386 case 1: 387 return ("2.5"); 388 case 2: 389 return ("5.0"); 390 case 3: 391 return ("8.0"); 392 default: 393 return ("undef"); 394 } 395 } 396 397 static const char * 398 aspm_string(uint8_t aspm) 399 { 400 401 switch (aspm) { 402 case 1: 403 return ("L0s"); 404 case 2: 405 return ("L1"); 406 case 3: 407 return ("L0s/L1"); 408 default: 409 return ("disabled"); 410 } 411 } 412 413 static int 414 slot_power(uint32_t cap) 415 { 416 int mwatts; 417 418 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 419 switch (cap & PCIEM_SLOT_CAP_SPLS) { 420 case 0x0: 421 mwatts *= 1000; 422 break; 423 case 0x1: 424 mwatts *= 100; 425 break; 426 case 0x2: 427 mwatts *= 10; 428 break; 429 default: 430 break; 431 } 432 return (mwatts); 433 } 434 435 static void 436 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 437 { 438 uint32_t cap; 439 uint16_t ctl, flags, sta; 440 unsigned int version; 441 442 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 443 version = flags & PCIEM_FLAGS_VERSION; 444 printf("PCI-Express %u ", version); 445 switch (flags & PCIEM_FLAGS_TYPE) { 446 case PCIEM_TYPE_ENDPOINT: 447 printf("endpoint"); 448 break; 449 case PCIEM_TYPE_LEGACY_ENDPOINT: 450 printf("legacy endpoint"); 451 break; 452 case PCIEM_TYPE_ROOT_PORT: 453 printf("root port"); 454 break; 455 case PCIEM_TYPE_UPSTREAM_PORT: 456 printf("upstream port"); 457 break; 458 case PCIEM_TYPE_DOWNSTREAM_PORT: 459 printf("downstream port"); 460 break; 461 case PCIEM_TYPE_PCI_BRIDGE: 462 printf("PCI bridge"); 463 break; 464 case PCIEM_TYPE_PCIE_BRIDGE: 465 printf("PCI to PCIe bridge"); 466 break; 467 case PCIEM_TYPE_ROOT_INT_EP: 468 printf("root endpoint"); 469 break; 470 case PCIEM_TYPE_ROOT_EC: 471 printf("event collector"); 472 break; 473 default: 474 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 475 break; 476 } 477 if (flags & PCIEM_FLAGS_IRQ) 478 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 479 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 480 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 481 printf(" max data %d(%d)", 482 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 483 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 484 if ((cap & PCIEM_CAP_FLR) != 0) 485 printf(" FLR"); 486 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 487 printf(" RO"); 488 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 489 printf(" NS"); 490 if (version >= 2) { 491 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 492 if ((cap & PCIEM_CAP2_ARI) != 0) { 493 ctl = read_config(fd, &p->pc_sel, 494 ptr + PCIER_DEVICE_CTL2, 4); 495 printf(" ARI %s", 496 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 497 } 498 } 499 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 500 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 501 if (cap == 0 && sta == 0) 502 return; 503 printf("\n "); 504 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 505 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 506 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 507 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 508 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 509 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 510 } 511 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 512 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 513 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 514 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 515 } 516 if (!(flags & PCIEM_FLAGS_SLOT)) 517 return; 518 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 519 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 520 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 521 printf("\n "); 522 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 523 printf(" power limit %d mW", slot_power(cap)); 524 if (cap & PCIEM_SLOT_CAP_HPC) 525 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 526 "empty"); 527 if (cap & PCIEM_SLOT_CAP_HPS) 528 printf(" surprise"); 529 if (cap & PCIEM_SLOT_CAP_APB) 530 printf(" Attn Button"); 531 if (cap & PCIEM_SLOT_CAP_PCP) 532 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on"); 533 if (cap & PCIEM_SLOT_CAP_MRLSP) 534 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 535 "closed"); 536 if (cap & PCIEM_SLOT_CAP_EIP) 537 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" : 538 "disengaged"); 539 } 540 541 static void 542 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 543 { 544 uint32_t pba_offset, table_offset, val; 545 int msgnum, pba_bar, table_bar; 546 uint16_t ctrl; 547 548 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 549 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 550 551 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 552 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 553 table_offset = val & ~PCIM_MSIX_BIR_MASK; 554 555 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 556 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 557 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 558 559 printf("MSI-X supports %d message%s%s\n", msgnum, 560 (msgnum == 1) ? "" : "s", 561 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 562 563 printf(" "); 564 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 565 table_bar, table_offset, pba_bar, pba_offset); 566 } 567 568 static void 569 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 570 { 571 572 printf("SATA Index-Data Pair"); 573 } 574 575 static void 576 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 577 { 578 uint8_t cap; 579 580 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 581 printf("PCI Advanced Features:%s%s", 582 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 583 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 584 } 585 586 static const char * 587 ea_bei_to_name(int bei) 588 { 589 static const char *barstr[] = { 590 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 591 }; 592 static const char *vfbarstr[] = { 593 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 594 }; 595 596 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 597 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 598 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 599 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 600 601 switch (bei) { 602 case PCIM_EA_BEI_BRIDGE: 603 return "BRIDGE"; 604 case PCIM_EA_BEI_ENI: 605 return "ENI"; 606 case PCIM_EA_BEI_ROM: 607 return "ROM"; 608 case PCIM_EA_BEI_RESERVED: 609 default: 610 return "RSVD"; 611 } 612 } 613 614 static const char * 615 ea_prop_to_name(uint8_t prop) 616 { 617 618 switch (prop) { 619 case PCIM_EA_P_MEM: 620 return "Non-Prefetchable Memory"; 621 case PCIM_EA_P_MEM_PREFETCH: 622 return "Prefetchable Memory"; 623 case PCIM_EA_P_IO: 624 return "I/O Space"; 625 case PCIM_EA_P_VF_MEM_PREFETCH: 626 return "VF Prefetchable Memory"; 627 case PCIM_EA_P_VF_MEM: 628 return "VF Non-Prefetchable Memory"; 629 case PCIM_EA_P_BRIDGE_MEM: 630 return "Bridge Non-Prefetchable Memory"; 631 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 632 return "Bridge Prefetchable Memory"; 633 case PCIM_EA_P_BRIDGE_IO: 634 return "Bridge I/O Space"; 635 case PCIM_EA_P_MEM_RESERVED: 636 return "Reserved Memory"; 637 case PCIM_EA_P_IO_RESERVED: 638 return "Reserved I/O Space"; 639 case PCIM_EA_P_UNAVAILABLE: 640 return "Unavailable"; 641 default: 642 return "Reserved"; 643 } 644 } 645 646 static void 647 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 648 { 649 int num_ent; 650 int a, b; 651 uint32_t bei; 652 uint32_t val; 653 int ent_size; 654 uint32_t dw[4]; 655 uint32_t flags, flags_pp, flags_sp; 656 uint64_t base, max_offset; 657 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 658 659 /* Determine the number of entries */ 660 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 661 num_ent &= PCIM_EA_NUM_ENT_MASK; 662 663 printf("PCI Enhanced Allocation (%d entries)", num_ent); 664 665 /* Find the first entry to care of */ 666 ptr += PCIR_EA_FIRST_ENT; 667 668 /* Print BUS numbers for bridges */ 669 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 670 val = read_config(fd, &p->pc_sel, ptr, 4); 671 672 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 673 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 674 675 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 676 fixed_sec_bus_nr, fixed_sub_bus_nr); 677 ptr += 4; 678 } 679 680 for (a = 0; a < num_ent; a++) { 681 /* Read a number of dwords in the entry */ 682 val = read_config(fd, &p->pc_sel, ptr, 4); 683 ptr += 4; 684 ent_size = (val & PCIM_EA_ES); 685 686 for (b = 0; b < ent_size; b++) { 687 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 688 ptr += 4; 689 } 690 691 flags = val; 692 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 693 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 694 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 695 696 base = dw[0] & PCIM_EA_FIELD_MASK; 697 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 698 b = 2; 699 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 700 base |= (uint64_t)dw[b] << 32UL; 701 b++; 702 } 703 if (((dw[1] & PCIM_EA_IS_64) != 0) 704 && (b < ent_size)) { 705 max_offset |= (uint64_t)dw[b] << 32UL; 706 b++; 707 } 708 709 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 710 "\n\t\t\tPrimary properties [0x%x] (%s)" 711 "\n\t\t\tSecondary properties [0x%x] (%s)", 712 bei, ea_bei_to_name(bei), 713 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 714 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 715 (uintmax_t)base, (uintmax_t)(max_offset + 1), 716 flags_pp, ea_prop_to_name(flags_pp), 717 flags_sp, ea_prop_to_name(flags_sp)); 718 } 719 } 720 721 void 722 list_caps(int fd, struct pci_conf *p) 723 { 724 int express; 725 uint16_t sta; 726 uint8_t ptr, cap; 727 728 /* Are capabilities present for this device? */ 729 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 730 if (!(sta & PCIM_STATUS_CAPPRESENT)) 731 return; 732 733 switch (p->pc_hdr & PCIM_HDRTYPE) { 734 case PCIM_HDRTYPE_NORMAL: 735 case PCIM_HDRTYPE_BRIDGE: 736 ptr = PCIR_CAP_PTR; 737 break; 738 case PCIM_HDRTYPE_CARDBUS: 739 ptr = PCIR_CAP_PTR_2; 740 break; 741 default: 742 errx(1, "list_caps: bad header type"); 743 } 744 745 /* Walk the capability list. */ 746 express = 0; 747 ptr = read_config(fd, &p->pc_sel, ptr, 1); 748 while (ptr != 0 && ptr != 0xff) { 749 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 750 printf(" cap %02x[%02x] = ", cap, ptr); 751 switch (cap) { 752 case PCIY_PMG: 753 cap_power(fd, p, ptr); 754 break; 755 case PCIY_AGP: 756 cap_agp(fd, p, ptr); 757 break; 758 case PCIY_VPD: 759 cap_vpd(fd, p, ptr); 760 break; 761 case PCIY_MSI: 762 cap_msi(fd, p, ptr); 763 break; 764 case PCIY_PCIX: 765 cap_pcix(fd, p, ptr); 766 break; 767 case PCIY_HT: 768 cap_ht(fd, p, ptr); 769 break; 770 case PCIY_VENDOR: 771 cap_vendor(fd, p, ptr); 772 break; 773 case PCIY_DEBUG: 774 cap_debug(fd, p, ptr); 775 break; 776 case PCIY_SUBVENDOR: 777 cap_subvendor(fd, p, ptr); 778 break; 779 case PCIY_EXPRESS: 780 express = 1; 781 cap_express(fd, p, ptr); 782 break; 783 case PCIY_MSIX: 784 cap_msix(fd, p, ptr); 785 break; 786 case PCIY_SATA: 787 cap_sata(fd, p, ptr); 788 break; 789 case PCIY_PCIAF: 790 cap_pciaf(fd, p, ptr); 791 break; 792 case PCIY_EA: 793 cap_ea(fd, p, ptr); 794 break; 795 default: 796 printf("unknown"); 797 break; 798 } 799 printf("\n"); 800 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 801 } 802 803 if (express) 804 list_ecaps(fd, p); 805 } 806 807 /* From <sys/systm.h>. */ 808 static __inline uint32_t 809 bitcount32(uint32_t x) 810 { 811 812 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 813 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 814 x = (x + (x >> 4)) & 0x0f0f0f0f; 815 x = (x + (x >> 8)); 816 x = (x + (x >> 16)) & 0x000000ff; 817 return (x); 818 } 819 820 static void 821 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 822 { 823 uint32_t sta, mask; 824 825 printf("AER %d", ver); 826 if (ver < 1) 827 return; 828 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 829 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 830 printf(" %d fatal", bitcount32(sta & mask)); 831 printf(" %d non-fatal", bitcount32(sta & ~mask)); 832 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 833 printf(" %d corrected\n", bitcount32(sta)); 834 } 835 836 static void 837 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 838 { 839 uint32_t cap1; 840 841 printf("VC %d", ver); 842 if (ver < 1) 843 return; 844 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 845 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 846 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 847 printf(" lowpri VC0-VC%d", 848 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 849 printf("\n"); 850 } 851 852 static void 853 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 854 { 855 uint32_t high, low; 856 857 printf("Serial %d", ver); 858 if (ver < 1) 859 return; 860 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 861 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 862 printf(" %08x%08x\n", high, low); 863 } 864 865 static void 866 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 867 { 868 uint32_t val; 869 870 printf("Vendor %d", ver); 871 if (ver < 1) 872 return; 873 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 874 printf(" ID %d\n", val & 0xffff); 875 } 876 877 static void 878 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 879 { 880 uint32_t val; 881 882 printf("PCIe Sec %d", ver); 883 if (ver < 1) 884 return; 885 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 886 printf(" lane errors %#x\n", val); 887 } 888 889 static const char * 890 check_enabled(int value) 891 { 892 893 return (value ? "enabled" : "disabled"); 894 } 895 896 static void 897 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 898 { 899 const char *comma, *enabled; 900 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 901 uint32_t page_caps, page_size, page_shift, size; 902 int i; 903 904 printf("SR-IOV %d ", ver); 905 906 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 907 printf("IOV %s, Memory Space %s, ARI %s\n", 908 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 909 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 910 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 911 912 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 913 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 914 printf(" "); 915 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 916 917 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 918 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 919 printf(" "); 920 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 921 vf_stride); 922 923 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 924 printf(" VF Device ID 0x%04x\n", vf_did); 925 926 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 927 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 928 printf(" "); 929 printf("Page Sizes: "); 930 comma = ""; 931 while (page_caps != 0) { 932 page_shift = ffs(page_caps) - 1; 933 934 if (page_caps & page_size) 935 enabled = " (enabled)"; 936 else 937 enabled = ""; 938 939 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 940 printf("%s%d%s", comma, size, enabled); 941 comma = ", "; 942 943 page_caps &= ~(1 << page_shift); 944 } 945 printf("\n"); 946 947 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 948 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 949 } 950 951 static struct { 952 uint16_t id; 953 const char *name; 954 } ecap_names[] = { 955 { PCIZ_PWRBDGT, "Power Budgeting" }, 956 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 957 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 958 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 959 { PCIZ_MFVC, "MFVC" }, 960 { PCIZ_RCRB, "RCRB" }, 961 { PCIZ_ACS, "ACS" }, 962 { PCIZ_ARI, "ARI" }, 963 { PCIZ_ATS, "ATS" }, 964 { PCIZ_MULTICAST, "Multicast" }, 965 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 966 { PCIZ_DPA, "DPA" }, 967 { PCIZ_TPH_REQ, "TPH Requester" }, 968 { PCIZ_LTR, "LTR" }, 969 { 0, NULL } 970 }; 971 972 static void 973 list_ecaps(int fd, struct pci_conf *p) 974 { 975 const char *name; 976 uint32_t ecap; 977 uint16_t ptr; 978 int i; 979 980 ptr = PCIR_EXTCAP; 981 ecap = read_config(fd, &p->pc_sel, ptr, 4); 982 if (ecap == 0xffffffff || ecap == 0) 983 return; 984 for (;;) { 985 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 986 switch (PCI_EXTCAP_ID(ecap)) { 987 case PCIZ_AER: 988 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 989 break; 990 case PCIZ_VC: 991 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 992 break; 993 case PCIZ_SERNUM: 994 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 995 break; 996 case PCIZ_VENDOR: 997 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 998 break; 999 case PCIZ_SEC_PCIE: 1000 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1001 break; 1002 case PCIZ_SRIOV: 1003 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1004 break; 1005 default: 1006 name = "unknown"; 1007 for (i = 0; ecap_names[i].name != NULL; i++) 1008 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1009 name = ecap_names[i].name; 1010 break; 1011 } 1012 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1013 break; 1014 } 1015 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1016 if (ptr == 0) 1017 break; 1018 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1019 } 1020 } 1021 1022 /* Find offset of a specific capability. Returns 0 on failure. */ 1023 uint8_t 1024 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1025 { 1026 uint16_t sta; 1027 uint8_t ptr, cap; 1028 1029 /* Are capabilities present for this device? */ 1030 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1031 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1032 return (0); 1033 1034 switch (p->pc_hdr & PCIM_HDRTYPE) { 1035 case PCIM_HDRTYPE_NORMAL: 1036 case PCIM_HDRTYPE_BRIDGE: 1037 ptr = PCIR_CAP_PTR; 1038 break; 1039 case PCIM_HDRTYPE_CARDBUS: 1040 ptr = PCIR_CAP_PTR_2; 1041 break; 1042 default: 1043 return (0); 1044 } 1045 1046 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1047 while (ptr != 0 && ptr != 0xff) { 1048 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1049 if (cap == id) 1050 return (ptr); 1051 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1052 } 1053 return (0); 1054 } 1055 1056 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1057 uint16_t 1058 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1059 { 1060 uint32_t ecap; 1061 uint16_t ptr; 1062 1063 ptr = PCIR_EXTCAP; 1064 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1065 if (ecap == 0xffffffff || ecap == 0) 1066 return (0); 1067 for (;;) { 1068 if (PCI_EXTCAP_ID(ecap) == id) 1069 return (ptr); 1070 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1071 if (ptr == 0) 1072 break; 1073 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1074 } 1075 return (0); 1076 } 1077