1*d0b3c59bSPatrick Mooney /*- 2*d0b3c59bSPatrick Mooney * Copyright (c) 1991 The Regents of the University of California. 3*d0b3c59bSPatrick Mooney * All rights reserved. 4*d0b3c59bSPatrick Mooney * 5*d0b3c59bSPatrick Mooney * Redistribution and use in source and binary forms, with or without 6*d0b3c59bSPatrick Mooney * modification, are permitted provided that the following conditions 7*d0b3c59bSPatrick Mooney * are met: 8*d0b3c59bSPatrick Mooney * 1. Redistributions of source code must retain the above copyright 9*d0b3c59bSPatrick Mooney * notice, this list of conditions and the following disclaimer. 10*d0b3c59bSPatrick Mooney * 2. Redistributions in binary form must reproduce the above copyright 11*d0b3c59bSPatrick Mooney * notice, this list of conditions and the following disclaimer in the 12*d0b3c59bSPatrick Mooney * documentation and/or other materials provided with the distribution. 13*d0b3c59bSPatrick Mooney * 4. Neither the name of the University nor the names of its contributors 14*d0b3c59bSPatrick Mooney * may be used to endorse or promote products derived from this software 15*d0b3c59bSPatrick Mooney * without specific prior written permission. 16*d0b3c59bSPatrick Mooney * 17*d0b3c59bSPatrick Mooney * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18*d0b3c59bSPatrick Mooney * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19*d0b3c59bSPatrick Mooney * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20*d0b3c59bSPatrick Mooney * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21*d0b3c59bSPatrick Mooney * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22*d0b3c59bSPatrick Mooney * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23*d0b3c59bSPatrick Mooney * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24*d0b3c59bSPatrick Mooney * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25*d0b3c59bSPatrick Mooney * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26*d0b3c59bSPatrick Mooney * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27*d0b3c59bSPatrick Mooney * SUCH DAMAGE. 28*d0b3c59bSPatrick Mooney * 29*d0b3c59bSPatrick Mooney * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30*d0b3c59bSPatrick Mooney * $FreeBSD: head/sys/dev/ic/ns16550.h 257170 2013-10-26 17:24:59Z zbb $ 31*d0b3c59bSPatrick Mooney */ 32*d0b3c59bSPatrick Mooney 33*d0b3c59bSPatrick Mooney /* 34*d0b3c59bSPatrick Mooney * NS8250... UART registers. 35*d0b3c59bSPatrick Mooney */ 36*d0b3c59bSPatrick Mooney 37*d0b3c59bSPatrick Mooney /* 8250 registers #[0-6]. */ 38*d0b3c59bSPatrick Mooney 39*d0b3c59bSPatrick Mooney #define com_data 0 /* data register (R/W) */ 40*d0b3c59bSPatrick Mooney #define REG_DATA com_data 41*d0b3c59bSPatrick Mooney 42*d0b3c59bSPatrick Mooney #define com_ier 1 /* interrupt enable register (W) */ 43*d0b3c59bSPatrick Mooney #define REG_IER com_ier 44*d0b3c59bSPatrick Mooney #define IER_ERXRDY 0x1 45*d0b3c59bSPatrick Mooney #define IER_ETXRDY 0x2 46*d0b3c59bSPatrick Mooney #define IER_ERLS 0x4 47*d0b3c59bSPatrick Mooney #define IER_EMSC 0x8 48*d0b3c59bSPatrick Mooney 49*d0b3c59bSPatrick Mooney #define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC" 50*d0b3c59bSPatrick Mooney 51*d0b3c59bSPatrick Mooney #define com_iir 2 /* interrupt identification register (R) */ 52*d0b3c59bSPatrick Mooney #define REG_IIR com_iir 53*d0b3c59bSPatrick Mooney #define IIR_IMASK 0xf 54*d0b3c59bSPatrick Mooney #define IIR_RXTOUT 0xc 55*d0b3c59bSPatrick Mooney #define IIR_BUSY 0x7 56*d0b3c59bSPatrick Mooney #define IIR_RLS 0x6 57*d0b3c59bSPatrick Mooney #define IIR_RXRDY 0x4 58*d0b3c59bSPatrick Mooney #define IIR_TXRDY 0x2 59*d0b3c59bSPatrick Mooney #define IIR_NOPEND 0x1 60*d0b3c59bSPatrick Mooney #define IIR_MLSC 0x0 61*d0b3c59bSPatrick Mooney #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 62*d0b3c59bSPatrick Mooney 63*d0b3c59bSPatrick Mooney #define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 64*d0b3c59bSPatrick Mooney 65*d0b3c59bSPatrick Mooney #define com_lcr 3 /* line control register (R/W) */ 66*d0b3c59bSPatrick Mooney #define com_cfcr com_lcr /* character format control register (R/W) */ 67*d0b3c59bSPatrick Mooney #define REG_LCR com_lcr 68*d0b3c59bSPatrick Mooney #define LCR_DLAB 0x80 69*d0b3c59bSPatrick Mooney #define CFCR_DLAB LCR_DLAB 70*d0b3c59bSPatrick Mooney #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 71*d0b3c59bSPatrick Mooney #define CFCR_EFR_ENABLE LCR_EFR_ENABLE 72*d0b3c59bSPatrick Mooney #define LCR_SBREAK 0x40 73*d0b3c59bSPatrick Mooney #define CFCR_SBREAK LCR_SBREAK 74*d0b3c59bSPatrick Mooney #define LCR_PZERO 0x30 75*d0b3c59bSPatrick Mooney #define CFCR_PZERO LCR_PZERO 76*d0b3c59bSPatrick Mooney #define LCR_PONE 0x20 77*d0b3c59bSPatrick Mooney #define CFCR_PONE LCR_PONE 78*d0b3c59bSPatrick Mooney #define LCR_PEVEN 0x10 79*d0b3c59bSPatrick Mooney #define CFCR_PEVEN LCR_PEVEN 80*d0b3c59bSPatrick Mooney #define LCR_PODD 0x00 81*d0b3c59bSPatrick Mooney #define CFCR_PODD LCR_PODD 82*d0b3c59bSPatrick Mooney #define LCR_PENAB 0x08 83*d0b3c59bSPatrick Mooney #define CFCR_PENAB LCR_PENAB 84*d0b3c59bSPatrick Mooney #define LCR_STOPB 0x04 85*d0b3c59bSPatrick Mooney #define CFCR_STOPB LCR_STOPB 86*d0b3c59bSPatrick Mooney #define LCR_8BITS 0x03 87*d0b3c59bSPatrick Mooney #define CFCR_8BITS LCR_8BITS 88*d0b3c59bSPatrick Mooney #define LCR_7BITS 0x02 89*d0b3c59bSPatrick Mooney #define CFCR_7BITS LCR_7BITS 90*d0b3c59bSPatrick Mooney #define LCR_6BITS 0x01 91*d0b3c59bSPatrick Mooney #define CFCR_6BITS LCR_6BITS 92*d0b3c59bSPatrick Mooney #define LCR_5BITS 0x00 93*d0b3c59bSPatrick Mooney #define CFCR_5BITS LCR_5BITS 94*d0b3c59bSPatrick Mooney 95*d0b3c59bSPatrick Mooney #define com_mcr 4 /* modem control register (R/W) */ 96*d0b3c59bSPatrick Mooney #define REG_MCR com_mcr 97*d0b3c59bSPatrick Mooney #define MCR_PRESCALE 0x80 /* only available on 16650 up */ 98*d0b3c59bSPatrick Mooney #define MCR_LOOPBACK 0x10 99*d0b3c59bSPatrick Mooney #define MCR_IE 0x08 100*d0b3c59bSPatrick Mooney #define MCR_IENABLE MCR_IE 101*d0b3c59bSPatrick Mooney #define MCR_DRS 0x04 102*d0b3c59bSPatrick Mooney #define MCR_RTS 0x02 103*d0b3c59bSPatrick Mooney #define MCR_DTR 0x01 104*d0b3c59bSPatrick Mooney 105*d0b3c59bSPatrick Mooney #define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 106*d0b3c59bSPatrick Mooney 107*d0b3c59bSPatrick Mooney #define com_lsr 5 /* line status register (R/W) */ 108*d0b3c59bSPatrick Mooney #define REG_LSR com_lsr 109*d0b3c59bSPatrick Mooney #define LSR_RCV_FIFO 0x80 110*d0b3c59bSPatrick Mooney #define LSR_TEMT 0x40 111*d0b3c59bSPatrick Mooney #define LSR_TSRE LSR_TEMT 112*d0b3c59bSPatrick Mooney #define LSR_THRE 0x20 113*d0b3c59bSPatrick Mooney #define LSR_TXRDY LSR_THRE 114*d0b3c59bSPatrick Mooney #define LSR_BI 0x10 115*d0b3c59bSPatrick Mooney #define LSR_FE 0x08 116*d0b3c59bSPatrick Mooney #define LSR_PE 0x04 117*d0b3c59bSPatrick Mooney #define LSR_OE 0x02 118*d0b3c59bSPatrick Mooney #define LSR_RXRDY 0x01 119*d0b3c59bSPatrick Mooney #define LSR_RCV_MASK 0x1f 120*d0b3c59bSPatrick Mooney 121*d0b3c59bSPatrick Mooney #define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 122*d0b3c59bSPatrick Mooney 123*d0b3c59bSPatrick Mooney #define com_msr 6 /* modem status register (R/W) */ 124*d0b3c59bSPatrick Mooney #define REG_MSR com_msr 125*d0b3c59bSPatrick Mooney #define MSR_DCD 0x80 126*d0b3c59bSPatrick Mooney #define MSR_RI 0x40 127*d0b3c59bSPatrick Mooney #define MSR_DSR 0x20 128*d0b3c59bSPatrick Mooney #define MSR_CTS 0x10 129*d0b3c59bSPatrick Mooney #define MSR_DDCD 0x08 130*d0b3c59bSPatrick Mooney #define MSR_TERI 0x04 131*d0b3c59bSPatrick Mooney #define MSR_DDSR 0x02 132*d0b3c59bSPatrick Mooney #define MSR_DCTS 0x01 133*d0b3c59bSPatrick Mooney 134*d0b3c59bSPatrick Mooney #define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 135*d0b3c59bSPatrick Mooney 136*d0b3c59bSPatrick Mooney /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 137*d0b3c59bSPatrick Mooney #define com_dll 0 /* divisor latch low (R/W) */ 138*d0b3c59bSPatrick Mooney #define com_dlbl com_dll 139*d0b3c59bSPatrick Mooney #define com_dlm 1 /* divisor latch high (R/W) */ 140*d0b3c59bSPatrick Mooney #define com_dlbh com_dlm 141*d0b3c59bSPatrick Mooney #define REG_DLL com_dll 142*d0b3c59bSPatrick Mooney #define REG_DLH com_dlm 143*d0b3c59bSPatrick Mooney 144*d0b3c59bSPatrick Mooney /* 16450 register #7. Not multiplexed. */ 145*d0b3c59bSPatrick Mooney #define com_scr 7 /* scratch register (R/W) */ 146*d0b3c59bSPatrick Mooney 147*d0b3c59bSPatrick Mooney /* 16550 register #2. Not multiplexed. */ 148*d0b3c59bSPatrick Mooney #define com_fcr 2 /* FIFO control register (W) */ 149*d0b3c59bSPatrick Mooney #define com_fifo com_fcr 150*d0b3c59bSPatrick Mooney #define REG_FCR com_fcr 151*d0b3c59bSPatrick Mooney #define FCR_ENABLE 0x01 152*d0b3c59bSPatrick Mooney #define FIFO_ENABLE FCR_ENABLE 153*d0b3c59bSPatrick Mooney #define FCR_RCV_RST 0x02 154*d0b3c59bSPatrick Mooney #define FIFO_RCV_RST FCR_RCV_RST 155*d0b3c59bSPatrick Mooney #define FCR_XMT_RST 0x04 156*d0b3c59bSPatrick Mooney #define FIFO_XMT_RST FCR_XMT_RST 157*d0b3c59bSPatrick Mooney #define FCR_DMA 0x08 158*d0b3c59bSPatrick Mooney #define FIFO_DMA_MODE FCR_DMA 159*d0b3c59bSPatrick Mooney #define FCR_RX_LOW 0x00 160*d0b3c59bSPatrick Mooney #define FIFO_RX_LOW FCR_RX_LOW 161*d0b3c59bSPatrick Mooney #define FCR_RX_MEDL 0x40 162*d0b3c59bSPatrick Mooney #define FIFO_RX_MEDL FCR_RX_MEDL 163*d0b3c59bSPatrick Mooney #define FCR_RX_MEDH 0x80 164*d0b3c59bSPatrick Mooney #define FIFO_RX_MEDH FCR_RX_MEDH 165*d0b3c59bSPatrick Mooney #define FCR_RX_HIGH 0xc0 166*d0b3c59bSPatrick Mooney #define FIFO_RX_HIGH FCR_RX_HIGH 167*d0b3c59bSPatrick Mooney 168*d0b3c59bSPatrick Mooney #define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 169*d0b3c59bSPatrick Mooney 170*d0b3c59bSPatrick Mooney /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 171*d0b3c59bSPatrick Mooney 172*d0b3c59bSPatrick Mooney #define com_efr 2 /* enhanced features register (R/W) */ 173*d0b3c59bSPatrick Mooney #define REG_EFR com_efr 174*d0b3c59bSPatrick Mooney #define EFR_CTS 0x80 175*d0b3c59bSPatrick Mooney #define EFR_AUTOCTS EFR_CTS 176*d0b3c59bSPatrick Mooney #define EFR_RTS 0x40 177*d0b3c59bSPatrick Mooney #define EFR_AUTORTS EFR_RTS 178*d0b3c59bSPatrick Mooney #define EFR_EFE 0x10 /* enhanced functions enable */ 179*d0b3c59bSPatrick Mooney 180*d0b3c59bSPatrick Mooney #define com_xon1 4 /* XON 1 character (R/W) */ 181*d0b3c59bSPatrick Mooney #define com_xon2 5 /* XON 2 character (R/W) */ 182*d0b3c59bSPatrick Mooney #define com_xoff1 6 /* XOFF 1 character (R/W) */ 183*d0b3c59bSPatrick Mooney #define com_xoff2 7 /* XOFF 2 character (R/W) */ 184*d0b3c59bSPatrick Mooney 185*d0b3c59bSPatrick Mooney #define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */ 186*d0b3c59bSPatrick Mooney #define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ 187*d0b3c59bSPatrick Mooney #define REG_USR com_usr 188*d0b3c59bSPatrick Mooney #define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */ 189*d0b3c59bSPatrick Mooney #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ 190*d0b3c59bSPatrick Mooney 191*d0b3c59bSPatrick Mooney /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 192*d0b3c59bSPatrick Mooney #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 193*d0b3c59bSPatrick Mooney 194*d0b3c59bSPatrick Mooney /* 16950 register #3. R/W access enabled by ACR[7]. */ 195*d0b3c59bSPatrick Mooney #define com_rfl 3 /* receiver fifo level (R) */ 196*d0b3c59bSPatrick Mooney 197*d0b3c59bSPatrick Mooney /* 198*d0b3c59bSPatrick Mooney * 16950 register #4. Access enabled by ACR[7]. Also requires 199*d0b3c59bSPatrick Mooney * !LCR_EFR_ENABLE. 200*d0b3c59bSPatrick Mooney */ 201*d0b3c59bSPatrick Mooney #define com_tfl 4 /* transmitter fifo level (R) */ 202*d0b3c59bSPatrick Mooney 203*d0b3c59bSPatrick Mooney /* 204*d0b3c59bSPatrick Mooney * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 205*d0b3c59bSPatrick Mooney * requires ACR[6]. 206*d0b3c59bSPatrick Mooney */ 207*d0b3c59bSPatrick Mooney #define com_icr 5 /* index control register (R/W) */ 208*d0b3c59bSPatrick Mooney 209*d0b3c59bSPatrick Mooney /* 210*d0b3c59bSPatrick Mooney * 16950 register #7. It is the same as com_scr except it has a different 211*d0b3c59bSPatrick Mooney * abbreviation in the manufacturer's data sheet and it also serves as an 212*d0b3c59bSPatrick Mooney * index into the Indexed Control register set. 213*d0b3c59bSPatrick Mooney */ 214*d0b3c59bSPatrick Mooney #define com_spr com_scr /* scratch pad (and index) register (R/W) */ 215*d0b3c59bSPatrick Mooney #define REG_SPR com_scr 216*d0b3c59bSPatrick Mooney 217*d0b3c59bSPatrick Mooney /* 218*d0b3c59bSPatrick Mooney * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 219*d0b3c59bSPatrick Mooney * data in ICR (if ICR is accessible). 220*d0b3c59bSPatrick Mooney */ 221*d0b3c59bSPatrick Mooney 222*d0b3c59bSPatrick Mooney #define com_acr 0 /* additional control register (R/W) */ 223*d0b3c59bSPatrick Mooney #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 224*d0b3c59bSPatrick Mooney #define ACR_ICRE 0x40 /* ICR enable */ 225*d0b3c59bSPatrick Mooney #define ACR_TLE 0x20 /* TTL/RTL enable */ 226*d0b3c59bSPatrick Mooney 227*d0b3c59bSPatrick Mooney #define com_cpr 1 /* clock prescaler register (R/W) */ 228*d0b3c59bSPatrick Mooney #define com_tcr 2 /* times clock register (R/W) */ 229*d0b3c59bSPatrick Mooney #define com_ttl 4 /* transmitter trigger level (R/W) */ 230*d0b3c59bSPatrick Mooney #define com_rtl 5 /* receiver trigger level (R/W) */ 231*d0b3c59bSPatrick Mooney /* ... */ 232*d0b3c59bSPatrick Mooney 233*d0b3c59bSPatrick Mooney /* Hardware extension mode register for RSB-2000/3000. */ 234*d0b3c59bSPatrick Mooney #define com_emr com_msr 235*d0b3c59bSPatrick Mooney #define EMR_EXBUFF 0x04 236*d0b3c59bSPatrick Mooney #define EMR_CTSFLW 0x08 237*d0b3c59bSPatrick Mooney #define EMR_DSRFLW 0x10 238*d0b3c59bSPatrick Mooney #define EMR_RTSFLW 0x20 239*d0b3c59bSPatrick Mooney #define EMR_DTRFLW 0x40 240*d0b3c59bSPatrick Mooney #define EMR_EFMODE 0x80 241