1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2022 Oxide Computer Company 14 */ 15 16 /* 17 * This tries to make sure that if we had invalid state somehow, we'd properly 18 * end up detecting an error. Note, for these we try to do include the most bare 19 * minimum style zen_umc_t to minimize the size (at least in this one file for a 20 * change). Note, testing hole decoding errors has been performed in 21 * zen_umc_test_hole.c. 22 */ 23 24 #include "zen_umc_test.h" 25 26 /* 27 * This first structure is used to test: 28 * o Being outside TOM2 29 * o Being in the 1 TiB reserved region 30 * o Not being covered by a valid DF rule 31 * o Several invalid interleave combinations 32 * o Unsupported interleave rule 33 * o Bad Remap set counts 34 */ 35 static const zen_umc_t zen_umc_bad_df = { 36 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 37 .umc_tom2 = 2ULL * 1024ULL * 1024ULL * 1024ULL * 1024ULL, 38 .umc_df_rev = DF_REV_3, 39 .umc_decomp = { 40 .dfd_sock_mask = 0x01, 41 .dfd_die_mask = 0x00, 42 .dfd_node_mask = 0x20, 43 .dfd_comp_mask = 0x1f, 44 .dfd_sock_shift = 0, 45 .dfd_die_shift = 0, 46 .dfd_node_shift = 5, 47 .dfd_comp_shift = 0 48 }, 49 .umc_ndfs = 1, 50 .umc_dfs = { { 51 .zud_dfno = 0, 52 .zud_dram_nrules = 10, 53 .zud_rules = { { 54 .ddr_flags = DF_DRAM_F_VALID, 55 .ddr_base = 0, 56 .ddr_limit = 1ULL * 1024ULL * 1024ULL, 57 .ddr_dest_fabid = 0, 58 .ddr_sock_ileave_bits = 1, 59 .ddr_die_ileave_bits = 0, 60 .ddr_addr_start = 9, 61 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD4_2CH 62 }, { 63 .ddr_flags = DF_DRAM_F_VALID, 64 .ddr_base = 2ULL * 1024ULL * 1024ULL, 65 .ddr_limit = 3ULL * 1024ULL * 1024ULL, 66 .ddr_dest_fabid = 0, 67 .ddr_sock_ileave_bits = 0, 68 .ddr_die_ileave_bits = 2, 69 .ddr_addr_start = 9, 70 .ddr_chan_ileave = DF_CHAN_ILEAVE_COD1_8CH 71 }, { 72 .ddr_flags = DF_DRAM_F_VALID, 73 .ddr_base = 4ULL * 1024ULL * 1024ULL, 74 .ddr_limit = 5ULL * 1024ULL * 1024ULL, 75 .ddr_dest_fabid = 0, 76 .ddr_sock_ileave_bits = 0, 77 .ddr_die_ileave_bits = 2, 78 .ddr_addr_start = 9, 79 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 80 }, { 81 .ddr_flags = DF_DRAM_F_VALID, 82 .ddr_base = 6ULL * 1024ULL * 1024ULL, 83 .ddr_limit = 7ULL * 1024ULL * 1024ULL, 84 .ddr_dest_fabid = 0, 85 .ddr_sock_ileave_bits = 2, 86 .ddr_die_ileave_bits = 0, 87 .ddr_addr_start = 9, 88 .ddr_chan_ileave = DF_CHAN_ILEAVE_6CH 89 }, { 90 .ddr_flags = DF_DRAM_F_VALID, 91 .ddr_base = 8ULL * 1024ULL * 1024ULL, 92 .ddr_limit = 9ULL * 1024ULL * 1024ULL, 93 .ddr_dest_fabid = 0, 94 .ddr_sock_ileave_bits = 2, 95 .ddr_die_ileave_bits = 0, 96 .ddr_addr_start = 9, 97 .ddr_chan_ileave = INT32_MAX 98 }, { 99 .ddr_flags = DF_DRAM_F_VALID, 100 .ddr_base = 10ULL * 1024ULL * 1024ULL, 101 .ddr_limit = 11ULL * 1024ULL * 1024ULL, 102 .ddr_dest_fabid = 0, 103 .ddr_sock_ileave_bits = 1, 104 .ddr_die_ileave_bits = 1, 105 .ddr_addr_start = 9, 106 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS2_5CH 107 }, { 108 .ddr_flags = DF_DRAM_F_VALID, 109 .ddr_base = 12ULL * 1024ULL * 1024ULL, 110 .ddr_limit = 13ULL * 1024ULL * 1024ULL, 111 .ddr_dest_fabid = 0, 112 .ddr_sock_ileave_bits = 0, 113 .ddr_die_ileave_bits = 2, 114 .ddr_addr_start = 9, 115 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 116 }, { 117 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 118 DF_DRAM_F_REMAP_SOCK, 119 .ddr_base = 14ULL * 1024ULL * 1024ULL, 120 .ddr_limit = 15ULL * 1024ULL * 1024ULL, 121 .ddr_dest_fabid = 0, 122 .ddr_sock_ileave_bits = 0, 123 .ddr_die_ileave_bits = 0, 124 .ddr_addr_start = 9, 125 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 126 }, { 127 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 128 .ddr_base = 16ULL * 1024ULL * 1024ULL, 129 .ddr_limit = 17ULL * 1024ULL * 1024ULL, 130 .ddr_dest_fabid = 0, 131 .ddr_sock_ileave_bits = 0, 132 .ddr_die_ileave_bits = 0, 133 .ddr_addr_start = 9, 134 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH 135 }, { 136 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 137 .ddr_base = 18ULL * 1024ULL * 1024ULL, 138 .ddr_limit = 19ULL * 1024ULL * 1024ULL, 139 .ddr_dest_fabid = 0, 140 .ddr_sock_ileave_bits = 0, 141 .ddr_die_ileave_bits = 0, 142 .ddr_addr_start = 9, 143 .ddr_chan_ileave = DF_CHAN_ILEAVE_4CH, 144 .ddr_remap_ent = 3 145 } }, 146 } } 147 }; 148 149 /* 150 * This UMC contains a weird relationship between its rule, TOM and the actual 151 * DRAM hole base. This creates an inconsistency that should underflow. This is 152 * honestly a bit odd to actually try to find in the wild. The fact that TOM is 153 * much greater than the hole base is key. This requires DFv4 for subtracting 154 * the base. 155 */ 156 static const zen_umc_t zen_umc_hole_underflow = { 157 .umc_tom = 3ULL * 1024ULL * 1024ULL * 1024ULL, 158 .umc_tom2 = 2ULL * 1024ULL * 1024ULL * 1024ULL * 1024ULL, 159 .umc_df_rev = DF_REV_4, 160 .umc_decomp = { 161 .dfd_sock_mask = 0x01, 162 .dfd_die_mask = 0x00, 163 .dfd_node_mask = 0x20, 164 .dfd_comp_mask = 0x1f, 165 .dfd_sock_shift = 0, 166 .dfd_die_shift = 0, 167 .dfd_node_shift = 5, 168 .dfd_comp_shift = 0 169 }, 170 .umc_ndfs = 1, 171 .umc_dfs = { { 172 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 173 .zud_dfno = 0, 174 .zud_dram_nrules = 2, 175 .zud_hole_base = 0x0, 176 .zud_rules = { { 177 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 178 .ddr_base = 1ULL * 1024ULL * 1024ULL, 179 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 180 .ddr_dest_fabid = 0, 181 .ddr_sock_ileave_bits = 0, 182 .ddr_die_ileave_bits = 0, 183 .ddr_addr_start = 9, 184 .ddr_chan_ileave = DF_CHAN_ILEAVE_NPS4_2CH 185 } } 186 } }, 187 }; 188 189 /* 190 * This is a variant of the previous one, but it takes place when normalization 191 * occurs. The biggest gotcha there is that for DFv3 the base isn't subtracted 192 * initially for interleaving, only when normalizing. 193 */ 194 static const zen_umc_t zen_umc_norm_underflow = { 195 .umc_tom = 3ULL * 1024ULL * 1024ULL * 1024ULL, 196 .umc_tom2 = 16ULL * 1024ULL * 1024ULL * 1024ULL, 197 .umc_df_rev = DF_REV_3, 198 .umc_decomp = { 199 .dfd_sock_mask = 0x01, 200 .dfd_die_mask = 0x00, 201 .dfd_node_mask = 0x20, 202 .dfd_comp_mask = 0x1f, 203 .dfd_sock_shift = 0, 204 .dfd_die_shift = 0, 205 .dfd_node_shift = 5, 206 .dfd_comp_shift = 0 207 }, 208 .umc_ndfs = 1, 209 .umc_dfs = { { 210 .zud_flags = ZEN_UMC_DF_F_HOLE_VALID, 211 .zud_dfno = 0, 212 .zud_dram_nrules = 2, 213 .zud_nchan = 1, 214 .zud_hole_base = 0xc0000000, 215 .zud_rules = { { 216 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 217 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 218 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 219 .ddr_dest_fabid = 0, 220 .ddr_sock_ileave_bits = 0, 221 .ddr_die_ileave_bits = 0, 222 .ddr_addr_start = 9, 223 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 224 } }, 225 .zud_chan = { { 226 .chan_flags = UMC_CHAN_F_ECC_EN, 227 .chan_fabid = 0, 228 .chan_instid = 0, 229 .chan_logid = 0, 230 .chan_nrules = 1, 231 .chan_rules = { { 232 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_HOLE, 233 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 234 .ddr_limit = 8ULL * 1024ULL * 1024ULL * 1024ULL, 235 .ddr_dest_fabid = 0, 236 .ddr_sock_ileave_bits = 0, 237 .ddr_die_ileave_bits = 0, 238 .ddr_addr_start = 9, 239 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 240 } }, 241 .chan_dimms = { { 242 .ud_flags = UMC_DIMM_F_VALID, 243 .ud_width = UMC_DIMM_W_X4, 244 .ud_type = UMC_DIMM_T_DDR4, 245 .ud_kind = UMC_DIMM_K_RDIMM, 246 .ud_dimmno = 0, 247 .ud_cs = { { 248 .ucs_base = { 249 .udb_base = 0, 250 .udb_valid = B_TRUE 251 }, 252 .ucs_base_mask = 0x3ffffffff, 253 .ucs_nbanks = 0x4, 254 .ucs_ncol = 0xa, 255 .ucs_nrow_lo = 0x11, 256 .ucs_nbank_groups = 0x2, 257 .ucs_row_hi_bit = 0x18, 258 .ucs_row_low_bit = 0x11, 259 .ucs_bank_bits = { 0xf, 0x10, 0xd, 260 0xe }, 261 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 262 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 263 } } 264 } }, 265 } } 266 } } 267 }; 268 269 /* 270 * This DF is designed to capture bad remap entry pointers and remap entries 271 * with bad components. 272 */ 273 static const zen_umc_t zen_umc_remap_errs = { 274 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 275 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 276 .umc_df_rev = DF_REV_3, 277 .umc_decomp = { 278 .dfd_sock_mask = 0x01, 279 .dfd_die_mask = 0x00, 280 .dfd_node_mask = 0x20, 281 .dfd_comp_mask = 0x1f, 282 .dfd_sock_shift = 0, 283 .dfd_die_shift = 0, 284 .dfd_node_shift = 5, 285 .dfd_comp_shift = 0 286 }, 287 .umc_ndfs = 1, 288 .umc_dfs = { { 289 .zud_dfno = 0, 290 .zud_dram_nrules = 2, 291 .zud_nchan = 4, 292 .zud_cs_nremap = 2, 293 .zud_hole_base = 0, 294 .zud_rules = { { 295 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN | 296 DF_DRAM_F_REMAP_SOCK, 297 .ddr_base = 0, 298 .ddr_limit = 32ULL * 1024ULL * 1024ULL * 1024ULL, 299 .ddr_dest_fabid = 0x1f, 300 .ddr_sock_ileave_bits = 0, 301 .ddr_die_ileave_bits = 0, 302 .ddr_addr_start = 12, 303 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH, 304 }, { 305 .ddr_flags = DF_DRAM_F_VALID | DF_DRAM_F_REMAP_EN, 306 .ddr_base = 32ULL * 1024ULL * 1024ULL * 1024ULL, 307 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 1024ULL, 308 .ddr_dest_fabid = 0, 309 .ddr_sock_ileave_bits = 0, 310 .ddr_die_ileave_bits = 0, 311 .ddr_addr_start = 12, 312 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH, 313 .ddr_remap_ent = 1 314 } }, 315 .zud_remap = { { 316 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 317 .csr_remaps = { 0x0 } 318 }, { 319 .csr_nremaps = ZEN_UMC_MAX_REMAP_ENTS, 320 .csr_remaps = { 0x21 } 321 } } 322 } } 323 }; 324 325 /* 326 * This umc is used to cover the cases where: 327 * o There is no match to the fabric ID 328 * o The UMC in question doesn't have rules for our PA 329 * o Normalization underflow 330 * o Failure to match a chip-select 331 */ 332 static const zen_umc_t zen_umc_fab_errs = { 333 .umc_tom = 4ULL * 1024ULL * 1024ULL * 1024ULL, 334 .umc_tom2 = 64ULL * 1024ULL * 1024ULL * 1024ULL, 335 .umc_df_rev = DF_REV_3, 336 .umc_decomp = { 337 .dfd_sock_mask = 0x01, 338 .dfd_die_mask = 0x00, 339 .dfd_node_mask = 0x20, 340 .dfd_comp_mask = 0x1f, 341 .dfd_sock_shift = 0, 342 .dfd_die_shift = 0, 343 .dfd_node_shift = 5, 344 .dfd_comp_shift = 0 345 }, 346 .umc_ndfs = 1, 347 .umc_dfs = { { 348 .zud_dfno = 0, 349 .zud_dram_nrules = 4, 350 .zud_nchan = 2, 351 .zud_cs_nremap = 0, 352 .zud_hole_base = 0, 353 .zud_rules = { { 354 .ddr_flags = DF_DRAM_F_VALID, 355 .ddr_base = 0, 356 .ddr_limit = 1ULL * 1024ULL * 1024ULL * 1024ULL, 357 .ddr_dest_fabid = 0x22, 358 .ddr_sock_ileave_bits = 0, 359 .ddr_die_ileave_bits = 0, 360 .ddr_addr_start = 9, 361 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 362 }, { 363 .ddr_flags = DF_DRAM_F_VALID, 364 .ddr_base = 2ULL * 1024ULL * 1024ULL * 1024ULL, 365 .ddr_limit = 3ULL * 1024ULL * 1024ULL * 1024ULL, 366 .ddr_dest_fabid = 0, 367 .ddr_sock_ileave_bits = 0, 368 .ddr_die_ileave_bits = 0, 369 .ddr_addr_start = 9, 370 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 371 }, { 372 .ddr_flags = DF_DRAM_F_VALID, 373 .ddr_base = 4ULL * 1024ULL * 1024ULL * 1024ULL, 374 .ddr_limit = 5ULL * 1024ULL * 1024ULL * 1024ULL, 375 .ddr_dest_fabid = 0x1, 376 .ddr_sock_ileave_bits = 0, 377 .ddr_die_ileave_bits = 0, 378 .ddr_addr_start = 9, 379 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 380 } }, 381 .zud_chan = { { 382 .chan_flags = UMC_CHAN_F_ECC_EN, 383 .chan_fabid = 0, 384 .chan_instid = 0, 385 .chan_logid = 0, 386 .chan_nrules = 1, 387 .chan_rules = { { 388 .ddr_flags = DF_DRAM_F_VALID, 389 .ddr_base = 32ULL * 1024ULL * 1024ULL * 390 1024ULL, 391 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 392 1024ULL, 393 .ddr_dest_fabid = 0, 394 .ddr_sock_ileave_bits = 0, 395 .ddr_die_ileave_bits = 0, 396 .ddr_addr_start = 9, 397 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 398 } } 399 }, { 400 .chan_flags = UMC_CHAN_F_ECC_EN, 401 .chan_fabid = 1, 402 .chan_instid = 1, 403 .chan_logid = 1, 404 .chan_nrules = 1, 405 .chan_rules = { { 406 .ddr_flags = DF_DRAM_F_VALID, 407 .ddr_base = 0, 408 .ddr_limit = 64ULL * 1024ULL * 1024ULL * 409 1024ULL, 410 .ddr_dest_fabid = 0, 411 .ddr_sock_ileave_bits = 0, 412 .ddr_die_ileave_bits = 0, 413 .ddr_addr_start = 9, 414 .ddr_chan_ileave = DF_CHAN_ILEAVE_1CH 415 } }, 416 .chan_dimms = { { 417 .ud_flags = UMC_DIMM_F_VALID, 418 .ud_width = UMC_DIMM_W_X4, 419 .ud_type = UMC_DIMM_T_DDR4, 420 .ud_kind = UMC_DIMM_K_RDIMM, 421 .ud_dimmno = 0, 422 .ud_cs = { { 423 .ucs_base = { 424 .udb_base = 0x400000000, 425 .udb_valid = B_TRUE 426 }, 427 .ucs_base_mask = 0x3ffffffff, 428 .ucs_nbanks = 0x4, 429 .ucs_ncol = 0xa, 430 .ucs_nrow_lo = 0x11, 431 .ucs_nbank_groups = 0x2, 432 .ucs_row_hi_bit = 0x18, 433 .ucs_row_low_bit = 0x11, 434 .ucs_bank_bits = { 0xf, 0x10, 0xd, 435 0xe }, 436 .ucs_col_bits = { 0x3, 0x4, 0x5, 0x6, 437 0x7, 0x8, 0x9, 0xa, 0xb, 0xc } 438 } } 439 } }, 440 } } 441 } } 442 }; 443 444 const umc_decode_test_t zen_umc_test_errors[] = { { 445 .udt_desc = "Memory beyond TOM2 doesn't decode (0)", 446 .udt_umc = &zen_umc_bad_df, 447 .udt_pa = 0x20000000000, 448 .udt_pass = B_FALSE, 449 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 450 }, { 451 .udt_desc = "Memory beyond TOM2 doesn't decode (1)", 452 .udt_umc = &zen_umc_bad_df, 453 .udt_pa = 0x2123456789a, 454 .udt_pass = B_FALSE, 455 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 456 }, { 457 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (0)", 458 .udt_umc = &zen_umc_bad_df, 459 .udt_pa = 0xfd00000000, 460 .udt_pass = B_FALSE, 461 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 462 }, { 463 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (1)", 464 .udt_umc = &zen_umc_bad_df, 465 .udt_pa = 0xfd00000001, 466 .udt_pass = B_FALSE, 467 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 468 }, { 469 .udt_desc = "Memory in 1 TiB-12 GiB hole doesn't decode (2)", 470 .udt_umc = &zen_umc_bad_df, 471 .udt_pa = 0xffffffffff, 472 .udt_pass = B_FALSE, 473 .udt_fail = ZEN_UMC_DECODE_F_OUTSIDE_DRAM 474 }, { 475 .udt_desc = "No valid DF rule (0)", 476 .udt_umc = &zen_umc_bad_df, 477 .udt_pa = 0x1ffffffffff, 478 .udt_pass = B_FALSE, 479 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 480 }, { 481 .udt_desc = "No valid DF rule (1)", 482 .udt_umc = &zen_umc_bad_df, 483 .udt_pa = 0xfcffffffff, 484 .udt_pass = B_FALSE, 485 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 486 }, { 487 .udt_desc = "No valid DF rule (2)", 488 .udt_umc = &zen_umc_bad_df, 489 .udt_pa = 0x123456, 490 .udt_pass = B_FALSE, 491 .udt_fail = ZEN_UMC_DECODE_F_NO_DF_RULE 492 }, { 493 .udt_desc = "Bad COD hash interleave - socket", 494 .udt_umc = &zen_umc_bad_df, 495 .udt_pa = 0x0, 496 .udt_pass = B_FALSE, 497 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 498 }, { 499 .udt_desc = "Bad COD hash interleave - die", 500 .udt_umc = &zen_umc_bad_df, 501 .udt_pa = 0x200000, 502 .udt_pass = B_FALSE, 503 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 504 }, { 505 .udt_desc = "Bad COD 6ch hash interleave - socket", 506 .udt_umc = &zen_umc_bad_df, 507 .udt_pa = 0x400000, 508 .udt_pass = B_FALSE, 509 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 510 }, { 511 .udt_desc = "Bad COD 6ch hash interleave - die", 512 .udt_umc = &zen_umc_bad_df, 513 .udt_pa = 0x600000, 514 .udt_pass = B_FALSE, 515 .udt_fail = ZEN_UMC_DECODE_F_COD_BAD_ILEAVE 516 }, { 517 .udt_desc = "Unknown interleave", 518 .udt_umc = &zen_umc_bad_df, 519 .udt_pa = 0x800000, 520 .udt_pass = B_FALSE, 521 .udt_fail = ZEN_UMC_DECODE_F_CHAN_ILEAVE_NOTSUP, 522 }, { 523 .udt_desc = "Bad NPS hash interleave - die", 524 .udt_umc = &zen_umc_bad_df, 525 .udt_pa = 0xc00000, 526 .udt_pass = B_FALSE, 527 .udt_fail = ZEN_UMC_DECODE_F_NPS_BAD_ILEAVE 528 }, { 529 .udt_desc = "Bad NPS NP2 hash interleave - die", 530 .udt_umc = &zen_umc_bad_df, 531 .udt_pa = 0xa00000, 532 .udt_pass = B_FALSE, 533 .udt_fail = ZEN_UMC_DECODE_F_NPS_BAD_ILEAVE 534 }, { 535 .udt_desc = "Bad Remap Set - DFv3", 536 .udt_umc = &zen_umc_bad_df, 537 .udt_pa = 0xe00000, 538 .udt_pass = B_FALSE, 539 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 540 }, { 541 .udt_desc = "Bad Remap Set - DFv4 (0)", 542 .udt_umc = &zen_umc_bad_df, 543 .udt_pa = 0x1000000, 544 .udt_pass = B_FALSE, 545 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 546 }, { 547 .udt_desc = "Bad Remap Set - DFv4 (1)", 548 .udt_umc = &zen_umc_bad_df, 549 .udt_pa = 0x1200000, 550 .udt_pass = B_FALSE, 551 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_SET 552 }, { 553 .udt_desc = "Interleave address underflow", 554 .udt_umc = &zen_umc_hole_underflow, 555 .udt_pa = 0x100000000, 556 .udt_pass = B_FALSE, 557 .udt_fail = ZEN_UMC_DECODE_F_ILEAVE_UNDERFLOW 558 }, { 559 .udt_desc = "Normal address underflow", 560 .udt_umc = &zen_umc_norm_underflow, 561 .udt_pa = 0x100000000, 562 .udt_pass = B_FALSE, 563 .udt_fail = ZEN_UMC_DECODE_F_CALC_NORM_UNDERFLOW 564 }, { 565 .udt_desc = "Non-existent remap entry", 566 .udt_umc = &zen_umc_remap_errs, 567 .udt_pa = 0x0, 568 .udt_pass = B_FALSE, 569 .udt_fail = ZEN_UMC_DECODE_F_BAD_REMAP_ENTRY 570 }, { 571 .udt_desc = "Remap entry has bogus ID", 572 .udt_umc = &zen_umc_remap_errs, 573 .udt_pa = 0x8f0000000, 574 .udt_pass = B_FALSE, 575 .udt_fail = ZEN_UMC_DECODE_F_REMAP_HAS_BAD_COMP 576 }, { 577 .udt_desc = "Target fabric ID doesn't exist", 578 .udt_umc = &zen_umc_fab_errs, 579 .udt_pa = 0x12345, 580 .udt_pass = B_FALSE, 581 .udt_fail = ZEN_UMC_DECODE_F_CANNOT_MAP_FABID 582 }, { 583 .udt_desc = "UMC doesn't have DRAM rule", 584 .udt_umc = &zen_umc_fab_errs, 585 .udt_pa = 0x87654321, 586 .udt_pass = B_FALSE, 587 .udt_fail = ZEN_UMC_DECODE_F_UMC_DOESNT_HAVE_PA 588 }, { 589 .udt_desc = "No matching chip-select", 590 .udt_umc = &zen_umc_fab_errs, 591 .udt_pa = 0x101234567, 592 .udt_pass = B_FALSE, 593 .udt_fail = ZEN_UMC_DECODE_F_NO_CS_BASE_MATCH 594 }, { 595 .udt_desc = NULL 596 } }; 597