1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * hci1394_q.c 31 * This code decouples some of the OpenHCI async descriptor logic/structures 32 * from the async processing. The goal was to combine as much of the 33 * duplicate code as possible for the different type of async transfers 34 * without going too overboard. 35 * 36 * There are two parts to the Q, the descriptor buffer and the data buffer. 37 * For the most part, data to be transmitted and data which is received go 38 * in the data buffers. The information of where to get the data and put 39 * the data reside in the descriptor buffers. There are exceptions to this. 40 */ 41 42 43 #include <sys/types.h> 44 #include <sys/conf.h> 45 #include <sys/ddi.h> 46 #include <sys/modctl.h> 47 #include <sys/stat.h> 48 #include <sys/sunddi.h> 49 #include <sys/cmn_err.h> 50 #include <sys/kmem.h> 51 #include <sys/note.h> 52 53 #include <sys/1394/adapters/hci1394.h> 54 55 56 static int hci1394_q_reserve(hci1394_q_buf_t *qbuf, uint_t size, 57 uint32_t *io_addr); 58 static void hci1394_q_unreserve(hci1394_q_buf_t *qbuf); 59 static void hci1394_q_buf_setup(hci1394_q_buf_t *qbuf); 60 static void hci1394_q_reset(hci1394_q_handle_t q_handle); 61 static void hci1394_q_next_buf(hci1394_q_buf_t *qbuf); 62 63 static void hci1394_q_at_write_OLI(hci1394_q_handle_t q_handle, 64 hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, hci1394_basic_pkt_t *hdr, 65 uint_t hdrsize); 66 static void hci1394_q_at_write_OMI(hci1394_q_handle_t q_handle, 67 hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, hci1394_basic_pkt_t *hdr, 68 uint_t hdrsize); 69 static void hci1394_q_at_write_OL(hci1394_q_handle_t q_handle, 70 hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, uint32_t io_addr, 71 uint_t datasize); 72 static void hci1394_q_at_rep_put8(hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, 73 uint8_t *data, uint_t datasize); 74 static void hci1394_q_at_copy_from_mblk(hci1394_q_buf_t *qbuf, 75 hci1394_q_cmd_t *cmd, h1394_mblk_t *mblk); 76 77 static void hci1394_q_ar_write_IM(hci1394_q_handle_t q_handle, 78 hci1394_q_buf_t *qbuf, uint32_t io_addr, uint_t datasize); 79 80 _NOTE(SCHEME_PROTECTS_DATA("unique", msgb)) 81 82 /* 83 * hci1394_q_init() 84 * Initialize a Q. A Q consists of a descriptor buffer and a data buffer and 85 * can be either an AT or AR Q. hci1394_q_init() returns a handle which 86 * should be used for the reset of the hci1394_q_* calls. 87 */ 88 int 89 hci1394_q_init(hci1394_drvinfo_t *drvinfo, 90 hci1394_ohci_handle_t ohci_handle, hci1394_q_info_t *qinfo, 91 hci1394_q_handle_t *q_handle) 92 { 93 hci1394_q_buf_t *desc; 94 hci1394_q_buf_t *data; 95 hci1394_buf_parms_t parms; 96 hci1394_q_t *q; 97 int status; 98 int index; 99 100 101 ASSERT(drvinfo != NULL); 102 ASSERT(qinfo != NULL); 103 ASSERT(q_handle != NULL); 104 TNF_PROBE_0_DEBUG(hci1394_q_init_enter, HCI1394_TNF_HAL_STACK, ""); 105 106 /* 107 * allocate the memory to track this Q. Initialize the internal Q 108 * structure. 109 */ 110 q = kmem_alloc(sizeof (hci1394_q_t), KM_SLEEP); 111 q->q_drvinfo = drvinfo; 112 q->q_info = *qinfo; 113 q->q_ohci = ohci_handle; 114 mutex_init(&q->q_mutex, NULL, MUTEX_DRIVER, drvinfo->di_iblock_cookie); 115 desc = &q->q_desc; 116 data = &q->q_data; 117 118 /* 119 * Allocate the Descriptor buffer. 120 * 121 * XXX - Only want 1 cookie for now. Change this to OHCI_MAX_COOKIE 122 * after we have tested the multiple cookie code on x86. 123 */ 124 parms.bp_length = qinfo->qi_desc_size; 125 parms.bp_max_cookies = 1; 126 parms.bp_alignment = 16; 127 status = hci1394_buf_alloc(drvinfo, &parms, &desc->qb_buf, 128 &desc->qb_buf_handle); 129 if (status != DDI_SUCCESS) { 130 mutex_destroy(&q->q_mutex); 131 kmem_free(q, sizeof (hci1394_q_t)); 132 *q_handle = NULL; 133 TNF_PROBE_0(hci1394_q_init_bae_fail, HCI1394_TNF_HAL_ERROR, ""); 134 TNF_PROBE_0_DEBUG(hci1394_q_init_exit, HCI1394_TNF_HAL_STACK, 135 ""); 136 return (DDI_FAILURE); 137 } 138 139 /* Copy in buffer cookies into our local cookie array */ 140 desc->qb_cookie[0] = desc->qb_buf.bi_cookie; 141 for (index = 1; index < desc->qb_buf.bi_cookie_count; index++) { 142 ddi_dma_nextcookie(desc->qb_buf.bi_dma_handle, 143 &desc->qb_buf.bi_cookie); 144 desc->qb_cookie[index] = desc->qb_buf.bi_cookie; 145 } 146 147 /* 148 * Allocate the Data buffer. 149 * 150 * XXX - Only want 1 cookie for now. Change this to OHCI_MAX_COOKIE 151 * after we have tested the multiple cookie code on x86. 152 */ 153 parms.bp_length = qinfo->qi_data_size; 154 parms.bp_max_cookies = 1; 155 parms.bp_alignment = 16; 156 status = hci1394_buf_alloc(drvinfo, &parms, &data->qb_buf, 157 &data->qb_buf_handle); 158 if (status != DDI_SUCCESS) { 159 hci1394_buf_free(&data->qb_buf_handle); 160 mutex_destroy(&q->q_mutex); 161 kmem_free(q, sizeof (hci1394_q_t)); 162 *q_handle = NULL; 163 TNF_PROBE_0(hci1394_q_init_baa_fail, HCI1394_TNF_HAL_ERROR, ""); 164 TNF_PROBE_0_DEBUG(hci1394_q_init_exit, HCI1394_TNF_HAL_STACK, 165 ""); 166 return (DDI_FAILURE); 167 } 168 169 /* 170 * We must have at least 2 ARQ data buffers, If we only have one, we 171 * will artificially create 2. We must have 2 so that we always have a 172 * descriptor with free data space to write AR data to. When one is 173 * empty, it will take us a bit to get a new descriptor back into the 174 * chain. 175 */ 176 if ((qinfo->qi_mode == HCI1394_ARQ) && 177 (data->qb_buf.bi_cookie_count == 1)) { 178 data->qb_buf.bi_cookie_count = 2; 179 data->qb_cookie[0] = data->qb_buf.bi_cookie; 180 data->qb_cookie[0].dmac_size /= 2; 181 data->qb_cookie[1] = data->qb_cookie[0]; 182 data->qb_cookie[1].dmac_laddress = 183 data->qb_cookie[0].dmac_laddress + 184 data->qb_cookie[0].dmac_size; 185 data->qb_cookie[1].dmac_address = 186 data->qb_cookie[0].dmac_address + 187 data->qb_cookie[0].dmac_size; 188 189 /* We have more than 1 cookie or we are an AT Q */ 190 } else { 191 /* Copy in buffer cookies into our local cookie array */ 192 data->qb_cookie[0] = data->qb_buf.bi_cookie; 193 for (index = 1; index < data->qb_buf.bi_cookie_count; index++) { 194 ddi_dma_nextcookie(data->qb_buf.bi_dma_handle, 195 &data->qb_buf.bi_cookie); 196 data->qb_cookie[index] = data->qb_buf.bi_cookie; 197 } 198 } 199 200 /* The top and bottom of the Q are only set once */ 201 desc->qb_ptrs.qp_top = desc->qb_buf.bi_kaddr; 202 desc->qb_ptrs.qp_bottom = desc->qb_buf.bi_kaddr + 203 desc->qb_buf.bi_real_length - 1; 204 data->qb_ptrs.qp_top = data->qb_buf.bi_kaddr; 205 data->qb_ptrs.qp_bottom = data->qb_buf.bi_kaddr + 206 data->qb_buf.bi_real_length - 1; 207 208 /* 209 * reset the Q pointers to their original settings. Setup IM 210 * descriptors if this is an AR Q. 211 */ 212 hci1394_q_reset(q); 213 214 /* if this is an AT Q, create a queued list for the AT descriptors */ 215 if (qinfo->qi_mode == HCI1394_ATQ) { 216 hci1394_tlist_init(drvinfo, NULL, &q->q_queued_list); 217 } 218 219 *q_handle = q; 220 221 TNF_PROBE_0_DEBUG(hci1394_q_init_exit, HCI1394_TNF_HAL_STACK, ""); 222 223 return (DDI_SUCCESS); 224 } 225 226 227 /* 228 * hci1394_q_fini() 229 * Cleanup after a successful hci1394_q_init(). Notice that a pointer to the 230 * handle is used for the parameter. fini() will set your handle to NULL 231 * before returning. 232 */ 233 void 234 hci1394_q_fini(hci1394_q_handle_t *q_handle) 235 { 236 hci1394_q_t *q; 237 238 ASSERT(q_handle != NULL); 239 TNF_PROBE_0_DEBUG(hci1394_q_fini_enter, HCI1394_TNF_HAL_STACK, ""); 240 241 q = *q_handle; 242 if (q->q_info.qi_mode == HCI1394_ATQ) { 243 hci1394_tlist_fini(&q->q_queued_list); 244 } 245 mutex_destroy(&q->q_mutex); 246 hci1394_buf_free(&q->q_desc.qb_buf_handle); 247 hci1394_buf_free(&q->q_data.qb_buf_handle); 248 kmem_free(q, sizeof (hci1394_q_t)); 249 *q_handle = NULL; 250 251 TNF_PROBE_0_DEBUG(hci1394_q_fini_exit, HCI1394_TNF_HAL_STACK, ""); 252 } 253 254 255 /* 256 * hci1394_q_buf_setup() 257 * Initialization of buffer pointers which are present in both the descriptor 258 * buffer and data buffer (No reason to duplicate the code) 259 */ 260 static void 261 hci1394_q_buf_setup(hci1394_q_buf_t *qbuf) 262 { 263 ASSERT(qbuf != NULL); 264 TNF_PROBE_0_DEBUG(hci1394_q_buf_setup_enter, HCI1394_TNF_HAL_STACK, ""); 265 266 /* start with the first cookie */ 267 qbuf->qb_ptrs.qp_current_buf = 0; 268 qbuf->qb_ptrs.qp_begin = qbuf->qb_ptrs.qp_top; 269 qbuf->qb_ptrs.qp_end = qbuf->qb_ptrs.qp_begin + 270 qbuf->qb_cookie[qbuf->qb_ptrs.qp_current_buf].dmac_size - 1; 271 qbuf->qb_ptrs.qp_current = qbuf->qb_ptrs.qp_begin; 272 qbuf->qb_ptrs.qp_offset = 0; 273 274 /* 275 * The free_buf and free pointer will change everytime an ACK (of some 276 * type) is processed. Free is the last byte in the last cookie. 277 */ 278 qbuf->qb_ptrs.qp_free_buf = qbuf->qb_buf.bi_cookie_count - 1; 279 qbuf->qb_ptrs.qp_free = qbuf->qb_ptrs.qp_bottom; 280 281 /* 282 * Start with no space to write descriptors. We first need to call 283 * hci1394_q_reserve() before calling hci1394_q_at_write_O*(). 284 */ 285 qbuf->qb_ptrs.qp_resv_size = 0; 286 287 TNF_PROBE_0_DEBUG(hci1394_q_buf_setup_exit, HCI1394_TNF_HAL_STACK, ""); 288 } 289 290 291 /* 292 * hci1394_q_reset() 293 * Resets the buffers to an initial state. This should be called during 294 * attach and resume. 295 */ 296 static void 297 hci1394_q_reset(hci1394_q_handle_t q_handle) 298 { 299 hci1394_q_buf_t *desc; 300 hci1394_q_buf_t *data; 301 int index; 302 303 ASSERT(q_handle != NULL); 304 TNF_PROBE_0_DEBUG(hci1394_q_reset_enter, HCI1394_TNF_HAL_STACK, ""); 305 306 mutex_enter(&q_handle->q_mutex); 307 desc = &q_handle->q_desc; 308 data = &q_handle->q_data; 309 310 hci1394_q_buf_setup(desc); 311 hci1394_q_buf_setup(data); 312 313 /* DMA starts off stopped, no previous descriptor to link from */ 314 q_handle->q_dma_running = B_FALSE; 315 q_handle->q_block_cnt = 0; 316 q_handle->q_previous = NULL; 317 318 /* If this is an AR Q, setup IM's for the data buffers that we have */ 319 if (q_handle->q_info.qi_mode == HCI1394_ARQ) { 320 /* 321 * This points to where to find the first IM descriptor. Since 322 * we just reset the pointers in hci1394_q_buf_setup(), the 323 * first IM we write below will be found at the top of the Q. 324 */ 325 q_handle->q_head = desc->qb_ptrs.qp_top; 326 327 for (index = 0; index < data->qb_buf.bi_cookie_count; index++) { 328 hci1394_q_ar_write_IM(q_handle, desc, 329 data->qb_cookie[index].dmac_address, 330 data->qb_cookie[index].dmac_size); 331 } 332 333 /* 334 * The space left in the current IM is the size of the buffer. 335 * The current buffer is the first buffer added to the AR Q. 336 */ 337 q_handle->q_space_left = data->qb_cookie[0].dmac_size; 338 } 339 340 mutex_exit(&q_handle->q_mutex); 341 TNF_PROBE_0_DEBUG(hci1394_q_reset_exit, HCI1394_TNF_HAL_STACK, ""); 342 } 343 344 345 /* 346 * hci1394_q_resume() 347 * This is called during a resume (after a successful suspend). Currently 348 * we only call reset. Since this is not a time critical function, we will 349 * leave this as a separate function to increase readability. 350 */ 351 void 352 hci1394_q_resume(hci1394_q_handle_t q_handle) 353 { 354 ASSERT(q_handle != NULL); 355 TNF_PROBE_0_DEBUG(hci1394_q_resume_enter, HCI1394_TNF_HAL_STACK, ""); 356 hci1394_q_reset(q_handle); 357 TNF_PROBE_0_DEBUG(hci1394_q_resume_exit, HCI1394_TNF_HAL_STACK, ""); 358 } 359 360 361 /* 362 * hci1394_q_stop() 363 * This call informs us that a DMA engine has been stopped. It does not 364 * perform the actual stop. We need to know this so that when we add a 365 * new descriptor, we do a start instead of a wake. 366 */ 367 void 368 hci1394_q_stop(hci1394_q_handle_t q_handle) 369 { 370 ASSERT(q_handle != NULL); 371 TNF_PROBE_0_DEBUG(hci1394_q_stop_enter, HCI1394_TNF_HAL_STACK, ""); 372 mutex_enter(&q_handle->q_mutex); 373 q_handle->q_dma_running = B_FALSE; 374 mutex_exit(&q_handle->q_mutex); 375 TNF_PROBE_0_DEBUG(hci1394_q_stop_exit, HCI1394_TNF_HAL_STACK, ""); 376 } 377 378 379 /* 380 * hci1394_q_reserve() 381 * Reserve space in the AT descriptor or data buffer. This ensures that we 382 * can get a contiguous buffer. Descriptors have to be in a contiguous 383 * buffer. Data does not have to be in a contiguous buffer but we do this to 384 * reduce complexity. For systems with small page sizes (e.g. x86), this 385 * could result in inefficient use of the data buffers when sending large 386 * data blocks (this only applies to non-physical block write ATREQs and 387 * block read ATRESP). Since it looks like most protocols that use large data 388 * blocks (like SPB-2), use physical transfers to do this (due to their 389 * efficiency), this will probably not be a real world problem. If it turns 390 * out to be a problem, the options are to force a single cookie for the data 391 * buffer, allow multiple cookies and have a larger data space, or change the 392 * data code to use a OMI, OM, OL descriptor sequence (instead of OMI, OL). 393 */ 394 static int 395 hci1394_q_reserve(hci1394_q_buf_t *qbuf, uint_t size, uint32_t *io_addr) 396 { 397 uint_t aligned_size; 398 399 400 ASSERT(qbuf != NULL); 401 TNF_PROBE_0_DEBUG(hci1394_q_reserve_enter, HCI1394_TNF_HAL_STACK, ""); 402 403 /* Save backup of pointers in case we have to unreserve */ 404 qbuf->qb_backup_ptrs = qbuf->qb_ptrs; 405 406 /* 407 * Make sure all alloc's are quadlet aligned. The data doesn't have to 408 * be, so we will force it to be. 409 */ 410 aligned_size = HCI1394_ALIGN_QUAD(size); 411 412 /* 413 * if the free pointer is in the current buffer and the free pointer 414 * is below the current pointer (i.e. has not wrapped around) 415 */ 416 if ((qbuf->qb_ptrs.qp_current_buf == qbuf->qb_ptrs.qp_free_buf) && 417 (qbuf->qb_ptrs.qp_free >= qbuf->qb_ptrs.qp_current)) { 418 /* 419 * The free pointer is in this buffer below the current pointer. 420 * Check to see if we have enough free space left. 421 */ 422 if ((qbuf->qb_ptrs.qp_current + aligned_size) <= 423 qbuf->qb_ptrs.qp_free) { 424 /* Setup up our reserved size, return the IO address */ 425 qbuf->qb_ptrs.qp_resv_size = aligned_size; 426 *io_addr = (uint32_t)(qbuf->qb_cookie[ 427 qbuf->qb_ptrs.qp_current_buf].dmac_address + 428 qbuf->qb_ptrs.qp_offset); 429 430 /* 431 * The free pointer is in this buffer below the current pointer. 432 * We do not have enough free space for the alloc. Return 433 * failure. 434 */ 435 } else { 436 qbuf->qb_ptrs.qp_resv_size = 0; 437 TNF_PROBE_0(hci1394_q_reserve_ns_fail, 438 HCI1394_TNF_HAL_ERROR, ""); 439 TNF_PROBE_0_DEBUG(hci1394_q_reserve_exit, 440 HCI1394_TNF_HAL_STACK, ""); 441 return (DDI_FAILURE); 442 } 443 444 /* 445 * If there is not enough room to fit in the current buffer (not 446 * including wrap around), we will go to the next buffer and check 447 * there. If we only have one buffer (i.e. one cookie), we will end up 448 * staying at the current buffer and wrapping the address back to the 449 * top. 450 */ 451 } else if ((qbuf->qb_ptrs.qp_current + aligned_size) > 452 qbuf->qb_ptrs.qp_end) { 453 /* Go to the next buffer (or the top of ours for one cookie) */ 454 hci1394_q_next_buf(qbuf); 455 456 /* If the free pointer is in the new current buffer */ 457 if (qbuf->qb_ptrs.qp_current_buf == qbuf->qb_ptrs.qp_free_buf) { 458 /* 459 * The free pointer is in this buffer. If we do not have 460 * enough free space for the alloc. Return failure. 461 */ 462 if ((qbuf->qb_ptrs.qp_current + aligned_size) > 463 qbuf->qb_ptrs.qp_free) { 464 qbuf->qb_ptrs.qp_resv_size = 0; 465 TNF_PROBE_0(hci1394_q_reserve_ns_fail, 466 HCI1394_TNF_HAL_ERROR, ""); 467 TNF_PROBE_0_DEBUG(hci1394_q_reserve_exit, 468 HCI1394_TNF_HAL_STACK, ""); 469 return (DDI_FAILURE); 470 /* 471 * The free pointer is in this buffer. We have enough 472 * free space left. 473 */ 474 } else { 475 /* 476 * Setup up our reserved size, return the IO 477 * address 478 */ 479 qbuf->qb_ptrs.qp_resv_size = aligned_size; 480 *io_addr = (uint32_t)(qbuf->qb_cookie[ 481 qbuf->qb_ptrs.qp_current_buf].dmac_address + 482 qbuf->qb_ptrs.qp_offset); 483 } 484 485 /* 486 * We switched buffers and the free pointer is still in another 487 * buffer. We have sufficient space in this buffer for the alloc 488 * after changing buffers. 489 */ 490 } else { 491 /* Setup up our reserved size, return the IO address */ 492 qbuf->qb_ptrs.qp_resv_size = aligned_size; 493 *io_addr = (uint32_t)(qbuf->qb_cookie[ 494 qbuf->qb_ptrs.qp_current_buf].dmac_address + 495 qbuf->qb_ptrs.qp_offset); 496 } 497 /* 498 * The free pointer is in another buffer. We have sufficient space in 499 * this buffer for the alloc. 500 */ 501 } else { 502 /* Setup up our reserved size, return the IO address */ 503 qbuf->qb_ptrs.qp_resv_size = aligned_size; 504 *io_addr = (uint32_t)(qbuf->qb_cookie[ 505 qbuf->qb_ptrs.qp_current_buf].dmac_address + 506 qbuf->qb_ptrs.qp_offset); 507 } 508 509 TNF_PROBE_0_DEBUG(hci1394_q_reserve_exit, HCI1394_TNF_HAL_STACK, ""); 510 511 return (DDI_SUCCESS); 512 } 513 514 /* 515 * hci1394_q_unreserve() 516 * Set the buffer pointer to what they were before hci1394_reserve(). This 517 * will be called when we encounter errors during hci1394_q_at*(). 518 */ 519 static void 520 hci1394_q_unreserve(hci1394_q_buf_t *qbuf) 521 { 522 ASSERT(qbuf != NULL); 523 TNF_PROBE_0_DEBUG(hci1394_q_unreserve_enter, HCI1394_TNF_HAL_STACK, ""); 524 525 /* Go back to pointer setting before the reserve */ 526 qbuf->qb_ptrs = qbuf->qb_backup_ptrs; 527 528 TNF_PROBE_0_DEBUG(hci1394_q_unreserve_exit, HCI1394_TNF_HAL_STACK, ""); 529 } 530 531 532 /* 533 * hci1394_q_next_buf() 534 * Set our current buffer to the next cookie. If we only have one cookie, we 535 * will go back to the top of our buffer. 536 */ 537 void 538 hci1394_q_next_buf(hci1394_q_buf_t *qbuf) 539 { 540 ASSERT(qbuf != NULL); 541 TNF_PROBE_0_DEBUG(hci1394_q_next_buf_enter, HCI1394_TNF_HAL_STACK, ""); 542 543 /* 544 * go to the next cookie, if we are >= the cookie count, go back to the 545 * first cookie. 546 */ 547 qbuf->qb_ptrs.qp_current_buf++; 548 if (qbuf->qb_ptrs.qp_current_buf >= qbuf->qb_buf.bi_cookie_count) { 549 qbuf->qb_ptrs.qp_current_buf = 0; 550 } 551 552 /* adjust the begin, end, current, and offset pointers */ 553 qbuf->qb_ptrs.qp_begin = qbuf->qb_ptrs.qp_end + 1; 554 if (qbuf->qb_ptrs.qp_begin > qbuf->qb_ptrs.qp_bottom) { 555 qbuf->qb_ptrs.qp_begin = qbuf->qb_ptrs.qp_top; 556 } 557 qbuf->qb_ptrs.qp_end = qbuf->qb_ptrs.qp_begin + 558 qbuf->qb_cookie[qbuf->qb_ptrs.qp_current_buf].dmac_size - 1; 559 qbuf->qb_ptrs.qp_current = qbuf->qb_ptrs.qp_begin; 560 qbuf->qb_ptrs.qp_offset = 0; 561 562 TNF_PROBE_0_DEBUG(hci1394_q_next_buf_exit, HCI1394_TNF_HAL_STACK, ""); 563 } 564 565 566 /* 567 * hci1394_q_at() 568 * Place an AT command that does NOT need the data buffer into the DMA chain. 569 * Some examples of this are quadlet read/write, PHY packets, ATREQ Block 570 * Read, and ATRESP block write. result is only valid on failure. 571 */ 572 int 573 hci1394_q_at(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 574 hci1394_basic_pkt_t *hdr, uint_t hdrsize, int *result) 575 { 576 int status; 577 uint32_t ioaddr; 578 579 580 ASSERT(q_handle != NULL); 581 ASSERT(cmd != NULL); 582 ASSERT(hdr != NULL); 583 TNF_PROBE_0_DEBUG(hci1394_q_at_enter, HCI1394_TNF_HAL_STACK, ""); 584 585 mutex_enter(&q_handle->q_mutex); 586 587 /* 588 * Check the HAL state and generation when the AT Q is locked. This 589 * will make sure that we get all the commands when we flush the Q's 590 * during a reset or shutdown. 591 */ 592 if ((hci1394_state(q_handle->q_drvinfo) != HCI1394_NORMAL) || 593 (hci1394_ohci_current_busgen(q_handle->q_ohci) != 594 cmd->qc_generation)) { 595 *result = H1394_STATUS_INVALID_BUSGEN; 596 mutex_exit(&q_handle->q_mutex); 597 TNF_PROBE_0(hci1394_q_at_st_fail, HCI1394_TNF_HAL_ERROR, ""); 598 TNF_PROBE_0_DEBUG(hci1394_q_at_exit, HCI1394_TNF_HAL_STACK, 599 ""); 600 return (DDI_FAILURE); 601 } 602 603 /* save away the argument to pass up when this command completes */ 604 cmd->qc_node.tln_addr = cmd; 605 606 /* we have not written any 16 byte blocks to the descriptor yet */ 607 q_handle->q_block_cnt = 0; 608 609 /* Reserve space for an OLI in the descriptor buffer */ 610 status = hci1394_q_reserve(&q_handle->q_desc, 611 sizeof (hci1394_desc_imm_t), &ioaddr); 612 if (status != DDI_SUCCESS) { 613 *result = H1394_STATUS_NOMORE_SPACE; 614 mutex_exit(&q_handle->q_mutex); 615 TNF_PROBE_0(hci1394_q_at_qre_fail, HCI1394_TNF_HAL_ERROR, ""); 616 TNF_PROBE_0_DEBUG(hci1394_q_at_exit, HCI1394_TNF_HAL_STACK, 617 ""); 618 return (DDI_FAILURE); 619 } 620 621 /* write the OLI to the descriptor buffer */ 622 hci1394_q_at_write_OLI(q_handle, &q_handle->q_desc, cmd, hdr, hdrsize); 623 624 /* Add the AT command to the queued list */ 625 hci1394_tlist_add(q_handle->q_queued_list, &cmd->qc_node); 626 627 mutex_exit(&q_handle->q_mutex); 628 TNF_PROBE_0_DEBUG(hci1394_q_at_exit, HCI1394_TNF_HAL_STACK, ""); 629 630 return (DDI_SUCCESS); 631 } 632 633 634 /* 635 * XXX - NOTE: POSSIBLE FUTURE OPTIMIZATION 636 * ATREQ Block read and write's that go through software are not very 637 * efficient (one of the reasons to use physical space). A copy is forced 638 * on all block reads due to the design of OpenHCI. Writes do not have this 639 * same restriction. This design forces a copy for writes too (we always 640 * copy into a data buffer before sending). There are many reasons for this 641 * including complexity reduction. There is a data size threshold where a 642 * copy is more expensive than mapping the data buffer address (or worse 643 * case a big enough difference where it pays to do it). However, we move 644 * block data around in mblks which means that our data may be scattered 645 * over many buffers. This adds to the complexity of mapping and setting 646 * up the OpenHCI descriptors. 647 * 648 * If someone really needs a speedup on block write ATREQs, my recommendation 649 * would be to add an additional command type at the target interface for a 650 * fast block write. The target driver would pass a mapped io addr to use. 651 * A function like "hci1394_q_at_with_ioaddr()" could be created which would 652 * be almost an exact copy of hci1394_q_at_with_data() without the 653 * hci1394_q_reserve() and hci1394_q_at_rep_put8() for the data buffer. 654 */ 655 656 657 /* 658 * hci1394_q_at_with_data() 659 * Place an AT command that does need the data buffer into the DMA chain. 660 * The data is passed as a pointer to a kernel virtual address. An example of 661 * this is the lock operations. result is only valid on failure. 662 */ 663 int 664 hci1394_q_at_with_data(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 665 hci1394_basic_pkt_t *hdr, uint_t hdrsize, uint8_t *data, uint_t datasize, 666 int *result) 667 { 668 uint32_t desc_ioaddr; 669 uint32_t data_ioaddr; 670 int status; 671 672 673 ASSERT(q_handle != NULL); 674 ASSERT(cmd != NULL); 675 ASSERT(hdr != NULL); 676 ASSERT(data != NULL); 677 TNF_PROBE_0_DEBUG(hci1394_q_at_with_data_enter, HCI1394_TNF_HAL_STACK, 678 ""); 679 680 mutex_enter(&q_handle->q_mutex); 681 682 /* 683 * Check the HAL state and generation when the AT Q is locked. This 684 * will make sure that we get all the commands when we flush the Q's 685 * during a reset or shutdown. 686 */ 687 if ((hci1394_state(q_handle->q_drvinfo) != HCI1394_NORMAL) || 688 (hci1394_ohci_current_busgen(q_handle->q_ohci) != 689 cmd->qc_generation)) { 690 *result = H1394_STATUS_INVALID_BUSGEN; 691 mutex_exit(&q_handle->q_mutex); 692 TNF_PROBE_0_DEBUG(hci1394_q_at_wd_st_fail, 693 HCI1394_TNF_HAL_STACK, ""); 694 return (DDI_FAILURE); 695 } 696 697 /* save away the argument to pass up when this command completes */ 698 cmd->qc_node.tln_addr = cmd; 699 700 /* we have not written any 16 byte blocks to the descriptor yet */ 701 q_handle->q_block_cnt = 0; 702 703 /* Reserve space for an OMI and OL in the descriptor buffer */ 704 status = hci1394_q_reserve(&q_handle->q_desc, 705 (sizeof (hci1394_desc_imm_t) + sizeof (hci1394_desc_t)), 706 &desc_ioaddr); 707 if (status != DDI_SUCCESS) { 708 *result = H1394_STATUS_NOMORE_SPACE; 709 mutex_exit(&q_handle->q_mutex); 710 TNF_PROBE_0(hci1394_q_at_wd_qre_fail, 711 HCI1394_TNF_HAL_ERROR, ""); 712 TNF_PROBE_0_DEBUG(hci1394_q_at_with_data_exit, 713 HCI1394_TNF_HAL_STACK, ""); 714 return (DDI_FAILURE); 715 } 716 717 /* allocate space for data in the data buffer */ 718 status = hci1394_q_reserve(&q_handle->q_data, datasize, &data_ioaddr); 719 if (status != DDI_SUCCESS) { 720 *result = H1394_STATUS_NOMORE_SPACE; 721 hci1394_q_unreserve(&q_handle->q_desc); 722 mutex_exit(&q_handle->q_mutex); 723 TNF_PROBE_0(hci1394_q_at_wd_qra_fail, 724 HCI1394_TNF_HAL_ERROR, ""); 725 TNF_PROBE_0_DEBUG(hci1394_q_at_with_data_exit, 726 HCI1394_TNF_HAL_STACK, ""); 727 return (DDI_FAILURE); 728 } 729 730 /* Copy data into data buffer */ 731 hci1394_q_at_rep_put8(&q_handle->q_data, cmd, data, datasize); 732 733 /* write the OMI to the descriptor buffer */ 734 hci1394_q_at_write_OMI(q_handle, &q_handle->q_desc, cmd, hdr, hdrsize); 735 736 /* write the OL to the descriptor buffer */ 737 hci1394_q_at_write_OL(q_handle, &q_handle->q_desc, cmd, data_ioaddr, 738 datasize); 739 740 /* Add the AT command to the queued list */ 741 hci1394_tlist_add(q_handle->q_queued_list, &cmd->qc_node); 742 743 mutex_exit(&q_handle->q_mutex); 744 TNF_PROBE_0_DEBUG(hci1394_q_at_with_data_exit, HCI1394_TNF_HAL_STACK, 745 ""); 746 747 return (DDI_SUCCESS); 748 } 749 750 751 /* 752 * hci1394_q_at_with_mblk() 753 * Place an AT command that does need the data buffer into the DMA chain. 754 * The data is passed in mblk_t(s). Examples of this are a block write 755 * ATREQ and a block read ATRESP. The services layer and the hal use a 756 * private structure (h1394_mblk_t) to keep track of how much of the mblk 757 * to send since we may have to break the transfer up into smaller blocks. 758 * (i.e. a 1MByte block write would go out in 2KByte chunks. result is only 759 * valid on failure. 760 */ 761 int 762 hci1394_q_at_with_mblk(hci1394_q_handle_t q_handle, hci1394_q_cmd_t *cmd, 763 hci1394_basic_pkt_t *hdr, uint_t hdrsize, h1394_mblk_t *mblk, int *result) 764 { 765 uint32_t desc_ioaddr; 766 uint32_t data_ioaddr; 767 int status; 768 769 770 ASSERT(q_handle != NULL); 771 ASSERT(cmd != NULL); 772 ASSERT(hdr != NULL); 773 ASSERT(mblk != NULL); 774 TNF_PROBE_0_DEBUG(hci1394_q_at_with_mblk_enter, HCI1394_TNF_HAL_STACK, 775 ""); 776 777 mutex_enter(&q_handle->q_mutex); 778 779 /* 780 * Check the HAL state and generation when the AT Q is locked. This 781 * will make sure that we get all the commands when we flush the Q's 782 * during a reset or shutdown. 783 */ 784 if ((hci1394_state(q_handle->q_drvinfo) != HCI1394_NORMAL) || 785 (hci1394_ohci_current_busgen(q_handle->q_ohci) != 786 cmd->qc_generation)) { 787 *result = H1394_STATUS_INVALID_BUSGEN; 788 mutex_exit(&q_handle->q_mutex); 789 TNF_PROBE_0_DEBUG(hci1394_q_at_wm_st_fail, 790 HCI1394_TNF_HAL_STACK, ""); 791 return (DDI_FAILURE); 792 } 793 794 /* save away the argument to pass up when this command completes */ 795 cmd->qc_node.tln_addr = cmd; 796 797 /* we have not written any 16 byte blocks to the descriptor yet */ 798 q_handle->q_block_cnt = 0; 799 800 /* Reserve space for an OMI and OL in the descriptor buffer */ 801 status = hci1394_q_reserve(&q_handle->q_desc, 802 (sizeof (hci1394_desc_imm_t) + sizeof (hci1394_desc_t)), 803 &desc_ioaddr); 804 if (status != DDI_SUCCESS) { 805 *result = H1394_STATUS_NOMORE_SPACE; 806 mutex_exit(&q_handle->q_mutex); 807 TNF_PROBE_0(hci1394_q_at_wm_qre_fail, 808 HCI1394_TNF_HAL_ERROR, ""); 809 TNF_PROBE_0_DEBUG(hci1394_q_at_with_mblk_exit, 810 HCI1394_TNF_HAL_STACK, ""); 811 return (DDI_FAILURE); 812 } 813 814 /* Reserve space for data in the data buffer */ 815 status = hci1394_q_reserve(&q_handle->q_data, mblk->length, 816 &data_ioaddr); 817 if (status != DDI_SUCCESS) { 818 *result = H1394_STATUS_NOMORE_SPACE; 819 hci1394_q_unreserve(&q_handle->q_desc); 820 mutex_exit(&q_handle->q_mutex); 821 TNF_PROBE_0(hci1394_q_at_wm_qra_fail, 822 HCI1394_TNF_HAL_ERROR, ""); 823 TNF_PROBE_0_DEBUG(hci1394_q_at_with_mblk_exit, 824 HCI1394_TNF_HAL_STACK, ""); 825 return (DDI_FAILURE); 826 } 827 828 /* Copy mblk data into data buffer */ 829 hci1394_q_at_copy_from_mblk(&q_handle->q_data, cmd, mblk); 830 831 /* write the OMI to the descriptor buffer */ 832 hci1394_q_at_write_OMI(q_handle, &q_handle->q_desc, cmd, hdr, hdrsize); 833 834 /* write the OL to the descriptor buffer */ 835 hci1394_q_at_write_OL(q_handle, &q_handle->q_desc, cmd, data_ioaddr, 836 mblk->length); 837 838 /* Add the AT command to the queued list */ 839 hci1394_tlist_add(q_handle->q_queued_list, &cmd->qc_node); 840 841 mutex_exit(&q_handle->q_mutex); 842 TNF_PROBE_0_DEBUG(hci1394_q_at_with_mblk_exit, HCI1394_TNF_HAL_STACK, 843 ""); 844 845 return (DDI_SUCCESS); 846 } 847 848 849 /* 850 * hci1394_q_at_next() 851 * Return the next completed AT command in cmd. If flush_q is true, we will 852 * return the command regardless if it finished or not. We will flush 853 * during bus reset processing, shutdown, and detach. 854 */ 855 void 856 hci1394_q_at_next(hci1394_q_handle_t q_handle, boolean_t flush_q, 857 hci1394_q_cmd_t **cmd) 858 { 859 hci1394_q_buf_t *desc; 860 hci1394_q_buf_t *data; 861 hci1394_tlist_node_t *node; 862 uint32_t cmd_status; 863 864 865 ASSERT(q_handle != NULL); 866 ASSERT(cmd != NULL); 867 TNF_PROBE_0_DEBUG(hci1394_q_at_next_enter, HCI1394_TNF_HAL_STACK, ""); 868 869 mutex_enter(&q_handle->q_mutex); 870 871 desc = &q_handle->q_desc; 872 data = &q_handle->q_data; 873 874 /* Sync descriptor buffer */ 875 (void) ddi_dma_sync(desc->qb_buf.bi_dma_handle, 0, 876 desc->qb_buf.bi_length, DDI_DMA_SYNC_FORKERNEL); 877 878 /* Look at the top cmd on the queued list (without removing it) */ 879 hci1394_tlist_peek(q_handle->q_queued_list, &node); 880 if (node == NULL) { 881 /* There are no more commands left on the queued list */ 882 *cmd = NULL; 883 mutex_exit(&q_handle->q_mutex); 884 TNF_PROBE_0_DEBUG(hci1394_q_at_next_exit, HCI1394_TNF_HAL_STACK, 885 ""); 886 return; 887 } 888 889 /* 890 * There is a command on the list, read its status and timestamp when 891 * it was sent 892 */ 893 *cmd = (hci1394_q_cmd_t *)node->tln_addr; 894 cmd_status = ddi_get32(desc->qb_buf.bi_handle, (*cmd)->qc_status_addr); 895 (*cmd)->qc_timestamp = cmd_status & DESC_ST_TIMESTAMP_MASK; 896 cmd_status = HCI1394_DESC_EVT_GET(cmd_status); 897 898 /* 899 * If we are flushing the q (e.g. due to a bus reset), we will return 900 * the command regardless of its completion status. If we are not 901 * flushing the Q and we do not have status on the command (e.g. status 902 * = 0), we are done with this Q for now. 903 */ 904 if (flush_q == B_FALSE) { 905 if (cmd_status == 0) { 906 *cmd = NULL; 907 mutex_exit(&q_handle->q_mutex); 908 TNF_PROBE_0_DEBUG(hci1394_q_at_next_exit, 909 HCI1394_TNF_HAL_STACK, ""); 910 return; 911 } 912 } 913 914 /* 915 * The command completed, remove it from the queued list. There is not 916 * a race condition to delete the node in the list here. This is the 917 * only place the node will be deleted so we do not need to check the 918 * return status. 919 */ 920 (void) hci1394_tlist_delete(q_handle->q_queued_list, node); 921 922 /* 923 * Free the space used by the command in the descriptor and data 924 * buffers. 925 */ 926 desc->qb_ptrs.qp_free_buf = (*cmd)->qc_descriptor_buf; 927 desc->qb_ptrs.qp_free = (*cmd)->qc_descriptor_end; 928 if ((*cmd)->qc_data_used == B_TRUE) { 929 data->qb_ptrs.qp_free_buf = (*cmd)->qc_data_buf; 930 data->qb_ptrs.qp_free = (*cmd)->qc_data_end; 931 } 932 933 /* return command status */ 934 (*cmd)->qc_status = cmd_status; 935 936 mutex_exit(&q_handle->q_mutex); 937 TNF_PROBE_0_DEBUG(hci1394_q_at_next_exit, HCI1394_TNF_HAL_STACK, ""); 938 } 939 940 941 /* 942 * hci1394_q_at_write_OMI() 943 * Write an OMI descriptor into the AT descriptor buffer passed in as qbuf. 944 * Buffer state information is stored in cmd. Use the hdr and hdr size for 945 * the additional information attached to an immediate descriptor. 946 */ 947 void 948 hci1394_q_at_write_OMI(hci1394_q_handle_t q_handle, hci1394_q_buf_t *qbuf, 949 hci1394_q_cmd_t *cmd, hci1394_basic_pkt_t *hdr, uint_t hdrsize) 950 { 951 hci1394_desc_imm_t *desc; 952 uint32_t data; 953 954 955 ASSERT(qbuf != NULL); 956 ASSERT(cmd != NULL); 957 ASSERT(hdr != NULL); 958 ASSERT(MUTEX_HELD(&q_handle->q_mutex)); 959 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OMI_enter, HCI1394_TNF_HAL_STACK, 960 ""); 961 962 /* The only valid "header" sizes for an OMI are 8 bytes or 16 bytes */ 963 ASSERT((hdrsize == 8) || (hdrsize == 16)); 964 965 /* Make sure enough room for OMI */ 966 ASSERT(qbuf->qb_ptrs.qp_resv_size >= sizeof (hci1394_desc_imm_t)); 967 968 /* Store the offset of the top of this descriptor block */ 969 qbuf->qb_ptrs.qp_offset = (uint32_t)(qbuf->qb_ptrs.qp_current - 970 qbuf->qb_ptrs.qp_begin); 971 972 /* Setup OpenHCI OMI Header */ 973 desc = (hci1394_desc_imm_t *)qbuf->qb_ptrs.qp_current; 974 data = DESC_AT_OMI | (hdrsize & DESC_HDR_REQCOUNT_MASK); 975 ddi_put32(qbuf->qb_buf.bi_handle, &desc->hdr, data); 976 ddi_put32(qbuf->qb_buf.bi_handle, &desc->data_addr, 0); 977 ddi_put32(qbuf->qb_buf.bi_handle, &desc->branch, 0); 978 ddi_put32(qbuf->qb_buf.bi_handle, &desc->status, cmd->qc_timestamp); 979 980 /* 981 * Copy in 1394 header. Size is in bytes, convert it to a 32-bit word 982 * count. 983 */ 984 ddi_rep_put32(qbuf->qb_buf.bi_handle, &hdr->q1, &desc->q1, 985 hdrsize >> 2, DDI_DEV_AUTOINCR); 986 987 /* 988 * We wrote 2 16 byte blocks in the descriptor buffer, update the count 989 * accordingly. Update the reserved size and current pointer. 990 */ 991 q_handle->q_block_cnt += 2; 992 qbuf->qb_ptrs.qp_resv_size -= sizeof (hci1394_desc_imm_t); 993 qbuf->qb_ptrs.qp_current += sizeof (hci1394_desc_imm_t); 994 995 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OMI_exit, HCI1394_TNF_HAL_STACK, 996 ""); 997 } 998 999 1000 /* 1001 * hci1394_q_at_write_OLI() 1002 * Write an OLI descriptor into the AT descriptor buffer passed in as qbuf. 1003 * Buffer state information is stored in cmd. Use the hdr and hdr size for 1004 * the additional information attached to an immediate descriptor. 1005 */ 1006 void 1007 hci1394_q_at_write_OLI(hci1394_q_handle_t q_handle, hci1394_q_buf_t *qbuf, 1008 hci1394_q_cmd_t *cmd, hci1394_basic_pkt_t *hdr, uint_t hdrsize) 1009 { 1010 hci1394_desc_imm_t *desc; 1011 uint32_t data; 1012 uint32_t command_ptr; 1013 uint32_t tcode; 1014 1015 1016 ASSERT(qbuf != NULL); 1017 ASSERT(cmd != NULL); 1018 ASSERT(hdr != NULL); 1019 ASSERT(MUTEX_HELD(&q_handle->q_mutex)); 1020 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OLI_enter, HCI1394_TNF_HAL_STACK, 1021 ""); 1022 1023 /* The only valid "header" sizes for an OLI are 8, 12, 16 bytes */ 1024 ASSERT((hdrsize == 8) || (hdrsize == 12) || (hdrsize == 16)); 1025 1026 /* make sure enough room for 1 OLI */ 1027 ASSERT(qbuf->qb_ptrs.qp_resv_size >= sizeof (hci1394_desc_imm_t)); 1028 1029 /* Store the offset of the top of this descriptor block */ 1030 qbuf->qb_ptrs.qp_offset = (uint32_t)(qbuf->qb_ptrs.qp_current - 1031 qbuf->qb_ptrs.qp_begin); 1032 1033 /* Setup OpenHCI OLI Header */ 1034 desc = (hci1394_desc_imm_t *)qbuf->qb_ptrs.qp_current; 1035 data = DESC_AT_OLI | (hdrsize & DESC_HDR_REQCOUNT_MASK); 1036 ddi_put32(qbuf->qb_buf.bi_handle, &desc->hdr, data); 1037 ddi_put32(qbuf->qb_buf.bi_handle, &desc->data_addr, 0); 1038 ddi_put32(qbuf->qb_buf.bi_handle, &desc->branch, 0); 1039 ddi_put32(qbuf->qb_buf.bi_handle, &desc->status, cmd->qc_timestamp); 1040 1041 /* Setup 1394 Header */ 1042 tcode = (hdr->q1 & DESC_PKT_TCODE_MASK) >> DESC_PKT_TCODE_SHIFT; 1043 if ((tcode == IEEE1394_TCODE_WRITE_QUADLET) || 1044 (tcode == IEEE1394_TCODE_READ_QUADLET_RESP)) { 1045 /* 1046 * if the tcode = a quadlet write, move the last quadlet as 1047 * 8-bit data. All data is treated as 8-bit data (even quadlet 1048 * reads and writes). Therefore, target drivers MUST take that 1049 * into consideration when accessing device registers. 1050 */ 1051 ddi_rep_put32(qbuf->qb_buf.bi_handle, &hdr->q1, &desc->q1, 3, 1052 DDI_DEV_AUTOINCR); 1053 ddi_rep_put8(qbuf->qb_buf.bi_handle, (uint8_t *)&hdr->q4, 1054 (uint8_t *)&desc->q4, 4, DDI_DEV_AUTOINCR); 1055 } else { 1056 ddi_rep_put32(qbuf->qb_buf.bi_handle, &hdr->q1, &desc->q1, 1057 hdrsize >> 2, DDI_DEV_AUTOINCR); 1058 } 1059 1060 /* 1061 * We wrote 2 16 byte blocks in the descriptor buffer, update the count 1062 * accordingly. 1063 */ 1064 q_handle->q_block_cnt += 2; 1065 1066 /* 1067 * Sync buffer in case DMA engine currently running. This must be done 1068 * before writing the command pointer in the previous descriptor. 1069 */ 1070 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1071 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1072 1073 /* save away the status address for quick access in at_next() */ 1074 cmd->qc_status_addr = &desc->status; 1075 1076 /* 1077 * Setup the command pointer. This tells the HW where to get the 1078 * descriptor we just setup. This includes the IO address along with 1079 * a 4 bit 16 byte block count 1080 */ 1081 command_ptr = (uint32_t)((qbuf->qb_cookie[qbuf->qb_ptrs.qp_current_buf 1082 ].dmac_address + qbuf->qb_ptrs.qp_offset) | (q_handle->q_block_cnt & 1083 DESC_Z_MASK)); 1084 1085 /* 1086 * if we previously setup a descriptor, add this new descriptor into 1087 * the previous descriptor's "next" pointer. 1088 */ 1089 if (q_handle->q_previous != NULL) { 1090 ddi_put32(qbuf->qb_buf.bi_handle, &q_handle->q_previous->branch, 1091 command_ptr); 1092 /* Sync buffer again, this gets the command pointer */ 1093 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1094 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1095 } 1096 1097 /* 1098 * this is now the previous descriptor. Update the current pointer, 1099 * clear the block count and reserved size since this is the end of 1100 * this command. 1101 */ 1102 q_handle->q_previous = (hci1394_desc_t *)desc; 1103 qbuf->qb_ptrs.qp_current += sizeof (hci1394_desc_imm_t); 1104 q_handle->q_block_cnt = 0; 1105 qbuf->qb_ptrs.qp_resv_size = 0; 1106 1107 /* save away cleanup info when we are done with the command */ 1108 cmd->qc_descriptor_buf = qbuf->qb_ptrs.qp_current_buf; 1109 cmd->qc_descriptor_end = qbuf->qb_ptrs.qp_current - 1; 1110 1111 /* If the DMA is not running, start it */ 1112 if (q_handle->q_dma_running == B_FALSE) { 1113 q_handle->q_info.qi_start(q_handle->q_info.qi_callback_arg, 1114 command_ptr); 1115 q_handle->q_dma_running = B_TRUE; 1116 /* the DMA is running, wake it up */ 1117 } else { 1118 q_handle->q_info.qi_wake(q_handle->q_info.qi_callback_arg); 1119 } 1120 1121 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OLI_exit, HCI1394_TNF_HAL_STACK, 1122 ""); 1123 } 1124 1125 1126 /* 1127 * hci1394_q_at_write_OL() 1128 * Write an OL descriptor into the AT descriptor buffer passed in as qbuf. 1129 * Buffer state information is stored in cmd. The IO address of the data 1130 * buffer is passed in io_addr. Size is the size of the data to be 1131 * transferred. 1132 */ 1133 void 1134 hci1394_q_at_write_OL(hci1394_q_handle_t q_handle, hci1394_q_buf_t *qbuf, 1135 hci1394_q_cmd_t *cmd, uint32_t io_addr, uint_t size) 1136 { 1137 hci1394_desc_t *desc; 1138 uint32_t data; 1139 uint32_t command_ptr; 1140 1141 1142 ASSERT(q_handle != NULL); 1143 ASSERT(qbuf != NULL); 1144 ASSERT(cmd != NULL); 1145 ASSERT(MUTEX_HELD(&q_handle->q_mutex)); 1146 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OL_enter, HCI1394_TNF_HAL_STACK, 1147 ""); 1148 1149 /* make sure enough room for OL */ 1150 ASSERT(qbuf->qb_ptrs.qp_resv_size >= sizeof (hci1394_desc_t)); 1151 1152 /* Setup OpenHCI OL Header */ 1153 desc = (hci1394_desc_t *)qbuf->qb_ptrs.qp_current; 1154 data = DESC_AT_OL | (size & DESC_HDR_REQCOUNT_MASK); 1155 ddi_put32(qbuf->qb_buf.bi_handle, &desc->hdr, data); 1156 ddi_put32(qbuf->qb_buf.bi_handle, &desc->data_addr, io_addr); 1157 ddi_put32(qbuf->qb_buf.bi_handle, &desc->branch, 0); 1158 ddi_put32(qbuf->qb_buf.bi_handle, &desc->status, 0); 1159 1160 /* 1161 * We wrote 1 16 byte block in the descriptor buffer, update the count 1162 * accordingly. 1163 */ 1164 q_handle->q_block_cnt++; 1165 1166 /* 1167 * Sync buffer in case DMA engine currently running. This must be done 1168 * before writing the command pointer in the previous descriptor. 1169 */ 1170 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1171 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1172 1173 /* save away the status address for quick access in at_next() */ 1174 cmd->qc_status_addr = &desc->status; 1175 1176 /* 1177 * Setup the command pointer. This tells the HW where to get the 1178 * descriptor we just setup. This includes the IO address along with 1179 * a 4 bit 16 byte block count 1180 */ 1181 command_ptr = (uint32_t)((qbuf->qb_cookie[qbuf->qb_ptrs.qp_current_buf 1182 ].dmac_address + qbuf->qb_ptrs.qp_offset) | (q_handle->q_block_cnt & 1183 DESC_Z_MASK)); 1184 1185 /* 1186 * if we previously setup a descriptor, add this new descriptor into 1187 * the previous descriptor's "next" pointer. 1188 */ 1189 if (q_handle->q_previous != NULL) { 1190 ddi_put32(qbuf->qb_buf.bi_handle, &q_handle->q_previous->branch, 1191 command_ptr); 1192 /* Sync buffer again, this gets the command pointer */ 1193 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1194 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1195 } 1196 1197 /* 1198 * this is now the previous descriptor. Update the current pointer, 1199 * clear the block count and reserved size since this is the end of 1200 * this command. 1201 */ 1202 q_handle->q_previous = desc; 1203 qbuf->qb_ptrs.qp_current += sizeof (hci1394_desc_t); 1204 q_handle->q_block_cnt = 0; 1205 qbuf->qb_ptrs.qp_resv_size = 0; 1206 1207 /* save away cleanup info when we are done with the command */ 1208 cmd->qc_descriptor_buf = qbuf->qb_ptrs.qp_current_buf; 1209 cmd->qc_descriptor_end = qbuf->qb_ptrs.qp_current - 1; 1210 1211 /* If the DMA is not running, start it */ 1212 if (q_handle->q_dma_running == B_FALSE) { 1213 q_handle->q_info.qi_start(q_handle->q_info.qi_callback_arg, 1214 command_ptr); 1215 q_handle->q_dma_running = B_TRUE; 1216 /* the DMA is running, wake it up */ 1217 } else { 1218 q_handle->q_info.qi_wake(q_handle->q_info.qi_callback_arg); 1219 } 1220 1221 TNF_PROBE_0_DEBUG(hci1394_q_at_write_OL_exit, HCI1394_TNF_HAL_STACK, 1222 ""); 1223 } 1224 1225 1226 /* 1227 * hci1394_q_at_rep_put8() 1228 * Copy a byte stream from a kernel virtual address (data) to a IO mapped 1229 * data buffer (qbuf). Copy datasize bytes. State information for the 1230 * data buffer is kept in cmd. 1231 */ 1232 void 1233 hci1394_q_at_rep_put8(hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, 1234 uint8_t *data, uint_t datasize) 1235 { 1236 ASSERT(qbuf != NULL); 1237 ASSERT(cmd != NULL); 1238 ASSERT(data != NULL); 1239 TNF_PROBE_0_DEBUG(hci1394_q_at_rep_put8_enter, HCI1394_TNF_HAL_STACK, 1240 ""); 1241 1242 /* Make sure enough room for data */ 1243 ASSERT(qbuf->qb_ptrs.qp_resv_size >= datasize); 1244 1245 /* Copy in data into the data buffer */ 1246 ddi_rep_put8(qbuf->qb_buf.bi_handle, data, 1247 (uint8_t *)qbuf->qb_ptrs.qp_current, datasize, DDI_DEV_AUTOINCR); 1248 1249 /* Update the current pointer, offset, and reserved size */ 1250 qbuf->qb_ptrs.qp_current += datasize; 1251 qbuf->qb_ptrs.qp_offset = (uint32_t)(qbuf->qb_ptrs.qp_current - 1252 qbuf->qb_ptrs.qp_begin); 1253 qbuf->qb_ptrs.qp_resv_size -= datasize; 1254 1255 /* save away cleanup info when we are done with the command */ 1256 cmd->qc_data_used = B_TRUE; 1257 cmd->qc_data_buf = qbuf->qb_ptrs.qp_current_buf; 1258 cmd->qc_data_end = qbuf->qb_ptrs.qp_current - 1; 1259 1260 /* Sync data buffer */ 1261 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1262 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1263 1264 TNF_PROBE_0_DEBUG(hci1394_q_at_rep_put8_exit, HCI1394_TNF_HAL_STACK, 1265 ""); 1266 } 1267 1268 1269 /* 1270 * hci1394_q_at_copy_from_mblk() 1271 * Copy a byte stream from a mblk(s) to a IO mapped data buffer (qbuf). 1272 * Copy mblk->length bytes. The services layer and the hal use a private 1273 * structure (h1394_mblk_t) to keep track of how much of the mblk to send 1274 * since we may have to break the transfer up into smaller blocks. (i.e. a 1275 * 1MByte block write would go out in 2KByte chunks. State information for 1276 * the data buffer is kept in cmd. 1277 */ 1278 static void 1279 hci1394_q_at_copy_from_mblk(hci1394_q_buf_t *qbuf, hci1394_q_cmd_t *cmd, 1280 h1394_mblk_t *mblk) 1281 { 1282 uint_t bytes_left; 1283 uint_t length; 1284 1285 1286 ASSERT(qbuf != NULL); 1287 ASSERT(cmd != NULL); 1288 ASSERT(mblk != NULL); 1289 TNF_PROBE_0_DEBUG(hci1394_q_at_copy_from_mblk_enter, 1290 HCI1394_TNF_HAL_STACK, ""); 1291 1292 /* We return these variables to the Services Layer when we are done */ 1293 mblk->next_offset = mblk->curr_offset; 1294 mblk->next_mblk = mblk->curr_mblk; 1295 bytes_left = mblk->length; 1296 1297 /* do while there are bytes left to copy */ 1298 do { 1299 /* 1300 * If the entire data portion of the current block transfer is 1301 * contained within a single mblk. 1302 */ 1303 if ((mblk->next_offset + bytes_left) <= 1304 (mblk->next_mblk->b_wptr)) { 1305 /* Copy the data into the data Q */ 1306 hci1394_q_at_rep_put8(qbuf, cmd, 1307 (uint8_t *)mblk->next_offset, bytes_left); 1308 1309 /* increment the mblk offset */ 1310 mblk->next_offset += bytes_left; 1311 1312 /* we have no more bytes to put into the buffer */ 1313 bytes_left = 0; 1314 1315 /* 1316 * If our offset is at the end of data in this mblk, go 1317 * to the next mblk. 1318 */ 1319 if (mblk->next_offset >= mblk->next_mblk->b_wptr) { 1320 mblk->next_mblk = mblk->next_mblk->b_cont; 1321 if (mblk->next_mblk != NULL) { 1322 mblk->next_offset = 1323 mblk->next_mblk->b_rptr; 1324 } 1325 } 1326 1327 /* 1328 * The data portion of the current block transfer is spread 1329 * across two or more mblk's 1330 */ 1331 } else { 1332 /* 1333 * Figure out how much data is in this mblk. 1334 */ 1335 length = mblk->next_mblk->b_wptr - mblk->next_offset; 1336 1337 /* Copy the data into the atreq data Q */ 1338 hci1394_q_at_rep_put8(qbuf, cmd, 1339 (uint8_t *)mblk->next_offset, length); 1340 1341 /* update the bytes left count, go to the next mblk */ 1342 bytes_left = bytes_left - length; 1343 mblk->next_mblk = mblk->next_mblk->b_cont; 1344 ASSERT(mblk->next_mblk != NULL); 1345 mblk->next_offset = mblk->next_mblk->b_rptr; 1346 } 1347 } while (bytes_left > 0); 1348 1349 TNF_PROBE_0_DEBUG(hci1394_q_at_copy_from_mblk_exit, 1350 HCI1394_TNF_HAL_STACK, ""); 1351 } 1352 1353 1354 /* 1355 * hci1394_q_ar_next() 1356 * Return an address to the next received AR packet. If there are no more 1357 * AR packets in the buffer, q_addr will be set to NULL. 1358 */ 1359 void 1360 hci1394_q_ar_next(hci1394_q_handle_t q_handle, uint32_t **q_addr) 1361 { 1362 hci1394_desc_t *desc; 1363 hci1394_q_buf_t *descb; 1364 hci1394_q_buf_t *datab; 1365 uint32_t residual_count; 1366 1367 1368 ASSERT(q_handle != NULL); 1369 ASSERT(q_addr != NULL); 1370 TNF_PROBE_0_DEBUG(hci1394_q_ar_next_enter, HCI1394_TNF_HAL_STACK, ""); 1371 1372 descb = &q_handle->q_desc; 1373 datab = &q_handle->q_data; 1374 1375 /* Sync Descriptor buffer */ 1376 (void) ddi_dma_sync(descb->qb_buf.bi_dma_handle, 0, 1377 descb->qb_buf.bi_length, DDI_DMA_SYNC_FORKERNEL); 1378 1379 /* 1380 * Check residual in current IM count vs q_space_left to see if we have 1381 * received any more responses 1382 */ 1383 desc = (hci1394_desc_t *)q_handle->q_head; 1384 residual_count = ddi_get32(descb->qb_buf.bi_handle, &desc->status); 1385 residual_count &= DESC_ST_RESCOUNT_MASK; 1386 if (residual_count >= q_handle->q_space_left) { 1387 /* No new packets received */ 1388 *q_addr = NULL; 1389 TNF_PROBE_0_DEBUG(hci1394_q_ar_next_exit, 1390 HCI1394_TNF_HAL_STACK, ""); 1391 return; 1392 } 1393 1394 /* Sync Data Q */ 1395 (void) ddi_dma_sync(datab->qb_buf.bi_dma_handle, 0, 1396 datab->qb_buf.bi_length, DDI_DMA_SYNC_FORKERNEL); 1397 1398 /* 1399 * We have a new packet, return the address of the start of the 1400 * packet. 1401 */ 1402 *q_addr = (uint32_t *)datab->qb_ptrs.qp_current; 1403 1404 TNF_PROBE_0_DEBUG(hci1394_q_ar_next_exit, HCI1394_TNF_HAL_STACK, ""); 1405 } 1406 1407 1408 /* 1409 * hci1394_q_ar_free() 1410 * Free the space used by the AR packet at the top of the data buffer. AR 1411 * packets are processed in the order that they are received. This will 1412 * free the oldest received packet which has not yet been freed. size is 1413 * how much space the packet takes up. 1414 */ 1415 void 1416 hci1394_q_ar_free(hci1394_q_handle_t q_handle, uint_t size) 1417 { 1418 hci1394_q_buf_t *descb; 1419 hci1394_q_buf_t *datab; 1420 1421 1422 ASSERT(q_handle != NULL); 1423 TNF_PROBE_0_DEBUG(hci1394_q_ar_free_enter, HCI1394_TNF_HAL_STACK, ""); 1424 1425 descb = &q_handle->q_desc; 1426 datab = &q_handle->q_data; 1427 1428 /* 1429 * Packet is in multiple buffers. Theoretically a buffer could be broken 1430 * in more than two buffers for an ARRESP. Since the buffers should be 1431 * in at least 4K increments this will not happen since the max packet 1432 * size is 2KBytes. 1433 */ 1434 if ((datab->qb_ptrs.qp_current + size) > datab->qb_ptrs.qp_end) { 1435 /* Add IM descriptor for used buffer back into Q */ 1436 hci1394_q_ar_write_IM(q_handle, descb, 1437 datab->qb_cookie[datab->qb_ptrs.qp_current_buf 1438 ].dmac_address, 1439 datab->qb_cookie[datab->qb_ptrs.qp_current_buf].dmac_size); 1440 1441 /* Go to the next buffer */ 1442 hci1394_q_next_buf(datab); 1443 1444 /* Update next buffers pointers for partial packet */ 1445 size -= q_handle->q_space_left; 1446 datab->qb_ptrs.qp_current += size; 1447 q_handle->q_space_left = 1448 datab->qb_cookie[datab->qb_ptrs.qp_current_buf].dmac_size - 1449 size; 1450 1451 /* Change the head pointer to the next IM descriptor */ 1452 q_handle->q_head += sizeof (hci1394_desc_t); 1453 if ((q_handle->q_head + sizeof (hci1394_desc_t)) > 1454 (descb->qb_ptrs.qp_bottom + 1)) { 1455 q_handle->q_head = descb->qb_ptrs.qp_top; 1456 } 1457 1458 /* Packet is only in one buffer */ 1459 } else { 1460 q_handle->q_space_left -= size; 1461 datab->qb_ptrs.qp_current += size; 1462 } 1463 1464 TNF_PROBE_0_DEBUG(hci1394_q_ar_free_exit, HCI1394_TNF_HAL_STACK, ""); 1465 } 1466 1467 1468 /* 1469 * hci1394_q_ar_get32() 1470 * Read a quadlet of data regardless if it is in the current buffer or has 1471 * wrapped to the top buffer. If the address passed to this routine is 1472 * passed the bottom of the data buffer, this routine will automatically 1473 * wrap back to the top of the Q and look in the correct offset from the 1474 * top. Copy the data into the kernel virtual address provided. 1475 */ 1476 uint32_t 1477 hci1394_q_ar_get32(hci1394_q_handle_t q_handle, uint32_t *addr) 1478 { 1479 hci1394_q_buf_t *data; 1480 uintptr_t new_addr; 1481 uint32_t data32; 1482 1483 1484 ASSERT(q_handle != NULL); 1485 ASSERT(addr != NULL); 1486 TNF_PROBE_0_DEBUG(hci1394_q_get32_enter, HCI1394_TNF_HAL_STACK, ""); 1487 1488 data = &q_handle->q_data; 1489 1490 /* 1491 * if the data has wrapped to the top of the buffer, adjust the address. 1492 */ 1493 if ((uintptr_t)addr > (uintptr_t)data->qb_ptrs.qp_bottom) { 1494 new_addr = (uintptr_t)data->qb_ptrs.qp_top + ((uintptr_t)addr - 1495 ((uintptr_t)data->qb_ptrs.qp_bottom + (uintptr_t)1)); 1496 data32 = ddi_get32(data->qb_buf.bi_handle, 1497 (uint32_t *)new_addr); 1498 1499 /* data is before end of buffer */ 1500 } else { 1501 data32 = ddi_get32(data->qb_buf.bi_handle, addr); 1502 } 1503 1504 TNF_PROBE_0_DEBUG(hci1394_q_get32_exit, HCI1394_TNF_HAL_STACK, ""); 1505 1506 return (data32); 1507 } 1508 1509 1510 /* 1511 * hci1394_q_ar_rep_get8() 1512 * Read a byte stream of data regardless if it is contiguous or has partially 1513 * or fully wrapped to the top buffer. If the address passed to this routine 1514 * is passed the bottom of the data buffer, or address + size is past the 1515 * bottom of the data buffer. this routine will automatically wrap back to 1516 * the top of the Q and look in the correct offset from the top. Copy the 1517 * data into the kernel virtual address provided. 1518 */ 1519 void 1520 hci1394_q_ar_rep_get8(hci1394_q_handle_t q_handle, uint8_t *dest, 1521 uint8_t *q_addr, uint_t size) 1522 { 1523 hci1394_q_buf_t *data; 1524 uintptr_t new_addr; 1525 uint_t new_size; 1526 uintptr_t new_dest; 1527 1528 1529 ASSERT(q_handle != NULL); 1530 ASSERT(dest != NULL); 1531 ASSERT(q_addr != NULL); 1532 TNF_PROBE_0_DEBUG(hci1394_q_ar_rep_get8_enter, HCI1394_TNF_HAL_STACK, 1533 ""); 1534 1535 data = &q_handle->q_data; 1536 1537 /* 1538 * There are three cases: 1539 * 1) All of the data has wrapped. 1540 * 2) Some of the data has not wrapped and some has wrapped. 1541 * 3) None of the data has wrapped. 1542 */ 1543 1544 /* All of the data has wrapped, just adjust the starting address */ 1545 if ((uintptr_t)q_addr > (uintptr_t)data->qb_ptrs.qp_bottom) { 1546 new_addr = (uintptr_t)data->qb_ptrs.qp_top + 1547 ((uintptr_t)q_addr - ((uintptr_t)data->qb_ptrs.qp_bottom + 1548 (uintptr_t)1)); 1549 ddi_rep_get8(data->qb_buf.bi_handle, dest, (uint8_t *)new_addr, 1550 size, DDI_DEV_AUTOINCR); 1551 1552 /* 1553 * Some of the data has wrapped. Copy the data that hasn't wrapped, 1554 * adjust the address, then copy the rest. 1555 */ 1556 } else if (((uintptr_t)q_addr + (uintptr_t)size) > 1557 ((uintptr_t)data->qb_ptrs.qp_bottom + (uintptr_t)1)) { 1558 /* Copy first half */ 1559 new_size = (uint_t)(((uintptr_t)data->qb_ptrs.qp_bottom + 1560 (uintptr_t)1) - (uintptr_t)q_addr); 1561 ddi_rep_get8(data->qb_buf.bi_handle, dest, q_addr, new_size, 1562 DDI_DEV_AUTOINCR); 1563 1564 /* copy second half */ 1565 new_dest = (uintptr_t)dest + (uintptr_t)new_size; 1566 new_size = size - new_size; 1567 new_addr = (uintptr_t)data->qb_ptrs.qp_top; 1568 ddi_rep_get8(data->qb_buf.bi_handle, (uint8_t *)new_dest, 1569 (uint8_t *)new_addr, new_size, DDI_DEV_AUTOINCR); 1570 1571 /* None of the data has wrapped */ 1572 } else { 1573 ddi_rep_get8(data->qb_buf.bi_handle, dest, q_addr, size, 1574 DDI_DEV_AUTOINCR); 1575 } 1576 1577 TNF_PROBE_0_DEBUG(hci1394_q_ar_rep_get8_exit, HCI1394_TNF_HAL_STACK, 1578 ""); 1579 } 1580 1581 1582 /* 1583 * hci1394_q_ar_copy_to_mblk() 1584 * Read a byte stream of data regardless if it is contiguous or has partially 1585 * or fully wrapped to the top buffer. If the address passed to this routine 1586 * is passed the bottom of the data buffer, or address + size is passed the 1587 * bottom of the data buffer. this routine will automatically wrap back to 1588 * the top of the Q and look in the correct offset from the top. Copy the 1589 * data into the mblk provided. The services layer and the hal use a private 1590 * structure (h1394_mblk_t) to keep track of how much of the mblk to receive 1591 * into since we may have to break the transfer up into smaller blocks. 1592 * (i.e. a 1MByte block read would go out in 2KByte requests. 1593 */ 1594 void 1595 hci1394_q_ar_copy_to_mblk(hci1394_q_handle_t q_handle, uint8_t *addr, 1596 h1394_mblk_t *mblk) 1597 { 1598 uint8_t *new_addr; 1599 uint_t bytes_left; 1600 uint_t length; 1601 1602 1603 ASSERT(q_handle != NULL); 1604 ASSERT(addr != NULL); 1605 ASSERT(mblk != NULL); 1606 TNF_PROBE_0_DEBUG(hci1394_q_copy_to_mblk_enter, 1607 HCI1394_TNF_HAL_STACK, ""); 1608 1609 /* We return these variables to the Services Layer when we are done */ 1610 mblk->next_offset = mblk->curr_offset; 1611 mblk->next_mblk = mblk->curr_mblk; 1612 bytes_left = mblk->length; 1613 1614 /* the address we copy from will change as we change mblks */ 1615 new_addr = addr; 1616 1617 /* do while there are bytes left to copy */ 1618 do { 1619 /* 1620 * If the entire data portion of the current block transfer is 1621 * contained within a single mblk. 1622 */ 1623 if ((mblk->next_offset + bytes_left) <= 1624 (mblk->next_mblk->b_datap->db_lim)) { 1625 /* Copy the data into the mblk */ 1626 hci1394_q_ar_rep_get8(q_handle, 1627 (uint8_t *)mblk->next_offset, new_addr, bytes_left); 1628 1629 /* increment the offset */ 1630 mblk->next_offset += bytes_left; 1631 mblk->next_mblk->b_wptr = mblk->next_offset; 1632 1633 /* we have no more bytes to put into the buffer */ 1634 bytes_left = 0; 1635 1636 /* 1637 * If our offset is at the end of data in this mblk, go 1638 * to the next mblk. 1639 */ 1640 if (mblk->next_offset >= 1641 mblk->next_mblk->b_datap->db_lim) { 1642 mblk->next_mblk = mblk->next_mblk->b_cont; 1643 if (mblk->next_mblk != NULL) { 1644 mblk->next_offset = 1645 mblk->next_mblk->b_wptr; 1646 } 1647 } 1648 1649 /* 1650 * The data portion of the current block transfer is spread 1651 * across two or more mblk's 1652 */ 1653 } else { 1654 /* Figure out how much data is in this mblk */ 1655 length = mblk->next_mblk->b_datap->db_lim - 1656 mblk->next_offset; 1657 1658 /* Copy the data into the mblk */ 1659 hci1394_q_ar_rep_get8(q_handle, 1660 (uint8_t *)mblk->next_offset, new_addr, length); 1661 mblk->next_mblk->b_wptr = 1662 mblk->next_mblk->b_datap->db_lim; 1663 1664 /* 1665 * update the bytes left and address to copy from, go 1666 * to the next mblk. 1667 */ 1668 bytes_left = bytes_left - length; 1669 new_addr = (uint8_t *)((uintptr_t)new_addr + 1670 (uintptr_t)length); 1671 mblk->next_mblk = mblk->next_mblk->b_cont; 1672 ASSERT(mblk->next_mblk != NULL); 1673 mblk->next_offset = mblk->next_mblk->b_wptr; 1674 } 1675 } while (bytes_left > 0); 1676 1677 TNF_PROBE_0_DEBUG(hci1394_q_copy_to_mblk_exit, 1678 HCI1394_TNF_HAL_STACK, ""); 1679 } 1680 1681 1682 /* 1683 * hci1394_q_ar_write_IM() 1684 * Write an IM descriptor into the AR descriptor buffer passed in as qbuf. 1685 * The IO address of the data buffer is passed in io_addr. datasize is the 1686 * size of the data data buffer to receive into. 1687 */ 1688 void 1689 hci1394_q_ar_write_IM(hci1394_q_handle_t q_handle, hci1394_q_buf_t *qbuf, 1690 uint32_t io_addr, uint_t datasize) 1691 { 1692 hci1394_desc_t *desc; 1693 uint32_t data; 1694 uint32_t command_ptr; 1695 1696 1697 ASSERT(q_handle != NULL); 1698 ASSERT(qbuf != NULL); 1699 TNF_PROBE_0_DEBUG(hci1394_q_ar_write_IM_enter, HCI1394_TNF_HAL_STACK, 1700 ""); 1701 1702 /* Make sure enough room for IM */ 1703 if ((qbuf->qb_ptrs.qp_current + sizeof (hci1394_desc_t)) > 1704 (qbuf->qb_ptrs.qp_bottom + 1)) { 1705 hci1394_q_next_buf(qbuf); 1706 } else { 1707 /* Store the offset of the top of this descriptor block */ 1708 qbuf->qb_ptrs.qp_offset = (uint32_t)(qbuf->qb_ptrs.qp_current - 1709 qbuf->qb_ptrs.qp_begin); 1710 } 1711 1712 /* Setup OpenHCI IM Header */ 1713 desc = (hci1394_desc_t *)qbuf->qb_ptrs.qp_current; 1714 data = DESC_AR_IM | (datasize & DESC_HDR_REQCOUNT_MASK); 1715 ddi_put32(qbuf->qb_buf.bi_handle, &desc->hdr, data); 1716 ddi_put32(qbuf->qb_buf.bi_handle, &desc->data_addr, io_addr); 1717 ddi_put32(qbuf->qb_buf.bi_handle, &desc->branch, 0); 1718 ddi_put32(qbuf->qb_buf.bi_handle, &desc->status, datasize & 1719 DESC_ST_RESCOUNT_MASK); 1720 1721 /* 1722 * Sync buffer in case DMA engine currently running. This must be done 1723 * before writing the command pointer in the previous descriptor. 1724 */ 1725 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1726 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1727 1728 /* 1729 * Setup the command pointer. This tells the HW where to get the 1730 * descriptor we just setup. This includes the IO address along with 1731 * a 4 bit 16 byte block count. We only wrote 1 16 byte block. 1732 */ 1733 command_ptr = (uint32_t)((qbuf->qb_cookie[qbuf->qb_ptrs.qp_current_buf 1734 ].dmac_address + qbuf->qb_ptrs.qp_offset) | 1); 1735 1736 /* 1737 * if we previously setup a descriptor, add this new descriptor into 1738 * the previous descriptor's "next" pointer. 1739 */ 1740 if (q_handle->q_previous != NULL) { 1741 ddi_put32(qbuf->qb_buf.bi_handle, 1742 &q_handle->q_previous->branch, command_ptr); 1743 /* Sync buffer again, this gets the command pointer */ 1744 (void) ddi_dma_sync(qbuf->qb_buf.bi_dma_handle, 0, 1745 qbuf->qb_buf.bi_length, DDI_DMA_SYNC_FORDEV); 1746 } 1747 1748 /* this is the new previous descriptor. Update the current pointer */ 1749 q_handle->q_previous = desc; 1750 qbuf->qb_ptrs.qp_current += sizeof (hci1394_desc_t); 1751 1752 /* If the DMA is not running, start it */ 1753 if (q_handle->q_dma_running == B_FALSE) { 1754 q_handle->q_info.qi_start(q_handle->q_info.qi_callback_arg, 1755 command_ptr); 1756 q_handle->q_dma_running = B_TRUE; 1757 /* the DMA is running, wake it up */ 1758 } else { 1759 q_handle->q_info.qi_wake(q_handle->q_info.qi_callback_arg); 1760 } 1761 1762 TNF_PROBE_0_DEBUG(hci1394_q_ar_write_IM_exit, HCI1394_TNF_HAL_STACK, 1763 ""); 1764 } 1765