xref: /illumos-gate/usr/src/uts/common/io/hxge/hpi.h (revision 2d6eb4a5)
1*3dec9fcdSqs148142 /*
2*3dec9fcdSqs148142  * CDDL HEADER START
3*3dec9fcdSqs148142  *
4*3dec9fcdSqs148142  * The contents of this file are subject to the terms of the
5*3dec9fcdSqs148142  * Common Development and Distribution License (the "License").
6*3dec9fcdSqs148142  * You may not use this file except in compliance with the License.
7*3dec9fcdSqs148142  *
8*3dec9fcdSqs148142  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*3dec9fcdSqs148142  * or http://www.opensolaris.org/os/licensing.
10*3dec9fcdSqs148142  * See the License for the specific language governing permissions
11*3dec9fcdSqs148142  * and limitations under the License.
12*3dec9fcdSqs148142  *
13*3dec9fcdSqs148142  * When distributing Covered Code, include this CDDL HEADER in each
14*3dec9fcdSqs148142  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*3dec9fcdSqs148142  * If applicable, add the following below this CDDL HEADER, with the
16*3dec9fcdSqs148142  * fields enclosed by brackets "[]" replaced with your own identifying
17*3dec9fcdSqs148142  * information: Portions Copyright [yyyy] [name of copyright owner]
18*3dec9fcdSqs148142  *
19*3dec9fcdSqs148142  * CDDL HEADER END
20*3dec9fcdSqs148142  */
21*3dec9fcdSqs148142 /*
22*3dec9fcdSqs148142  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23*3dec9fcdSqs148142  * Use is subject to license terms.
24*3dec9fcdSqs148142  */
25*3dec9fcdSqs148142 
26*3dec9fcdSqs148142 #ifndef _HPI_H
27*3dec9fcdSqs148142 #define	_HPI_H
28*3dec9fcdSqs148142 
29*3dec9fcdSqs148142 #ifdef	__cplusplus
30*3dec9fcdSqs148142 extern "C" {
31*3dec9fcdSqs148142 #endif
32*3dec9fcdSqs148142 
33*3dec9fcdSqs148142 #include <sys/types.h>
34*3dec9fcdSqs148142 #include <hxge_common_impl.h>
35*3dec9fcdSqs148142 #include <hxge_common.h>
36*3dec9fcdSqs148142 
37*3dec9fcdSqs148142 typedef	uint32_t hpi_status_t;
38*3dec9fcdSqs148142 
39*3dec9fcdSqs148142 /* Common Block ID */
40*3dec9fcdSqs148142 #define	VMAC_BLK_ID			0x1
41*3dec9fcdSqs148142 #define	TXDMA_BLK_ID			0x2
42*3dec9fcdSqs148142 #define	RXDMA_BLK_ID			0x3
43*3dec9fcdSqs148142 #define	PFC_BLK_ID			0x4
44*3dec9fcdSqs148142 #define	VIR_BLK_ID			0x5
45*3dec9fcdSqs148142 #define	PEU_BLK_ID			0x6
46*3dec9fcdSqs148142 
47*3dec9fcdSqs148142 /* Common HW error code */
48*3dec9fcdSqs148142 /* HW unable to exit from reset state. */
49*3dec9fcdSqs148142 #define	RESET_FAILED			0x81
50*3dec9fcdSqs148142 
51*3dec9fcdSqs148142 /* Write operation failed on indirect write. */
52*3dec9fcdSqs148142 #define	WRITE_FAILED			0x82
53*3dec9fcdSqs148142 /* Read operation failed on indirect read.	 */
54*3dec9fcdSqs148142 #define	READ_FAILED			0x83
55*3dec9fcdSqs148142 
56*3dec9fcdSqs148142 /* Common SW errors code */
57*3dec9fcdSqs148142 
58*3dec9fcdSqs148142 #define	PORT_INVALID			0x41	/* Invalid port number */
59*3dec9fcdSqs148142 #define	CHANNEL_INVALID			0x42	/* Invalid dma channel number */
60*3dec9fcdSqs148142 #define	OPCODE_INVALID			0x43	/* Invalid opcode */
61*3dec9fcdSqs148142 #define	REGISTER_INVALID		0x44	/* Invalid register number */
62*3dec9fcdSqs148142 #define	COUNTER_INVALID			0x45	/* Invalid counter number */
63*3dec9fcdSqs148142 #define	CONFIG_INVALID			0x46	/* Invalid config input */
64*3dec9fcdSqs148142 #define	LOGICAL_PAGE_INVALID		0x47	/* Invalid logical page # */
65*3dec9fcdSqs148142 #define	VLAN_INVALID			0x48	/* Invalid Vlan ID */
66*3dec9fcdSqs148142 #define	RDC_TAB_INVALID			0x49	/* Invalid RDC Group Number */
67*3dec9fcdSqs148142 #define	LOCATION_INVALID		0x4a	/* Invalid Entry Location */
68*3dec9fcdSqs148142 
69*3dec9fcdSqs148142 #define	HPI_SUCCESS			0		/* Operation succeed */
70*3dec9fcdSqs148142 #define	HPI_FAILURE			0x80000000	/* Operation failed */
71*3dec9fcdSqs148142 
72*3dec9fcdSqs148142 /*
73*3dec9fcdSqs148142  * Block identifier starts at bit 8.
74*3dec9fcdSqs148142  */
75*3dec9fcdSqs148142 #define	HPI_BLOCK_ID_SHIFT		8
76*3dec9fcdSqs148142 
77*3dec9fcdSqs148142 /*
78*3dec9fcdSqs148142  * Port, channel and misc. information starts at bit 12.
79*3dec9fcdSqs148142  */
80*3dec9fcdSqs148142 #define	HPI_PORT_CHAN_SHIFT		12
81*3dec9fcdSqs148142 
82*3dec9fcdSqs148142 /*
83*3dec9fcdSqs148142  * Software Block specific error codes start at 0x50.
84*3dec9fcdSqs148142  */
85*3dec9fcdSqs148142 #define	HPI_BK_ERROR_START		0x50
86*3dec9fcdSqs148142 
87*3dec9fcdSqs148142 /*
88*3dec9fcdSqs148142  * Hardware block specific error codes start at 0x90.
89*3dec9fcdSqs148142  */
90*3dec9fcdSqs148142 #define	HPI_BK_HW_ER_START		0x90
91*3dec9fcdSqs148142 
92*3dec9fcdSqs148142 /* Structures for register tracing */
93*3dec9fcdSqs148142 
94*3dec9fcdSqs148142 typedef struct _rt_buf {
95*3dec9fcdSqs148142 	uint32_t	ctl_addr;
96*3dec9fcdSqs148142 	uint32_t	val_l32;
97*3dec9fcdSqs148142 	uint32_t	val_h32;
98*3dec9fcdSqs148142 } rt_buf_t;
99*3dec9fcdSqs148142 
100*3dec9fcdSqs148142 /*
101*3dec9fcdSqs148142  * Control Address field format
102*3dec9fcdSqs148142  *
103*3dec9fcdSqs148142  * Bit 0 - 23: Address
104*3dec9fcdSqs148142  * Bit 24 - 25: Function Number
105*3dec9fcdSqs148142  * Bit 26 - 29: Instance Number
106*3dec9fcdSqs148142  * Bit 30: Read/Write Direction bit
107*3dec9fcdSqs148142  * Bit 31: Invalid bit
108*3dec9fcdSqs148142  */
109*3dec9fcdSqs148142 
110*3dec9fcdSqs148142 #define	MAX_RTRACE_ENTRIES	1024
111*3dec9fcdSqs148142 #define	MAX_RTRACE_IOC_ENTRIES	64
112*3dec9fcdSqs148142 #define	TRACE_ADDR_MASK		0x00FFFFFF
113*3dec9fcdSqs148142 #define	TRACE_FUNC_MASK		0x03000000
114*3dec9fcdSqs148142 #define	TRACE_INST_MASK		0x3C000000
115*3dec9fcdSqs148142 #define	TRACE_CTL_WR		0x40000000
116*3dec9fcdSqs148142 #define	TRACE_CTL_INVALID	0x80000000
117*3dec9fcdSqs148142 #define	TRACE_FUNC_SHIFT	24
118*3dec9fcdSqs148142 #define	TRACE_INST_SHIFT	26
119*3dec9fcdSqs148142 #define	MSG_BUF_SIZE		1024
120*3dec9fcdSqs148142 
121*3dec9fcdSqs148142 
122*3dec9fcdSqs148142 typedef struct _rtrace {
123*3dec9fcdSqs148142 	uint16_t	next_idx;
124*3dec9fcdSqs148142 	uint16_t	last_idx;
125*3dec9fcdSqs148142 	boolean_t	wrapped;
126*3dec9fcdSqs148142 	rt_buf_t	buf[MAX_RTRACE_ENTRIES];
127*3dec9fcdSqs148142 } rtrace_t;
128*3dec9fcdSqs148142 
129*3dec9fcdSqs148142 /* Configuration options */
130*3dec9fcdSqs148142 typedef enum config_op {
131*3dec9fcdSqs148142 	DISABLE = 0,
132*3dec9fcdSqs148142 	ENABLE,
133*3dec9fcdSqs148142 	INIT
134*3dec9fcdSqs148142 } config_op_t;
135*3dec9fcdSqs148142 
136*3dec9fcdSqs148142 /* I/O options */
137*3dec9fcdSqs148142 typedef enum io_op {
138*3dec9fcdSqs148142 	OP_SET = 0,
139*3dec9fcdSqs148142 	OP_GET,
140*3dec9fcdSqs148142 	OP_UPDATE,
141*3dec9fcdSqs148142 	OP_CLEAR
142*3dec9fcdSqs148142 } io_op_t;
143*3dec9fcdSqs148142 
144*3dec9fcdSqs148142 /* HPI Handle */
145*3dec9fcdSqs148142 typedef	struct	_hpi_handle_function {
146*3dec9fcdSqs148142 	uint16_t		instance;
147*3dec9fcdSqs148142 	uint16_t		function;
148*3dec9fcdSqs148142 } hpi_handle_function_t;
149*3dec9fcdSqs148142 
150*3dec9fcdSqs148142 /* HPI Handle */
151*3dec9fcdSqs148142 typedef	struct	_hpi_handle {
152*3dec9fcdSqs148142 	hpi_reg_handle_t	regh;
153*3dec9fcdSqs148142 	hpi_reg_ptr_t		regp;
154*3dec9fcdSqs148142 	boolean_t		is_vraddr; /* virtualization region address */
155*3dec9fcdSqs148142 	hpi_handle_function_t	function;
156*3dec9fcdSqs148142 	void			*hxgep;
157*3dec9fcdSqs148142 } hpi_handle_t;
158*3dec9fcdSqs148142 
159*3dec9fcdSqs148142 extern	rtrace_t hpi_rtracebuf;
160*3dec9fcdSqs148142 void hpi_rtrace_update(hpi_handle_t handle, boolean_t wr, rtrace_t *rt,
161*3dec9fcdSqs148142     uint32_t addr, uint64_t val);
162*3dec9fcdSqs148142 void hpi_rtrace_buf_init(rtrace_t *rt);
163*3dec9fcdSqs148142 
164*3dec9fcdSqs148142 void hpi_debug_msg(hpi_handle_function_t function, uint64_t level,
165*3dec9fcdSqs148142     char *fmt, ...);
166*3dec9fcdSqs148142 
167*3dec9fcdSqs148142 #ifdef	HPI_DEBUG
168*3dec9fcdSqs148142 #define	HPI_DEBUG_MSG(params) hpi_debug_msg params
169*3dec9fcdSqs148142 #else
170*3dec9fcdSqs148142 #define	HPI_DEBUG_MSG(params)
171*3dec9fcdSqs148142 #endif
172*3dec9fcdSqs148142 
173*3dec9fcdSqs148142 #define	HPI_ERROR_MSG(params) hpi_debug_msg params
174*3dec9fcdSqs148142 
175*3dec9fcdSqs148142 #ifdef	__cplusplus
176*3dec9fcdSqs148142 }
177*3dec9fcdSqs148142 #endif
178*3dec9fcdSqs148142 
179*3dec9fcdSqs148142 #endif	/* _HPI_H */
180