16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 22*678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _NPI_MAC_H 276f45ec7bSml29623 #define _NPI_MAC_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 #include <npi.h> 346f45ec7bSml29623 #include <nxge_mac_hw.h> 356f45ec7bSml29623 #include <nxge_mii.h> 366f45ec7bSml29623 376f45ec7bSml29623 typedef struct _npi_mac_addr { 386f45ec7bSml29623 uint16_t w0; 396f45ec7bSml29623 uint16_t w1; 406f45ec7bSml29623 uint16_t w2; 416f45ec7bSml29623 } npi_mac_addr_t; 426f45ec7bSml29623 436f45ec7bSml29623 typedef enum npi_mac_attr { 446f45ec7bSml29623 MAC_PORT_MODE = 0, 456f45ec7bSml29623 MAC_PORT_FRAME_SIZE, 466f45ec7bSml29623 MAC_PORT_ADDR, 476f45ec7bSml29623 MAC_PORT_ADDR_FILTER, 486f45ec7bSml29623 MAC_PORT_ADDR_FILTER_MASK, 496f45ec7bSml29623 XMAC_PORT_IPG, 506f45ec7bSml29623 XMAC_10G_PORT_IPG, 516f45ec7bSml29623 BMAC_PORT_MAX_BURST_SIZE, 526f45ec7bSml29623 BMAC_PORT_PA_SIZE, 536f45ec7bSml29623 BMAC_PORT_CTRL_TYPE 546f45ec7bSml29623 } npi_mac_attr_t; 556f45ec7bSml29623 566f45ec7bSml29623 /* MAC Mode options */ 576f45ec7bSml29623 586f45ec7bSml29623 typedef enum npi_mac_mode_e { 596f45ec7bSml29623 MAC_MII_MODE = 0, 606f45ec7bSml29623 MAC_GMII_MODE, 616f45ec7bSml29623 MAC_XGMII_MODE 626f45ec7bSml29623 } npi_mac_mode_t; 636f45ec7bSml29623 646f45ec7bSml29623 typedef enum npi_mac_reset_e { 656f45ec7bSml29623 TX_MAC_RESET = 1, 666f45ec7bSml29623 RX_MAC_RESET, 676f45ec7bSml29623 XTX_MAC_REG_RESET, 686f45ec7bSml29623 XRX_MAC_REG_RESET, 696f45ec7bSml29623 XTX_MAC_LOGIC_RESET, 706f45ec7bSml29623 XRX_MAC_LOGIC_RESET, 716f45ec7bSml29623 XTX_MAC_RESET_ALL, 726f45ec7bSml29623 XRX_MAC_RESET_ALL, 736f45ec7bSml29623 BMAC_RESET_ALL, 746f45ec7bSml29623 XMAC_RESET_ALL 756f45ec7bSml29623 } npi_mac_reset_t; 766f45ec7bSml29623 776f45ec7bSml29623 typedef enum xmac_tx_iconfig_e { 786f45ec7bSml29623 ICFG_XMAC_TX_FRAME_XMIT = XMAC_TX_FRAME_XMIT, 796f45ec7bSml29623 ICFG_XMAC_TX_UNDERRUN = XMAC_TX_UNDERRUN, 806f45ec7bSml29623 ICFG_XMAC_TX_MAX_PACKET_ERR = XMAC_TX_MAX_PACKET_ERR, 816f45ec7bSml29623 ICFG_XMAC_TX_OVERFLOW = XMAC_TX_OVERFLOW, 826f45ec7bSml29623 ICFG_XMAC_TX_FIFO_XFR_ERR = XMAC_TX_FIFO_XFR_ERR, 836f45ec7bSml29623 ICFG_XMAC_TX_BYTE_CNT_EXP = XMAC_TX_BYTE_CNT_EXP, 846f45ec7bSml29623 ICFG_XMAC_TX_FRAME_CNT_EXP = XMAC_TX_FRAME_CNT_EXP, 856f45ec7bSml29623 ICFG_XMAC_TX_ALL = (XMAC_TX_FRAME_XMIT | XMAC_TX_UNDERRUN | 866f45ec7bSml29623 XMAC_TX_MAX_PACKET_ERR | XMAC_TX_OVERFLOW | 876f45ec7bSml29623 XMAC_TX_FIFO_XFR_ERR | XMAC_TX_BYTE_CNT_EXP | 886f45ec7bSml29623 XMAC_TX_FRAME_CNT_EXP) 896f45ec7bSml29623 } xmac_tx_iconfig_t; 906f45ec7bSml29623 916f45ec7bSml29623 typedef enum xmac_rx_iconfig_e { 926f45ec7bSml29623 ICFG_XMAC_RX_FRAME_RCVD = XMAC_RX_FRAME_RCVD, 936f45ec7bSml29623 ICFG_XMAC_RX_OVERFLOW = XMAC_RX_OVERFLOW, 946f45ec7bSml29623 ICFG_XMAC_RX_UNDERFLOW = XMAC_RX_UNDERFLOW, 956f45ec7bSml29623 ICFG_XMAC_RX_CRC_ERR_CNT_EXP = XMAC_RX_CRC_ERR_CNT_EXP, 966f45ec7bSml29623 ICFG_XMAC_RX_LEN_ERR_CNT_EXP = XMAC_RX_LEN_ERR_CNT_EXP, 976f45ec7bSml29623 ICFG_XMAC_RX_VIOL_ERR_CNT_EXP = XMAC_RX_VIOL_ERR_CNT_EXP, 986f45ec7bSml29623 ICFG_XMAC_RX_OCT_CNT_EXP = XMAC_RX_OCT_CNT_EXP, 996f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT1_EXP = XMAC_RX_HST_CNT1_EXP, 1006f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT2_EXP = XMAC_RX_HST_CNT2_EXP, 1016f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT3_EXP = XMAC_RX_HST_CNT3_EXP, 1026f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT4_EXP = XMAC_RX_HST_CNT4_EXP, 1036f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT5_EXP = XMAC_RX_HST_CNT5_EXP, 1046f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT6_EXP = XMAC_RX_HST_CNT6_EXP, 1056f45ec7bSml29623 ICFG_XMAC_RX_BCAST_CNT_EXP = XMAC_RX_BCAST_CNT_EXP, 1066f45ec7bSml29623 ICFG_XMAC_RX_MCAST_CNT_EXP = XMAC_RX_MCAST_CNT_EXP, 1076f45ec7bSml29623 ICFG_XMAC_RX_FRAG_CNT_EXP = XMAC_RX_FRAG_CNT_EXP, 1086f45ec7bSml29623 ICFG_XMAC_RX_ALIGNERR_CNT_EXP = XMAC_RX_ALIGNERR_CNT_EXP, 1096f45ec7bSml29623 ICFG_XMAC_RX_LINK_FLT_CNT_EXP = XMAC_RX_LINK_FLT_CNT_EXP, 1106f45ec7bSml29623 ICFG_XMAC_RX_HST_CNT7_EXP = XMAC_RX_HST_CNT7_EXP, 1116f45ec7bSml29623 ICFG_XMAC_RX_REMOTE_FLT_DET = XMAC_RX_REMOTE_FLT_DET, 1126f45ec7bSml29623 ICFG_XMAC_RX_LOCAL_FLT_DET = XMAC_RX_LOCAL_FLT_DET, 1136f45ec7bSml29623 ICFG_XMAC_RX_ALL = (XMAC_RX_FRAME_RCVD | XMAC_RX_OVERFLOW | 1146f45ec7bSml29623 XMAC_RX_UNDERFLOW | XMAC_RX_CRC_ERR_CNT_EXP | 1156f45ec7bSml29623 XMAC_RX_LEN_ERR_CNT_EXP | 1166f45ec7bSml29623 XMAC_RX_VIOL_ERR_CNT_EXP | 1176f45ec7bSml29623 XMAC_RX_OCT_CNT_EXP | XMAC_RX_HST_CNT1_EXP | 1186f45ec7bSml29623 XMAC_RX_HST_CNT2_EXP | XMAC_RX_HST_CNT3_EXP | 1196f45ec7bSml29623 XMAC_RX_HST_CNT4_EXP | XMAC_RX_HST_CNT5_EXP | 1206f45ec7bSml29623 XMAC_RX_HST_CNT6_EXP | XMAC_RX_BCAST_CNT_EXP | 1216f45ec7bSml29623 XMAC_RX_MCAST_CNT_EXP | XMAC_RX_FRAG_CNT_EXP | 1226f45ec7bSml29623 XMAC_RX_ALIGNERR_CNT_EXP | 1236f45ec7bSml29623 XMAC_RX_LINK_FLT_CNT_EXP | 1246f45ec7bSml29623 XMAC_RX_HST_CNT7_EXP | 1256f45ec7bSml29623 XMAC_RX_REMOTE_FLT_DET | XMAC_RX_LOCAL_FLT_DET) 1266f45ec7bSml29623 } xmac_rx_iconfig_t; 1276f45ec7bSml29623 1286f45ec7bSml29623 typedef enum xmac_ctl_iconfig_e { 1296f45ec7bSml29623 ICFG_XMAC_CTRL_PAUSE_RCVD = XMAC_CTRL_PAUSE_RCVD, 1306f45ec7bSml29623 ICFG_XMAC_CTRL_PAUSE_STATE = XMAC_CTRL_PAUSE_STATE, 1316f45ec7bSml29623 ICFG_XMAC_CTRL_NOPAUSE_STATE = XMAC_CTRL_NOPAUSE_STATE, 1326f45ec7bSml29623 ICFG_XMAC_CTRL_ALL = (XMAC_CTRL_PAUSE_RCVD | XMAC_CTRL_PAUSE_STATE | 1336f45ec7bSml29623 XMAC_CTRL_NOPAUSE_STATE) 1346f45ec7bSml29623 } xmac_ctl_iconfig_t; 1356f45ec7bSml29623 1366f45ec7bSml29623 1376f45ec7bSml29623 typedef enum bmac_tx_iconfig_e { 1386f45ec7bSml29623 ICFG_BMAC_TX_FRAME_SENT = MAC_TX_FRAME_XMIT, 1396f45ec7bSml29623 ICFG_BMAC_TX_UNDERFLOW = MAC_TX_UNDERRUN, 1406f45ec7bSml29623 ICFG_BMAC_TX_MAXPKTSZ_ERR = MAC_TX_MAX_PACKET_ERR, 1416f45ec7bSml29623 ICFG_BMAC_TX_BYTE_CNT_EXP = MAC_TX_BYTE_CNT_EXP, 1426f45ec7bSml29623 ICFG_BMAC_TX_FRAME_CNT_EXP = MAC_TX_FRAME_CNT_EXP, 1436f45ec7bSml29623 ICFG_BMAC_TX_ALL = (MAC_TX_FRAME_XMIT | MAC_TX_UNDERRUN | 1446f45ec7bSml29623 MAC_TX_MAX_PACKET_ERR | MAC_TX_BYTE_CNT_EXP | 1456f45ec7bSml29623 MAC_TX_FRAME_CNT_EXP) 1466f45ec7bSml29623 } bmac_tx_iconfig_t; 1476f45ec7bSml29623 1486f45ec7bSml29623 typedef enum bmac_rx_iconfig_e { 1496f45ec7bSml29623 ICFG_BMAC_RX_FRAME_RCVD = MAC_RX_FRAME_RECV, 1506f45ec7bSml29623 ICFG_BMAC_RX_OVERFLOW = MAC_RX_OVERFLOW, 1516f45ec7bSml29623 ICFG_BMAC_RX_FRAME_CNT_EXP = MAC_RX_FRAME_COUNT, 1526f45ec7bSml29623 ICFG_BMAC_RX_CRC_ERR_CNT_EXP = MAC_RX_ALIGN_ERR, 1536f45ec7bSml29623 ICFG_BMAC_RX_LEN_ERR_CNT_EXP = MAC_RX_CRC_ERR, 1546f45ec7bSml29623 ICFG_BMAC_RX_VIOL_ERR_CNT_EXP = MAC_RX_LEN_ERR, 1556f45ec7bSml29623 ICFG_BMAC_RX_BYTE_CNT_EXP = MAC_RX_VIOL_ERR, 1566f45ec7bSml29623 ICFG_BMAC_RX_ALIGNERR_CNT_EXP = MAC_RX_BYTE_CNT_EXP, 1576f45ec7bSml29623 ICFG_BMAC_RX_ALL = (MAC_RX_FRAME_RECV | MAC_RX_OVERFLOW | 1586f45ec7bSml29623 MAC_RX_FRAME_COUNT | MAC_RX_ALIGN_ERR | 1596f45ec7bSml29623 MAC_RX_CRC_ERR | MAC_RX_LEN_ERR | 1606f45ec7bSml29623 MAC_RX_VIOL_ERR | MAC_RX_BYTE_CNT_EXP) 1616f45ec7bSml29623 } bmac_rx_iconfig_t; 1626f45ec7bSml29623 1636f45ec7bSml29623 typedef enum bmac_ctl_iconfig_e { 1646f45ec7bSml29623 ICFG_BMAC_CTL_RCVPAUSE = MAC_CTRL_PAUSE_RECEIVED, 1656f45ec7bSml29623 ICFG_BMAC_CTL_INPAUSE_ST = MAC_CTRL_PAUSE_STATE, 1666f45ec7bSml29623 ICFG_BMAC_CTL_INNOTPAUSE_ST = MAC_CTRL_NOPAUSE_STATE, 1676f45ec7bSml29623 ICFG_BMAC_CTL_ALL = (MAC_CTRL_PAUSE_RECEIVED | MAC_CTRL_PAUSE_STATE | 1686f45ec7bSml29623 MAC_CTRL_NOPAUSE_STATE) 1696f45ec7bSml29623 } bmac_ctl_iconfig_t; 1706f45ec7bSml29623 1716f45ec7bSml29623 typedef enum xmac_tx_config_e { 1726f45ec7bSml29623 CFG_XMAC_TX = 0x00000001, 1736f45ec7bSml29623 CFG_XMAC_TX_STRETCH_MODE = 0x00000002, 1746f45ec7bSml29623 CFG_XMAC_VAR_IPG = 0x00000004, 1756f45ec7bSml29623 CFG_XMAC_TX_CRC = 0x00000008, 1766f45ec7bSml29623 CFG_XMAC_TX_ALL = 0x0000000F 1776f45ec7bSml29623 } xmac_tx_config_t; 1786f45ec7bSml29623 1796f45ec7bSml29623 typedef enum xmac_rx_config_e { 1806f45ec7bSml29623 CFG_XMAC_RX = 0x00000001, 1816f45ec7bSml29623 CFG_XMAC_RX_PROMISCUOUS = 0x00000002, 1826f45ec7bSml29623 CFG_XMAC_RX_PROMISCUOUSGROUP = 0x00000004, 1836f45ec7bSml29623 CFG_XMAC_RX_ERRCHK = 0x00000008, 1846f45ec7bSml29623 CFG_XMAC_RX_CRC_CHK = 0x00000010, 1856f45ec7bSml29623 CFG_XMAC_RX_RESV_MULTICAST = 0x00000020, 1866f45ec7bSml29623 CFG_XMAC_RX_CODE_VIO_CHK = 0x00000040, 1876f45ec7bSml29623 CFG_XMAC_RX_HASH_FILTER = 0x00000080, 1886f45ec7bSml29623 CFG_XMAC_RX_ADDR_FILTER = 0x00000100, 1896f45ec7bSml29623 CFG_XMAC_RX_STRIP_CRC = 0x00000200, 1906f45ec7bSml29623 CFG_XMAC_RX_PAUSE = 0x00000400, 1916f45ec7bSml29623 CFG_XMAC_RX_PASS_FC_FRAME = 0x00000800, 1926f45ec7bSml29623 CFG_XMAC_RX_MAC2IPP_PKT_CNT = 0x00001000, 1936f45ec7bSml29623 CFG_XMAC_RX_ALL = 0x00001FFF 1946f45ec7bSml29623 } xmac_rx_config_t; 1956f45ec7bSml29623 1966f45ec7bSml29623 typedef enum xmac_xif_config_e { 1976f45ec7bSml29623 CFG_XMAC_XIF_LED_FORCE = 0x00000001, 1986f45ec7bSml29623 CFG_XMAC_XIF_LED_POLARITY = 0x00000002, 1996f45ec7bSml29623 CFG_XMAC_XIF_SEL_POR_CLK_SRC = 0x00000004, 2006f45ec7bSml29623 CFG_XMAC_XIF_TX_OUTPUT = 0x00000008, 2016f45ec7bSml29623 CFG_XMAC_XIF_LOOPBACK = 0x00000010, 2026f45ec7bSml29623 CFG_XMAC_XIF_LFS = 0x00000020, 2036f45ec7bSml29623 CFG_XMAC_XIF_XPCS_BYPASS = 0x00000040, 2046f45ec7bSml29623 CFG_XMAC_XIF_1G_PCS_BYPASS = 0x00000080, 2056f45ec7bSml29623 CFG_XMAC_XIF_SEL_CLK_25MHZ = 0x00000100, 2066f45ec7bSml29623 CFG_XMAC_XIF_ALL = 0x000001FF 2076f45ec7bSml29623 } xmac_xif_config_t; 2086f45ec7bSml29623 2096f45ec7bSml29623 typedef enum bmac_tx_config_e { 2106f45ec7bSml29623 CFG_BMAC_TX = 0x00000001, 2116f45ec7bSml29623 CFG_BMAC_TX_CRC = 0x00000002, 2126f45ec7bSml29623 CFG_BMAC_TX_ALL = 0x00000003 2136f45ec7bSml29623 } bmac_tx_config_t; 2146f45ec7bSml29623 2156f45ec7bSml29623 typedef enum bmac_rx_config_e { 2166f45ec7bSml29623 CFG_BMAC_RX = 0x00000001, 2176f45ec7bSml29623 CFG_BMAC_RX_STRIP_PAD = 0x00000002, 2186f45ec7bSml29623 CFG_BMAC_RX_STRIP_CRC = 0x00000004, 2196f45ec7bSml29623 CFG_BMAC_RX_PROMISCUOUS = 0x00000008, 2206f45ec7bSml29623 CFG_BMAC_RX_PROMISCUOUSGROUP = 0x00000010, 2216f45ec7bSml29623 CFG_BMAC_RX_HASH_FILTER = 0x00000020, 2226f45ec7bSml29623 CFG_BMAC_RX_ADDR_FILTER = 0x00000040, 2236f45ec7bSml29623 CFG_BMAC_RX_DISCARD_ON_ERR = 0x00000080, 2246f45ec7bSml29623 CFG_BMAC_RX_ALL = 0x000000FF 2256f45ec7bSml29623 } bmac_rx_config_t; 2266f45ec7bSml29623 2276f45ec7bSml29623 typedef enum bmac_xif_config_e { 2286f45ec7bSml29623 CFG_BMAC_XIF_TX_OUTPUT = 0x00000001, 2296f45ec7bSml29623 CFG_BMAC_XIF_LOOPBACK = 0x00000002, 2306f45ec7bSml29623 CFG_BMAC_XIF_GMII_MODE = 0x00000008, 2316f45ec7bSml29623 CFG_BMAC_XIF_LINKLED = 0x00000020, 2326f45ec7bSml29623 CFG_BMAC_XIF_LED_POLARITY = 0x00000040, 2336f45ec7bSml29623 CFG_BMAC_XIF_SEL_CLK_25MHZ = 0x00000080, 2346f45ec7bSml29623 CFG_BMAC_XIF_ALL = 0x000000FF 2356f45ec7bSml29623 } bmac_xif_config_t; 2366f45ec7bSml29623 2376f45ec7bSml29623 2386f45ec7bSml29623 typedef enum xmac_ipg_e { 2396f45ec7bSml29623 XGMII_IPG_12_15 = 0, 2406f45ec7bSml29623 XGMII_IPG_16_19, 2416f45ec7bSml29623 XGMII_IPG_20_23, 2426f45ec7bSml29623 MII_GMII_IPG_12, 2436f45ec7bSml29623 MII_GMII_IPG_13, 2446f45ec7bSml29623 MII_GMII_IPG_14, 2456f45ec7bSml29623 MII_GMII_IPG_15, 2466f45ec7bSml29623 MII_GMII_IPG_16 2476f45ec7bSml29623 } xmac_ipg_t; 2486f45ec7bSml29623 2496f45ec7bSml29623 typedef enum xpcs_reg_e { 2506f45ec7bSml29623 XPCS_REG_CONTROL1, 2516f45ec7bSml29623 XPCS_REG_STATUS1, 2526f45ec7bSml29623 XPCS_REG_DEVICE_ID, 2536f45ec7bSml29623 XPCS_REG_SPEED_ABILITY, 2546f45ec7bSml29623 XPCS_REG_DEVICE_IN_PKG, 2556f45ec7bSml29623 XPCS_REG_CONTROL2, 2566f45ec7bSml29623 XPCS_REG_STATUS2, 2576f45ec7bSml29623 XPCS_REG_PKG_ID, 2586f45ec7bSml29623 XPCS_REG_STATUS, 2596f45ec7bSml29623 XPCS_REG_TEST_CONTROL, 2606f45ec7bSml29623 XPCS_REG_CONFIG_VENDOR1, 2616f45ec7bSml29623 XPCS_REG_DIAG_VENDOR2, 2626f45ec7bSml29623 XPCS_REG_MASK1, 2636f45ec7bSml29623 XPCS_REG_PACKET_COUNTER, 2646f45ec7bSml29623 XPCS_REG_TX_STATEMACHINE, 2656f45ec7bSml29623 XPCS_REG_DESCWERR_COUNTER, 2666f45ec7bSml29623 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, 2676f45ec7bSml29623 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, 2686f45ec7bSml29623 XPCS_REG_TRAINING_VECTOR 2696f45ec7bSml29623 } xpcs_reg_t; 2706f45ec7bSml29623 2716f45ec7bSml29623 #define IS_XMAC_PORT_NUM_VALID(portn)\ 2726f45ec7bSml29623 ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) 2736f45ec7bSml29623 2746f45ec7bSml29623 #define IS_BMAC_PORT_NUM_VALID(portn)\ 2756f45ec7bSml29623 ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1)) 2766f45ec7bSml29623 2776f45ec7bSml29623 #define XMAC_REG_WR(handle, portn, reg, val)\ 2786f45ec7bSml29623 NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val)) 2796f45ec7bSml29623 2806f45ec7bSml29623 #define XMAC_REG_RD(handle, portn, reg, val_p)\ 2816f45ec7bSml29623 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p)) 2826f45ec7bSml29623 2836f45ec7bSml29623 #define BMAC_REG_WR(handle, portn, reg, val)\ 2846f45ec7bSml29623 NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val)) 2856f45ec7bSml29623 2866f45ec7bSml29623 #define BMAC_REG_RD(handle, portn, reg, val_p)\ 2876f45ec7bSml29623 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p)) 2886f45ec7bSml29623 2896f45ec7bSml29623 #define PCS_REG_WR(handle, portn, reg, val)\ 2906f45ec7bSml29623 NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val)) 2916f45ec7bSml29623 2926f45ec7bSml29623 #define PCS_REG_RD(handle, portn, reg, val_p)\ 2936f45ec7bSml29623 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p)) 2946f45ec7bSml29623 2956f45ec7bSml29623 #define XPCS_REG_WR(handle, portn, reg, val)\ 2966f45ec7bSml29623 NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val)) 2976f45ec7bSml29623 2986f45ec7bSml29623 #define XPCS_REG_RD(handle, portn, reg, val_p)\ 2996f45ec7bSml29623 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p)) 3006f45ec7bSml29623 3016f45ec7bSml29623 #define MIF_REG_WR(handle, reg, val)\ 3026f45ec7bSml29623 NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val)) 3036f45ec7bSml29623 3046f45ec7bSml29623 #define MIF_REG_RD(handle, reg, val_p)\ 3056f45ec7bSml29623 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 3066f45ec7bSml29623 3076f45ec7bSml29623 3086f45ec7bSml29623 /* 3096f45ec7bSml29623 * When MIF_REG_RD is called inside a poll loop and if the poll takes 3106f45ec7bSml29623 * very long time to complete, then each poll will print a rt_show_reg 3116f45ec7bSml29623 * result on the screen and the rtrace "register show" result may 3126f45ec7bSml29623 * become too messy to read. The solution is to call MIF_REG_RD_NO_SHOW 3136f45ec7bSml29623 * instead of MIF_REG_RD in a polling loop. When COSIM or REG_SHOW is 3146f45ec7bSml29623 * not defined, this macro is the same as MIF_REG_RD. When both COSIM 3156f45ec7bSml29623 * and REG_SHOW are defined, this macro calls NXGE_REG_RD64_NO_SHOW 3166f45ec7bSml29623 * which does not call rt_show_reg. 3176f45ec7bSml29623 */ 3186f45ec7bSml29623 #if defined(COSIM) && defined(REG_SHOW) 3196f45ec7bSml29623 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 3206f45ec7bSml29623 NXGE_REG_RD64_NO_SHOW(handle, MIF_ADDR((reg)), (val_p)) 3216f45ec7bSml29623 #else 3226f45ec7bSml29623 /* If not COSIM or REG_SHOW, still show */ 3236f45ec7bSml29623 #define MIF_REG_RD_NO_SHOW(handle, reg, val_p)\ 3246f45ec7bSml29623 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p)) 3256f45ec7bSml29623 #endif 3266f45ec7bSml29623 3276f45ec7bSml29623 #define ESR_REG_WR(handle, reg, val)\ 3286f45ec7bSml29623 NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val)) 3296f45ec7bSml29623 3306f45ec7bSml29623 #define ESR_REG_RD(handle, reg, val_p)\ 3316f45ec7bSml29623 NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p)) 3326f45ec7bSml29623 3336f45ec7bSml29623 /* Macros to read/modify MAC attributes */ 3346f45ec7bSml29623 3356f45ec7bSml29623 #define SET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 3366f45ec7bSml29623 p.type = attr;\ 3376f45ec7bSml29623 p.idata[0] = (uint32_t)val;\ 3386f45ec7bSml29623 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 3396f45ec7bSml29623 } 3406f45ec7bSml29623 3416f45ec7bSml29623 #define SET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 3426f45ec7bSml29623 p.type = attr;\ 3436f45ec7bSml29623 p.idata[0] = (uint32_t)val0;\ 3446f45ec7bSml29623 p.idata[1] = (uint32_t)val1;\ 3456f45ec7bSml29623 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 3466f45ec7bSml29623 } 3476f45ec7bSml29623 3486f45ec7bSml29623 #define SET_MAC_ATTR3(handle, p, portn, attr, val0, val1, val2, stat) {\ 3496f45ec7bSml29623 p.type = attr;\ 3506f45ec7bSml29623 p.idata[0] = (uint32_t)val0;\ 3516f45ec7bSml29623 p.idata[1] = (uint32_t)val1;\ 3526f45ec7bSml29623 p.idata[2] = (uint32_t)val2;\ 3536f45ec7bSml29623 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 3546f45ec7bSml29623 } 3556f45ec7bSml29623 3566f45ec7bSml29623 #define SET_MAC_ATTR4(handle, p, portn, attr, val0, val1, val2, val3, stat) {\ 3576f45ec7bSml29623 p.type = attr;\ 3586f45ec7bSml29623 p.idata[0] = (uint32_t)val0;\ 3596f45ec7bSml29623 p.idata[1] = (uint32_t)val1;\ 3606f45ec7bSml29623 p.idata[2] = (uint32_t)val2;\ 3616f45ec7bSml29623 p.idata[3] = (uint32_t)val3;\ 3626f45ec7bSml29623 stat = npi_mac_port_attr(handle, OP_SET, portn, (npi_attr_t *)&p);\ 3636f45ec7bSml29623 } 3646f45ec7bSml29623 3656f45ec7bSml29623 #define GET_MAC_ATTR1(handle, p, portn, attr, val, stat) {\ 3666f45ec7bSml29623 p.type = attr;\ 3676f45ec7bSml29623 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 3686f45ec7bSml29623 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 3696f45ec7bSml29623 val = p.odata[0];\ 3706f45ec7bSml29623 }\ 3716f45ec7bSml29623 } 3726f45ec7bSml29623 3736f45ec7bSml29623 #define GET_MAC_ATTR2(handle, p, portn, attr, val0, val1, stat) {\ 3746f45ec7bSml29623 p.type = attr;\ 3756f45ec7bSml29623 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 3766f45ec7bSml29623 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 3776f45ec7bSml29623 val0 = p.odata[0];\ 3786f45ec7bSml29623 val1 = p.odata[1];\ 3796f45ec7bSml29623 }\ 3806f45ec7bSml29623 } 3816f45ec7bSml29623 3826f45ec7bSml29623 #define GET_MAC_ATTR3(handle, p, portn, attr, val0, val1, \ 3836f45ec7bSml29623 val2, stat) {\ 3846f45ec7bSml29623 p.type = attr;\ 3856f45ec7bSml29623 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 3866f45ec7bSml29623 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 3876f45ec7bSml29623 val0 = p.odata[0];\ 3886f45ec7bSml29623 val1 = p.odata[1];\ 3896f45ec7bSml29623 val2 = p.odata[2];\ 3906f45ec7bSml29623 }\ 3916f45ec7bSml29623 } 3926f45ec7bSml29623 3936f45ec7bSml29623 #define GET_MAC_ATTR4(handle, p, portn, attr, val0, val1, \ 3946f45ec7bSml29623 val2, val3, stat) {\ 3956f45ec7bSml29623 p.type = attr;\ 3966f45ec7bSml29623 if ((stat = npi_mac_port_attr(handle, OP_GET, portn, \ 3976f45ec7bSml29623 (npi_attr_t *)&p)) == NPI_SUCCESS) {\ 3986f45ec7bSml29623 val0 = p.odata[0];\ 3996f45ec7bSml29623 val1 = p.odata[1];\ 4006f45ec7bSml29623 val2 = p.odata[2];\ 4016f45ec7bSml29623 val3 = p.odata[3];\ 4026f45ec7bSml29623 }\ 4036f45ec7bSml29623 } 4046f45ec7bSml29623 4056f45ec7bSml29623 /* MAC specific errors */ 4066f45ec7bSml29623 4076f45ec7bSml29623 #define MAC_PORT_ATTR_INVALID 0x50 4086f45ec7bSml29623 #define MAC_RESET_MODE_INVALID 0x51 4096f45ec7bSml29623 #define MAC_HASHTAB_ENTRY_INVALID 0x52 4106f45ec7bSml29623 #define MAC_HOSTINFO_ENTRY_INVALID 0x53 4116f45ec7bSml29623 #define MAC_ALT_ADDR_ENTRY_INVALID 0x54 4126f45ec7bSml29623 4136f45ec7bSml29623 /* MAC error return macros */ 4146f45ec7bSml29623 4156f45ec7bSml29623 #define NPI_MAC_PORT_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4166f45ec7bSml29623 PORT_INVALID | IS_PORT | (portn << 12)) 4176f45ec7bSml29623 #define NPI_MAC_OPCODE_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4186f45ec7bSml29623 OPCODE_INVALID |\ 4196f45ec7bSml29623 IS_PORT | (portn << 12)) 4206f45ec7bSml29623 #define NPI_MAC_HASHTAB_ENTRY_INVALID(portn)\ 4216f45ec7bSml29623 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4226f45ec7bSml29623 MAC_HASHTAB_ENTRY_INVALID |\ 4236f45ec7bSml29623 IS_PORT | (portn << 12)) 4246f45ec7bSml29623 #define NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)\ 4256f45ec7bSml29623 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4266f45ec7bSml29623 MAC_HOSTINFO_ENTRY_INVALID |\ 4276f45ec7bSml29623 IS_PORT | (portn << 12)) 4286f45ec7bSml29623 #define NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)\ 4296f45ec7bSml29623 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4306f45ec7bSml29623 MAC_ALT_ADDR_ENTRY_INVALID |\ 4316f45ec7bSml29623 IS_PORT | (portn << 12)) 4326f45ec7bSml29623 #define NPI_MAC_PORT_ATTR_INVALID(portn)\ 4336f45ec7bSml29623 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4346f45ec7bSml29623 MAC_PORT_ATTR_INVALID |\ 4356f45ec7bSml29623 IS_PORT | (portn << 12)) 4366f45ec7bSml29623 #define NPI_MAC_RESET_MODE_INVALID(portn)\ 4376f45ec7bSml29623 ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4386f45ec7bSml29623 MAC_RESET_MODE_INVALID |\ 4396f45ec7bSml29623 IS_PORT | (portn << 12)) 4406f45ec7bSml29623 #define NPI_MAC_PCS_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4416f45ec7bSml29623 REGISTER_INVALID |\ 4426f45ec7bSml29623 IS_PORT | (portn << 12)) 4436f45ec7bSml29623 #define NPI_TXMAC_RESET_FAILED(portn) ((TXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4446f45ec7bSml29623 RESET_FAILED | IS_PORT | (portn << 12)) 4456f45ec7bSml29623 #define NPI_RXMAC_RESET_FAILED(portn) ((RXMAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4466f45ec7bSml29623 RESET_FAILED | IS_PORT | (portn << 12)) 4476f45ec7bSml29623 #define NPI_MAC_CONFIG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4486f45ec7bSml29623 CONFIG_INVALID |\ 4496f45ec7bSml29623 IS_PORT | (portn << 12)) 4506f45ec7bSml29623 #define NPI_MAC_REG_INVALID(portn) ((MAC_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4516f45ec7bSml29623 REGISTER_INVALID |\ 4526f45ec7bSml29623 IS_PORT | (portn << 12)) 4536f45ec7bSml29623 #define NPI_MAC_MII_READ_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4546f45ec7bSml29623 READ_FAILED | IS_PORT | (portn << 12)) 4556f45ec7bSml29623 #define NPI_MAC_MII_WRITE_FAILED(portn) ((MIF_BLK_ID << NPI_BLOCK_ID_SHIFT) |\ 4566f45ec7bSml29623 WRITE_FAILED | IS_PORT | (portn << 12)) 4576f45ec7bSml29623 4586f45ec7bSml29623 /* library functions prototypes */ 4596f45ec7bSml29623 4606f45ec7bSml29623 /* general mac functions */ 4616f45ec7bSml29623 npi_status_t npi_mac_hashtab_entry(npi_handle_t, io_op_t, 4626f45ec7bSml29623 uint8_t, uint8_t, uint16_t *); 4636f45ec7bSml29623 npi_status_t npi_mac_hostinfo_entry(npi_handle_t, io_op_t, 4646f45ec7bSml29623 uint8_t, uint8_t, 4656f45ec7bSml29623 hostinfo_t *); 4666f45ec7bSml29623 npi_status_t npi_mac_altaddr_enable(npi_handle_t, uint8_t, 4676f45ec7bSml29623 uint8_t); 468*678453a8Sspeer npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, 4696f45ec7bSml29623 uint8_t); 4706f45ec7bSml29623 npi_status_t npi_mac_altaddr_entry(npi_handle_t, io_op_t, 4716f45ec7bSml29623 uint8_t, uint8_t, 4726f45ec7bSml29623 npi_mac_addr_t *); 4736f45ec7bSml29623 npi_status_t npi_mac_port_attr(npi_handle_t, io_op_t, uint8_t, 4746f45ec7bSml29623 npi_attr_t *); 4756f45ec7bSml29623 npi_status_t npi_mac_get_link_status(npi_handle_t, uint8_t, 4766f45ec7bSml29623 boolean_t *); 4776f45ec7bSml29623 npi_status_t npi_mac_get_10g_link_status(npi_handle_t, uint8_t, 4786f45ec7bSml29623 boolean_t *); 4796f45ec7bSml29623 npi_status_t npi_mac_mif_mii_read(npi_handle_t, uint8_t, 4806f45ec7bSml29623 uint8_t, uint16_t *); 4816f45ec7bSml29623 npi_status_t npi_mac_mif_mii_write(npi_handle_t, uint8_t, 4826f45ec7bSml29623 uint8_t, uint16_t); 4836f45ec7bSml29623 npi_status_t npi_mac_mif_link_intr_enable(npi_handle_t, uint8_t, 4846f45ec7bSml29623 uint8_t, uint16_t); 4856f45ec7bSml29623 npi_status_t npi_mac_mif_mdio_read(npi_handle_t, uint8_t, 4866f45ec7bSml29623 uint8_t, uint16_t, 4876f45ec7bSml29623 uint16_t *); 4886f45ec7bSml29623 npi_status_t npi_mac_mif_mdio_write(npi_handle_t, uint8_t, 4896f45ec7bSml29623 uint8_t, uint16_t, 4906f45ec7bSml29623 uint16_t); 4916f45ec7bSml29623 npi_status_t npi_mac_mif_mdio_link_intr_enable(npi_handle_t, 4926f45ec7bSml29623 uint8_t, uint8_t, 4936f45ec7bSml29623 uint16_t, uint16_t); 4946f45ec7bSml29623 npi_status_t npi_mac_mif_link_intr_disable(npi_handle_t, uint8_t); 4956f45ec7bSml29623 npi_status_t npi_mac_pcs_mii_read(npi_handle_t, uint8_t, 4966f45ec7bSml29623 uint8_t, uint16_t *); 4976f45ec7bSml29623 npi_status_t npi_mac_pcs_mii_write(npi_handle_t, uint8_t, 4986f45ec7bSml29623 uint8_t, uint16_t); 4996f45ec7bSml29623 npi_status_t npi_mac_pcs_link_intr_enable(npi_handle_t, uint8_t); 5006f45ec7bSml29623 npi_status_t npi_mac_pcs_link_intr_disable(npi_handle_t, uint8_t); 5016f45ec7bSml29623 npi_status_t npi_mac_pcs_reset(npi_handle_t, uint8_t); 5026f45ec7bSml29623 5036f45ec7bSml29623 /* xmac functions */ 5046f45ec7bSml29623 npi_status_t npi_xmac_reset(npi_handle_t, uint8_t, 5056f45ec7bSml29623 npi_mac_reset_t); 5066f45ec7bSml29623 npi_status_t npi_xmac_xif_config(npi_handle_t, config_op_t, 5076f45ec7bSml29623 uint8_t, xmac_xif_config_t); 5086f45ec7bSml29623 npi_status_t npi_xmac_tx_config(npi_handle_t, config_op_t, 5096f45ec7bSml29623 uint8_t, xmac_tx_config_t); 5106f45ec7bSml29623 npi_status_t npi_xmac_rx_config(npi_handle_t, config_op_t, 5116f45ec7bSml29623 uint8_t, xmac_rx_config_t); 5126f45ec7bSml29623 npi_status_t npi_xmac_tx_iconfig(npi_handle_t, config_op_t, 5136f45ec7bSml29623 uint8_t, xmac_tx_iconfig_t); 5146f45ec7bSml29623 npi_status_t npi_xmac_rx_iconfig(npi_handle_t, config_op_t, 5156f45ec7bSml29623 uint8_t, xmac_rx_iconfig_t); 5166f45ec7bSml29623 npi_status_t npi_xmac_ctl_iconfig(npi_handle_t, config_op_t, 5176f45ec7bSml29623 uint8_t, xmac_ctl_iconfig_t); 5186f45ec7bSml29623 npi_status_t npi_xmac_tx_get_istatus(npi_handle_t, uint8_t, 5196f45ec7bSml29623 xmac_tx_iconfig_t *); 5206f45ec7bSml29623 npi_status_t npi_xmac_rx_get_istatus(npi_handle_t, uint8_t, 5216f45ec7bSml29623 xmac_rx_iconfig_t *); 5226f45ec7bSml29623 npi_status_t npi_xmac_ctl_get_istatus(npi_handle_t, uint8_t, 5236f45ec7bSml29623 xmac_ctl_iconfig_t *); 5246f45ec7bSml29623 npi_status_t npi_xmac_xpcs_reset(npi_handle_t, uint8_t); 5256f45ec7bSml29623 npi_status_t npi_xmac_xpcs_enable(npi_handle_t, uint8_t); 5266f45ec7bSml29623 npi_status_t npi_xmac_xpcs_disable(npi_handle_t, uint8_t); 5276f45ec7bSml29623 npi_status_t npi_xmac_xpcs_read(npi_handle_t, uint8_t, 5286f45ec7bSml29623 uint8_t, uint32_t *); 5296f45ec7bSml29623 npi_status_t npi_xmac_xpcs_write(npi_handle_t, uint8_t, 5306f45ec7bSml29623 uint8_t, uint32_t); 5316f45ec7bSml29623 npi_status_t npi_xmac_xpcs_link_intr_enable(npi_handle_t, uint8_t); 5326f45ec7bSml29623 npi_status_t npi_xmac_xpcs_link_intr_disable(npi_handle_t, 5336f45ec7bSml29623 uint8_t); 5346f45ec7bSml29623 npi_status_t npi_xmac_xif_led(npi_handle_t, uint8_t, 5356f45ec7bSml29623 boolean_t); 5366f45ec7bSml29623 npi_status_t npi_xmac_zap_tx_counters(npi_handle_t, uint8_t); 5376f45ec7bSml29623 npi_status_t npi_xmac_zap_rx_counters(npi_handle_t, uint8_t); 5386f45ec7bSml29623 5396f45ec7bSml29623 /* bmac functions */ 5406f45ec7bSml29623 npi_status_t npi_bmac_reset(npi_handle_t, uint8_t, 5416f45ec7bSml29623 npi_mac_reset_t mode); 5426f45ec7bSml29623 npi_status_t npi_bmac_tx_config(npi_handle_t, config_op_t, 5436f45ec7bSml29623 uint8_t, bmac_tx_config_t); 5446f45ec7bSml29623 npi_status_t npi_bmac_rx_config(npi_handle_t, config_op_t, 5456f45ec7bSml29623 uint8_t, bmac_rx_config_t); 5466f45ec7bSml29623 npi_status_t npi_bmac_rx_iconfig(npi_handle_t, config_op_t, 5476f45ec7bSml29623 uint8_t, bmac_rx_iconfig_t); 5486f45ec7bSml29623 npi_status_t npi_bmac_xif_config(npi_handle_t, config_op_t, 5496f45ec7bSml29623 uint8_t, bmac_xif_config_t); 5506f45ec7bSml29623 npi_status_t npi_bmac_tx_iconfig(npi_handle_t, config_op_t, 5516f45ec7bSml29623 uint8_t, bmac_tx_iconfig_t); 5526f45ec7bSml29623 npi_status_t npi_bmac_ctl_iconfig(npi_handle_t, config_op_t, 5536f45ec7bSml29623 uint8_t, bmac_ctl_iconfig_t); 5546f45ec7bSml29623 npi_status_t npi_bmac_tx_get_istatus(npi_handle_t, uint8_t, 5556f45ec7bSml29623 bmac_tx_iconfig_t *); 5566f45ec7bSml29623 npi_status_t npi_bmac_rx_get_istatus(npi_handle_t, uint8_t, 5576f45ec7bSml29623 bmac_rx_iconfig_t *); 5586f45ec7bSml29623 npi_status_t npi_bmac_ctl_get_istatus(npi_handle_t, uint8_t, 5596f45ec7bSml29623 bmac_ctl_iconfig_t *); 5606f45ec7bSml29623 npi_status_t npi_bmac_send_pause(npi_handle_t, uint8_t, 5616f45ec7bSml29623 uint16_t); 5626f45ec7bSml29623 npi_status_t npi_mac_dump_regs(npi_handle_t, uint8_t); 5636f45ec7bSml29623 5646f45ec7bSml29623 /* MIF common functions */ 5656f45ec7bSml29623 void npi_mac_mif_set_indirect_mode(npi_handle_t, boolean_t); 566d81011f0Ssbehera void npi_mac_mif_set_atca_mode(npi_handle_t, boolean_t); 5676f45ec7bSml29623 5686f45ec7bSml29623 #ifdef __cplusplus 5696f45ec7bSml29623 } 5706f45ec7bSml29623 #endif 5716f45ec7bSml29623 5726f45ec7bSml29623 #endif /* _NPI_MAC_H */ 573