16f45ec7bSml29623 /*
26f45ec7bSml29623 * CDDL HEADER START
36f45ec7bSml29623 *
46f45ec7bSml29623 * The contents of this file are subject to the terms of the
56f45ec7bSml29623 * Common Development and Distribution License (the "License").
66f45ec7bSml29623 * You may not use this file except in compliance with the License.
76f45ec7bSml29623 *
86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing.
106f45ec7bSml29623 * See the License for the specific language governing permissions
116f45ec7bSml29623 * and limitations under the License.
126f45ec7bSml29623 *
136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each
146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the
166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying
176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner]
186f45ec7bSml29623 *
196f45ec7bSml29623 * CDDL HEADER END
206f45ec7bSml29623 */
21ef523517SMichael Speer
226f45ec7bSml29623 /*
230dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
246f45ec7bSml29623 * Use is subject to license terms.
256f45ec7bSml29623 */
266f45ec7bSml29623
276f45ec7bSml29623 #include <sys/nxge/nxge_impl.h>
286f45ec7bSml29623 #include <sys/nxge/nxge_rxdma.h>
29678453a8Sspeer #include <sys/nxge/nxge_hio.h>
30678453a8Sspeer
31678453a8Sspeer #if !defined(_BIG_ENDIAN)
32678453a8Sspeer #include <npi_rx_rd32.h>
33678453a8Sspeer #endif
34678453a8Sspeer #include <npi_rx_rd64.h>
35678453a8Sspeer #include <npi_rx_wr64.h>
366f45ec7bSml29623
376f45ec7bSml29623 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \
38678453a8Sspeer (rdcgrp + nxgep->pt_config.hw_config.def_mac_rxdma_grpid)
396f45ec7bSml29623 #define NXGE_ACTUAL_RDC(nxgep, rdc) \
406f45ec7bSml29623 (rdc + nxgep->pt_config.hw_config.start_rdc)
416f45ec7bSml29623
426f45ec7bSml29623 /*
436f45ec7bSml29623 * Globals: tunable parameters (/etc/system or adb)
446f45ec7bSml29623 *
456f45ec7bSml29623 */
466f45ec7bSml29623 extern uint32_t nxge_rbr_size;
476f45ec7bSml29623 extern uint32_t nxge_rcr_size;
486f45ec7bSml29623 extern uint32_t nxge_rbr_spare_size;
494df55fdeSJanie Lu extern uint16_t nxge_rdc_buf_offset;
506f45ec7bSml29623
516f45ec7bSml29623 extern uint32_t nxge_mblks_pending;
526f45ec7bSml29623
536f45ec7bSml29623 /*
546f45ec7bSml29623 * Tunable to reduce the amount of time spent in the
556f45ec7bSml29623 * ISR doing Rx Processing.
566f45ec7bSml29623 */
576f45ec7bSml29623 extern uint32_t nxge_max_rx_pkts;
586f45ec7bSml29623
596f45ec7bSml29623 /*
606f45ec7bSml29623 * Tunables to manage the receive buffer blocks.
616f45ec7bSml29623 *
626f45ec7bSml29623 * nxge_rx_threshold_hi: copy all buffers.
636f45ec7bSml29623 * nxge_rx_bcopy_size_type: receive buffer block size type.
646f45ec7bSml29623 * nxge_rx_threshold_lo: copy only up to tunable block size type.
656f45ec7bSml29623 */
666f45ec7bSml29623 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi;
676f45ec7bSml29623 extern nxge_rxbuf_type_t nxge_rx_buf_size_type;
686f45ec7bSml29623 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo;
696f45ec7bSml29623
70b4d05839Sml29623 extern uint32_t nxge_cksum_offload;
71678453a8Sspeer
72678453a8Sspeer static nxge_status_t nxge_map_rxdma(p_nxge_t, int);
73678453a8Sspeer static void nxge_unmap_rxdma(p_nxge_t, int);
746f45ec7bSml29623
756f45ec7bSml29623 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t);
766f45ec7bSml29623
77678453a8Sspeer static nxge_status_t nxge_rxdma_hw_start(p_nxge_t, int);
78678453a8Sspeer static void nxge_rxdma_hw_stop(p_nxge_t, int);
796f45ec7bSml29623
806f45ec7bSml29623 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t,
816f45ec7bSml29623 p_nxge_dma_common_t *, p_rx_rbr_ring_t *,
826f45ec7bSml29623 uint32_t,
836f45ec7bSml29623 p_nxge_dma_common_t *, p_rx_rcr_ring_t *,
846f45ec7bSml29623 p_rx_mbox_t *);
856f45ec7bSml29623 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t,
866f45ec7bSml29623 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
876f45ec7bSml29623
886f45ec7bSml29623 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t,
896f45ec7bSml29623 uint16_t,
906f45ec7bSml29623 p_nxge_dma_common_t *, p_rx_rbr_ring_t *,
916f45ec7bSml29623 p_rx_rcr_ring_t *, p_rx_mbox_t *);
926f45ec7bSml29623 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t,
936f45ec7bSml29623 p_rx_rcr_ring_t, p_rx_mbox_t);
946f45ec7bSml29623
956f45ec7bSml29623 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t,
966f45ec7bSml29623 uint16_t,
976f45ec7bSml29623 p_nxge_dma_common_t *,
986f45ec7bSml29623 p_rx_rbr_ring_t *, uint32_t);
996f45ec7bSml29623 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t,
1006f45ec7bSml29623 p_rx_rbr_ring_t);
1016f45ec7bSml29623
1026f45ec7bSml29623 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t,
1036f45ec7bSml29623 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
1046f45ec7bSml29623 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t);
1056f45ec7bSml29623
106678453a8Sspeer static mblk_t *
107678453a8Sspeer nxge_rx_pkts(p_nxge_t, p_rx_rcr_ring_t, rx_dma_ctl_stat_t, int);
1086f45ec7bSml29623
1096f45ec7bSml29623 static void nxge_receive_packet(p_nxge_t,
1106f45ec7bSml29623 p_rx_rcr_ring_t,
1116f45ec7bSml29623 p_rcr_entry_t,
1126f45ec7bSml29623 boolean_t *,
1136f45ec7bSml29623 mblk_t **, mblk_t **);
1146f45ec7bSml29623
1156f45ec7bSml29623 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t);
1166f45ec7bSml29623
1176f45ec7bSml29623 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t);
1186f45ec7bSml29623 static void nxge_freeb(p_rx_msg_t);
119678453a8Sspeer static nxge_status_t nxge_rx_err_evnts(p_nxge_t, int, rx_dma_ctl_stat_t);
1206f45ec7bSml29623
1216f45ec7bSml29623 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t,
1226f45ec7bSml29623 uint32_t, uint32_t);
1236f45ec7bSml29623
1246f45ec7bSml29623 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t,
1256f45ec7bSml29623 p_rx_rbr_ring_t);
1266f45ec7bSml29623
1276f45ec7bSml29623
1286f45ec7bSml29623 static nxge_status_t
1296f45ec7bSml29623 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t);
1306f45ec7bSml29623
1316f45ec7bSml29623 nxge_status_t
1326f45ec7bSml29623 nxge_rx_port_fatal_err_recover(p_nxge_t);
1336f45ec7bSml29623
134678453a8Sspeer static void nxge_rxdma_databuf_free(p_rx_rbr_ring_t);
135678453a8Sspeer
1366f45ec7bSml29623 nxge_status_t
nxge_init_rxdma_channels(p_nxge_t nxgep)1376f45ec7bSml29623 nxge_init_rxdma_channels(p_nxge_t nxgep)
1386f45ec7bSml29623 {
139678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
140da14cebeSEric Cheng int i, count, channel;
141e11f0814SMichael Speer nxge_grp_t *group;
142da14cebeSEric Cheng dc_map_t map;
143da14cebeSEric Cheng int dev_gindex;
1446f45ec7bSml29623
1456f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels"));
1466f45ec7bSml29623
147678453a8Sspeer if (!isLDOMguest(nxgep)) {
148678453a8Sspeer if (nxge_rxdma_hw_start_common(nxgep) != NXGE_OK) {
149678453a8Sspeer cmn_err(CE_NOTE, "hw_start_common");
150678453a8Sspeer return (NXGE_ERROR);
151678453a8Sspeer }
152678453a8Sspeer }
153678453a8Sspeer
154678453a8Sspeer /*
155678453a8Sspeer * NXGE_LOGICAL_GROUP_MAX > NXGE_MAX_RDC_GROUPS (8)
156678453a8Sspeer * We only have 8 hardware RDC tables, but we may have
157678453a8Sspeer * up to 16 logical (software-defined) groups of RDCS,
158678453a8Sspeer * if we make use of layer 3 & 4 hardware classification.
159678453a8Sspeer */
160678453a8Sspeer for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
161678453a8Sspeer if ((1 << i) & set->lg.map) {
162e11f0814SMichael Speer group = set->group[i];
163da14cebeSEric Cheng dev_gindex =
164da14cebeSEric Cheng nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
165da14cebeSEric Cheng map = nxgep->pt_config.rdc_grps[dev_gindex].map;
166678453a8Sspeer for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
167da14cebeSEric Cheng if ((1 << channel) & map) {
168678453a8Sspeer if ((nxge_grp_dc_add(nxgep,
1696920a987SMisaki Miyashita group, VP_BOUND_RX, channel)))
170e11f0814SMichael Speer goto init_rxdma_channels_exit;
171678453a8Sspeer }
172678453a8Sspeer }
173678453a8Sspeer }
174678453a8Sspeer if (++count == set->lg.count)
175678453a8Sspeer break;
176678453a8Sspeer }
177678453a8Sspeer
178678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
179678453a8Sspeer return (NXGE_OK);
180e11f0814SMichael Speer
181e11f0814SMichael Speer init_rxdma_channels_exit:
182e11f0814SMichael Speer for (i = 0, count = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) {
183e11f0814SMichael Speer if ((1 << i) & set->lg.map) {
184e11f0814SMichael Speer group = set->group[i];
185da14cebeSEric Cheng dev_gindex =
186da14cebeSEric Cheng nxgep->pt_config.hw_config.def_mac_rxdma_grpid + i;
187da14cebeSEric Cheng map = nxgep->pt_config.rdc_grps[dev_gindex].map;
188da14cebeSEric Cheng for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
189da14cebeSEric Cheng if ((1 << channel) & map) {
190e11f0814SMichael Speer nxge_grp_dc_remove(nxgep,
191da14cebeSEric Cheng VP_BOUND_RX, channel);
192e11f0814SMichael Speer }
193e11f0814SMichael Speer }
194e11f0814SMichael Speer }
195e11f0814SMichael Speer if (++count == set->lg.count)
196e11f0814SMichael Speer break;
197e11f0814SMichael Speer }
198e11f0814SMichael Speer
199e11f0814SMichael Speer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_init_rxdma_channels"));
200e11f0814SMichael Speer return (NXGE_ERROR);
201678453a8Sspeer }
202678453a8Sspeer
203678453a8Sspeer nxge_status_t
nxge_init_rxdma_channel(p_nxge_t nxge,int channel)204678453a8Sspeer nxge_init_rxdma_channel(p_nxge_t nxge, int channel)
205678453a8Sspeer {
206678453a8Sspeer nxge_status_t status;
207678453a8Sspeer
208678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL, "==> nxge_init_rxdma_channel"));
209678453a8Sspeer
210678453a8Sspeer status = nxge_map_rxdma(nxge, channel);
2116f45ec7bSml29623 if (status != NXGE_OK) {
212678453a8Sspeer NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL,
2136f45ec7bSml29623 "<== nxge_init_rxdma: status 0x%x", status));
2146f45ec7bSml29623 return (status);
2156f45ec7bSml29623 }
2166f45ec7bSml29623
21708ac1c49SNicolas Droux #if defined(sun4v)
21808ac1c49SNicolas Droux if (isLDOMguest(nxge)) {
21908ac1c49SNicolas Droux /* set rcr_ring */
22008ac1c49SNicolas Droux p_rx_rcr_ring_t ring = nxge->rx_rcr_rings->rcr_rings[channel];
22108ac1c49SNicolas Droux
22208ac1c49SNicolas Droux status = nxge_hio_rxdma_bind_intr(nxge, ring, channel);
22308ac1c49SNicolas Droux if (status != NXGE_OK) {
22408ac1c49SNicolas Droux nxge_unmap_rxdma(nxge, channel);
22508ac1c49SNicolas Droux return (status);
22608ac1c49SNicolas Droux }
22708ac1c49SNicolas Droux }
22808ac1c49SNicolas Droux #endif
22908ac1c49SNicolas Droux
230678453a8Sspeer status = nxge_rxdma_hw_start(nxge, channel);
2316f45ec7bSml29623 if (status != NXGE_OK) {
232678453a8Sspeer nxge_unmap_rxdma(nxge, channel);
2336f45ec7bSml29623 }
2346f45ec7bSml29623
235678453a8Sspeer if (!nxge->statsp->rdc_ksp[channel])
236678453a8Sspeer nxge_setup_rdc_kstats(nxge, channel);
2376f45ec7bSml29623
238678453a8Sspeer NXGE_DEBUG_MSG((nxge, MEM2_CTL,
239678453a8Sspeer "<== nxge_init_rxdma_channel: status 0x%x", status));
2406f45ec7bSml29623
2416f45ec7bSml29623 return (status);
2426f45ec7bSml29623 }
2436f45ec7bSml29623
2446f45ec7bSml29623 void
nxge_uninit_rxdma_channels(p_nxge_t nxgep)2456f45ec7bSml29623 nxge_uninit_rxdma_channels(p_nxge_t nxgep)
2466f45ec7bSml29623 {
247678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
248678453a8Sspeer int rdc;
249678453a8Sspeer
2506f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels"));
2516f45ec7bSml29623
252678453a8Sspeer if (set->owned.map == 0) {
2536f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
254678453a8Sspeer "nxge_uninit_rxdma_channels: no channels"));
255678453a8Sspeer return;
256678453a8Sspeer }
257678453a8Sspeer
258678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
259678453a8Sspeer if ((1 << rdc) & set->owned.map) {
260678453a8Sspeer nxge_grp_dc_remove(nxgep, VP_BOUND_RX, rdc);
261678453a8Sspeer }
262678453a8Sspeer }
263678453a8Sspeer
264678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uninit_rxdma_channels"));
265678453a8Sspeer }
266678453a8Sspeer
267678453a8Sspeer void
nxge_uninit_rxdma_channel(p_nxge_t nxgep,int channel)268678453a8Sspeer nxge_uninit_rxdma_channel(p_nxge_t nxgep, int channel)
269678453a8Sspeer {
270678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channel"));
271678453a8Sspeer
272678453a8Sspeer if (nxgep->statsp->rdc_ksp[channel]) {
273678453a8Sspeer kstat_delete(nxgep->statsp->rdc_ksp[channel]);
274678453a8Sspeer nxgep->statsp->rdc_ksp[channel] = 0;
275678453a8Sspeer }
276678453a8Sspeer
277678453a8Sspeer nxge_rxdma_hw_stop(nxgep, channel);
278678453a8Sspeer nxge_unmap_rxdma(nxgep, channel);
279678453a8Sspeer
280678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_uinit_rxdma_channel"));
2816f45ec7bSml29623 }
2826f45ec7bSml29623
2836f45ec7bSml29623 nxge_status_t
nxge_reset_rxdma_channel(p_nxge_t nxgep,uint16_t channel)2846f45ec7bSml29623 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
2856f45ec7bSml29623 {
2866f45ec7bSml29623 npi_handle_t handle;
2876f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
2886f45ec7bSml29623 nxge_status_t status = NXGE_OK;
2896f45ec7bSml29623
290330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_reset_rxdma_channel"));
2916f45ec7bSml29623
2926f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
2936f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_reset(handle, channel);
2946f45ec7bSml29623
2956f45ec7bSml29623 if (rs != NPI_SUCCESS) {
2966f45ec7bSml29623 status = NXGE_ERROR | rs;
2976f45ec7bSml29623 }
2986f45ec7bSml29623
299330cd344SMichael Speer NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel"));
300330cd344SMichael Speer
3016f45ec7bSml29623 return (status);
3026f45ec7bSml29623 }
3036f45ec7bSml29623
3046f45ec7bSml29623 void
nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)3056f45ec7bSml29623 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep)
3066f45ec7bSml29623 {
307678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
308678453a8Sspeer int rdc;
3096f45ec7bSml29623
3106f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels"));
3116f45ec7bSml29623
312678453a8Sspeer if (!isLDOMguest(nxgep)) {
313678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
3146f45ec7bSml29623 (void) npi_rxdma_dump_fzc_regs(handle);
3156f45ec7bSml29623 }
316678453a8Sspeer
317678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
318678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL,
319678453a8Sspeer "nxge_rxdma_regs_dump_channels: "
320678453a8Sspeer "NULL ring pointer(s)"));
3216f45ec7bSml29623 return;
3226f45ec7bSml29623 }
3236f45ec7bSml29623
324678453a8Sspeer if (set->owned.map == 0) {
3256f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
326678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels"));
3276f45ec7bSml29623 return;
3286f45ec7bSml29623 }
3296f45ec7bSml29623
330678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
331678453a8Sspeer if ((1 << rdc) & set->owned.map) {
332678453a8Sspeer rx_rbr_ring_t *ring =
333678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc];
334678453a8Sspeer if (ring) {
335678453a8Sspeer (void) nxge_dump_rxdma_channel(nxgep, rdc);
3366f45ec7bSml29623 }
337678453a8Sspeer }
3386f45ec7bSml29623 }
3396f45ec7bSml29623
3406f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump"));
3416f45ec7bSml29623 }
3426f45ec7bSml29623
3436f45ec7bSml29623 nxge_status_t
nxge_dump_rxdma_channel(p_nxge_t nxgep,uint8_t channel)3446f45ec7bSml29623 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel)
3456f45ec7bSml29623 {
3466f45ec7bSml29623 npi_handle_t handle;
3476f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
3486f45ec7bSml29623 nxge_status_t status = NXGE_OK;
3496f45ec7bSml29623
3506f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel"));
3516f45ec7bSml29623
3526f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3536f45ec7bSml29623 rs = npi_rxdma_dump_rdc_regs(handle, channel);
3546f45ec7bSml29623
3556f45ec7bSml29623 if (rs != NPI_SUCCESS) {
3566f45ec7bSml29623 status = NXGE_ERROR | rs;
3576f45ec7bSml29623 }
3586f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel"));
3596f45ec7bSml29623 return (status);
3606f45ec7bSml29623 }
3616f45ec7bSml29623
3626f45ec7bSml29623 nxge_status_t
nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep,uint16_t channel,p_rx_dma_ent_msk_t mask_p)3636f45ec7bSml29623 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel,
3646f45ec7bSml29623 p_rx_dma_ent_msk_t mask_p)
3656f45ec7bSml29623 {
3666f45ec7bSml29623 npi_handle_t handle;
3676f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
3686f45ec7bSml29623 nxge_status_t status = NXGE_OK;
3696f45ec7bSml29623
3706f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3716f45ec7bSml29623 "<== nxge_init_rxdma_channel_event_mask"));
3726f45ec7bSml29623
3736f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3746f45ec7bSml29623 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p);
3756f45ec7bSml29623 if (rs != NPI_SUCCESS) {
3766f45ec7bSml29623 status = NXGE_ERROR | rs;
3776f45ec7bSml29623 }
3786f45ec7bSml29623
3796f45ec7bSml29623 return (status);
3806f45ec7bSml29623 }
3816f45ec7bSml29623
3826f45ec7bSml29623 nxge_status_t
nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep,uint16_t channel,p_rx_dma_ctl_stat_t cs_p)3836f45ec7bSml29623 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel,
3846f45ec7bSml29623 p_rx_dma_ctl_stat_t cs_p)
3856f45ec7bSml29623 {
3866f45ec7bSml29623 npi_handle_t handle;
3876f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
3886f45ec7bSml29623 nxge_status_t status = NXGE_OK;
3896f45ec7bSml29623
3906f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
3916f45ec7bSml29623 "<== nxge_init_rxdma_channel_cntl_stat"));
3926f45ec7bSml29623
3936f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3946f45ec7bSml29623 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p);
3956f45ec7bSml29623
3966f45ec7bSml29623 if (rs != NPI_SUCCESS) {
3976f45ec7bSml29623 status = NXGE_ERROR | rs;
3986f45ec7bSml29623 }
3996f45ec7bSml29623
4006f45ec7bSml29623 return (status);
4016f45ec7bSml29623 }
4026f45ec7bSml29623
403678453a8Sspeer /*
404678453a8Sspeer * nxge_rxdma_cfg_rdcgrp_default_rdc
405678453a8Sspeer *
406678453a8Sspeer * Set the default RDC for an RDC Group (Table)
407678453a8Sspeer *
408678453a8Sspeer * Arguments:
409678453a8Sspeer * nxgep
410678453a8Sspeer * rdcgrp The group to modify
411678453a8Sspeer * rdc The new default RDC.
412678453a8Sspeer *
413678453a8Sspeer * Notes:
414678453a8Sspeer *
415678453a8Sspeer * NPI/NXGE function calls:
416678453a8Sspeer * npi_rxdma_cfg_rdc_table_default_rdc()
417678453a8Sspeer *
418678453a8Sspeer * Registers accessed:
419678453a8Sspeer * RDC_TBL_REG: FZC_ZCP + 0x10000
420678453a8Sspeer *
421678453a8Sspeer * Context:
422678453a8Sspeer * Service domain
423678453a8Sspeer */
4246f45ec7bSml29623 nxge_status_t
nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep,uint8_t rdcgrp,uint8_t rdc)425678453a8Sspeer nxge_rxdma_cfg_rdcgrp_default_rdc(
426678453a8Sspeer p_nxge_t nxgep,
427678453a8Sspeer uint8_t rdcgrp,
4286f45ec7bSml29623 uint8_t rdc)
4296f45ec7bSml29623 {
4306f45ec7bSml29623 npi_handle_t handle;
4316f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
4326f45ec7bSml29623 p_nxge_dma_pt_cfg_t p_dma_cfgp;
4336f45ec7bSml29623 p_nxge_rdc_grp_t rdc_grp_p;
4346f45ec7bSml29623 uint8_t actual_rdcgrp, actual_rdc;
4356f45ec7bSml29623
4366f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
4376f45ec7bSml29623 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc"));
4386f45ec7bSml29623 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
4396f45ec7bSml29623
4406f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
4416f45ec7bSml29623
442678453a8Sspeer /*
443678453a8Sspeer * This has to be rewritten. Do we even allow this anymore?
444678453a8Sspeer */
4456f45ec7bSml29623 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp];
446678453a8Sspeer RDC_MAP_IN(rdc_grp_p->map, rdc);
447678453a8Sspeer rdc_grp_p->def_rdc = rdc;
4486f45ec7bSml29623
4496f45ec7bSml29623 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp);
4506f45ec7bSml29623 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc);
4516f45ec7bSml29623
452678453a8Sspeer rs = npi_rxdma_cfg_rdc_table_default_rdc(
453678453a8Sspeer handle, actual_rdcgrp, actual_rdc);
4546f45ec7bSml29623
4556f45ec7bSml29623 if (rs != NPI_SUCCESS) {
4566f45ec7bSml29623 return (NXGE_ERROR | rs);
4576f45ec7bSml29623 }
4586f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
4596f45ec7bSml29623 " <== nxge_rxdma_cfg_rdcgrp_default_rdc"));
4606f45ec7bSml29623 return (NXGE_OK);
4616f45ec7bSml29623 }
4626f45ec7bSml29623
4636f45ec7bSml29623 nxge_status_t
nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep,uint8_t port,uint8_t rdc)4646f45ec7bSml29623 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc)
4656f45ec7bSml29623 {
4666f45ec7bSml29623 npi_handle_t handle;
4676f45ec7bSml29623
4686f45ec7bSml29623 uint8_t actual_rdc;
4696f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
4706f45ec7bSml29623
4716f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
4726f45ec7bSml29623 " ==> nxge_rxdma_cfg_port_default_rdc"));
4736f45ec7bSml29623
4746f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
475678453a8Sspeer actual_rdc = rdc; /* XXX Hack! */
4766f45ec7bSml29623 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc);
4776f45ec7bSml29623
4786f45ec7bSml29623
4796f45ec7bSml29623 if (rs != NPI_SUCCESS) {
4806f45ec7bSml29623 return (NXGE_ERROR | rs);
4816f45ec7bSml29623 }
4826f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
4836f45ec7bSml29623 " <== nxge_rxdma_cfg_port_default_rdc"));
4846f45ec7bSml29623
4856f45ec7bSml29623 return (NXGE_OK);
4866f45ec7bSml29623 }
4876f45ec7bSml29623
4886f45ec7bSml29623 nxge_status_t
nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep,uint8_t channel,uint16_t pkts)4896f45ec7bSml29623 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel,
4906f45ec7bSml29623 uint16_t pkts)
4916f45ec7bSml29623 {
4926f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
4936f45ec7bSml29623 npi_handle_t handle;
4946f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
4956f45ec7bSml29623 " ==> nxge_rxdma_cfg_rcr_threshold"));
4966f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
4976f45ec7bSml29623
4986f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts);
4996f45ec7bSml29623
5006f45ec7bSml29623 if (rs != NPI_SUCCESS) {
5016f45ec7bSml29623 return (NXGE_ERROR | rs);
5026f45ec7bSml29623 }
5036f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold"));
5046f45ec7bSml29623 return (NXGE_OK);
5056f45ec7bSml29623 }
5066f45ec7bSml29623
5076f45ec7bSml29623 nxge_status_t
nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep,uint8_t channel,uint16_t tout,uint8_t enable)5086f45ec7bSml29623 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel,
5096f45ec7bSml29623 uint16_t tout, uint8_t enable)
5106f45ec7bSml29623 {
5116f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
5126f45ec7bSml29623 npi_handle_t handle;
5136f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout"));
5146f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
5156f45ec7bSml29623 if (enable == 0) {
5166f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel);
5176f45ec7bSml29623 } else {
5186f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
5196f45ec7bSml29623 tout);
5206f45ec7bSml29623 }
5216f45ec7bSml29623
5226f45ec7bSml29623 if (rs != NPI_SUCCESS) {
5236f45ec7bSml29623 return (NXGE_ERROR | rs);
5246f45ec7bSml29623 }
5256f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout"));
5266f45ec7bSml29623 return (NXGE_OK);
5276f45ec7bSml29623 }
5286f45ec7bSml29623
5296f45ec7bSml29623 nxge_status_t
nxge_enable_rxdma_channel(p_nxge_t nxgep,uint16_t channel,p_rx_rbr_ring_t rbr_p,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t mbox_p)5306f45ec7bSml29623 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
5316f45ec7bSml29623 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
5326f45ec7bSml29623 {
5336f45ec7bSml29623 npi_handle_t handle;
5346f45ec7bSml29623 rdc_desc_cfg_t rdc_desc;
5356f45ec7bSml29623 p_rcrcfig_b_t cfgb_p;
5366f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
5376f45ec7bSml29623
5386f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel"));
5396f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
5406f45ec7bSml29623 /*
5416f45ec7bSml29623 * Use configuration data composed at init time.
5426f45ec7bSml29623 * Write to hardware the receive ring configurations.
5436f45ec7bSml29623 */
5446f45ec7bSml29623 rdc_desc.mbox_enable = 1;
5456f45ec7bSml29623 rdc_desc.mbox_addr = mbox_p->mbox_addr;
5466f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
5476f45ec7bSml29623 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)",
5486f45ec7bSml29623 mbox_p->mbox_addr, rdc_desc.mbox_addr));
5496f45ec7bSml29623
5506f45ec7bSml29623 rdc_desc.rbr_len = rbr_p->rbb_max;
5516f45ec7bSml29623 rdc_desc.rbr_addr = rbr_p->rbr_addr;
5526f45ec7bSml29623
5536f45ec7bSml29623 switch (nxgep->rx_bksize_code) {
5546f45ec7bSml29623 case RBR_BKSIZE_4K:
5556f45ec7bSml29623 rdc_desc.page_size = SIZE_4KB;
5566f45ec7bSml29623 break;
5576f45ec7bSml29623 case RBR_BKSIZE_8K:
5586f45ec7bSml29623 rdc_desc.page_size = SIZE_8KB;
5596f45ec7bSml29623 break;
5606f45ec7bSml29623 case RBR_BKSIZE_16K:
5616f45ec7bSml29623 rdc_desc.page_size = SIZE_16KB;
5626f45ec7bSml29623 break;
5636f45ec7bSml29623 case RBR_BKSIZE_32K:
5646f45ec7bSml29623 rdc_desc.page_size = SIZE_32KB;
5656f45ec7bSml29623 break;
5666f45ec7bSml29623 }
5676f45ec7bSml29623
5686f45ec7bSml29623 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0;
5696f45ec7bSml29623 rdc_desc.valid0 = 1;
5706f45ec7bSml29623
5716f45ec7bSml29623 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1;
5726f45ec7bSml29623 rdc_desc.valid1 = 1;
5736f45ec7bSml29623
5746f45ec7bSml29623 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2;
5756f45ec7bSml29623 rdc_desc.valid2 = 1;
5766f45ec7bSml29623
5776f45ec7bSml29623 rdc_desc.full_hdr = rcr_p->full_hdr_flag;
5786f45ec7bSml29623 rdc_desc.offset = rcr_p->sw_priv_hdr_len;
5796f45ec7bSml29623
5806f45ec7bSml29623 rdc_desc.rcr_len = rcr_p->comp_size;
5816f45ec7bSml29623 rdc_desc.rcr_addr = rcr_p->rcr_addr;
5826f45ec7bSml29623
5836f45ec7bSml29623 cfgb_p = &(rcr_p->rcr_cfgb);
5846f45ec7bSml29623 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres;
585678453a8Sspeer /* For now, disable this timeout in a guest domain. */
586678453a8Sspeer if (isLDOMguest(nxgep)) {
587678453a8Sspeer rdc_desc.rcr_timeout = 0;
588678453a8Sspeer rdc_desc.rcr_timeout_enable = 0;
589678453a8Sspeer } else {
5906f45ec7bSml29623 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout;
5916f45ec7bSml29623 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout;
592678453a8Sspeer }
5936f45ec7bSml29623
5946f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
5956f45ec7bSml29623 "rbr_len qlen %d pagesize code %d rcr_len %d",
5966f45ec7bSml29623 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len));
5976f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: "
5986f45ec7bSml29623 "size 0 %d size 1 %d size 2 %d",
5996f45ec7bSml29623 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1,
6006f45ec7bSml29623 rbr_p->npi_pkt_buf_size2));
6016f45ec7bSml29623
6024df55fdeSJanie Lu if (nxgep->niu_hw_type == NIU_HW_TYPE_RF)
6034df55fdeSJanie Lu rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
6044df55fdeSJanie Lu &rdc_desc, B_TRUE);
6054df55fdeSJanie Lu else
6064df55fdeSJanie Lu rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc,
6074df55fdeSJanie Lu &rdc_desc, B_FALSE);
6086f45ec7bSml29623 if (rs != NPI_SUCCESS) {
6096f45ec7bSml29623 return (NXGE_ERROR | rs);
6106f45ec7bSml29623 }
6116f45ec7bSml29623
6126f45ec7bSml29623 /*
6136f45ec7bSml29623 * Enable the timeout and threshold.
6146f45ec7bSml29623 */
6156f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel,
6166f45ec7bSml29623 rdc_desc.rcr_threshold);
6176f45ec7bSml29623 if (rs != NPI_SUCCESS) {
6186f45ec7bSml29623 return (NXGE_ERROR | rs);
6196f45ec7bSml29623 }
6206f45ec7bSml29623
6216f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel,
6226f45ec7bSml29623 rdc_desc.rcr_timeout);
6236f45ec7bSml29623 if (rs != NPI_SUCCESS) {
6246f45ec7bSml29623 return (NXGE_ERROR | rs);
6256f45ec7bSml29623 }
6266f45ec7bSml29623
627e759c33aSMichael Speer if (!isLDOMguest(nxgep)) {
6286f45ec7bSml29623 /* Enable the DMA */
6296f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_enable(handle, channel);
6306f45ec7bSml29623 if (rs != NPI_SUCCESS) {
6316f45ec7bSml29623 return (NXGE_ERROR | rs);
6326f45ec7bSml29623 }
633e759c33aSMichael Speer }
6346f45ec7bSml29623
6356f45ec7bSml29623 /* Kick the DMA engine. */
6366f45ec7bSml29623 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max);
637e759c33aSMichael Speer
638e759c33aSMichael Speer if (!isLDOMguest(nxgep)) {
6396f45ec7bSml29623 /* Clear the rbr empty bit */
6406f45ec7bSml29623 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel);
641e759c33aSMichael Speer }
6426f45ec7bSml29623
6436f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel"));
6446f45ec7bSml29623
6456f45ec7bSml29623 return (NXGE_OK);
6466f45ec7bSml29623 }
6476f45ec7bSml29623
6486f45ec7bSml29623 nxge_status_t
nxge_disable_rxdma_channel(p_nxge_t nxgep,uint16_t channel)6496f45ec7bSml29623 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
6506f45ec7bSml29623 {
6516f45ec7bSml29623 npi_handle_t handle;
6526f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
6536f45ec7bSml29623
6546f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel"));
6556f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
6566f45ec7bSml29623
6576f45ec7bSml29623 /* disable the DMA */
6586f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_disable(handle, channel);
6596f45ec7bSml29623 if (rs != NPI_SUCCESS) {
6606f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
6616f45ec7bSml29623 "<== nxge_disable_rxdma_channel:failed (0x%x)",
6626f45ec7bSml29623 rs));
6636f45ec7bSml29623 return (NXGE_ERROR | rs);
6646f45ec7bSml29623 }
6656f45ec7bSml29623
6666f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel"));
6676f45ec7bSml29623 return (NXGE_OK);
6686f45ec7bSml29623 }
6696f45ec7bSml29623
6706f45ec7bSml29623 nxge_status_t
nxge_rxdma_channel_rcrflush(p_nxge_t nxgep,uint8_t channel)6716f45ec7bSml29623 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel)
6726f45ec7bSml29623 {
6736f45ec7bSml29623 npi_handle_t handle;
6746f45ec7bSml29623 nxge_status_t status = NXGE_OK;
6756f45ec7bSml29623
6766f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
6776f45ec7bSml29623 "<== nxge_init_rxdma_channel_rcrflush"));
6786f45ec7bSml29623
6796f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
6806f45ec7bSml29623 npi_rxdma_rdc_rcr_flush(handle, channel);
6816f45ec7bSml29623
6826f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
6836f45ec7bSml29623 "<== nxge_init_rxdma_channel_rcrflsh"));
6846f45ec7bSml29623 return (status);
6856f45ec7bSml29623
6866f45ec7bSml29623 }
6876f45ec7bSml29623
6886f45ec7bSml29623 #define MID_INDEX(l, r) ((r + l + 1) >> 1)
6896f45ec7bSml29623
6906f45ec7bSml29623 #define TO_LEFT -1
6916f45ec7bSml29623 #define TO_RIGHT 1
6926f45ec7bSml29623 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT)
6936f45ec7bSml29623 #define BOTH_LEFT (TO_LEFT + TO_LEFT)
6946f45ec7bSml29623 #define IN_MIDDLE (TO_RIGHT + TO_LEFT)
6956f45ec7bSml29623 #define NO_HINT 0xffffffff
6966f45ec7bSml29623
6976f45ec7bSml29623 /*ARGSUSED*/
6986f45ec7bSml29623 nxge_status_t
nxge_rxbuf_pp_to_vp(p_nxge_t nxgep,p_rx_rbr_ring_t rbr_p,uint8_t pktbufsz_type,uint64_t * pkt_buf_addr_pp,uint64_t ** pkt_buf_addr_p,uint32_t * bufoffset,uint32_t * msg_index)6996f45ec7bSml29623 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p,
7006f45ec7bSml29623 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp,
7016f45ec7bSml29623 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index)
7026f45ec7bSml29623 {
7036f45ec7bSml29623 int bufsize;
7046f45ec7bSml29623 uint64_t pktbuf_pp;
7056f45ec7bSml29623 uint64_t dvma_addr;
7066f45ec7bSml29623 rxring_info_t *ring_info;
7076f45ec7bSml29623 int base_side, end_side;
7086f45ec7bSml29623 int r_index, l_index, anchor_index;
7096f45ec7bSml29623 int found, search_done;
7106f45ec7bSml29623 uint32_t offset, chunk_size, block_size, page_size_mask;
7116f45ec7bSml29623 uint32_t chunk_index, block_index, total_index;
7126f45ec7bSml29623 int max_iterations, iteration;
7136f45ec7bSml29623 rxbuf_index_info_t *bufinfo;
7146f45ec7bSml29623
7156f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp"));
7166f45ec7bSml29623
7176f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
7186f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d",
7196f45ec7bSml29623 pkt_buf_addr_pp,
7206f45ec7bSml29623 pktbufsz_type));
7216f45ec7bSml29623 pktbuf_pp = (uint64_t)pkt_buf_addr_pp;
7226f45ec7bSml29623
7236f45ec7bSml29623 switch (pktbufsz_type) {
7246f45ec7bSml29623 case 0:
7256f45ec7bSml29623 bufsize = rbr_p->pkt_buf_size0;
7266f45ec7bSml29623 break;
7276f45ec7bSml29623 case 1:
7286f45ec7bSml29623 bufsize = rbr_p->pkt_buf_size1;
7296f45ec7bSml29623 break;
7306f45ec7bSml29623 case 2:
7316f45ec7bSml29623 bufsize = rbr_p->pkt_buf_size2;
7326f45ec7bSml29623 break;
7336f45ec7bSml29623 case RCR_SINGLE_BLOCK:
7346f45ec7bSml29623 bufsize = 0;
7356f45ec7bSml29623 anchor_index = 0;
7366f45ec7bSml29623 break;
7376f45ec7bSml29623 default:
7386f45ec7bSml29623 return (NXGE_ERROR);
7396f45ec7bSml29623 }
7406f45ec7bSml29623
7416f45ec7bSml29623 if (rbr_p->num_blocks == 1) {
7426f45ec7bSml29623 anchor_index = 0;
7436f45ec7bSml29623 ring_info = rbr_p->ring_info;
7446f45ec7bSml29623 bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
7456f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
7466f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) "
7476f45ec7bSml29623 "buf_pp $%p btype %d anchor_index %d "
7486f45ec7bSml29623 "bufinfo $%p",
7496f45ec7bSml29623 pkt_buf_addr_pp,
7506f45ec7bSml29623 pktbufsz_type,
7516f45ec7bSml29623 anchor_index,
7526f45ec7bSml29623 bufinfo));
7536f45ec7bSml29623
7546f45ec7bSml29623 goto found_index;
7556f45ec7bSml29623 }
7566f45ec7bSml29623
7576f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
7586f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: "
7596f45ec7bSml29623 "buf_pp $%p btype %d anchor_index %d",
7606f45ec7bSml29623 pkt_buf_addr_pp,
7616f45ec7bSml29623 pktbufsz_type,
7626f45ec7bSml29623 anchor_index));
7636f45ec7bSml29623
7646f45ec7bSml29623 ring_info = rbr_p->ring_info;
7656f45ec7bSml29623 found = B_FALSE;
7666f45ec7bSml29623 bufinfo = (rxbuf_index_info_t *)ring_info->buffer;
7676f45ec7bSml29623 iteration = 0;
7686f45ec7bSml29623 max_iterations = ring_info->max_iterations;
7696f45ec7bSml29623 /*
7706f45ec7bSml29623 * First check if this block has been seen
7716f45ec7bSml29623 * recently. This is indicated by a hint which
7726f45ec7bSml29623 * is initialized when the first buffer of the block
7736f45ec7bSml29623 * is seen. The hint is reset when the last buffer of
7746f45ec7bSml29623 * the block has been processed.
7756f45ec7bSml29623 * As three block sizes are supported, three hints
7766f45ec7bSml29623 * are kept. The idea behind the hints is that once
7776f45ec7bSml29623 * the hardware uses a block for a buffer of that
7786f45ec7bSml29623 * size, it will use it exclusively for that size
7796f45ec7bSml29623 * and will use it until it is exhausted. It is assumed
7806f45ec7bSml29623 * that there would a single block being used for the same
7816f45ec7bSml29623 * buffer sizes at any given time.
7826f45ec7bSml29623 */
7836f45ec7bSml29623 if (ring_info->hint[pktbufsz_type] != NO_HINT) {
7846f45ec7bSml29623 anchor_index = ring_info->hint[pktbufsz_type];
7856f45ec7bSml29623 dvma_addr = bufinfo[anchor_index].dvma_addr;
7866f45ec7bSml29623 chunk_size = bufinfo[anchor_index].buf_size;
7876f45ec7bSml29623 if ((pktbuf_pp >= dvma_addr) &&
7886f45ec7bSml29623 (pktbuf_pp < (dvma_addr + chunk_size))) {
7896f45ec7bSml29623 found = B_TRUE;
7906f45ec7bSml29623 /*
7916f45ec7bSml29623 * check if this is the last buffer in the block
7926f45ec7bSml29623 * If so, then reset the hint for the size;
7936f45ec7bSml29623 */
7946f45ec7bSml29623
7956f45ec7bSml29623 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size))
7966f45ec7bSml29623 ring_info->hint[pktbufsz_type] = NO_HINT;
7976f45ec7bSml29623 }
7986f45ec7bSml29623 }
7996f45ec7bSml29623
8006f45ec7bSml29623 if (found == B_FALSE) {
8016f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
8026f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (!found)"
8036f45ec7bSml29623 "buf_pp $%p btype %d anchor_index %d",
8046f45ec7bSml29623 pkt_buf_addr_pp,
8056f45ec7bSml29623 pktbufsz_type,
8066f45ec7bSml29623 anchor_index));
8076f45ec7bSml29623
8086f45ec7bSml29623 /*
8096f45ec7bSml29623 * This is the first buffer of the block of this
8106f45ec7bSml29623 * size. Need to search the whole information
8116f45ec7bSml29623 * array.
8126f45ec7bSml29623 * the search algorithm uses a binary tree search
8136f45ec7bSml29623 * algorithm. It assumes that the information is
8146f45ec7bSml29623 * already sorted with increasing order
8156f45ec7bSml29623 * info[0] < info[1] < info[2] .... < info[n-1]
8166f45ec7bSml29623 * where n is the size of the information array
8176f45ec7bSml29623 */
8186f45ec7bSml29623 r_index = rbr_p->num_blocks - 1;
8196f45ec7bSml29623 l_index = 0;
8206f45ec7bSml29623 search_done = B_FALSE;
8216f45ec7bSml29623 anchor_index = MID_INDEX(r_index, l_index);
8226f45ec7bSml29623 while (search_done == B_FALSE) {
8236f45ec7bSml29623 if ((r_index == l_index) ||
8246f45ec7bSml29623 (iteration >= max_iterations))
8256f45ec7bSml29623 search_done = B_TRUE;
8266f45ec7bSml29623 end_side = TO_RIGHT; /* to the right */
8276f45ec7bSml29623 base_side = TO_LEFT; /* to the left */
8286f45ec7bSml29623 /* read the DVMA address information and sort it */
8296f45ec7bSml29623 dvma_addr = bufinfo[anchor_index].dvma_addr;
8306f45ec7bSml29623 chunk_size = bufinfo[anchor_index].buf_size;
8316f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
8326f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (searching)"
8336f45ec7bSml29623 "buf_pp $%p btype %d "
8346f45ec7bSml29623 "anchor_index %d chunk_size %d dvmaaddr $%p",
8356f45ec7bSml29623 pkt_buf_addr_pp,
8366f45ec7bSml29623 pktbufsz_type,
8376f45ec7bSml29623 anchor_index,
8386f45ec7bSml29623 chunk_size,
8396f45ec7bSml29623 dvma_addr));
8406f45ec7bSml29623
8416f45ec7bSml29623 if (pktbuf_pp >= dvma_addr)
8426f45ec7bSml29623 base_side = TO_RIGHT; /* to the right */
8436f45ec7bSml29623 if (pktbuf_pp < (dvma_addr + chunk_size))
8446f45ec7bSml29623 end_side = TO_LEFT; /* to the left */
8456f45ec7bSml29623
8466f45ec7bSml29623 switch (base_side + end_side) {
8476f45ec7bSml29623 case IN_MIDDLE:
8486f45ec7bSml29623 /* found */
8496f45ec7bSml29623 found = B_TRUE;
8506f45ec7bSml29623 search_done = B_TRUE;
8516f45ec7bSml29623 if ((pktbuf_pp + bufsize) <
8526f45ec7bSml29623 (dvma_addr + chunk_size))
8536f45ec7bSml29623 ring_info->hint[pktbufsz_type] =
8546f45ec7bSml29623 bufinfo[anchor_index].buf_index;
8556f45ec7bSml29623 break;
8566f45ec7bSml29623 case BOTH_RIGHT:
8576f45ec7bSml29623 /* not found: go to the right */
8586f45ec7bSml29623 l_index = anchor_index + 1;
85952ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index);
8606f45ec7bSml29623 break;
8616f45ec7bSml29623
8626f45ec7bSml29623 case BOTH_LEFT:
8636f45ec7bSml29623 /* not found: go to the left */
8646f45ec7bSml29623 r_index = anchor_index - 1;
86552ccf843Smisaki anchor_index = MID_INDEX(r_index, l_index);
8666f45ec7bSml29623 break;
8676f45ec7bSml29623 default: /* should not come here */
8686f45ec7bSml29623 return (NXGE_ERROR);
8696f45ec7bSml29623 }
8706f45ec7bSml29623 iteration++;
8716f45ec7bSml29623 }
8726f45ec7bSml29623
8736f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
8746f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (search done)"
8756f45ec7bSml29623 "buf_pp $%p btype %d anchor_index %d",
8766f45ec7bSml29623 pkt_buf_addr_pp,
8776f45ec7bSml29623 pktbufsz_type,
8786f45ec7bSml29623 anchor_index));
8796f45ec7bSml29623 }
8806f45ec7bSml29623
8816f45ec7bSml29623 if (found == B_FALSE) {
8826f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
8836f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (search failed)"
8846f45ec7bSml29623 "buf_pp $%p btype %d anchor_index %d",
8856f45ec7bSml29623 pkt_buf_addr_pp,
8866f45ec7bSml29623 pktbufsz_type,
8876f45ec7bSml29623 anchor_index));
8886f45ec7bSml29623 return (NXGE_ERROR);
8896f45ec7bSml29623 }
8906f45ec7bSml29623
8916f45ec7bSml29623 found_index:
8926f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
8936f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (FOUND1)"
8946f45ec7bSml29623 "buf_pp $%p btype %d bufsize %d anchor_index %d",
8956f45ec7bSml29623 pkt_buf_addr_pp,
8966f45ec7bSml29623 pktbufsz_type,
8976f45ec7bSml29623 bufsize,
8986f45ec7bSml29623 anchor_index));
8996f45ec7bSml29623
9006f45ec7bSml29623 /* index of the first block in this chunk */
9016f45ec7bSml29623 chunk_index = bufinfo[anchor_index].start_index;
9026f45ec7bSml29623 dvma_addr = bufinfo[anchor_index].dvma_addr;
9036f45ec7bSml29623 page_size_mask = ring_info->block_size_mask;
9046f45ec7bSml29623
9056f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
9066f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)"
9076f45ec7bSml29623 "buf_pp $%p btype %d bufsize %d "
9086f45ec7bSml29623 "anchor_index %d chunk_index %d dvma $%p",
9096f45ec7bSml29623 pkt_buf_addr_pp,
9106f45ec7bSml29623 pktbufsz_type,
9116f45ec7bSml29623 bufsize,
9126f45ec7bSml29623 anchor_index,
9136f45ec7bSml29623 chunk_index,
9146f45ec7bSml29623 dvma_addr));
9156f45ec7bSml29623
9166f45ec7bSml29623 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */
9176f45ec7bSml29623 block_size = rbr_p->block_size; /* System block(page) size */
9186f45ec7bSml29623
9196f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
9206f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)"
9216f45ec7bSml29623 "buf_pp $%p btype %d bufsize %d "
9226f45ec7bSml29623 "anchor_index %d chunk_index %d dvma $%p "
9236f45ec7bSml29623 "offset %d block_size %d",
9246f45ec7bSml29623 pkt_buf_addr_pp,
9256f45ec7bSml29623 pktbufsz_type,
9266f45ec7bSml29623 bufsize,
9276f45ec7bSml29623 anchor_index,
9286f45ec7bSml29623 chunk_index,
9296f45ec7bSml29623 dvma_addr,
9306f45ec7bSml29623 offset,
9316f45ec7bSml29623 block_size));
9326f45ec7bSml29623
9336f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index"));
9346f45ec7bSml29623
9356f45ec7bSml29623 block_index = (offset / block_size); /* index within chunk */
9366f45ec7bSml29623 total_index = chunk_index + block_index;
9376f45ec7bSml29623
9386f45ec7bSml29623
9396f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
9406f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: "
9416f45ec7bSml29623 "total_index %d dvma_addr $%p "
9426f45ec7bSml29623 "offset %d block_size %d "
9436f45ec7bSml29623 "block_index %d ",
9446f45ec7bSml29623 total_index, dvma_addr,
9456f45ec7bSml29623 offset, block_size,
9466f45ec7bSml29623 block_index));
947adfcba55Sjoycey *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr +
948adfcba55Sjoycey (uint64_t)offset);
9496f45ec7bSml29623
9506f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
9516f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: "
9526f45ec7bSml29623 "total_index %d dvma_addr $%p "
9536f45ec7bSml29623 "offset %d block_size %d "
9546f45ec7bSml29623 "block_index %d "
9556f45ec7bSml29623 "*pkt_buf_addr_p $%p",
9566f45ec7bSml29623 total_index, dvma_addr,
9576f45ec7bSml29623 offset, block_size,
9586f45ec7bSml29623 block_index,
9596f45ec7bSml29623 *pkt_buf_addr_p));
9606f45ec7bSml29623
9616f45ec7bSml29623
9626f45ec7bSml29623 *msg_index = total_index;
9636f45ec7bSml29623 *bufoffset = (offset & page_size_mask);
9646f45ec7bSml29623
9656f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
9666f45ec7bSml29623 "==> nxge_rxbuf_pp_to_vp: get msg index: "
9676f45ec7bSml29623 "msg_index %d bufoffset_index %d",
9686f45ec7bSml29623 *msg_index,
9696f45ec7bSml29623 *bufoffset));
9706f45ec7bSml29623
9716f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp"));
9726f45ec7bSml29623
9736f45ec7bSml29623 return (NXGE_OK);
9746f45ec7bSml29623 }
9756f45ec7bSml29623
9766f45ec7bSml29623 /*
9776f45ec7bSml29623 * used by quick sort (qsort) function
9786f45ec7bSml29623 * to perform comparison
9796f45ec7bSml29623 */
9806f45ec7bSml29623 static int
nxge_sort_compare(const void * p1,const void * p2)9816f45ec7bSml29623 nxge_sort_compare(const void *p1, const void *p2)
9826f45ec7bSml29623 {
9836f45ec7bSml29623
9846f45ec7bSml29623 rxbuf_index_info_t *a, *b;
9856f45ec7bSml29623
9866f45ec7bSml29623 a = (rxbuf_index_info_t *)p1;
9876f45ec7bSml29623 b = (rxbuf_index_info_t *)p2;
9886f45ec7bSml29623
9896f45ec7bSml29623 if (a->dvma_addr > b->dvma_addr)
9906f45ec7bSml29623 return (1);
9916f45ec7bSml29623 if (a->dvma_addr < b->dvma_addr)
9926f45ec7bSml29623 return (-1);
9936f45ec7bSml29623 return (0);
9946f45ec7bSml29623 }
9956f45ec7bSml29623
9966f45ec7bSml29623
9976f45ec7bSml29623
9986f45ec7bSml29623 /*
9996f45ec7bSml29623 * grabbed this sort implementation from common/syscall/avl.c
10006f45ec7bSml29623 *
10016f45ec7bSml29623 */
10026f45ec7bSml29623 /*
10036f45ec7bSml29623 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified.
10046f45ec7bSml29623 * v = Ptr to array/vector of objs
10056f45ec7bSml29623 * n = # objs in the array
10066f45ec7bSml29623 * s = size of each obj (must be multiples of a word size)
10076f45ec7bSml29623 * f = ptr to function to compare two objs
10086f45ec7bSml29623 * returns (-1 = less than, 0 = equal, 1 = greater than
10096f45ec7bSml29623 */
10106f45ec7bSml29623 void
nxge_ksort(caddr_t v,int n,int s,int (* f)())10116f45ec7bSml29623 nxge_ksort(caddr_t v, int n, int s, int (*f)())
10126f45ec7bSml29623 {
10136f45ec7bSml29623 int g, i, j, ii;
10146f45ec7bSml29623 unsigned int *p1, *p2;
10156f45ec7bSml29623 unsigned int tmp;
10166f45ec7bSml29623
10176f45ec7bSml29623 /* No work to do */
10186f45ec7bSml29623 if (v == NULL || n <= 1)
10196f45ec7bSml29623 return;
10206f45ec7bSml29623 /* Sanity check on arguments */
10216f45ec7bSml29623 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0);
10226f45ec7bSml29623 ASSERT(s > 0);
10236f45ec7bSml29623
10246f45ec7bSml29623 for (g = n / 2; g > 0; g /= 2) {
10256f45ec7bSml29623 for (i = g; i < n; i++) {
10266f45ec7bSml29623 for (j = i - g; j >= 0 &&
10276f45ec7bSml29623 (*f)(v + j * s, v + (j + g) * s) == 1;
10286f45ec7bSml29623 j -= g) {
10296f45ec7bSml29623 p1 = (unsigned *)(v + j * s);
10306f45ec7bSml29623 p2 = (unsigned *)(v + (j + g) * s);
10316f45ec7bSml29623 for (ii = 0; ii < s / 4; ii++) {
10326f45ec7bSml29623 tmp = *p1;
10336f45ec7bSml29623 *p1++ = *p2;
10346f45ec7bSml29623 *p2++ = tmp;
10356f45ec7bSml29623 }
10366f45ec7bSml29623 }
10376f45ec7bSml29623 }
10386f45ec7bSml29623 }
10396f45ec7bSml29623 }
10406f45ec7bSml29623
10416f45ec7bSml29623 /*
10426f45ec7bSml29623 * Initialize data structures required for rxdma
10436f45ec7bSml29623 * buffer dvma->vmem address lookup
10446f45ec7bSml29623 */
10456f45ec7bSml29623 /*ARGSUSED*/
10466f45ec7bSml29623 static nxge_status_t
nxge_rxbuf_index_info_init(p_nxge_t nxgep,p_rx_rbr_ring_t rbrp)10476f45ec7bSml29623 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp)
10486f45ec7bSml29623 {
10496f45ec7bSml29623
10506f45ec7bSml29623 int index;
10516f45ec7bSml29623 rxring_info_t *ring_info;
10526f45ec7bSml29623 int max_iteration = 0, max_index = 0;
10536f45ec7bSml29623
10546f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init"));
10556f45ec7bSml29623
10566f45ec7bSml29623 ring_info = rbrp->ring_info;
10576f45ec7bSml29623 ring_info->hint[0] = NO_HINT;
10586f45ec7bSml29623 ring_info->hint[1] = NO_HINT;
10596f45ec7bSml29623 ring_info->hint[2] = NO_HINT;
10606f45ec7bSml29623 max_index = rbrp->num_blocks;
10616f45ec7bSml29623
10626f45ec7bSml29623 /* read the DVMA address information and sort it */
10636f45ec7bSml29623 /* do init of the information array */
10646f45ec7bSml29623
10656f45ec7bSml29623
10666f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
10676f45ec7bSml29623 " nxge_rxbuf_index_info_init Sort ptrs"));
10686f45ec7bSml29623
10696f45ec7bSml29623 /* sort the array */
10706f45ec7bSml29623 nxge_ksort((void *)ring_info->buffer, max_index,
10716f45ec7bSml29623 sizeof (rxbuf_index_info_t), nxge_sort_compare);
10726f45ec7bSml29623
10736f45ec7bSml29623
10746f45ec7bSml29623
10756f45ec7bSml29623 for (index = 0; index < max_index; index++) {
10766f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
10776f45ec7bSml29623 " nxge_rxbuf_index_info_init: sorted chunk %d "
10786f45ec7bSml29623 " ioaddr $%p kaddr $%p size %x",
10796f45ec7bSml29623 index, ring_info->buffer[index].dvma_addr,
10806f45ec7bSml29623 ring_info->buffer[index].kaddr,
10816f45ec7bSml29623 ring_info->buffer[index].buf_size));
10826f45ec7bSml29623 }
10836f45ec7bSml29623
10846f45ec7bSml29623 max_iteration = 0;
10856f45ec7bSml29623 while (max_index >= (1ULL << max_iteration))
10866f45ec7bSml29623 max_iteration++;
10876f45ec7bSml29623 ring_info->max_iterations = max_iteration + 1;
10886f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA2_CTL,
10896f45ec7bSml29623 " nxge_rxbuf_index_info_init Find max iter %d",
10906f45ec7bSml29623 ring_info->max_iterations));
10916f45ec7bSml29623
10926f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init"));
10936f45ec7bSml29623 return (NXGE_OK);
10946f45ec7bSml29623 }
10956f45ec7bSml29623
10966f45ec7bSml29623 /* ARGSUSED */
10976f45ec7bSml29623 void
nxge_dump_rcr_entry(p_nxge_t nxgep,p_rcr_entry_t entry_p)10986f45ec7bSml29623 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p)
10996f45ec7bSml29623 {
11006f45ec7bSml29623 #ifdef NXGE_DEBUG
11016f45ec7bSml29623
11026f45ec7bSml29623 uint32_t bptr;
11036f45ec7bSml29623 uint64_t pp;
11046f45ec7bSml29623
11056f45ec7bSml29623 bptr = entry_p->bits.hdw.pkt_buf_addr;
11066f45ec7bSml29623
11076f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
11086f45ec7bSml29623 "\trcr entry $%p "
11096f45ec7bSml29623 "\trcr entry 0x%0llx "
11106f45ec7bSml29623 "\trcr entry 0x%08x "
11116f45ec7bSml29623 "\trcr entry 0x%08x "
11126f45ec7bSml29623 "\tvalue 0x%0llx\n"
11136f45ec7bSml29623 "\tmulti = %d\n"
11146f45ec7bSml29623 "\tpkt_type = 0x%x\n"
11156f45ec7bSml29623 "\tzero_copy = %d\n"
11166f45ec7bSml29623 "\tnoport = %d\n"
11176f45ec7bSml29623 "\tpromis = %d\n"
11186f45ec7bSml29623 "\terror = 0x%04x\n"
11196f45ec7bSml29623 "\tdcf_err = 0x%01x\n"
11206f45ec7bSml29623 "\tl2_len = %d\n"
11216f45ec7bSml29623 "\tpktbufsize = %d\n"
11226f45ec7bSml29623 "\tpkt_buf_addr = $%p\n"
11236f45ec7bSml29623 "\tpkt_buf_addr (<< 6) = $%p\n",
11246f45ec7bSml29623 entry_p,
11256f45ec7bSml29623 *(int64_t *)entry_p,
11266f45ec7bSml29623 *(int32_t *)entry_p,
11276f45ec7bSml29623 *(int32_t *)((char *)entry_p + 32),
11286f45ec7bSml29623 entry_p->value,
11296f45ec7bSml29623 entry_p->bits.hdw.multi,
11306f45ec7bSml29623 entry_p->bits.hdw.pkt_type,
11316f45ec7bSml29623 entry_p->bits.hdw.zero_copy,
11326f45ec7bSml29623 entry_p->bits.hdw.noport,
11336f45ec7bSml29623 entry_p->bits.hdw.promis,
11346f45ec7bSml29623 entry_p->bits.hdw.error,
11356f45ec7bSml29623 entry_p->bits.hdw.dcf_err,
11366f45ec7bSml29623 entry_p->bits.hdw.l2_len,
11376f45ec7bSml29623 entry_p->bits.hdw.pktbufsz,
11386f45ec7bSml29623 bptr,
11396f45ec7bSml29623 entry_p->bits.ldw.pkt_buf_addr));
11406f45ec7bSml29623
11416f45ec7bSml29623 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) <<
11426f45ec7bSml29623 RCR_PKT_BUF_ADDR_SHIFT;
11436f45ec7bSml29623
11446f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d",
11456f45ec7bSml29623 pp, (*(int64_t *)entry_p >> 40) & 0x3fff));
11466f45ec7bSml29623 #endif
11476f45ec7bSml29623 }
11486f45ec7bSml29623
11496f45ec7bSml29623 void
nxge_rxdma_regs_dump(p_nxge_t nxgep,int rdc)11506f45ec7bSml29623 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc)
11516f45ec7bSml29623 {
11526f45ec7bSml29623 npi_handle_t handle;
11536f45ec7bSml29623 rbr_stat_t rbr_stat;
11546f45ec7bSml29623 addr44_t hd_addr;
11556f45ec7bSml29623 addr44_t tail_addr;
11566f45ec7bSml29623 uint16_t qlen;
11576f45ec7bSml29623
11586f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
11596f45ec7bSml29623 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc));
11606f45ec7bSml29623
11616f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
11626f45ec7bSml29623
11636f45ec7bSml29623 /* RBR head */
11646f45ec7bSml29623 hd_addr.addr = 0;
11656f45ec7bSml29623 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr);
116653f3d8ecSyc148097 printf("nxge_rxdma_regs_dump: got hdptr $%p \n",
11676f45ec7bSml29623 (void *)hd_addr.addr);
11686f45ec7bSml29623
11696f45ec7bSml29623 /* RBR stats */
11706f45ec7bSml29623 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat);
11716f45ec7bSml29623 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen);
11726f45ec7bSml29623
11736f45ec7bSml29623 /* RCR tail */
11746f45ec7bSml29623 tail_addr.addr = 0;
11756f45ec7bSml29623 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr);
117653f3d8ecSyc148097 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n",
11776f45ec7bSml29623 (void *)tail_addr.addr);
11786f45ec7bSml29623
11796f45ec7bSml29623 /* RCR qlen */
11806f45ec7bSml29623 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen);
11816f45ec7bSml29623 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen);
11826f45ec7bSml29623
11836f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
11846f45ec7bSml29623 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc));
11856f45ec7bSml29623 }
11866f45ec7bSml29623
11876f45ec7bSml29623 nxge_status_t
nxge_rxdma_hw_mode(p_nxge_t nxgep,boolean_t enable)11886f45ec7bSml29623 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable)
11896f45ec7bSml29623 {
1190678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
1191678453a8Sspeer nxge_status_t status;
1192678453a8Sspeer npi_status_t rs;
1193678453a8Sspeer int rdc;
11946f45ec7bSml29623
11956f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
11966f45ec7bSml29623 "==> nxge_rxdma_hw_mode: mode %d", enable));
11976f45ec7bSml29623
11986f45ec7bSml29623 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
11996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
12006f45ec7bSml29623 "<== nxge_rxdma_mode: not initialized"));
12016f45ec7bSml29623 return (NXGE_ERROR);
12026f45ec7bSml29623 }
12036f45ec7bSml29623
1204678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1205678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL,
1206678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: "
1207678453a8Sspeer "NULL ring pointer(s)"));
12086f45ec7bSml29623 return (NXGE_ERROR);
12096f45ec7bSml29623 }
12106f45ec7bSml29623
1211678453a8Sspeer if (set->owned.map == 0) {
12126f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1213678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels"));
1214b37cc459SToomas Soome return (0);
12156f45ec7bSml29623 }
12166f45ec7bSml29623
1217*e3d11eeeSToomas Soome rs = 0;
1218678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1219678453a8Sspeer if ((1 << rdc) & set->owned.map) {
1220678453a8Sspeer rx_rbr_ring_t *ring =
1221678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc];
1222678453a8Sspeer npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep);
1223678453a8Sspeer if (ring) {
12246f45ec7bSml29623 if (enable) {
12256f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1226678453a8Sspeer "==> nxge_rxdma_hw_mode: "
1227678453a8Sspeer "channel %d (enable)", rdc));
1228678453a8Sspeer rs = npi_rxdma_cfg_rdc_enable
1229678453a8Sspeer (handle, rdc);
12306f45ec7bSml29623 } else {
12316f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
1232678453a8Sspeer "==> nxge_rxdma_hw_mode: "
1233678453a8Sspeer "channel %d disable)", rdc));
1234678453a8Sspeer rs = npi_rxdma_cfg_rdc_disable
1235678453a8Sspeer (handle, rdc);
1236678453a8Sspeer }
1237678453a8Sspeer }
12386f45ec7bSml29623 }
12396f45ec7bSml29623 }
12406f45ec7bSml29623
12416f45ec7bSml29623 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs);
12426f45ec7bSml29623
12436f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
12446f45ec7bSml29623 "<== nxge_rxdma_hw_mode: status 0x%x", status));
12456f45ec7bSml29623
12466f45ec7bSml29623 return (status);
12476f45ec7bSml29623 }
12486f45ec7bSml29623
12496f45ec7bSml29623 void
nxge_rxdma_enable_channel(p_nxge_t nxgep,uint16_t channel)12506f45ec7bSml29623 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel)
12516f45ec7bSml29623 {
12526f45ec7bSml29623 npi_handle_t handle;
12536f45ec7bSml29623
12546f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
12556f45ec7bSml29623 "==> nxge_rxdma_enable_channel: channel %d", channel));
12566f45ec7bSml29623
12576f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
12586f45ec7bSml29623 (void) npi_rxdma_cfg_rdc_enable(handle, channel);
12596f45ec7bSml29623
12606f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel"));
12616f45ec7bSml29623 }
12626f45ec7bSml29623
12636f45ec7bSml29623 void
nxge_rxdma_disable_channel(p_nxge_t nxgep,uint16_t channel)12646f45ec7bSml29623 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel)
12656f45ec7bSml29623 {
12666f45ec7bSml29623 npi_handle_t handle;
12676f45ec7bSml29623
12686f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL,
12696f45ec7bSml29623 "==> nxge_rxdma_disable_channel: channel %d", channel));
12706f45ec7bSml29623
12716f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
12726f45ec7bSml29623 (void) npi_rxdma_cfg_rdc_disable(handle, channel);
12736f45ec7bSml29623
12746f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel"));
12756f45ec7bSml29623 }
12766f45ec7bSml29623
12776f45ec7bSml29623 void
nxge_hw_start_rx(p_nxge_t nxgep)12786f45ec7bSml29623 nxge_hw_start_rx(p_nxge_t nxgep)
12796f45ec7bSml29623 {
12806f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx"));
12816f45ec7bSml29623
12826f45ec7bSml29623 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START);
12836f45ec7bSml29623 (void) nxge_rx_mac_enable(nxgep);
12846f45ec7bSml29623
12856f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx"));
12866f45ec7bSml29623 }
12876f45ec7bSml29623
12886f45ec7bSml29623 /*ARGSUSED*/
12896f45ec7bSml29623 void
nxge_fixup_rxdma_rings(p_nxge_t nxgep)12906f45ec7bSml29623 nxge_fixup_rxdma_rings(p_nxge_t nxgep)
12916f45ec7bSml29623 {
1292678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
1293678453a8Sspeer int rdc;
12946f45ec7bSml29623
12956f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings"));
12966f45ec7bSml29623
1297678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1298678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL,
1299678453a8Sspeer "<== nxge_tx_port_fatal_err_recover: "
1300678453a8Sspeer "NULL ring pointer(s)"));
13016f45ec7bSml29623 return;
13026f45ec7bSml29623 }
13036f45ec7bSml29623
1304678453a8Sspeer if (set->owned.map == 0) {
13056f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1306678453a8Sspeer "nxge_rxdma_regs_dump_channels: no channels"));
13076f45ec7bSml29623 return;
13086f45ec7bSml29623 }
13096f45ec7bSml29623
1310678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1311678453a8Sspeer if ((1 << rdc) & set->owned.map) {
1312678453a8Sspeer rx_rbr_ring_t *ring =
1313678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc];
1314678453a8Sspeer if (ring) {
1315678453a8Sspeer nxge_rxdma_hw_stop(nxgep, rdc);
13166f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1317678453a8Sspeer "==> nxge_fixup_rxdma_rings: "
1318678453a8Sspeer "channel %d ring $%px",
1319678453a8Sspeer rdc, ring));
13203587e8e2SMichael Speer (void) nxge_rxdma_fix_channel(nxgep, rdc);
1321678453a8Sspeer }
1322678453a8Sspeer }
13236f45ec7bSml29623 }
13246f45ec7bSml29623
13256f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings"));
13266f45ec7bSml29623 }
13276f45ec7bSml29623
13286f45ec7bSml29623 void
nxge_rxdma_fix_channel(p_nxge_t nxgep,uint16_t channel)13296f45ec7bSml29623 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel)
13306f45ec7bSml29623 {
13316f45ec7bSml29623 int ndmas;
13326f45ec7bSml29623 p_rx_rbr_rings_t rx_rbr_rings;
13336f45ec7bSml29623 p_rx_rbr_ring_t *rbr_rings;
13346f45ec7bSml29623 p_rx_rcr_rings_t rx_rcr_rings;
13356f45ec7bSml29623 p_rx_rcr_ring_t *rcr_rings;
13366f45ec7bSml29623 p_rx_mbox_areas_t rx_mbox_areas_p;
13376f45ec7bSml29623 p_rx_mbox_t *rx_mbox_p;
13386f45ec7bSml29623 p_nxge_dma_pool_t dma_buf_poolp;
13396f45ec7bSml29623 p_nxge_dma_pool_t dma_cntl_poolp;
13406f45ec7bSml29623 p_rx_rbr_ring_t rbrp;
13416f45ec7bSml29623 p_rx_rcr_ring_t rcrp;
13426f45ec7bSml29623 p_rx_mbox_t mboxp;
13436f45ec7bSml29623 p_nxge_dma_common_t dmap;
13446f45ec7bSml29623 nxge_status_t status = NXGE_OK;
13456f45ec7bSml29623
13463587e8e2SMichael Speer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel"));
13476f45ec7bSml29623
13486f45ec7bSml29623 (void) nxge_rxdma_stop_channel(nxgep, channel);
13496f45ec7bSml29623
13506f45ec7bSml29623 dma_buf_poolp = nxgep->rx_buf_pool_p;
13516f45ec7bSml29623 dma_cntl_poolp = nxgep->rx_cntl_pool_p;
13526f45ec7bSml29623
13536f45ec7bSml29623 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) {
13546f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
13553587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: buf not allocated"));
13566f45ec7bSml29623 return;
13576f45ec7bSml29623 }
13586f45ec7bSml29623
13596f45ec7bSml29623 ndmas = dma_buf_poolp->ndmas;
13606f45ec7bSml29623 if (!ndmas) {
13616f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
13623587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: no dma allocated"));
13636f45ec7bSml29623 return;
13646f45ec7bSml29623 }
13656f45ec7bSml29623
13666f45ec7bSml29623 rx_rbr_rings = nxgep->rx_rbr_rings;
13676f45ec7bSml29623 rx_rcr_rings = nxgep->rx_rcr_rings;
13686f45ec7bSml29623 rbr_rings = rx_rbr_rings->rbr_rings;
13696f45ec7bSml29623 rcr_rings = rx_rcr_rings->rcr_rings;
13706f45ec7bSml29623 rx_mbox_areas_p = nxgep->rx_mbox_areas_p;
13716f45ec7bSml29623 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas;
13726f45ec7bSml29623
13736f45ec7bSml29623 /* Reinitialize the receive block and completion rings */
13743587e8e2SMichael Speer rbrp = (p_rx_rbr_ring_t)rbr_rings[channel],
13753587e8e2SMichael Speer rcrp = (p_rx_rcr_ring_t)rcr_rings[channel],
13763587e8e2SMichael Speer mboxp = (p_rx_mbox_t)rx_mbox_p[channel];
13776f45ec7bSml29623
13786f45ec7bSml29623 rbrp->rbr_wr_index = (rbrp->rbb_max - 1);
13796f45ec7bSml29623 rbrp->rbr_rd_index = 0;
13806f45ec7bSml29623 rcrp->comp_rd_index = 0;
13816f45ec7bSml29623 rcrp->comp_wt_index = 0;
13826f45ec7bSml29623
13836f45ec7bSml29623 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
13846f45ec7bSml29623 bzero((caddr_t)dmap->kaddrp, dmap->alength);
13856f45ec7bSml29623
13866f45ec7bSml29623 status = nxge_rxdma_start_channel(nxgep, channel,
13876f45ec7bSml29623 rbrp, rcrp, mboxp);
13886f45ec7bSml29623 if (status != NXGE_OK) {
13893587e8e2SMichael Speer goto nxge_rxdma_fix_channel_fail;
1390da14cebeSEric Cheng }
1391da14cebeSEric Cheng
1392da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL,
13933587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: success (0x%08x)", status));
13943587e8e2SMichael Speer return;
1395da14cebeSEric Cheng
13963587e8e2SMichael Speer nxge_rxdma_fix_channel_fail:
1397da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL,
13983587e8e2SMichael Speer "<== nxge_rxdma_fix_channel: failed (0x%08x)", status));
13996f45ec7bSml29623 }
14006f45ec7bSml29623
14016f45ec7bSml29623 p_rx_rbr_ring_t
nxge_rxdma_get_rbr_ring(p_nxge_t nxgep,uint16_t channel)14026f45ec7bSml29623 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel)
14036f45ec7bSml29623 {
1404678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
1405678453a8Sspeer nxge_channel_t rdc;
14066f45ec7bSml29623
14076f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
14086f45ec7bSml29623 "==> nxge_rxdma_get_rbr_ring: channel %d", channel));
14096f45ec7bSml29623
1410678453a8Sspeer if (nxgep->rx_rbr_rings == 0 || nxgep->rx_rbr_rings->rbr_rings == 0) {
1411678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL,
1412678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: "
1413678453a8Sspeer "NULL ring pointer(s)"));
14146f45ec7bSml29623 return (NULL);
14156f45ec7bSml29623 }
14166f45ec7bSml29623
1417678453a8Sspeer if (set->owned.map == 0) {
14186f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1419678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels"));
1420678453a8Sspeer return (NULL);
1421678453a8Sspeer }
14226f45ec7bSml29623
1423678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1424678453a8Sspeer if ((1 << rdc) & set->owned.map) {
1425678453a8Sspeer rx_rbr_ring_t *ring =
1426678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[rdc];
1427678453a8Sspeer if (ring) {
1428678453a8Sspeer if (channel == ring->rdc) {
14296f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1430678453a8Sspeer "==> nxge_rxdma_get_rbr_ring: "
1431678453a8Sspeer "channel %d ring $%p", rdc, ring));
1432678453a8Sspeer return (ring);
1433678453a8Sspeer }
1434678453a8Sspeer }
14356f45ec7bSml29623 }
14366f45ec7bSml29623 }
14376f45ec7bSml29623
14386f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
14396f45ec7bSml29623 "<== nxge_rxdma_get_rbr_ring: not found"));
14406f45ec7bSml29623
14416f45ec7bSml29623 return (NULL);
14426f45ec7bSml29623 }
14436f45ec7bSml29623
14446f45ec7bSml29623 p_rx_rcr_ring_t
nxge_rxdma_get_rcr_ring(p_nxge_t nxgep,uint16_t channel)14456f45ec7bSml29623 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel)
14466f45ec7bSml29623 {
1447678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
1448678453a8Sspeer nxge_channel_t rdc;
14496f45ec7bSml29623
14506f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
14516f45ec7bSml29623 "==> nxge_rxdma_get_rcr_ring: channel %d", channel));
14526f45ec7bSml29623
1453678453a8Sspeer if (nxgep->rx_rcr_rings == 0 || nxgep->rx_rcr_rings->rcr_rings == 0) {
1454678453a8Sspeer NXGE_DEBUG_MSG((nxgep, TX_CTL,
1455678453a8Sspeer "<== nxge_rxdma_get_rcr_ring: "
1456678453a8Sspeer "NULL ring pointer(s)"));
14576f45ec7bSml29623 return (NULL);
14586f45ec7bSml29623 }
14596f45ec7bSml29623
1460678453a8Sspeer if (set->owned.map == 0) {
14616f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1462678453a8Sspeer "<== nxge_rxdma_get_rbr_ring: no channels"));
1463678453a8Sspeer return (NULL);
1464678453a8Sspeer }
14656f45ec7bSml29623
1466678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
1467678453a8Sspeer if ((1 << rdc) & set->owned.map) {
1468678453a8Sspeer rx_rcr_ring_t *ring =
1469678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[rdc];
1470678453a8Sspeer if (ring) {
1471678453a8Sspeer if (channel == ring->rdc) {
14726f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
1473678453a8Sspeer "==> nxge_rxdma_get_rcr_ring: "
1474678453a8Sspeer "channel %d ring $%p", rdc, ring));
1475678453a8Sspeer return (ring);
1476678453a8Sspeer }
1477678453a8Sspeer }
14786f45ec7bSml29623 }
14796f45ec7bSml29623 }
14806f45ec7bSml29623
14816f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
14826f45ec7bSml29623 "<== nxge_rxdma_get_rcr_ring: not found"));
14836f45ec7bSml29623
14846f45ec7bSml29623 return (NULL);
14856f45ec7bSml29623 }
14866f45ec7bSml29623
14876f45ec7bSml29623 /*
14886f45ec7bSml29623 * Static functions start here.
14896f45ec7bSml29623 */
14906f45ec7bSml29623 static p_rx_msg_t
nxge_allocb(size_t size,uint32_t pri,p_nxge_dma_common_t dmabuf_p)14916f45ec7bSml29623 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p)
14926f45ec7bSml29623 {
14936f45ec7bSml29623 p_rx_msg_t nxge_mp = NULL;
14946f45ec7bSml29623 p_nxge_dma_common_t dmamsg_p;
14956f45ec7bSml29623 uchar_t *buffer;
14966f45ec7bSml29623
14976f45ec7bSml29623 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP);
14986f45ec7bSml29623 if (nxge_mp == NULL) {
149956d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
15006f45ec7bSml29623 "Allocation of a rx msg failed."));
15016f45ec7bSml29623 goto nxge_allocb_exit;
15026f45ec7bSml29623 }
15036f45ec7bSml29623
15046f45ec7bSml29623 nxge_mp->use_buf_pool = B_FALSE;
15056f45ec7bSml29623 if (dmabuf_p) {
15066f45ec7bSml29623 nxge_mp->use_buf_pool = B_TRUE;
15076f45ec7bSml29623 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma;
15086f45ec7bSml29623 *dmamsg_p = *dmabuf_p;
15096f45ec7bSml29623 dmamsg_p->nblocks = 1;
15106f45ec7bSml29623 dmamsg_p->block_size = size;
15116f45ec7bSml29623 dmamsg_p->alength = size;
15126f45ec7bSml29623 buffer = (uchar_t *)dmabuf_p->kaddrp;
15136f45ec7bSml29623
15146f45ec7bSml29623 dmabuf_p->kaddrp = (void *)
15156f45ec7bSml29623 ((char *)dmabuf_p->kaddrp + size);
15166f45ec7bSml29623 dmabuf_p->ioaddr_pp = (void *)
15176f45ec7bSml29623 ((char *)dmabuf_p->ioaddr_pp + size);
15186f45ec7bSml29623 dmabuf_p->alength -= size;
15196f45ec7bSml29623 dmabuf_p->offset += size;
15206f45ec7bSml29623 dmabuf_p->dma_cookie.dmac_laddress += size;
15216f45ec7bSml29623 dmabuf_p->dma_cookie.dmac_size -= size;
15226f45ec7bSml29623
15236f45ec7bSml29623 } else {
15246f45ec7bSml29623 buffer = KMEM_ALLOC(size, KM_NOSLEEP);
15256f45ec7bSml29623 if (buffer == NULL) {
152656d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
15276f45ec7bSml29623 "Allocation of a receive page failed."));
15286f45ec7bSml29623 goto nxge_allocb_fail1;
15296f45ec7bSml29623 }
15306f45ec7bSml29623 }
15316f45ec7bSml29623
15326f45ec7bSml29623 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb);
15336f45ec7bSml29623 if (nxge_mp->rx_mblk_p == NULL) {
153456d930aeSspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed."));
15356f45ec7bSml29623 goto nxge_allocb_fail2;
15366f45ec7bSml29623 }
15376f45ec7bSml29623
15386f45ec7bSml29623 nxge_mp->buffer = buffer;
15396f45ec7bSml29623 nxge_mp->block_size = size;
15406f45ec7bSml29623 nxge_mp->freeb.free_func = (void (*)())nxge_freeb;
15416f45ec7bSml29623 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp;
15426f45ec7bSml29623 nxge_mp->ref_cnt = 1;
15436f45ec7bSml29623 nxge_mp->free = B_TRUE;
15446f45ec7bSml29623 nxge_mp->rx_use_bcopy = B_FALSE;
15456f45ec7bSml29623
15466f45ec7bSml29623 atomic_inc_32(&nxge_mblks_pending);
15476f45ec7bSml29623
15486f45ec7bSml29623 goto nxge_allocb_exit;
15496f45ec7bSml29623
15506f45ec7bSml29623 nxge_allocb_fail2:
15516f45ec7bSml29623 if (!nxge_mp->use_buf_pool) {
15526f45ec7bSml29623 KMEM_FREE(buffer, size);
15536f45ec7bSml29623 }
15546f45ec7bSml29623
15556f45ec7bSml29623 nxge_allocb_fail1:
15566f45ec7bSml29623 KMEM_FREE(nxge_mp, sizeof (rx_msg_t));
15576f45ec7bSml29623 nxge_mp = NULL;
15586f45ec7bSml29623
15596f45ec7bSml29623 nxge_allocb_exit:
15606f45ec7bSml29623 return (nxge_mp);
15616f45ec7bSml29623 }
15626f45ec7bSml29623
15636f45ec7bSml29623 p_mblk_t
nxge_dupb(p_rx_msg_t nxge_mp,uint_t offset,size_t size)15646f45ec7bSml29623 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size)
15656f45ec7bSml29623 {
15666f45ec7bSml29623 p_mblk_t mp;
15676f45ec7bSml29623
15686f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb"));
15696f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p "
15706f45ec7bSml29623 "offset = 0x%08X "
15716f45ec7bSml29623 "size = 0x%08X",
15726f45ec7bSml29623 nxge_mp, offset, size));
15736f45ec7bSml29623
15746f45ec7bSml29623 mp = desballoc(&nxge_mp->buffer[offset], size,
15756f45ec7bSml29623 0, &nxge_mp->freeb);
15766f45ec7bSml29623 if (mp == NULL) {
15776f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed"));
15786f45ec7bSml29623 goto nxge_dupb_exit;
15796f45ec7bSml29623 }
15806f45ec7bSml29623 atomic_inc_32(&nxge_mp->ref_cnt);
15816f45ec7bSml29623
15826f45ec7bSml29623
15836f45ec7bSml29623 nxge_dupb_exit:
15846f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p",
15856f45ec7bSml29623 nxge_mp));
15866f45ec7bSml29623 return (mp);
15876f45ec7bSml29623 }
15886f45ec7bSml29623
15896f45ec7bSml29623 p_mblk_t
nxge_dupb_bcopy(p_rx_msg_t nxge_mp,uint_t offset,size_t size)15906f45ec7bSml29623 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size)
15916f45ec7bSml29623 {
15926f45ec7bSml29623 p_mblk_t mp;
15936f45ec7bSml29623 uchar_t *dp;
15946f45ec7bSml29623
15956f45ec7bSml29623 mp = allocb(size + NXGE_RXBUF_EXTRA, 0);
15966f45ec7bSml29623 if (mp == NULL) {
15976f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed"));
15986f45ec7bSml29623 goto nxge_dupb_bcopy_exit;
15996f45ec7bSml29623 }
16006f45ec7bSml29623 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA;
16016f45ec7bSml29623 bcopy((void *)&nxge_mp->buffer[offset], dp, size);
16026f45ec7bSml29623 mp->b_wptr = dp + size;
16036f45ec7bSml29623
16046f45ec7bSml29623 nxge_dupb_bcopy_exit:
16056f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p",
16066f45ec7bSml29623 nxge_mp));
16076f45ec7bSml29623 return (mp);
16086f45ec7bSml29623 }
16096f45ec7bSml29623
16106f45ec7bSml29623 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p,
16116f45ec7bSml29623 p_rx_msg_t rx_msg_p);
16126f45ec7bSml29623
16136f45ec7bSml29623 void
nxge_post_page(p_nxge_t nxgep,p_rx_rbr_ring_t rx_rbr_p,p_rx_msg_t rx_msg_p)16146f45ec7bSml29623 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p)
16156f45ec7bSml29623 {
16166f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page"));
16176f45ec7bSml29623
16186f45ec7bSml29623 /* Reuse this buffer */
16196f45ec7bSml29623 rx_msg_p->free = B_FALSE;
16206f45ec7bSml29623 rx_msg_p->cur_usage_cnt = 0;
16216f45ec7bSml29623 rx_msg_p->max_usage_cnt = 0;
16226f45ec7bSml29623 rx_msg_p->pkt_buf_size = 0;
16236f45ec7bSml29623
16246f45ec7bSml29623 if (rx_rbr_p->rbr_use_bcopy) {
16256f45ec7bSml29623 rx_msg_p->rx_use_bcopy = B_FALSE;
16266f45ec7bSml29623 atomic_dec_32(&rx_rbr_p->rbr_consumed);
16276f45ec7bSml29623 }
16286f45ec7bSml29623
16296f45ec7bSml29623 /*
16306f45ec7bSml29623 * Get the rbr header pointer and its offset index.
16316f45ec7bSml29623 */
16326f45ec7bSml29623 MUTEX_ENTER(&rx_rbr_p->post_lock);
16336f45ec7bSml29623 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) &
16346f45ec7bSml29623 rx_rbr_p->rbr_wrap_mask);
16356f45ec7bSml29623 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr;
16366f45ec7bSml29623 MUTEX_EXIT(&rx_rbr_p->post_lock);
163730ac2e7bSml29623 npi_rxdma_rdc_rbr_kick(NXGE_DEV_NPI_HANDLE(nxgep),
163830ac2e7bSml29623 rx_rbr_p->rdc, 1);
16396f45ec7bSml29623
16406f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
16416f45ec7bSml29623 "<== nxge_post_page (channel %d post_next_index %d)",
16426f45ec7bSml29623 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index));
16436f45ec7bSml29623
16446f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page"));
16456f45ec7bSml29623 }
16466f45ec7bSml29623
16476f45ec7bSml29623 void
nxge_freeb(p_rx_msg_t rx_msg_p)16486f45ec7bSml29623 nxge_freeb(p_rx_msg_t rx_msg_p)
16496f45ec7bSml29623 {
16506f45ec7bSml29623 size_t size;
16516f45ec7bSml29623 uchar_t *buffer = NULL;
16526f45ec7bSml29623 int ref_cnt;
1653958cea9eSml29623 boolean_t free_state = B_FALSE;
16546f45ec7bSml29623
1655007969e0Stm144005 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p;
1656007969e0Stm144005
16576f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb"));
16586f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM2_CTL,
16596f45ec7bSml29623 "nxge_freeb:rx_msg_p = $%p (block pending %d)",
16606f45ec7bSml29623 rx_msg_p, nxge_mblks_pending));
16616f45ec7bSml29623
1662958cea9eSml29623 /*
1663958cea9eSml29623 * First we need to get the free state, then
1664958cea9eSml29623 * atomic decrement the reference count to prevent
1665958cea9eSml29623 * the race condition with the interrupt thread that
1666958cea9eSml29623 * is processing a loaned up buffer block.
1667958cea9eSml29623 */
1668958cea9eSml29623 free_state = rx_msg_p->free;
16691a5e258fSJosef 'Jeff' Sipek ref_cnt = atomic_dec_32_nv(&rx_msg_p->ref_cnt);
16706f45ec7bSml29623 if (!ref_cnt) {
167130ac2e7bSml29623 atomic_dec_32(&nxge_mblks_pending);
16726f45ec7bSml29623 buffer = rx_msg_p->buffer;
16736f45ec7bSml29623 size = rx_msg_p->block_size;
16746f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: "
16756f45ec7bSml29623 "will free: rx_msg_p = $%p (block pending %d)",
167656d930aeSspeer rx_msg_p, nxge_mblks_pending));
16776f45ec7bSml29623
16786f45ec7bSml29623 if (!rx_msg_p->use_buf_pool) {
16796f45ec7bSml29623 KMEM_FREE(buffer, size);
16806f45ec7bSml29623 }
16816f45ec7bSml29623
16826f45ec7bSml29623 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t));
1683007969e0Stm144005
16843e82a89eSmisaki if (ring) {
16853e82a89eSmisaki /*
16863e82a89eSmisaki * Decrement the receive buffer ring's reference
16873e82a89eSmisaki * count, too.
16883e82a89eSmisaki */
1689007969e0Stm144005 atomic_dec_32(&ring->rbr_ref_cnt);
1690007969e0Stm144005
1691007969e0Stm144005 /*
1692678453a8Sspeer * Free the receive buffer ring, if
1693007969e0Stm144005 * 1. all the receive buffers have been freed
1694007969e0Stm144005 * 2. and we are in the proper state (that is,
1695007969e0Stm144005 * we are not UNMAPPING).
1696007969e0Stm144005 */
1697007969e0Stm144005 if (ring->rbr_ref_cnt == 0 &&
1698007969e0Stm144005 ring->rbr_state == RBR_UNMAPPED) {
1699678453a8Sspeer /*
1700678453a8Sspeer * Free receive data buffers,
1701678453a8Sspeer * buffer index information
1702678453a8Sspeer * (rxring_info) and
1703678453a8Sspeer * the message block ring.
1704678453a8Sspeer */
1705678453a8Sspeer NXGE_DEBUG_MSG((NULL, RX_CTL,
1706678453a8Sspeer "nxge_freeb:rx_msg_p = $%p "
1707678453a8Sspeer "(block pending %d) free buffers",
1708678453a8Sspeer rx_msg_p, nxge_mblks_pending));
1709678453a8Sspeer nxge_rxdma_databuf_free(ring);
1710678453a8Sspeer if (ring->ring_info) {
1711678453a8Sspeer KMEM_FREE(ring->ring_info,
1712678453a8Sspeer sizeof (rxring_info_t));
1713678453a8Sspeer }
1714678453a8Sspeer
1715678453a8Sspeer if (ring->rx_msg_ring) {
1716678453a8Sspeer KMEM_FREE(ring->rx_msg_ring,
1717678453a8Sspeer ring->tnblocks *
1718678453a8Sspeer sizeof (p_rx_msg_t));
1719678453a8Sspeer }
1720007969e0Stm144005 KMEM_FREE(ring, sizeof (*ring));
1721007969e0Stm144005 }
17223e82a89eSmisaki }
17236f45ec7bSml29623 return;
17246f45ec7bSml29623 }
17256f45ec7bSml29623
17266f45ec7bSml29623 /*
17276f45ec7bSml29623 * Repost buffer.
17286f45ec7bSml29623 */
17293e82a89eSmisaki if (free_state && (ref_cnt == 1) && ring) {
17306f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, RX_CTL,
17316f45ec7bSml29623 "nxge_freeb: post page $%p:", rx_msg_p));
1732007969e0Stm144005 if (ring->rbr_state == RBR_POSTING)
1733007969e0Stm144005 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p);
17346f45ec7bSml29623 }
17356f45ec7bSml29623
17366f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb"));
17376f45ec7bSml29623 }
17386f45ec7bSml29623
17396f45ec7bSml29623 uint_t
nxge_rx_intr(char * arg1,char * arg2)1740*e3d11eeeSToomas Soome nxge_rx_intr(char *arg1, char *arg2)
17416f45ec7bSml29623 {
17426f45ec7bSml29623 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1;
17436f45ec7bSml29623 p_nxge_t nxgep = (p_nxge_t)arg2;
17446f45ec7bSml29623 p_nxge_ldg_t ldgp;
17456f45ec7bSml29623 uint8_t channel;
17466f45ec7bSml29623 npi_handle_t handle;
17476f45ec7bSml29623 rx_dma_ctl_stat_t cs;
174863f531d1SSriharsha Basavapatna p_rx_rcr_ring_t rcrp;
174948056c53SMichael Speer mblk_t *mp = NULL;
17506f45ec7bSml29623
17516f45ec7bSml29623 if (ldvp == NULL) {
17526f45ec7bSml29623 NXGE_DEBUG_MSG((NULL, INT_CTL,
17536f45ec7bSml29623 "<== nxge_rx_intr: arg2 $%p arg1 $%p",
17546f45ec7bSml29623 nxgep, ldvp));
17556f45ec7bSml29623 return (DDI_INTR_CLAIMED);
17566f45ec7bSml29623 }
17576f45ec7bSml29623
17586f45ec7bSml29623 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) {
17596f45ec7bSml29623 nxgep = ldvp->nxgep;
17606f45ec7bSml29623 }
17611d36aa9eSspeer
17621d36aa9eSspeer if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) ||
17631d36aa9eSspeer (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) {
17641d36aa9eSspeer NXGE_DEBUG_MSG((nxgep, INT_CTL,
17651d36aa9eSspeer "<== nxge_rx_intr: interface not started or intialized"));
17661d36aa9eSspeer return (DDI_INTR_CLAIMED);
17671d36aa9eSspeer }
17681d36aa9eSspeer
17696f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
17706f45ec7bSml29623 "==> nxge_rx_intr: arg2 $%p arg1 $%p",
17716f45ec7bSml29623 nxgep, ldvp));
17726f45ec7bSml29623
17736f45ec7bSml29623 /*
1774e759c33aSMichael Speer * Get the PIO handle.
17756f45ec7bSml29623 */
17766f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
1777da14cebeSEric Cheng
1778e759c33aSMichael Speer /*
1779e759c33aSMichael Speer * Get the ring to enable us to process packets.
1780e759c33aSMichael Speer */
178163f531d1SSriharsha Basavapatna rcrp = nxgep->rx_rcr_rings->rcr_rings[ldvp->vdma_index];
1782da14cebeSEric Cheng
1783da14cebeSEric Cheng /*
1784da14cebeSEric Cheng * The RCR ring lock must be held when packets
1785da14cebeSEric Cheng * are being processed and the hardware registers are
1786da14cebeSEric Cheng * being read or written to prevent race condition
1787da14cebeSEric Cheng * among the interrupt thread, the polling thread
1788da14cebeSEric Cheng * (will cause fatal errors such as rcrincon bit set)
1789da14cebeSEric Cheng * and the setting of the poll_flag.
1790da14cebeSEric Cheng */
179163f531d1SSriharsha Basavapatna MUTEX_ENTER(&rcrp->lock);
1792da14cebeSEric Cheng
17936f45ec7bSml29623 /*
17946f45ec7bSml29623 * Get the control and status for this channel.
17956f45ec7bSml29623 */
17966f45ec7bSml29623 channel = ldvp->channel;
17976f45ec7bSml29623 ldgp = ldvp->ldgp;
1798da14cebeSEric Cheng
17990dc2366fSVenugopal Iyer if (!isLDOMguest(nxgep) && (!rcrp->started)) {
1800da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, INT_CTL,
1801da14cebeSEric Cheng "<== nxge_rx_intr: channel is not started"));
1802e759c33aSMichael Speer
1803e759c33aSMichael Speer /*
1804e759c33aSMichael Speer * We received an interrupt before the ring is started.
1805e759c33aSMichael Speer */
1806e759c33aSMichael Speer RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel,
1807e759c33aSMichael Speer &cs.value);
1808e759c33aSMichael Speer cs.value &= RX_DMA_CTL_STAT_WR1C;
1809e759c33aSMichael Speer cs.bits.hdw.mex = 1;
1810e759c33aSMichael Speer RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
1811e759c33aSMichael Speer cs.value);
1812e759c33aSMichael Speer
1813e759c33aSMichael Speer /*
1814e759c33aSMichael Speer * Rearm this logical group if this is a single device
1815e759c33aSMichael Speer * group.
1816e759c33aSMichael Speer */
1817e759c33aSMichael Speer if (ldgp->nldvs == 1) {
1818e759c33aSMichael Speer if (isLDOMguest(nxgep)) {
1819e759c33aSMichael Speer nxge_hio_ldgimgn(nxgep, ldgp);
1820e759c33aSMichael Speer } else {
1821e759c33aSMichael Speer ldgimgm_t mgm;
1822e759c33aSMichael Speer
1823e759c33aSMichael Speer mgm.value = 0;
1824e759c33aSMichael Speer mgm.bits.ldw.arm = 1;
1825e759c33aSMichael Speer mgm.bits.ldw.timer = ldgp->ldg_timer;
1826e759c33aSMichael Speer
1827e759c33aSMichael Speer NXGE_REG_WR64(handle,
1828e759c33aSMichael Speer LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg),
1829e759c33aSMichael Speer mgm.value);
1830e759c33aSMichael Speer }
1831e759c33aSMichael Speer }
183263f531d1SSriharsha Basavapatna MUTEX_EXIT(&rcrp->lock);
1833da14cebeSEric Cheng return (DDI_INTR_CLAIMED);
1834da14cebeSEric Cheng }
1835da14cebeSEric Cheng
183663f531d1SSriharsha Basavapatna ASSERT(rcrp->ldgp == ldgp);
183763f531d1SSriharsha Basavapatna ASSERT(rcrp->ldvp == ldvp);
1838da14cebeSEric Cheng
18396f45ec7bSml29623 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value);
18406f45ec7bSml29623
18416f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d "
18426f45ec7bSml29623 "cs 0x%016llx rcrto 0x%x rcrthres %x",
18436f45ec7bSml29623 channel,
18446f45ec7bSml29623 cs.value,
18456f45ec7bSml29623 cs.bits.hdw.rcrto,
18466f45ec7bSml29623 cs.bits.hdw.rcrthres));
18476f45ec7bSml29623
184863f531d1SSriharsha Basavapatna if (!rcrp->poll_flag) {
184963f531d1SSriharsha Basavapatna mp = nxge_rx_pkts(nxgep, rcrp, cs, -1);
185048056c53SMichael Speer }
18516f45ec7bSml29623
18526f45ec7bSml29623 /* error events. */
18536f45ec7bSml29623 if (cs.value & RX_DMA_CTL_STAT_ERROR) {
1854678453a8Sspeer (void) nxge_rx_err_evnts(nxgep, channel, cs);
18556f45ec7bSml29623 }
18566f45ec7bSml29623
18576f45ec7bSml29623 /*
18586f45ec7bSml29623 * Enable the mailbox update interrupt if we want
18596f45ec7bSml29623 * to use mailbox. We probably don't need to use
18606f45ec7bSml29623 * mailbox as it only saves us one pio read.
18616f45ec7bSml29623 * Also write 1 to rcrthres and rcrto to clear
18626f45ec7bSml29623 * these two edge triggered bits.
18636f45ec7bSml29623 */
18646f45ec7bSml29623 cs.value &= RX_DMA_CTL_STAT_WR1C;
186563f531d1SSriharsha Basavapatna cs.bits.hdw.mex = rcrp->poll_flag ? 0 : 1;
18666f45ec7bSml29623 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
18676f45ec7bSml29623 cs.value);
18686f45ec7bSml29623
18696f45ec7bSml29623 /*
1870da14cebeSEric Cheng * If the polling mode is enabled, disable the interrupt.
1871da14cebeSEric Cheng */
187263f531d1SSriharsha Basavapatna if (rcrp->poll_flag) {
1873da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
1874da14cebeSEric Cheng "==> nxge_rx_intr: rdc %d ldgp $%p ldvp $%p "
1875da14cebeSEric Cheng "(disabling interrupts)", channel, ldgp, ldvp));
187663f531d1SSriharsha Basavapatna
1877da14cebeSEric Cheng /*
1878da14cebeSEric Cheng * Disarm this logical group if this is a single device
18796f45ec7bSml29623 * group.
18806f45ec7bSml29623 */
18816f45ec7bSml29623 if (ldgp->nldvs == 1) {
188263f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) {
188363f531d1SSriharsha Basavapatna ldgp->arm = B_FALSE;
188463f531d1SSriharsha Basavapatna nxge_hio_ldgimgn(nxgep, ldgp);
188563f531d1SSriharsha Basavapatna } else {
18866f45ec7bSml29623 ldgimgm_t mgm;
18876f45ec7bSml29623 mgm.value = 0;
1888da14cebeSEric Cheng mgm.bits.ldw.arm = 0;
1889da14cebeSEric Cheng NXGE_REG_WR64(handle,
189063f531d1SSriharsha Basavapatna LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg),
189163f531d1SSriharsha Basavapatna mgm.value);
189263f531d1SSriharsha Basavapatna }
1893da14cebeSEric Cheng }
1894da14cebeSEric Cheng } else {
1895da14cebeSEric Cheng /*
189608ac1c49SNicolas Droux * Rearm this logical group if this is a single device
189708ac1c49SNicolas Droux * group.
1898da14cebeSEric Cheng */
1899da14cebeSEric Cheng if (ldgp->nldvs == 1) {
1900678453a8Sspeer if (isLDOMguest(nxgep)) {
1901678453a8Sspeer nxge_hio_ldgimgn(nxgep, ldgp);
1902678453a8Sspeer } else {
1903da14cebeSEric Cheng ldgimgm_t mgm;
1904da14cebeSEric Cheng
1905da14cebeSEric Cheng mgm.value = 0;
1906da14cebeSEric Cheng mgm.bits.ldw.arm = 1;
1907da14cebeSEric Cheng mgm.bits.ldw.timer = ldgp->ldg_timer;
1908da14cebeSEric Cheng
19096f45ec7bSml29623 NXGE_REG_WR64(handle,
19106f45ec7bSml29623 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg),
19116f45ec7bSml29623 mgm.value);
19126f45ec7bSml29623 }
1913678453a8Sspeer }
19146f45ec7bSml29623
1915da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
1916da14cebeSEric Cheng "==> nxge_rx_intr: rdc %d ldgp $%p "
1917da14cebeSEric Cheng "exiting ISR (and call mac_rx_ring)", channel, ldgp));
1918da14cebeSEric Cheng }
191963f531d1SSriharsha Basavapatna MUTEX_EXIT(&rcrp->lock);
1920da14cebeSEric Cheng
192148056c53SMichael Speer if (mp != NULL) {
192263f531d1SSriharsha Basavapatna mac_rx_ring(nxgep->mach, rcrp->rcr_mac_handle, mp,
192363f531d1SSriharsha Basavapatna rcrp->rcr_gen_num);
1924da14cebeSEric Cheng }
1925da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: DDI_INTR_CLAIMED"));
1926da14cebeSEric Cheng return (DDI_INTR_CLAIMED);
19276f45ec7bSml29623 }
19286f45ec7bSml29623
19296f45ec7bSml29623 /*
19306f45ec7bSml29623 * This routine is the main packet receive processing function.
19316f45ec7bSml29623 * It gets the packet type, error code, and buffer related
19326f45ec7bSml29623 * information from the receive completion entry.
19336f45ec7bSml29623 * How many completion entries to process is based on the number of packets
19346f45ec7bSml29623 * queued by the hardware, a hardware maintained tail pointer
19356f45ec7bSml29623 * and a configurable receive packet count.
19366f45ec7bSml29623 *
19376f45ec7bSml29623 * A chain of message blocks will be created as result of processing
19386f45ec7bSml29623 * the completion entries. This chain of message blocks will be returned and
19396f45ec7bSml29623 * a hardware control status register will be updated with the number of
19406f45ec7bSml29623 * packets were removed from the hardware queue.
19416f45ec7bSml29623 *
1942da14cebeSEric Cheng * The RCR ring lock is held when entering this function.
19436f45ec7bSml29623 */
1944678453a8Sspeer static mblk_t *
nxge_rx_pkts(p_nxge_t nxgep,p_rx_rcr_ring_t rcr_p,rx_dma_ctl_stat_t cs,int bytes_to_pickup)1945678453a8Sspeer nxge_rx_pkts(p_nxge_t nxgep, p_rx_rcr_ring_t rcr_p, rx_dma_ctl_stat_t cs,
1946678453a8Sspeer int bytes_to_pickup)
19476f45ec7bSml29623 {
19486f45ec7bSml29623 npi_handle_t handle;
19496f45ec7bSml29623 uint8_t channel;
19506f45ec7bSml29623 uint32_t comp_rd_index;
19516f45ec7bSml29623 p_rcr_entry_t rcr_desc_rd_head_p;
19526f45ec7bSml29623 p_rcr_entry_t rcr_desc_rd_head_pp;
19536f45ec7bSml29623 p_mblk_t nmp, mp_cont, head_mp, *tail_mp;
19546f45ec7bSml29623 uint16_t qlen, nrcr_read, npkt_read;
19556f45ec7bSml29623 uint32_t qlen_hw;
19566f45ec7bSml29623 boolean_t multi;
19576f45ec7bSml29623 rcrcfig_b_t rcr_cfg_b;
1958678453a8Sspeer int totallen = 0;
19596f45ec7bSml29623 #if defined(_BIG_ENDIAN)
19606f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
19616f45ec7bSml29623 #endif
19626f45ec7bSml29623
1963da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_rx_pkts: "
1964678453a8Sspeer "channel %d", rcr_p->rdc));
19656f45ec7bSml29623
19666f45ec7bSml29623 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) {
19676f45ec7bSml29623 return (NULL);
19686f45ec7bSml29623 }
19696f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
19706f45ec7bSml29623 channel = rcr_p->rdc;
19716f45ec7bSml29623
19726f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
19736f45ec7bSml29623 "==> nxge_rx_pkts: START: rcr channel %d "
19746f45ec7bSml29623 "head_p $%p head_pp $%p index %d ",
19756f45ec7bSml29623 channel, rcr_p->rcr_desc_rd_head_p,
19766f45ec7bSml29623 rcr_p->rcr_desc_rd_head_pp,
19776f45ec7bSml29623 rcr_p->comp_rd_index));
19786f45ec7bSml29623
19796f45ec7bSml29623
19806f45ec7bSml29623 #if !defined(_BIG_ENDIAN)
19816f45ec7bSml29623 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff;
19826f45ec7bSml29623 #else
19836f45ec7bSml29623 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen);
19846f45ec7bSml29623 if (rs != NPI_SUCCESS) {
1985678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts: "
19866f45ec7bSml29623 "channel %d, get qlen failed 0x%08x",
1987678453a8Sspeer channel, rs));
19886f45ec7bSml29623 return (NULL);
19896f45ec7bSml29623 }
19906f45ec7bSml29623 #endif
19916f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d "
19926f45ec7bSml29623 "qlen %d", channel, qlen));
19936f45ec7bSml29623
19946f45ec7bSml29623
19956f45ec7bSml29623
19966f45ec7bSml29623 if (!qlen) {
1997da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
19986f45ec7bSml29623 "==> nxge_rx_pkts:rcr channel %d "
19996f45ec7bSml29623 "qlen %d (no pkts)", channel, qlen));
20006f45ec7bSml29623
20016f45ec7bSml29623 return (NULL);
20026f45ec7bSml29623 }
20036f45ec7bSml29623
20046f45ec7bSml29623 comp_rd_index = rcr_p->comp_rd_index;
20056f45ec7bSml29623
20066f45ec7bSml29623 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p;
20076f45ec7bSml29623 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp;
20086f45ec7bSml29623 nrcr_read = npkt_read = 0;
20096f45ec7bSml29623
20106f45ec7bSml29623 /*
20116f45ec7bSml29623 * Number of packets queued
20126f45ec7bSml29623 * (The jumbo or multi packet will be counted as only one
20136f45ec7bSml29623 * packets and it may take up more than one completion entry).
20146f45ec7bSml29623 */
20156f45ec7bSml29623 qlen_hw = (qlen < nxge_max_rx_pkts) ?
20166f45ec7bSml29623 qlen : nxge_max_rx_pkts;
20176f45ec7bSml29623 head_mp = NULL;
20186f45ec7bSml29623 tail_mp = &head_mp;
20196f45ec7bSml29623 nmp = mp_cont = NULL;
20206f45ec7bSml29623 multi = B_FALSE;
20216f45ec7bSml29623
20226f45ec7bSml29623 while (qlen_hw) {
20236f45ec7bSml29623
20246f45ec7bSml29623 #ifdef NXGE_DEBUG
20256f45ec7bSml29623 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p);
20266f45ec7bSml29623 #endif
20276f45ec7bSml29623 /*
20286f45ec7bSml29623 * Process one completion ring entry.
20296f45ec7bSml29623 */
20306f45ec7bSml29623 nxge_receive_packet(nxgep,
20316f45ec7bSml29623 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont);
20326f45ec7bSml29623
20336f45ec7bSml29623 /*
20346f45ec7bSml29623 * message chaining modes
20356f45ec7bSml29623 */
20366f45ec7bSml29623 if (nmp) {
20376f45ec7bSml29623 nmp->b_next = NULL;
20386f45ec7bSml29623 if (!multi && !mp_cont) { /* frame fits a partition */
20396f45ec7bSml29623 *tail_mp = nmp;
20406f45ec7bSml29623 tail_mp = &nmp->b_next;
2041678453a8Sspeer totallen += MBLKL(nmp);
20426f45ec7bSml29623 nmp = NULL;
20436f45ec7bSml29623 } else if (multi && !mp_cont) { /* first segment */
20446f45ec7bSml29623 *tail_mp = nmp;
20456f45ec7bSml29623 tail_mp = &nmp->b_cont;
2046678453a8Sspeer totallen += MBLKL(nmp);
20476f45ec7bSml29623 } else if (multi && mp_cont) { /* mid of multi segs */
20486f45ec7bSml29623 *tail_mp = mp_cont;
20496f45ec7bSml29623 tail_mp = &mp_cont->b_cont;
2050678453a8Sspeer totallen += MBLKL(mp_cont);
20516f45ec7bSml29623 } else if (!multi && mp_cont) { /* last segment */
20526f45ec7bSml29623 *tail_mp = mp_cont;
20536f45ec7bSml29623 tail_mp = &nmp->b_next;
2054678453a8Sspeer totallen += MBLKL(mp_cont);
20556f45ec7bSml29623 nmp = NULL;
20566f45ec7bSml29623 }
20576f45ec7bSml29623 }
20586f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
20596f45ec7bSml29623 "==> nxge_rx_pkts: loop: rcr channel %d "
20606f45ec7bSml29623 "before updating: multi %d "
20616f45ec7bSml29623 "nrcr_read %d "
20626f45ec7bSml29623 "npk read %d "
20636f45ec7bSml29623 "head_pp $%p index %d ",
20646f45ec7bSml29623 channel,
20656f45ec7bSml29623 multi,
20666f45ec7bSml29623 nrcr_read, npkt_read, rcr_desc_rd_head_pp,
20676f45ec7bSml29623 comp_rd_index));
20686f45ec7bSml29623
20696f45ec7bSml29623 if (!multi) {
20706f45ec7bSml29623 qlen_hw--;
20716f45ec7bSml29623 npkt_read++;
20726f45ec7bSml29623 }
20736f45ec7bSml29623
20746f45ec7bSml29623 /*
20756f45ec7bSml29623 * Update the next read entry.
20766f45ec7bSml29623 */
20776f45ec7bSml29623 comp_rd_index = NEXT_ENTRY(comp_rd_index,
20786f45ec7bSml29623 rcr_p->comp_wrap_mask);
20796f45ec7bSml29623
20806f45ec7bSml29623 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p,
20816f45ec7bSml29623 rcr_p->rcr_desc_first_p,
20826f45ec7bSml29623 rcr_p->rcr_desc_last_p);
20836f45ec7bSml29623
20846f45ec7bSml29623 nrcr_read++;
20856f45ec7bSml29623
20866f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
20876f45ec7bSml29623 "<== nxge_rx_pkts: (SAM, process one packet) "
20886f45ec7bSml29623 "nrcr_read %d",
20896f45ec7bSml29623 nrcr_read));
20906f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
20916f45ec7bSml29623 "==> nxge_rx_pkts: loop: rcr channel %d "
20926f45ec7bSml29623 "multi %d "
20936f45ec7bSml29623 "nrcr_read %d "
20946f45ec7bSml29623 "npk read %d "
20956f45ec7bSml29623 "head_pp $%p index %d ",
20966f45ec7bSml29623 channel,
20976f45ec7bSml29623 multi,
20986f45ec7bSml29623 nrcr_read, npkt_read, rcr_desc_rd_head_pp,
20996f45ec7bSml29623 comp_rd_index));
21006f45ec7bSml29623
2101678453a8Sspeer if ((bytes_to_pickup != -1) &&
2102678453a8Sspeer (totallen >= bytes_to_pickup)) {
2103678453a8Sspeer break;
2104678453a8Sspeer }
21056f45ec7bSml29623 }
21066f45ec7bSml29623
21076f45ec7bSml29623 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp;
21086f45ec7bSml29623 rcr_p->comp_rd_index = comp_rd_index;
21096f45ec7bSml29623 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p;
21106f45ec7bSml29623 if ((nxgep->intr_timeout != rcr_p->intr_timeout) ||
21116f45ec7bSml29623 (nxgep->intr_threshold != rcr_p->intr_threshold)) {
21127b26d9ffSSantwona Behera
21137b26d9ffSSantwona Behera rcr_p->intr_timeout = (nxgep->intr_timeout <
21147b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN :
21157b26d9ffSSantwona Behera nxgep->intr_timeout;
21167b26d9ffSSantwona Behera
21177b26d9ffSSantwona Behera rcr_p->intr_threshold = (nxgep->intr_threshold <
21187b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN :
21197b26d9ffSSantwona Behera nxgep->intr_threshold;
21207b26d9ffSSantwona Behera
21216f45ec7bSml29623 rcr_cfg_b.value = 0x0ULL;
21226f45ec7bSml29623 rcr_cfg_b.bits.ldw.entout = 1;
21236f45ec7bSml29623 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout;
21246f45ec7bSml29623 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold;
21257b26d9ffSSantwona Behera
21266f45ec7bSml29623 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG,
21276f45ec7bSml29623 channel, rcr_cfg_b.value);
21286f45ec7bSml29623 }
21296f45ec7bSml29623
21306f45ec7bSml29623 cs.bits.ldw.pktread = npkt_read;
21316f45ec7bSml29623 cs.bits.ldw.ptrread = nrcr_read;
21326f45ec7bSml29623 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG,
21336f45ec7bSml29623 channel, cs.value);
21346f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
21356f45ec7bSml29623 "==> nxge_rx_pkts: EXIT: rcr channel %d "
21366f45ec7bSml29623 "head_pp $%p index %016llx ",
21376f45ec7bSml29623 channel,
21386f45ec7bSml29623 rcr_p->rcr_desc_rd_head_pp,
21396f45ec7bSml29623 rcr_p->comp_rd_index));
21406f45ec7bSml29623 /*
21416f45ec7bSml29623 * Update RCR buffer pointer read and number of packets
21426f45ec7bSml29623 * read.
21436f45ec7bSml29623 */
21446f45ec7bSml29623
2145da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_rx_pkts: return"
2146da14cebeSEric Cheng "channel %d", rcr_p->rdc));
2147da14cebeSEric Cheng
21486f45ec7bSml29623 return (head_mp);
21496f45ec7bSml29623 }
21506f45ec7bSml29623
21516f45ec7bSml29623 void
nxge_receive_packet(p_nxge_t nxgep,p_rx_rcr_ring_t rcr_p,p_rcr_entry_t rcr_desc_rd_head_p,boolean_t * multi_p,mblk_t ** mp,mblk_t ** mp_cont)21526f45ec7bSml29623 nxge_receive_packet(p_nxge_t nxgep,
21536f45ec7bSml29623 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p,
21546f45ec7bSml29623 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont)
21556f45ec7bSml29623 {
21566f45ec7bSml29623 p_mblk_t nmp = NULL;
21576f45ec7bSml29623 uint64_t multi;
21586f45ec7bSml29623 uint64_t dcf_err;
21596f45ec7bSml29623 uint8_t channel;
21606f45ec7bSml29623
21616f45ec7bSml29623 boolean_t first_entry = B_TRUE;
21626f45ec7bSml29623 boolean_t is_tcp_udp = B_FALSE;
21636f45ec7bSml29623 boolean_t buffer_free = B_FALSE;
21646f45ec7bSml29623 boolean_t error_send_up = B_FALSE;
21656f45ec7bSml29623 uint8_t error_type;
21666f45ec7bSml29623 uint16_t l2_len;
21676f45ec7bSml29623 uint16_t skip_len;
21686f45ec7bSml29623 uint8_t pktbufsz_type;
21696f45ec7bSml29623 uint64_t rcr_entry;
21706f45ec7bSml29623 uint64_t *pkt_buf_addr_pp;
21716f45ec7bSml29623 uint64_t *pkt_buf_addr_p;
21726f45ec7bSml29623 uint32_t buf_offset;
21736f45ec7bSml29623 uint32_t bsize;
21746f45ec7bSml29623 uint32_t error_disp_cnt;
21756f45ec7bSml29623 uint32_t msg_index;
21766f45ec7bSml29623 p_rx_rbr_ring_t rx_rbr_p;
21776f45ec7bSml29623 p_rx_msg_t *rx_msg_ring_p;
21786f45ec7bSml29623 p_rx_msg_t rx_msg_p;
21796f45ec7bSml29623 uint16_t sw_offset_bytes = 0, hdr_size = 0;
21806f45ec7bSml29623 nxge_status_t status = NXGE_OK;
21816f45ec7bSml29623 boolean_t is_valid = B_FALSE;
21826f45ec7bSml29623 p_nxge_rx_ring_stats_t rdc_stats;
21836f45ec7bSml29623 uint32_t bytes_read;
21846f45ec7bSml29623 uint64_t pkt_type;
21856f45ec7bSml29623 uint64_t frag;
21864202ea4bSsbehera boolean_t pkt_too_long_err = B_FALSE;
21876f45ec7bSml29623 #ifdef NXGE_DEBUG
21886f45ec7bSml29623 int dump_len;
21896f45ec7bSml29623 #endif
21906f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet"));
21916f45ec7bSml29623 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE;
21926f45ec7bSml29623
21936f45ec7bSml29623 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p);
21946f45ec7bSml29623
21956f45ec7bSml29623 multi = (rcr_entry & RCR_MULTI_MASK);
21966f45ec7bSml29623 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK);
21976f45ec7bSml29623 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK);
21986f45ec7bSml29623
21996f45ec7bSml29623 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT);
22006f45ec7bSml29623 frag = (rcr_entry & RCR_FRAG_MASK);
22016f45ec7bSml29623
22026f45ec7bSml29623 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT);
22036f45ec7bSml29623
22046f45ec7bSml29623 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >>
22056f45ec7bSml29623 RCR_PKTBUFSZ_SHIFT);
22066f45ec7bSml29623 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) <<
22076f45ec7bSml29623 RCR_PKT_BUF_ADDR_SHIFT);
22086f45ec7bSml29623
22096f45ec7bSml29623 channel = rcr_p->rdc;
22106f45ec7bSml29623
22116f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
22126f45ec7bSml29623 "==> nxge_receive_packet: entryp $%p entry 0x%0llx "
22136f45ec7bSml29623 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx "
22146f45ec7bSml29623 "error_type 0x%x pkt_type 0x%x "
22156f45ec7bSml29623 "pktbufsz_type %d ",
22166f45ec7bSml29623 rcr_desc_rd_head_p,
22176f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len,
22186f45ec7bSml29623 multi,
22196f45ec7bSml29623 error_type,
22206f45ec7bSml29623 pkt_type,
22216f45ec7bSml29623 pktbufsz_type));
22226f45ec7bSml29623
22236f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
22246f45ec7bSml29623 "==> nxge_receive_packet: entryp $%p entry 0x%0llx "
22256f45ec7bSml29623 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx "
22266f45ec7bSml29623 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p,
22276f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len,
22286f45ec7bSml29623 multi,
22296f45ec7bSml29623 error_type,
22306f45ec7bSml29623 pkt_type));
22316f45ec7bSml29623
22326f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
22336f45ec7bSml29623 "==> (rbr) nxge_receive_packet: entry 0x%0llx "
22346f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
22356f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len));
22366f45ec7bSml29623
22376f45ec7bSml29623 /* get the stats ptr */
22386f45ec7bSml29623 rdc_stats = rcr_p->rdc_stats;
22396f45ec7bSml29623
22406f45ec7bSml29623 if (!l2_len) {
22416f45ec7bSml29623
22426f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
22436f45ec7bSml29623 "<== nxge_receive_packet: failed: l2 length is 0."));
22446f45ec7bSml29623 return;
22456f45ec7bSml29623 }
22466f45ec7bSml29623
22474202ea4bSsbehera /*
2248da14cebeSEric Cheng * Software workaround for BMAC hardware limitation that allows
22494202ea4bSsbehera * maxframe size of 1526, instead of 1522 for non-jumbo and 0x2406
22504202ea4bSsbehera * instead of 0x2400 for jumbo.
22514202ea4bSsbehera */
22524202ea4bSsbehera if (l2_len > nxgep->mac.maxframesize) {
22534202ea4bSsbehera pkt_too_long_err = B_TRUE;
22544202ea4bSsbehera }
22554202ea4bSsbehera
225656d930aeSspeer /* Hardware sends us 4 bytes of CRC as no stripping is done. */
225756d930aeSspeer l2_len -= ETHERFCSL;
225856d930aeSspeer
22596f45ec7bSml29623 /* shift 6 bits to get the full io address */
22606f45ec7bSml29623 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp <<
22616f45ec7bSml29623 RCR_PKT_BUF_ADDR_SHIFT_FULL);
22626f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
22636f45ec7bSml29623 "==> (rbr) nxge_receive_packet: entry 0x%0llx "
22646f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
22656f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len));
22666f45ec7bSml29623
22676f45ec7bSml29623 rx_rbr_p = rcr_p->rx_rbr_p;
22686f45ec7bSml29623 rx_msg_ring_p = rx_rbr_p->rx_msg_ring;
22696f45ec7bSml29623
22706f45ec7bSml29623 if (first_entry) {
22716f45ec7bSml29623 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL :
22726f45ec7bSml29623 RXDMA_HDR_SIZE_DEFAULT);
22736f45ec7bSml29623
22746f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
22756f45ec7bSml29623 "==> nxge_receive_packet: first entry 0x%016llx "
22766f45ec7bSml29623 "pkt_buf_addr_pp $%p l2_len %d hdr %d",
22776f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len,
22786f45ec7bSml29623 hdr_size));
22796f45ec7bSml29623 }
22806f45ec7bSml29623
22816f45ec7bSml29623 MUTEX_ENTER(&rx_rbr_p->lock);
22826f45ec7bSml29623
22836f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
22846f45ec7bSml29623 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx "
22856f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
22866f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len));
22876f45ec7bSml29623
22886f45ec7bSml29623 /*
22896f45ec7bSml29623 * Packet buffer address in the completion entry points
22906f45ec7bSml29623 * to the starting buffer address (offset 0).
22916f45ec7bSml29623 * Use the starting buffer address to locate the corresponding
22926f45ec7bSml29623 * kernel address.
22936f45ec7bSml29623 */
22946f45ec7bSml29623 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p,
22956f45ec7bSml29623 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p,
22966f45ec7bSml29623 &buf_offset,
22976f45ec7bSml29623 &msg_index);
22986f45ec7bSml29623
22996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
23006f45ec7bSml29623 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx "
23016f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
23026f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len));
23036f45ec7bSml29623
23046f45ec7bSml29623 if (status != NXGE_OK) {
23056f45ec7bSml29623 MUTEX_EXIT(&rx_rbr_p->lock);
23066f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
23076f45ec7bSml29623 "<== nxge_receive_packet: found vaddr failed %d",
23086f45ec7bSml29623 status));
23096f45ec7bSml29623 return;
23106f45ec7bSml29623 }
23116f45ec7bSml29623
23126f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23136f45ec7bSml29623 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx "
23146f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
23156f45ec7bSml29623 rcr_entry, pkt_buf_addr_pp, l2_len));
23166f45ec7bSml29623
23176f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23186f45ec7bSml29623 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx "
23196f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
23206f45ec7bSml29623 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len));
23216f45ec7bSml29623
23226f45ec7bSml29623 rx_msg_p = rx_msg_ring_p[msg_index];
23236f45ec7bSml29623
23246f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23256f45ec7bSml29623 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx "
23266f45ec7bSml29623 "full pkt_buf_addr_pp $%p l2_len %d",
23276f45ec7bSml29623 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len));
23286f45ec7bSml29623
23296f45ec7bSml29623 switch (pktbufsz_type) {
23306f45ec7bSml29623 case RCR_PKTBUFSZ_0:
23316f45ec7bSml29623 bsize = rx_rbr_p->pkt_buf_size0_bytes;
23326f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23336f45ec7bSml29623 "==> nxge_receive_packet: 0 buf %d", bsize));
23346f45ec7bSml29623 break;
23356f45ec7bSml29623 case RCR_PKTBUFSZ_1:
23366f45ec7bSml29623 bsize = rx_rbr_p->pkt_buf_size1_bytes;
23376f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23386f45ec7bSml29623 "==> nxge_receive_packet: 1 buf %d", bsize));
23396f45ec7bSml29623 break;
23406f45ec7bSml29623 case RCR_PKTBUFSZ_2:
23416f45ec7bSml29623 bsize = rx_rbr_p->pkt_buf_size2_bytes;
23426f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
23436f45ec7bSml29623 "==> nxge_receive_packet: 2 buf %d", bsize));
23446f45ec7bSml29623 break;
23456f45ec7bSml29623 case RCR_SINGLE_BLOCK:
23466f45ec7bSml29623 bsize = rx_msg_p->block_size;
23476f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23486f45ec7bSml29623 "==> nxge_receive_packet: single %d", bsize));
23496f45ec7bSml29623
23506f45ec7bSml29623 break;
23516f45ec7bSml29623 default:
23526f45ec7bSml29623 MUTEX_EXIT(&rx_rbr_p->lock);
23536f45ec7bSml29623 return;
23546f45ec7bSml29623 }
23556f45ec7bSml29623
23564df55fdeSJanie Lu switch (nxge_rdc_buf_offset) {
23574df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET:
23584df55fdeSJanie Lu sw_offset_bytes = 0;
23594df55fdeSJanie Lu break;
23604df55fdeSJanie Lu case SW_OFFSET_64:
23614df55fdeSJanie Lu sw_offset_bytes = 64;
23624df55fdeSJanie Lu break;
23634df55fdeSJanie Lu case SW_OFFSET_128:
23644df55fdeSJanie Lu sw_offset_bytes = 128;
23654df55fdeSJanie Lu break;
23664df55fdeSJanie Lu case SW_OFFSET_192:
23674df55fdeSJanie Lu sw_offset_bytes = 192;
23684df55fdeSJanie Lu break;
23694df55fdeSJanie Lu case SW_OFFSET_256:
23704df55fdeSJanie Lu sw_offset_bytes = 256;
23714df55fdeSJanie Lu break;
23724df55fdeSJanie Lu case SW_OFFSET_320:
23734df55fdeSJanie Lu sw_offset_bytes = 320;
23744df55fdeSJanie Lu break;
23754df55fdeSJanie Lu case SW_OFFSET_384:
23764df55fdeSJanie Lu sw_offset_bytes = 384;
23774df55fdeSJanie Lu break;
23784df55fdeSJanie Lu case SW_OFFSET_448:
23794df55fdeSJanie Lu sw_offset_bytes = 448;
23804df55fdeSJanie Lu break;
23814df55fdeSJanie Lu default:
23824df55fdeSJanie Lu sw_offset_bytes = 0;
23834df55fdeSJanie Lu break;
23844df55fdeSJanie Lu }
23854df55fdeSJanie Lu
23866f45ec7bSml29623 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma,
23876f45ec7bSml29623 (buf_offset + sw_offset_bytes),
23886f45ec7bSml29623 (hdr_size + l2_len),
23896f45ec7bSml29623 DDI_DMA_SYNC_FORCPU);
23906f45ec7bSml29623
23916f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
23926f45ec7bSml29623 "==> nxge_receive_packet: after first dump:usage count"));
23936f45ec7bSml29623
23946f45ec7bSml29623 if (rx_msg_p->cur_usage_cnt == 0) {
23956f45ec7bSml29623 if (rx_rbr_p->rbr_use_bcopy) {
23966f45ec7bSml29623 atomic_inc_32(&rx_rbr_p->rbr_consumed);
23976f45ec7bSml29623 if (rx_rbr_p->rbr_consumed <
23986f45ec7bSml29623 rx_rbr_p->rbr_threshold_hi) {
23996f45ec7bSml29623 if (rx_rbr_p->rbr_threshold_lo == 0 ||
24006f45ec7bSml29623 ((rx_rbr_p->rbr_consumed >=
24016f45ec7bSml29623 rx_rbr_p->rbr_threshold_lo) &&
24026f45ec7bSml29623 (rx_rbr_p->rbr_bufsize_type >=
24036f45ec7bSml29623 pktbufsz_type))) {
24046f45ec7bSml29623 rx_msg_p->rx_use_bcopy = B_TRUE;
24056f45ec7bSml29623 }
24066f45ec7bSml29623 } else {
24076f45ec7bSml29623 rx_msg_p->rx_use_bcopy = B_TRUE;
24086f45ec7bSml29623 }
24096f45ec7bSml29623 }
24106f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
24116f45ec7bSml29623 "==> nxge_receive_packet: buf %d (new block) ",
24126f45ec7bSml29623 bsize));
24136f45ec7bSml29623
24146f45ec7bSml29623 rx_msg_p->pkt_buf_size_code = pktbufsz_type;
24156f45ec7bSml29623 rx_msg_p->pkt_buf_size = bsize;
24166f45ec7bSml29623 rx_msg_p->cur_usage_cnt = 1;
24176f45ec7bSml29623 if (pktbufsz_type == RCR_SINGLE_BLOCK) {
24186f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
24196f45ec7bSml29623 "==> nxge_receive_packet: buf %d "
24206f45ec7bSml29623 "(single block) ",
24216f45ec7bSml29623 bsize));
24226f45ec7bSml29623 /*
24236f45ec7bSml29623 * Buffer can be reused once the free function
24246f45ec7bSml29623 * is called.
24256f45ec7bSml29623 */
24266f45ec7bSml29623 rx_msg_p->max_usage_cnt = 1;
24276f45ec7bSml29623 buffer_free = B_TRUE;
24286f45ec7bSml29623 } else {
24296f45ec7bSml29623 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize;
24306f45ec7bSml29623 if (rx_msg_p->max_usage_cnt == 1) {
24316f45ec7bSml29623 buffer_free = B_TRUE;
24326f45ec7bSml29623 }
24336f45ec7bSml29623 }
24346f45ec7bSml29623 } else {
24356f45ec7bSml29623 rx_msg_p->cur_usage_cnt++;
24366f45ec7bSml29623 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) {
24376f45ec7bSml29623 buffer_free = B_TRUE;
24386f45ec7bSml29623 }
24396f45ec7bSml29623 }
24406f45ec7bSml29623
24416f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
24426f45ec7bSml29623 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ",
24436f45ec7bSml29623 msg_index, l2_len,
24446f45ec7bSml29623 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt));
24456f45ec7bSml29623
24464202ea4bSsbehera if ((error_type) || (dcf_err) || (pkt_too_long_err)) {
24476f45ec7bSml29623 rdc_stats->ierrors++;
24486f45ec7bSml29623 if (dcf_err) {
24496f45ec7bSml29623 rdc_stats->dcf_err++;
24506f45ec7bSml29623 #ifdef NXGE_DEBUG
24516f45ec7bSml29623 if (!rdc_stats->dcf_err) {
24526f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
24536f45ec7bSml29623 "nxge_receive_packet: channel %d dcf_err rcr"
24546f45ec7bSml29623 " 0x%llx", channel, rcr_entry));
24556f45ec7bSml29623 }
24566f45ec7bSml29623 #endif
2457b37cc459SToomas Soome NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, 0,
24586f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_DCF_ERR);
24594202ea4bSsbehera } else if (pkt_too_long_err) {
24604202ea4bSsbehera rdc_stats->pkt_too_long_err++;
24614202ea4bSsbehera NXGE_DEBUG_MSG((nxgep, RX_CTL, " nxge_receive_packet:"
24624202ea4bSsbehera " channel %d packet length [%d] > "
24634202ea4bSsbehera "maxframesize [%d]", channel, l2_len + ETHERFCSL,
24644202ea4bSsbehera nxgep->mac.maxframesize));
24656f45ec7bSml29623 } else {
24666f45ec7bSml29623 /* Update error stats */
24676f45ec7bSml29623 error_disp_cnt = NXGE_ERROR_SHOW_MAX;
24686f45ec7bSml29623 rdc_stats->errlog.compl_err_type = error_type;
24696f45ec7bSml29623
24706f45ec7bSml29623 switch (error_type) {
2471f6485eecSyc148097 /*
2472f6485eecSyc148097 * Do not send FMA ereport for RCR_L2_ERROR and
2473f6485eecSyc148097 * RCR_L4_CSUM_ERROR because most likely they indicate
2474f6485eecSyc148097 * back pressure rather than HW failures.
2475f6485eecSyc148097 */
24766f45ec7bSml29623 case RCR_L2_ERROR:
24776f45ec7bSml29623 rdc_stats->l2_err++;
24786f45ec7bSml29623 if (rdc_stats->l2_err <
247953f3d8ecSyc148097 error_disp_cnt) {
248053f3d8ecSyc148097 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
24816f45ec7bSml29623 " nxge_receive_packet:"
24826f45ec7bSml29623 " channel %d RCR L2_ERROR",
24836f45ec7bSml29623 channel));
248453f3d8ecSyc148097 }
24856f45ec7bSml29623 break;
24866f45ec7bSml29623 case RCR_L4_CSUM_ERROR:
24876f45ec7bSml29623 error_send_up = B_TRUE;
24886f45ec7bSml29623 rdc_stats->l4_cksum_err++;
24896f45ec7bSml29623 if (rdc_stats->l4_cksum_err <
249053f3d8ecSyc148097 error_disp_cnt) {
249153f3d8ecSyc148097 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
24926f45ec7bSml29623 " nxge_receive_packet:"
24936f45ec7bSml29623 " channel %d"
249453f3d8ecSyc148097 " RCR L4_CSUM_ERROR", channel));
249553f3d8ecSyc148097 }
24966f45ec7bSml29623 break;
2497f6485eecSyc148097 /*
2498f6485eecSyc148097 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and
2499f6485eecSyc148097 * RCR_ZCP_SOFT_ERROR because they reflect the same
2500f6485eecSyc148097 * FFLP and ZCP errors that have been reported by
2501f6485eecSyc148097 * nxge_fflp.c and nxge_zcp.c.
2502f6485eecSyc148097 */
25036f45ec7bSml29623 case RCR_FFLP_SOFT_ERROR:
25046f45ec7bSml29623 error_send_up = B_TRUE;
25056f45ec7bSml29623 rdc_stats->fflp_soft_err++;
25066f45ec7bSml29623 if (rdc_stats->fflp_soft_err <
250753f3d8ecSyc148097 error_disp_cnt) {
25086f45ec7bSml29623 NXGE_ERROR_MSG((nxgep,
25096f45ec7bSml29623 NXGE_ERR_CTL,
25106f45ec7bSml29623 " nxge_receive_packet:"
25116f45ec7bSml29623 " channel %d"
251253f3d8ecSyc148097 " RCR FFLP_SOFT_ERROR", channel));
251353f3d8ecSyc148097 }
25146f45ec7bSml29623 break;
25156f45ec7bSml29623 case RCR_ZCP_SOFT_ERROR:
25166f45ec7bSml29623 error_send_up = B_TRUE;
25176f45ec7bSml29623 rdc_stats->fflp_soft_err++;
25186f45ec7bSml29623 if (rdc_stats->zcp_soft_err <
25196f45ec7bSml29623 error_disp_cnt)
252053f3d8ecSyc148097 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
252153f3d8ecSyc148097 " nxge_receive_packet: Channel %d"
252253f3d8ecSyc148097 " RCR ZCP_SOFT_ERROR", channel));
25236f45ec7bSml29623 break;
25246f45ec7bSml29623 default:
252553f3d8ecSyc148097 rdc_stats->rcr_unknown_err++;
252653f3d8ecSyc148097 if (rdc_stats->rcr_unknown_err
252753f3d8ecSyc148097 < error_disp_cnt) {
25286f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
252953f3d8ecSyc148097 " nxge_receive_packet: Channel %d"
253053f3d8ecSyc148097 " RCR entry 0x%llx error 0x%x",
253153f3d8ecSyc148097 rcr_entry, channel, error_type));
253253f3d8ecSyc148097 }
25336f45ec7bSml29623 break;
25346f45ec7bSml29623 }
25356f45ec7bSml29623 }
25366f45ec7bSml29623
25376f45ec7bSml29623 /*
25386f45ec7bSml29623 * Update and repost buffer block if max usage
25396f45ec7bSml29623 * count is reached.
25406f45ec7bSml29623 */
25416f45ec7bSml29623 if (error_send_up == B_FALSE) {
2542958cea9eSml29623 atomic_inc_32(&rx_msg_p->ref_cnt);
25436f45ec7bSml29623 if (buffer_free == B_TRUE) {
25446f45ec7bSml29623 rx_msg_p->free = B_TRUE;
25456f45ec7bSml29623 }
25466f45ec7bSml29623
25476f45ec7bSml29623 MUTEX_EXIT(&rx_rbr_p->lock);
25486f45ec7bSml29623 nxge_freeb(rx_msg_p);
25496f45ec7bSml29623 return;
25506f45ec7bSml29623 }
25516f45ec7bSml29623 }
25526f45ec7bSml29623
25536f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
25546f45ec7bSml29623 "==> nxge_receive_packet: DMA sync second "));
25556f45ec7bSml29623
255653f3d8ecSyc148097 bytes_read = rcr_p->rcvd_pkt_bytes;
25576f45ec7bSml29623 skip_len = sw_offset_bytes + hdr_size;
25586f45ec7bSml29623 if (!rx_msg_p->rx_use_bcopy) {
2559958cea9eSml29623 /*
2560958cea9eSml29623 * For loaned up buffers, the driver reference count
2561958cea9eSml29623 * will be incremented first and then the free state.
2562958cea9eSml29623 */
256353f3d8ecSyc148097 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) {
25646f45ec7bSml29623 if (first_entry) {
25656f45ec7bSml29623 nmp->b_rptr = &nmp->b_rptr[skip_len];
256653f3d8ecSyc148097 if (l2_len < bsize - skip_len) {
25676f45ec7bSml29623 nmp->b_wptr = &nmp->b_rptr[l2_len];
25686f45ec7bSml29623 } else {
256953f3d8ecSyc148097 nmp->b_wptr = &nmp->b_rptr[bsize
257053f3d8ecSyc148097 - skip_len];
257153f3d8ecSyc148097 }
257253f3d8ecSyc148097 } else {
257353f3d8ecSyc148097 if (l2_len - bytes_read < bsize) {
25746f45ec7bSml29623 nmp->b_wptr =
25756f45ec7bSml29623 &nmp->b_rptr[l2_len - bytes_read];
257653f3d8ecSyc148097 } else {
257753f3d8ecSyc148097 nmp->b_wptr = &nmp->b_rptr[bsize];
25786f45ec7bSml29623 }
257953f3d8ecSyc148097 }
258053f3d8ecSyc148097 }
258153f3d8ecSyc148097 } else {
258253f3d8ecSyc148097 if (first_entry) {
258353f3d8ecSyc148097 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len,
258453f3d8ecSyc148097 l2_len < bsize - skip_len ?
258553f3d8ecSyc148097 l2_len : bsize - skip_len);
258653f3d8ecSyc148097 } else {
258753f3d8ecSyc148097 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset,
258853f3d8ecSyc148097 l2_len - bytes_read < bsize ?
258953f3d8ecSyc148097 l2_len - bytes_read : bsize);
259053f3d8ecSyc148097 }
259153f3d8ecSyc148097 }
259253f3d8ecSyc148097 if (nmp != NULL) {
2593f720bc57Syc148097 if (first_entry) {
2594f720bc57Syc148097 /*
2595f720bc57Syc148097 * Jumbo packets may be received with more than one
2596f720bc57Syc148097 * buffer, increment ipackets for the first entry only.
2597f720bc57Syc148097 */
2598f720bc57Syc148097 rdc_stats->ipackets++;
2599f720bc57Syc148097
2600f720bc57Syc148097 /* Update ibytes for kstat. */
2601f720bc57Syc148097 rdc_stats->ibytes += skip_len
2602f720bc57Syc148097 + l2_len < bsize ? l2_len : bsize;
2603f720bc57Syc148097 /*
2604f720bc57Syc148097 * Update the number of bytes read so far for the
2605f720bc57Syc148097 * current frame.
2606f720bc57Syc148097 */
260753f3d8ecSyc148097 bytes_read = nmp->b_wptr - nmp->b_rptr;
2608f720bc57Syc148097 } else {
2609f720bc57Syc148097 rdc_stats->ibytes += l2_len - bytes_read < bsize ?
2610f720bc57Syc148097 l2_len - bytes_read : bsize;
26116f45ec7bSml29623 bytes_read += nmp->b_wptr - nmp->b_rptr;
2612f720bc57Syc148097 }
261353f3d8ecSyc148097
26146f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
26156f45ec7bSml29623 "==> nxge_receive_packet after dupb: "
26166f45ec7bSml29623 "rbr consumed %d "
26176f45ec7bSml29623 "pktbufsz_type %d "
26186f45ec7bSml29623 "nmp $%p rptr $%p wptr $%p "
26196f45ec7bSml29623 "buf_offset %d bzise %d l2_len %d skip_len %d",
26206f45ec7bSml29623 rx_rbr_p->rbr_consumed,
26216f45ec7bSml29623 pktbufsz_type,
26226f45ec7bSml29623 nmp, nmp->b_rptr, nmp->b_wptr,
26236f45ec7bSml29623 buf_offset, bsize, l2_len, skip_len));
26246f45ec7bSml29623 } else {
26256f45ec7bSml29623 cmn_err(CE_WARN, "!nxge_receive_packet: "
26266f45ec7bSml29623 "update stats (error)");
26272e59129aSraghus atomic_inc_32(&rx_msg_p->ref_cnt);
26282e59129aSraghus if (buffer_free == B_TRUE) {
26292e59129aSraghus rx_msg_p->free = B_TRUE;
26302e59129aSraghus }
26312e59129aSraghus MUTEX_EXIT(&rx_rbr_p->lock);
26322e59129aSraghus nxge_freeb(rx_msg_p);
26332e59129aSraghus return;
26346f45ec7bSml29623 }
2635ee5416c9Syc148097
26366f45ec7bSml29623 if (buffer_free == B_TRUE) {
26376f45ec7bSml29623 rx_msg_p->free = B_TRUE;
26386f45ec7bSml29623 }
2639f720bc57Syc148097
26406f45ec7bSml29623 is_valid = (nmp != NULL);
264153f3d8ecSyc148097
264253f3d8ecSyc148097 rcr_p->rcvd_pkt_bytes = bytes_read;
264353f3d8ecSyc148097
26446f45ec7bSml29623 MUTEX_EXIT(&rx_rbr_p->lock);
26456f45ec7bSml29623
26466f45ec7bSml29623 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) {
26476f45ec7bSml29623 atomic_inc_32(&rx_msg_p->ref_cnt);
26486f45ec7bSml29623 nxge_freeb(rx_msg_p);
26496f45ec7bSml29623 }
26506f45ec7bSml29623
26516f45ec7bSml29623 if (is_valid) {
26526f45ec7bSml29623 nmp->b_cont = NULL;
26536f45ec7bSml29623 if (first_entry) {
26546f45ec7bSml29623 *mp = nmp;
26556f45ec7bSml29623 *mp_cont = NULL;
265653f3d8ecSyc148097 } else {
26576f45ec7bSml29623 *mp_cont = nmp;
26586f45ec7bSml29623 }
265953f3d8ecSyc148097 }
26606f45ec7bSml29623
26616f45ec7bSml29623 /*
2662f720bc57Syc148097 * ERROR, FRAG and PKT_TYPE are only reported in the first entry.
2663f720bc57Syc148097 * If a packet is not fragmented and no error bit is set, then
2664f720bc57Syc148097 * L4 checksum is OK.
26656f45ec7bSml29623 */
2666f720bc57Syc148097
26676f45ec7bSml29623 if (is_valid && !multi) {
2668678453a8Sspeer /*
2669b4d05839Sml29623 * If the checksum flag nxge_chksum_offload
2670b4d05839Sml29623 * is 1, TCP and UDP packets can be sent
2671678453a8Sspeer * up with good checksum. If the checksum flag
2672b4d05839Sml29623 * is set to 0, checksum reporting will apply to
2673678453a8Sspeer * TCP packets only (workaround for a hardware bug).
2674b4d05839Sml29623 * If the checksum flag nxge_cksum_offload is
2675b4d05839Sml29623 * greater than 1, both TCP and UDP packets
2676b4d05839Sml29623 * will not be reported its hardware checksum results.
2677678453a8Sspeer */
2678b4d05839Sml29623 if (nxge_cksum_offload == 1) {
26796f45ec7bSml29623 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP ||
26806f45ec7bSml29623 pkt_type == RCR_PKT_IS_UDP) ?
26816f45ec7bSml29623 B_TRUE: B_FALSE);
2682b4d05839Sml29623 } else if (!nxge_cksum_offload) {
2683678453a8Sspeer /* TCP checksum only. */
2684678453a8Sspeer is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP) ?
2685678453a8Sspeer B_TRUE: B_FALSE);
2686678453a8Sspeer }
26876f45ec7bSml29623
26886f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: "
26896f45ec7bSml29623 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d",
26906f45ec7bSml29623 is_valid, multi, is_tcp_udp, frag, error_type));
26916f45ec7bSml29623
26926f45ec7bSml29623 if (is_tcp_udp && !frag && !error_type) {
26930dc2366fSVenugopal Iyer mac_hcksum_set(nmp, 0, 0, 0, 0, HCK_FULLCKSUM_OK);
26946f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
26956f45ec7bSml29623 "==> nxge_receive_packet: Full tcp/udp cksum "
26966f45ec7bSml29623 "is_valid 0x%x multi 0x%llx pkt %d frag %d "
26976f45ec7bSml29623 "error %d",
26986f45ec7bSml29623 is_valid, multi, is_tcp_udp, frag, error_type));
26996f45ec7bSml29623 }
27006f45ec7bSml29623 }
27016f45ec7bSml29623
27026f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL,
27036f45ec7bSml29623 "==> nxge_receive_packet: *mp 0x%016llx", *mp));
27046f45ec7bSml29623
27056f45ec7bSml29623 *multi_p = (multi == RCR_MULTI_MASK);
27066f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: "
27076f45ec7bSml29623 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx",
27086f45ec7bSml29623 *multi_p, nmp, *mp, *mp_cont));
27096f45ec7bSml29623 }
27106f45ec7bSml29623
2711da14cebeSEric Cheng /*
2712da14cebeSEric Cheng * Enable polling for a ring. Interrupt for the ring is disabled when
2713da14cebeSEric Cheng * the nxge interrupt comes (see nxge_rx_intr).
2714da14cebeSEric Cheng */
2715da14cebeSEric Cheng int
nxge_enable_poll(void * arg)2716da14cebeSEric Cheng nxge_enable_poll(void *arg)
2717da14cebeSEric Cheng {
2718da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg;
2719da14cebeSEric Cheng p_rx_rcr_ring_t ringp;
2720da14cebeSEric Cheng p_nxge_t nxgep;
2721da14cebeSEric Cheng p_nxge_ldg_t ldgp;
2722da14cebeSEric Cheng uint32_t channel;
2723da14cebeSEric Cheng
2724da14cebeSEric Cheng if (ring_handle == NULL) {
272563f531d1SSriharsha Basavapatna ASSERT(ring_handle != NULL);
2726da14cebeSEric Cheng return (0);
2727da14cebeSEric Cheng }
2728da14cebeSEric Cheng
2729da14cebeSEric Cheng nxgep = ring_handle->nxgep;
2730da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2731da14cebeSEric Cheng ringp = nxgep->rx_rcr_rings->rcr_rings[channel];
2732da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2733da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d ", ringp->rdc));
2734da14cebeSEric Cheng ldgp = ringp->ldgp;
2735da14cebeSEric Cheng if (ldgp == NULL) {
2736da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2737da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d NULL ldgp: no change",
2738da14cebeSEric Cheng ringp->rdc));
2739da14cebeSEric Cheng return (0);
2740da14cebeSEric Cheng }
2741da14cebeSEric Cheng
2742da14cebeSEric Cheng MUTEX_ENTER(&ringp->lock);
2743da14cebeSEric Cheng /* enable polling */
2744da14cebeSEric Cheng if (ringp->poll_flag == 0) {
2745da14cebeSEric Cheng ringp->poll_flag = 1;
2746da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2747da14cebeSEric Cheng "==> nxge_enable_poll: rdc %d set poll flag to 1",
2748da14cebeSEric Cheng ringp->rdc));
2749da14cebeSEric Cheng }
2750da14cebeSEric Cheng
2751da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock);
2752da14cebeSEric Cheng return (0);
2753da14cebeSEric Cheng }
2754da14cebeSEric Cheng /*
2755da14cebeSEric Cheng * Disable polling for a ring and enable its interrupt.
2756da14cebeSEric Cheng */
2757da14cebeSEric Cheng int
nxge_disable_poll(void * arg)2758da14cebeSEric Cheng nxge_disable_poll(void *arg)
2759da14cebeSEric Cheng {
2760da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg;
2761da14cebeSEric Cheng p_rx_rcr_ring_t ringp;
2762da14cebeSEric Cheng p_nxge_t nxgep;
2763da14cebeSEric Cheng uint32_t channel;
2764da14cebeSEric Cheng
2765da14cebeSEric Cheng if (ring_handle == NULL) {
276663f531d1SSriharsha Basavapatna ASSERT(ring_handle != NULL);
2767da14cebeSEric Cheng return (0);
2768da14cebeSEric Cheng }
2769da14cebeSEric Cheng
2770da14cebeSEric Cheng nxgep = ring_handle->nxgep;
2771da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2772da14cebeSEric Cheng ringp = nxgep->rx_rcr_rings->rcr_rings[channel];
2773da14cebeSEric Cheng
2774da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2775da14cebeSEric Cheng "==> nxge_disable_poll: rdc %d poll_flag %d", ringp->rdc));
2776da14cebeSEric Cheng
2777da14cebeSEric Cheng MUTEX_ENTER(&ringp->lock);
2778da14cebeSEric Cheng
2779da14cebeSEric Cheng /* disable polling: enable interrupt */
2780da14cebeSEric Cheng if (ringp->poll_flag) {
2781da14cebeSEric Cheng npi_handle_t handle;
2782da14cebeSEric Cheng rx_dma_ctl_stat_t cs;
2783da14cebeSEric Cheng uint8_t channel;
2784da14cebeSEric Cheng p_nxge_ldg_t ldgp;
2785da14cebeSEric Cheng
2786da14cebeSEric Cheng /*
2787da14cebeSEric Cheng * Get the control and status for this channel.
2788da14cebeSEric Cheng */
2789da14cebeSEric Cheng handle = NXGE_DEV_NPI_HANDLE(nxgep);
2790da14cebeSEric Cheng channel = ringp->rdc;
2791da14cebeSEric Cheng RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG,
2792da14cebeSEric Cheng channel, &cs.value);
2793da14cebeSEric Cheng
2794da14cebeSEric Cheng /*
2795da14cebeSEric Cheng * Enable mailbox update
2796da14cebeSEric Cheng * Since packets were not read and the hardware uses
2797da14cebeSEric Cheng * bits pktread and ptrread to update the queue
2798da14cebeSEric Cheng * length, we need to set both bits to 0.
2799da14cebeSEric Cheng */
2800da14cebeSEric Cheng cs.bits.ldw.pktread = 0;
2801da14cebeSEric Cheng cs.bits.ldw.ptrread = 0;
2802da14cebeSEric Cheng cs.bits.hdw.mex = 1;
2803da14cebeSEric Cheng RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel,
2804da14cebeSEric Cheng cs.value);
2805da14cebeSEric Cheng
2806da14cebeSEric Cheng /*
2807da14cebeSEric Cheng * Rearm this logical group if this is a single device
2808da14cebeSEric Cheng * group.
2809da14cebeSEric Cheng */
2810da14cebeSEric Cheng ldgp = ringp->ldgp;
2811da14cebeSEric Cheng if (ldgp == NULL) {
2812da14cebeSEric Cheng ringp->poll_flag = 0;
2813da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock);
2814da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2815da14cebeSEric Cheng "==> nxge_disable_poll: no ldgp rdc %d "
2816da14cebeSEric Cheng "(still set poll to 0", ringp->rdc));
2817da14cebeSEric Cheng return (0);
2818da14cebeSEric Cheng }
2819da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2820da14cebeSEric Cheng "==> nxge_disable_poll: rdc %d ldgp $%p (enable intr)",
2821da14cebeSEric Cheng ringp->rdc, ldgp));
2822da14cebeSEric Cheng if (ldgp->nldvs == 1) {
282363f531d1SSriharsha Basavapatna if (isLDOMguest(nxgep)) {
282463f531d1SSriharsha Basavapatna ldgp->arm = B_TRUE;
282563f531d1SSriharsha Basavapatna nxge_hio_ldgimgn(nxgep, ldgp);
282663f531d1SSriharsha Basavapatna } else {
2827da14cebeSEric Cheng ldgimgm_t mgm;
2828da14cebeSEric Cheng mgm.value = 0;
2829da14cebeSEric Cheng mgm.bits.ldw.arm = 1;
2830da14cebeSEric Cheng mgm.bits.ldw.timer = ldgp->ldg_timer;
2831da14cebeSEric Cheng NXGE_REG_WR64(handle,
283263f531d1SSriharsha Basavapatna LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg),
283363f531d1SSriharsha Basavapatna mgm.value);
283463f531d1SSriharsha Basavapatna }
2835da14cebeSEric Cheng }
2836da14cebeSEric Cheng ringp->poll_flag = 0;
2837da14cebeSEric Cheng }
2838da14cebeSEric Cheng
2839da14cebeSEric Cheng MUTEX_EXIT(&ringp->lock);
2840da14cebeSEric Cheng return (0);
2841da14cebeSEric Cheng }
2842da14cebeSEric Cheng
2843da14cebeSEric Cheng /*
2844da14cebeSEric Cheng * Poll 'bytes_to_pickup' bytes of message from the rx ring.
2845da14cebeSEric Cheng */
2846da14cebeSEric Cheng mblk_t *
nxge_rx_poll(void * arg,int bytes_to_pickup)2847da14cebeSEric Cheng nxge_rx_poll(void *arg, int bytes_to_pickup)
2848da14cebeSEric Cheng {
2849da14cebeSEric Cheng p_nxge_ring_handle_t ring_handle = (p_nxge_ring_handle_t)arg;
2850da14cebeSEric Cheng p_rx_rcr_ring_t rcr_p;
2851da14cebeSEric Cheng p_nxge_t nxgep;
2852da14cebeSEric Cheng npi_handle_t handle;
2853da14cebeSEric Cheng rx_dma_ctl_stat_t cs;
2854da14cebeSEric Cheng mblk_t *mblk;
2855da14cebeSEric Cheng p_nxge_ldv_t ldvp;
2856da14cebeSEric Cheng uint32_t channel;
2857da14cebeSEric Cheng
2858da14cebeSEric Cheng nxgep = ring_handle->nxgep;
2859da14cebeSEric Cheng
2860da14cebeSEric Cheng /*
2861da14cebeSEric Cheng * Get the control and status for this channel.
2862da14cebeSEric Cheng */
2863da14cebeSEric Cheng handle = NXGE_DEV_NPI_HANDLE(nxgep);
2864da14cebeSEric Cheng channel = nxgep->pt_config.hw_config.start_rdc + ring_handle->index;
2865da14cebeSEric Cheng rcr_p = nxgep->rx_rcr_rings->rcr_rings[channel];
2866da14cebeSEric Cheng MUTEX_ENTER(&rcr_p->lock);
2867da14cebeSEric Cheng ASSERT(rcr_p->poll_flag == 1);
2868da14cebeSEric Cheng
2869da14cebeSEric Cheng RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, rcr_p->rdc, &cs.value);
2870da14cebeSEric Cheng
2871da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2872da14cebeSEric Cheng "==> nxge_rx_poll: calling nxge_rx_pkts: rdc %d poll_flag %d",
2873da14cebeSEric Cheng rcr_p->rdc, rcr_p->poll_flag));
2874da14cebeSEric Cheng mblk = nxge_rx_pkts(nxgep, rcr_p, cs, bytes_to_pickup);
2875da14cebeSEric Cheng
2876da14cebeSEric Cheng ldvp = rcr_p->ldvp;
2877da14cebeSEric Cheng /* error events. */
2878da14cebeSEric Cheng if (ldvp && (cs.value & RX_DMA_CTL_STAT_ERROR)) {
2879da14cebeSEric Cheng (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, cs);
2880da14cebeSEric Cheng }
2881da14cebeSEric Cheng
2882da14cebeSEric Cheng MUTEX_EXIT(&rcr_p->lock);
2883da14cebeSEric Cheng
2884da14cebeSEric Cheng NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL,
2885da14cebeSEric Cheng "<== nxge_rx_poll: rdc %d mblk $%p", rcr_p->rdc, mblk));
2886da14cebeSEric Cheng return (mblk);
2887da14cebeSEric Cheng }
2888da14cebeSEric Cheng
2889da14cebeSEric Cheng
28906f45ec7bSml29623 /*ARGSUSED*/
28916f45ec7bSml29623 static nxge_status_t
nxge_rx_err_evnts(p_nxge_t nxgep,int channel,rx_dma_ctl_stat_t cs)2892678453a8Sspeer nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs)
28936f45ec7bSml29623 {
28946f45ec7bSml29623 p_nxge_rx_ring_stats_t rdc_stats;
28956f45ec7bSml29623 npi_handle_t handle;
28966f45ec7bSml29623 npi_status_t rs;
28976f45ec7bSml29623 boolean_t rxchan_fatal = B_FALSE;
28986f45ec7bSml29623 boolean_t rxport_fatal = B_FALSE;
28996f45ec7bSml29623 uint8_t portn;
29006f45ec7bSml29623 nxge_status_t status = NXGE_OK;
29016f45ec7bSml29623 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX;
29026f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts"));
29036f45ec7bSml29623
29046f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
29056f45ec7bSml29623 portn = nxgep->mac.portnum;
2906678453a8Sspeer rdc_stats = &nxgep->statsp->rdc_stats[channel];
29076f45ec7bSml29623
29086f45ec7bSml29623 if (cs.bits.hdw.rbr_tmout) {
29096f45ec7bSml29623 rdc_stats->rx_rbr_tmout++;
29106f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29116f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RBR_TMOUT);
29126f45ec7bSml29623 rxchan_fatal = B_TRUE;
29136f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29146f45ec7bSml29623 "==> nxge_rx_err_evnts: rx_rbr_timeout"));
29156f45ec7bSml29623 }
29166f45ec7bSml29623 if (cs.bits.hdw.rsp_cnt_err) {
29176f45ec7bSml29623 rdc_stats->rsp_cnt_err++;
29186f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29196f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR);
29206f45ec7bSml29623 rxchan_fatal = B_TRUE;
29216f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29226f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29236f45ec7bSml29623 "rsp_cnt_err", channel));
29246f45ec7bSml29623 }
29256f45ec7bSml29623 if (cs.bits.hdw.byte_en_bus) {
29266f45ec7bSml29623 rdc_stats->byte_en_bus++;
29276f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29286f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS);
29296f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29306f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29316f45ec7bSml29623 "fatal error: byte_en_bus", channel));
29326f45ec7bSml29623 rxchan_fatal = B_TRUE;
29336f45ec7bSml29623 }
29346f45ec7bSml29623 if (cs.bits.hdw.rsp_dat_err) {
29356f45ec7bSml29623 rdc_stats->rsp_dat_err++;
29366f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29376f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR);
29386f45ec7bSml29623 rxchan_fatal = B_TRUE;
29396f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29406f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29416f45ec7bSml29623 "fatal error: rsp_dat_err", channel));
29426f45ec7bSml29623 }
29436f45ec7bSml29623 if (cs.bits.hdw.rcr_ack_err) {
29446f45ec7bSml29623 rdc_stats->rcr_ack_err++;
29456f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29466f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR);
29476f45ec7bSml29623 rxchan_fatal = B_TRUE;
29486f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29496f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29506f45ec7bSml29623 "fatal error: rcr_ack_err", channel));
29516f45ec7bSml29623 }
29526f45ec7bSml29623 if (cs.bits.hdw.dc_fifo_err) {
29536f45ec7bSml29623 rdc_stats->dc_fifo_err++;
29546f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29556f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR);
29566f45ec7bSml29623 /* This is not a fatal error! */
29576f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29586f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29596f45ec7bSml29623 "dc_fifo_err", channel));
29606f45ec7bSml29623 rxport_fatal = B_TRUE;
29616f45ec7bSml29623 }
29626f45ec7bSml29623 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) {
29636f45ec7bSml29623 if ((rs = npi_rxdma_ring_perr_stat_get(handle,
29646f45ec7bSml29623 &rdc_stats->errlog.pre_par,
29656f45ec7bSml29623 &rdc_stats->errlog.sha_par))
29666f45ec7bSml29623 != NPI_SUCCESS) {
29676f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29686f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29696f45ec7bSml29623 "rcr_sha_par: get perr", channel));
29706f45ec7bSml29623 return (NXGE_ERROR | rs);
29716f45ec7bSml29623 }
29726f45ec7bSml29623 if (cs.bits.hdw.rcr_sha_par) {
29736f45ec7bSml29623 rdc_stats->rcr_sha_par++;
29746f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29756f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR);
29766f45ec7bSml29623 rxchan_fatal = B_TRUE;
29776f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29786f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29796f45ec7bSml29623 "fatal error: rcr_sha_par", channel));
29806f45ec7bSml29623 }
29816f45ec7bSml29623 if (cs.bits.hdw.rbr_pre_par) {
29826f45ec7bSml29623 rdc_stats->rbr_pre_par++;
29836f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
29846f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR);
29856f45ec7bSml29623 rxchan_fatal = B_TRUE;
29866f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
29876f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
29886f45ec7bSml29623 "fatal error: rbr_pre_par", channel));
29896f45ec7bSml29623 }
29906f45ec7bSml29623 }
299163e23a19Syc148097 /*
299263e23a19Syc148097 * The Following 4 status bits are for information, the system
299363e23a19Syc148097 * is running fine. There is no need to send FMA ereports or
299463e23a19Syc148097 * log messages.
299563e23a19Syc148097 */
29966f45ec7bSml29623 if (cs.bits.hdw.port_drop_pkt) {
29976f45ec7bSml29623 rdc_stats->port_drop_pkt++;
29986f45ec7bSml29623 }
29996f45ec7bSml29623 if (cs.bits.hdw.wred_drop) {
30006f45ec7bSml29623 rdc_stats->wred_drop++;
30016f45ec7bSml29623 }
30026f45ec7bSml29623 if (cs.bits.hdw.rbr_pre_empty) {
30036f45ec7bSml29623 rdc_stats->rbr_pre_empty++;
30046f45ec7bSml29623 }
30056f45ec7bSml29623 if (cs.bits.hdw.rcr_shadow_full) {
30066f45ec7bSml29623 rdc_stats->rcr_shadow_full++;
30076f45ec7bSml29623 }
30086f45ec7bSml29623 if (cs.bits.hdw.config_err) {
30096f45ec7bSml29623 rdc_stats->config_err++;
30106f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30116f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_CONFIG_ERR);
30126f45ec7bSml29623 rxchan_fatal = B_TRUE;
30136f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30146f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30156f45ec7bSml29623 "config error", channel));
30166f45ec7bSml29623 }
30176f45ec7bSml29623 if (cs.bits.hdw.rcrincon) {
30186f45ec7bSml29623 rdc_stats->rcrincon++;
30196f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30206f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RCRINCON);
30216f45ec7bSml29623 rxchan_fatal = B_TRUE;
30226f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30236f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30246f45ec7bSml29623 "fatal error: rcrincon error", channel));
30256f45ec7bSml29623 }
30266f45ec7bSml29623 if (cs.bits.hdw.rcrfull) {
30276f45ec7bSml29623 rdc_stats->rcrfull++;
30286f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30296f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RCRFULL);
30306f45ec7bSml29623 rxchan_fatal = B_TRUE;
30314df3b64dSToomas Soome if (rdc_stats->rcrfull < error_disp_cnt) {
30326f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30336f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30346f45ec7bSml29623 "fatal error: rcrfull error", channel));
30356f45ec7bSml29623 }
30364df3b64dSToomas Soome }
30376f45ec7bSml29623 if (cs.bits.hdw.rbr_empty) {
303863e23a19Syc148097 /*
303963e23a19Syc148097 * This bit is for information, there is no need
304063e23a19Syc148097 * send FMA ereport or log a message.
304163e23a19Syc148097 */
30426f45ec7bSml29623 rdc_stats->rbr_empty++;
30436f45ec7bSml29623 }
30446f45ec7bSml29623 if (cs.bits.hdw.rbrfull) {
30456f45ec7bSml29623 rdc_stats->rbrfull++;
30466f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30476f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RBRFULL);
30486f45ec7bSml29623 rxchan_fatal = B_TRUE;
30496f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30506f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30516f45ec7bSml29623 "fatal error: rbr_full error", channel));
30526f45ec7bSml29623 }
30536f45ec7bSml29623 if (cs.bits.hdw.rbrlogpage) {
30546f45ec7bSml29623 rdc_stats->rbrlogpage++;
30556f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30566f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE);
30576f45ec7bSml29623 rxchan_fatal = B_TRUE;
30586f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30596f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30606f45ec7bSml29623 "fatal error: rbr logical page error", channel));
30616f45ec7bSml29623 }
30626f45ec7bSml29623 if (cs.bits.hdw.cfiglogpage) {
30636f45ec7bSml29623 rdc_stats->cfiglogpage++;
30646f45ec7bSml29623 NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
30656f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE);
30666f45ec7bSml29623 rxchan_fatal = B_TRUE;
30676f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
30686f45ec7bSml29623 "==> nxge_rx_err_evnts(channel %d): "
30696f45ec7bSml29623 "fatal error: cfig logical page error", channel));
30706f45ec7bSml29623 }
30716f45ec7bSml29623
30726f45ec7bSml29623 if (rxport_fatal) {
30736f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3074678453a8Sspeer " nxge_rx_err_evnts: fatal error on Port #%d\n",
30756f45ec7bSml29623 portn));
3076678453a8Sspeer if (isLDOMguest(nxgep)) {
3077678453a8Sspeer status = NXGE_ERROR;
3078678453a8Sspeer } else {
30796f45ec7bSml29623 status = nxge_ipp_fatal_err_recover(nxgep);
30806f45ec7bSml29623 if (status == NXGE_OK) {
30816f45ec7bSml29623 FM_SERVICE_RESTORED(nxgep);
30826f45ec7bSml29623 }
30836f45ec7bSml29623 }
3084678453a8Sspeer }
30856f45ec7bSml29623
30866f45ec7bSml29623 if (rxchan_fatal) {
30876f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3088678453a8Sspeer " nxge_rx_err_evnts: fatal error on Channel #%d\n",
30896f45ec7bSml29623 channel));
3090678453a8Sspeer if (isLDOMguest(nxgep)) {
3091678453a8Sspeer status = NXGE_ERROR;
3092678453a8Sspeer } else {
30936f45ec7bSml29623 status = nxge_rxdma_fatal_err_recover(nxgep, channel);
30946f45ec7bSml29623 if (status == NXGE_OK) {
30956f45ec7bSml29623 FM_SERVICE_RESTORED(nxgep);
30966f45ec7bSml29623 }
30976f45ec7bSml29623 }
3098678453a8Sspeer }
30996f45ec7bSml29623
31006f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts"));
31016f45ec7bSml29623
31026f45ec7bSml29623 return (status);
31036f45ec7bSml29623 }
31046f45ec7bSml29623
3105678453a8Sspeer /*
3106678453a8Sspeer * nxge_rdc_hvio_setup
3107678453a8Sspeer *
3108678453a8Sspeer * This code appears to setup some Hypervisor variables.
3109678453a8Sspeer *
3110678453a8Sspeer * Arguments:
3111678453a8Sspeer * nxgep
3112678453a8Sspeer * channel
3113678453a8Sspeer *
3114678453a8Sspeer * Notes:
3115678453a8Sspeer * What does NIU_LP_WORKAROUND mean?
3116678453a8Sspeer *
3117678453a8Sspeer * NPI/NXGE function calls:
3118678453a8Sspeer * na
3119678453a8Sspeer *
3120678453a8Sspeer * Context:
3121678453a8Sspeer * Any domain
3122678453a8Sspeer */
31236f45ec7bSml29623 #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
3124678453a8Sspeer static void
nxge_rdc_hvio_setup(nxge_t * nxgep,int channel)3125678453a8Sspeer nxge_rdc_hvio_setup(
3126678453a8Sspeer nxge_t *nxgep, int channel)
3127678453a8Sspeer {
3128678453a8Sspeer nxge_dma_common_t *dma_common;
3129678453a8Sspeer nxge_dma_common_t *dma_control;
3130678453a8Sspeer rx_rbr_ring_t *ring;
3131678453a8Sspeer
3132678453a8Sspeer ring = nxgep->rx_rbr_rings->rbr_rings[channel];
3133678453a8Sspeer dma_common = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
3134678453a8Sspeer
3135678453a8Sspeer ring->hv_set = B_FALSE;
3136678453a8Sspeer
3137678453a8Sspeer ring->hv_rx_buf_base_ioaddr_pp = (uint64_t)
3138678453a8Sspeer dma_common->orig_ioaddr_pp;
3139678453a8Sspeer ring->hv_rx_buf_ioaddr_size = (uint64_t)
3140678453a8Sspeer dma_common->orig_alength;
3141678453a8Sspeer
3142678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: "
3143678453a8Sspeer "channel %d data buf base io $%lx ($%p) size 0x%lx (%ld 0x%lx)",
3144678453a8Sspeer channel, ring->hv_rx_buf_base_ioaddr_pp,
3145678453a8Sspeer dma_common->ioaddr_pp, ring->hv_rx_buf_ioaddr_size,
3146678453a8Sspeer dma_common->orig_alength, dma_common->orig_alength));
3147678453a8Sspeer
3148678453a8Sspeer dma_control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
3149678453a8Sspeer
3150678453a8Sspeer ring->hv_rx_cntl_base_ioaddr_pp =
3151678453a8Sspeer (uint64_t)dma_control->orig_ioaddr_pp;
3152678453a8Sspeer ring->hv_rx_cntl_ioaddr_size =
3153678453a8Sspeer (uint64_t)dma_control->orig_alength;
3154678453a8Sspeer
3155678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma_channel: "
3156678453a8Sspeer "channel %d cntl base io $%p ($%p) size 0x%llx (%d 0x%x)",
3157678453a8Sspeer channel, ring->hv_rx_cntl_base_ioaddr_pp,
3158678453a8Sspeer dma_control->ioaddr_pp, ring->hv_rx_cntl_ioaddr_size,
3159678453a8Sspeer dma_control->orig_alength, dma_control->orig_alength));
3160678453a8Sspeer }
31616f45ec7bSml29623 #endif
31626f45ec7bSml29623
3163678453a8Sspeer /*
3164678453a8Sspeer * nxge_map_rxdma
3165678453a8Sspeer *
3166678453a8Sspeer * Map an RDC into our kernel space.
3167678453a8Sspeer *
3168678453a8Sspeer * Arguments:
3169678453a8Sspeer * nxgep
3170678453a8Sspeer * channel The channel to map.
3171678453a8Sspeer *
3172678453a8Sspeer * Notes:
3173678453a8Sspeer * 1. Allocate & initialise a memory pool, if necessary.
3174678453a8Sspeer * 2. Allocate however many receive buffers are required.
3175678453a8Sspeer * 3. Setup buffers, descriptors, and mailbox.
3176678453a8Sspeer *
3177678453a8Sspeer * NPI/NXGE function calls:
3178678453a8Sspeer * nxge_alloc_rx_mem_pool()
3179678453a8Sspeer * nxge_alloc_rbb()
3180678453a8Sspeer * nxge_map_rxdma_channel()
3181678453a8Sspeer *
3182678453a8Sspeer * Registers accessed:
3183678453a8Sspeer *
3184678453a8Sspeer * Context:
3185678453a8Sspeer * Any domain
3186678453a8Sspeer */
3187678453a8Sspeer static nxge_status_t
nxge_map_rxdma(p_nxge_t nxgep,int channel)3188678453a8Sspeer nxge_map_rxdma(p_nxge_t nxgep, int channel)
3189678453a8Sspeer {
3190678453a8Sspeer nxge_dma_common_t **data;
3191678453a8Sspeer nxge_dma_common_t **control;
3192678453a8Sspeer rx_rbr_ring_t **rbr_ring;
3193678453a8Sspeer rx_rcr_ring_t **rcr_ring;
3194678453a8Sspeer rx_mbox_t **mailbox;
3195678453a8Sspeer uint32_t chunks;
3196678453a8Sspeer
3197678453a8Sspeer nxge_status_t status;
3198678453a8Sspeer
31996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma"));
32006f45ec7bSml29623
3201678453a8Sspeer if (!nxgep->rx_buf_pool_p) {
3202678453a8Sspeer if (nxge_alloc_rx_mem_pool(nxgep) != NXGE_OK) {
32036f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
32046f45ec7bSml29623 "<== nxge_map_rxdma: buf not allocated"));
32056f45ec7bSml29623 return (NXGE_ERROR);
32066f45ec7bSml29623 }
32076f45ec7bSml29623 }
32086f45ec7bSml29623
3209678453a8Sspeer if (nxge_alloc_rxb(nxgep, channel) != NXGE_OK)
3210678453a8Sspeer return (NXGE_ERROR);
32116f45ec7bSml29623
32126f45ec7bSml29623 /*
3213678453a8Sspeer * Map descriptors from the buffer polls for each dma channel.
32146f45ec7bSml29623 */
3215678453a8Sspeer
32166f45ec7bSml29623 /*
32176f45ec7bSml29623 * Set up and prepare buffer blocks, descriptors
32186f45ec7bSml29623 * and mailbox.
32196f45ec7bSml29623 */
3220678453a8Sspeer data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel];
3221678453a8Sspeer rbr_ring = &nxgep->rx_rbr_rings->rbr_rings[channel];
3222678453a8Sspeer chunks = nxgep->rx_buf_pool_p->num_chunks[channel];
3223678453a8Sspeer
3224678453a8Sspeer control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel];
3225678453a8Sspeer rcr_ring = &nxgep->rx_rcr_rings->rcr_rings[channel];
3226678453a8Sspeer
3227678453a8Sspeer mailbox = &nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
3228678453a8Sspeer
3229678453a8Sspeer status = nxge_map_rxdma_channel(nxgep, channel, data, rbr_ring,
3230678453a8Sspeer chunks, control, rcr_ring, mailbox);
32316f45ec7bSml29623 if (status != NXGE_OK) {
3232678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3233678453a8Sspeer "==> nxge_map_rxdma: nxge_map_rxdma_channel(%d) "
3234678453a8Sspeer "returned 0x%x",
3235678453a8Sspeer channel, status));
3236678453a8Sspeer return (status);
32376f45ec7bSml29623 }
3238678453a8Sspeer nxgep->rx_rbr_rings->rbr_rings[channel]->index = (uint16_t)channel;
3239678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->index = (uint16_t)channel;
3240678453a8Sspeer nxgep->rx_rcr_rings->rcr_rings[channel]->rdc_stats =
3241678453a8Sspeer &nxgep->statsp->rdc_stats[channel];
32426f45ec7bSml29623
32436f45ec7bSml29623 #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
3244678453a8Sspeer if (!isLDOMguest(nxgep))
3245678453a8Sspeer nxge_rdc_hvio_setup(nxgep, channel);
3246678453a8Sspeer #endif
32476f45ec7bSml29623
32486f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3249678453a8Sspeer "<== nxge_map_rxdma: (status 0x%x channel %d)", status, channel));
32506f45ec7bSml29623
32516f45ec7bSml29623 return (status);
32526f45ec7bSml29623 }
32536f45ec7bSml29623
32546f45ec7bSml29623 static void
nxge_unmap_rxdma(p_nxge_t nxgep,int channel)3255678453a8Sspeer nxge_unmap_rxdma(p_nxge_t nxgep, int channel)
32566f45ec7bSml29623 {
3257678453a8Sspeer rx_rbr_ring_t *rbr_ring;
3258678453a8Sspeer rx_rcr_ring_t *rcr_ring;
3259678453a8Sspeer rx_mbox_t *mailbox;
32606f45ec7bSml29623
3261678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma(%d)", channel));
32626f45ec7bSml29623
3263678453a8Sspeer if (!nxgep->rx_rbr_rings || !nxgep->rx_rcr_rings ||
3264678453a8Sspeer !nxgep->rx_mbox_areas_p)
32656f45ec7bSml29623 return;
32666f45ec7bSml29623
3267678453a8Sspeer rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel];
3268678453a8Sspeer rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel];
3269678453a8Sspeer mailbox = nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
3270678453a8Sspeer
3271678453a8Sspeer if (!rbr_ring || !rcr_ring || !mailbox)
32726f45ec7bSml29623 return;
32736f45ec7bSml29623
3274678453a8Sspeer (void) nxge_unmap_rxdma_channel(
3275678453a8Sspeer nxgep, channel, rbr_ring, rcr_ring, mailbox);
32766f45ec7bSml29623
3277678453a8Sspeer nxge_free_rxb(nxgep, channel);
32786f45ec7bSml29623
3279678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma"));
32806f45ec7bSml29623 }
32816f45ec7bSml29623
32826f45ec7bSml29623 nxge_status_t
nxge_map_rxdma_channel(p_nxge_t nxgep,uint16_t channel,p_nxge_dma_common_t * dma_buf_p,p_rx_rbr_ring_t * rbr_p,uint32_t num_chunks,p_nxge_dma_common_t * dma_cntl_p,p_rx_rcr_ring_t * rcr_p,p_rx_mbox_t * rx_mbox_p)32836f45ec7bSml29623 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
32846f45ec7bSml29623 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p,
32856f45ec7bSml29623 uint32_t num_chunks,
32866f45ec7bSml29623 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p,
32876f45ec7bSml29623 p_rx_mbox_t *rx_mbox_p)
32886f45ec7bSml29623 {
32896f45ec7bSml29623 int status = NXGE_OK;
32906f45ec7bSml29623
32916f45ec7bSml29623 /*
32926f45ec7bSml29623 * Set up and prepare buffer blocks, descriptors
32936f45ec7bSml29623 * and mailbox.
32946f45ec7bSml29623 */
32956f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
32966f45ec7bSml29623 "==> nxge_map_rxdma_channel (channel %d)", channel));
32976f45ec7bSml29623 /*
32986f45ec7bSml29623 * Receive buffer blocks
32996f45ec7bSml29623 */
33006f45ec7bSml29623 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel,
33016f45ec7bSml29623 dma_buf_p, rbr_p, num_chunks);
33026f45ec7bSml29623 if (status != NXGE_OK) {
33036f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
33046f45ec7bSml29623 "==> nxge_map_rxdma_channel (channel %d): "
33056f45ec7bSml29623 "map buffer failed 0x%x", channel, status));
33066f45ec7bSml29623 goto nxge_map_rxdma_channel_exit;
33076f45ec7bSml29623 }
33086f45ec7bSml29623
33096f45ec7bSml29623 /*
33106f45ec7bSml29623 * Receive block ring, completion ring and mailbox.
33116f45ec7bSml29623 */
33126f45ec7bSml29623 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel,
33136f45ec7bSml29623 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p);
33146f45ec7bSml29623 if (status != NXGE_OK) {
33156f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
33166f45ec7bSml29623 "==> nxge_map_rxdma_channel (channel %d): "
33176f45ec7bSml29623 "map config failed 0x%x", channel, status));
33186f45ec7bSml29623 goto nxge_map_rxdma_channel_fail2;
33196f45ec7bSml29623 }
33206f45ec7bSml29623
33216f45ec7bSml29623 goto nxge_map_rxdma_channel_exit;
33226f45ec7bSml29623
33236f45ec7bSml29623 nxge_map_rxdma_channel_fail3:
33246f45ec7bSml29623 /* Free rbr, rcr */
33256f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
33266f45ec7bSml29623 "==> nxge_map_rxdma_channel: free rbr/rcr "
33276f45ec7bSml29623 "(status 0x%x channel %d)",
33286f45ec7bSml29623 status, channel));
33296f45ec7bSml29623 nxge_unmap_rxdma_channel_cfg_ring(nxgep,
33306f45ec7bSml29623 *rcr_p, *rx_mbox_p);
33316f45ec7bSml29623
33326f45ec7bSml29623 nxge_map_rxdma_channel_fail2:
33336f45ec7bSml29623 /* Free buffer blocks */
33346f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
33356f45ec7bSml29623 "==> nxge_map_rxdma_channel: free rx buffers"
33366f45ec7bSml29623 "(nxgep 0x%x status 0x%x channel %d)",
33376f45ec7bSml29623 nxgep, status, channel));
33386f45ec7bSml29623 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p);
33396f45ec7bSml29623
334056d930aeSspeer status = NXGE_ERROR;
334156d930aeSspeer
33426f45ec7bSml29623 nxge_map_rxdma_channel_exit:
33436f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
33446f45ec7bSml29623 "<== nxge_map_rxdma_channel: "
33456f45ec7bSml29623 "(nxgep 0x%x status 0x%x channel %d)",
33466f45ec7bSml29623 nxgep, status, channel));
33476f45ec7bSml29623
33486f45ec7bSml29623 return (status);
33496f45ec7bSml29623 }
33506f45ec7bSml29623
33516f45ec7bSml29623 /*ARGSUSED*/
33526f45ec7bSml29623 static void
nxge_unmap_rxdma_channel(p_nxge_t nxgep,uint16_t channel,p_rx_rbr_ring_t rbr_p,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t rx_mbox_p)33536f45ec7bSml29623 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel,
33546f45ec7bSml29623 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p)
33556f45ec7bSml29623 {
33566f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
33576f45ec7bSml29623 "==> nxge_unmap_rxdma_channel (channel %d)", channel));
33586f45ec7bSml29623
33596f45ec7bSml29623 /*
33606f45ec7bSml29623 * unmap receive block ring, completion ring and mailbox.
33616f45ec7bSml29623 */
33626f45ec7bSml29623 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep,
33636f45ec7bSml29623 rcr_p, rx_mbox_p);
33646f45ec7bSml29623
33656f45ec7bSml29623 /* unmap buffer blocks */
33666f45ec7bSml29623 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p);
33676f45ec7bSml29623
33686f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel"));
33696f45ec7bSml29623 }
33706f45ec7bSml29623
33716f45ec7bSml29623 /*ARGSUSED*/
33726f45ec7bSml29623 static nxge_status_t
nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep,uint16_t dma_channel,p_nxge_dma_common_t * dma_cntl_p,p_rx_rbr_ring_t * rbr_p,p_rx_rcr_ring_t * rcr_p,p_rx_mbox_t * rx_mbox_p)33736f45ec7bSml29623 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel,
33746f45ec7bSml29623 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p,
33756f45ec7bSml29623 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p)
33766f45ec7bSml29623 {
33776f45ec7bSml29623 p_rx_rbr_ring_t rbrp;
33786f45ec7bSml29623 p_rx_rcr_ring_t rcrp;
33796f45ec7bSml29623 p_rx_mbox_t mboxp;
33806f45ec7bSml29623 p_nxge_dma_common_t cntl_dmap;
33816f45ec7bSml29623 p_nxge_dma_common_t dmap;
33826f45ec7bSml29623 p_rx_msg_t *rx_msg_ring;
33836f45ec7bSml29623 p_rx_msg_t rx_msg_p;
33846f45ec7bSml29623 p_rbr_cfig_a_t rcfga_p;
33856f45ec7bSml29623 p_rbr_cfig_b_t rcfgb_p;
33866f45ec7bSml29623 p_rcrcfig_a_t cfga_p;
33876f45ec7bSml29623 p_rcrcfig_b_t cfgb_p;
33886f45ec7bSml29623 p_rxdma_cfig1_t cfig1_p;
33896f45ec7bSml29623 p_rxdma_cfig2_t cfig2_p;
33906f45ec7bSml29623 p_rbr_kick_t kick_p;
33916f45ec7bSml29623 uint32_t dmaaddrp;
33926f45ec7bSml29623 uint32_t *rbr_vaddrp;
33936f45ec7bSml29623 uint32_t bkaddr;
33946f45ec7bSml29623 nxge_status_t status = NXGE_OK;
33956f45ec7bSml29623 int i;
33966f45ec7bSml29623 uint32_t nxge_port_rcr_size;
33976f45ec7bSml29623
33986f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
33996f45ec7bSml29623 "==> nxge_map_rxdma_channel_cfg_ring"));
34006f45ec7bSml29623
34016f45ec7bSml29623 cntl_dmap = *dma_cntl_p;
34026f45ec7bSml29623
34036f45ec7bSml29623 /* Map in the receive block ring */
34046f45ec7bSml29623 rbrp = *rbr_p;
34056f45ec7bSml29623 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc;
34066f45ec7bSml29623 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4);
34076f45ec7bSml29623 /*
34086f45ec7bSml29623 * Zero out buffer block ring descriptors.
34096f45ec7bSml29623 */
34106f45ec7bSml29623 bzero((caddr_t)dmap->kaddrp, dmap->alength);
34116f45ec7bSml29623
34126f45ec7bSml29623 rcfga_p = &(rbrp->rbr_cfga);
34136f45ec7bSml29623 rcfgb_p = &(rbrp->rbr_cfgb);
34146f45ec7bSml29623 kick_p = &(rbrp->rbr_kick);
34156f45ec7bSml29623 rcfga_p->value = 0;
34166f45ec7bSml29623 rcfgb_p->value = 0;
34176f45ec7bSml29623 kick_p->value = 0;
34186f45ec7bSml29623 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress;
34196f45ec7bSml29623 rcfga_p->value = (rbrp->rbr_addr &
34206f45ec7bSml29623 (RBR_CFIG_A_STDADDR_MASK |
34216f45ec7bSml29623 RBR_CFIG_A_STDADDR_BASE_MASK));
34226f45ec7bSml29623 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT);
34236f45ec7bSml29623
34246f45ec7bSml29623 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0;
34256f45ec7bSml29623 rcfgb_p->bits.ldw.vld0 = 1;
34266f45ec7bSml29623 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1;
34276f45ec7bSml29623 rcfgb_p->bits.ldw.vld1 = 1;
34286f45ec7bSml29623 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2;
34296f45ec7bSml29623 rcfgb_p->bits.ldw.vld2 = 1;
34306f45ec7bSml29623 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code;
34316f45ec7bSml29623
34326f45ec7bSml29623 /*
34336f45ec7bSml29623 * For each buffer block, enter receive block address to the ring.
34346f45ec7bSml29623 */
34356f45ec7bSml29623 rbr_vaddrp = (uint32_t *)dmap->kaddrp;
34366f45ec7bSml29623 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp;
34376f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
34386f45ec7bSml29623 "==> nxge_map_rxdma_channel_cfg_ring: channel %d "
34396f45ec7bSml29623 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp));
34406f45ec7bSml29623
34416f45ec7bSml29623 rx_msg_ring = rbrp->rx_msg_ring;
34426f45ec7bSml29623 for (i = 0; i < rbrp->tnblocks; i++) {
34436f45ec7bSml29623 rx_msg_p = rx_msg_ring[i];
34446f45ec7bSml29623 rx_msg_p->nxgep = nxgep;
34456f45ec7bSml29623 rx_msg_p->rx_rbr_p = rbrp;
34466f45ec7bSml29623 bkaddr = (uint32_t)
34476f45ec7bSml29623 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress
34486f45ec7bSml29623 >> RBR_BKADDR_SHIFT));
34496f45ec7bSml29623 rx_msg_p->free = B_FALSE;
34506f45ec7bSml29623 rx_msg_p->max_usage_cnt = 0xbaddcafe;
34516f45ec7bSml29623
34526f45ec7bSml29623 *rbr_vaddrp++ = bkaddr;
34536f45ec7bSml29623 }
34546f45ec7bSml29623
34556f45ec7bSml29623 kick_p->bits.ldw.bkadd = rbrp->rbb_max;
34566f45ec7bSml29623 rbrp->rbr_wr_index = (rbrp->rbb_max - 1);
34576f45ec7bSml29623
34586f45ec7bSml29623 rbrp->rbr_rd_index = 0;
34596f45ec7bSml29623
34606f45ec7bSml29623 rbrp->rbr_consumed = 0;
34616f45ec7bSml29623 rbrp->rbr_use_bcopy = B_TRUE;
34626f45ec7bSml29623 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0;
34636f45ec7bSml29623 /*
34646f45ec7bSml29623 * Do bcopy on packets greater than bcopy size once
34656f45ec7bSml29623 * the lo threshold is reached.
34666f45ec7bSml29623 * This lo threshold should be less than the hi threshold.
34676f45ec7bSml29623 *
34686f45ec7bSml29623 * Do bcopy on every packet once the hi threshold is reached.
34696f45ec7bSml29623 */
34706f45ec7bSml29623 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) {
34716f45ec7bSml29623 /* default it to use hi */
34726f45ec7bSml29623 nxge_rx_threshold_lo = nxge_rx_threshold_hi;
34736f45ec7bSml29623 }
34746f45ec7bSml29623
34756f45ec7bSml29623 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) {
34766f45ec7bSml29623 nxge_rx_buf_size_type = NXGE_RBR_TYPE2;
34776f45ec7bSml29623 }
34786f45ec7bSml29623 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type;
34796f45ec7bSml29623
34806f45ec7bSml29623 switch (nxge_rx_threshold_hi) {
34816f45ec7bSml29623 default:
34826f45ec7bSml29623 case NXGE_RX_COPY_NONE:
34836f45ec7bSml29623 /* Do not do bcopy at all */
34846f45ec7bSml29623 rbrp->rbr_use_bcopy = B_FALSE;
34856f45ec7bSml29623 rbrp->rbr_threshold_hi = rbrp->rbb_max;
34866f45ec7bSml29623 break;
34876f45ec7bSml29623
34886f45ec7bSml29623 case NXGE_RX_COPY_1:
34896f45ec7bSml29623 case NXGE_RX_COPY_2:
34906f45ec7bSml29623 case NXGE_RX_COPY_3:
34916f45ec7bSml29623 case NXGE_RX_COPY_4:
34926f45ec7bSml29623 case NXGE_RX_COPY_5:
34936f45ec7bSml29623 case NXGE_RX_COPY_6:
34946f45ec7bSml29623 case NXGE_RX_COPY_7:
34956f45ec7bSml29623 rbrp->rbr_threshold_hi =
34966f45ec7bSml29623 rbrp->rbb_max *
34976f45ec7bSml29623 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE;
34986f45ec7bSml29623 break;
34996f45ec7bSml29623
35006f45ec7bSml29623 case NXGE_RX_COPY_ALL:
35016f45ec7bSml29623 rbrp->rbr_threshold_hi = 0;
35026f45ec7bSml29623 break;
35036f45ec7bSml29623 }
35046f45ec7bSml29623
35056f45ec7bSml29623 switch (nxge_rx_threshold_lo) {
35066f45ec7bSml29623 default:
35076f45ec7bSml29623 case NXGE_RX_COPY_NONE:
35086f45ec7bSml29623 /* Do not do bcopy at all */
35096f45ec7bSml29623 if (rbrp->rbr_use_bcopy) {
35106f45ec7bSml29623 rbrp->rbr_use_bcopy = B_FALSE;
35116f45ec7bSml29623 }
35126f45ec7bSml29623 rbrp->rbr_threshold_lo = rbrp->rbb_max;
35136f45ec7bSml29623 break;
35146f45ec7bSml29623
35156f45ec7bSml29623 case NXGE_RX_COPY_1:
35166f45ec7bSml29623 case NXGE_RX_COPY_2:
35176f45ec7bSml29623 case NXGE_RX_COPY_3:
35186f45ec7bSml29623 case NXGE_RX_COPY_4:
35196f45ec7bSml29623 case NXGE_RX_COPY_5:
35206f45ec7bSml29623 case NXGE_RX_COPY_6:
35216f45ec7bSml29623 case NXGE_RX_COPY_7:
35226f45ec7bSml29623 rbrp->rbr_threshold_lo =
35236f45ec7bSml29623 rbrp->rbb_max *
35246f45ec7bSml29623 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE;
35256f45ec7bSml29623 break;
35266f45ec7bSml29623
35276f45ec7bSml29623 case NXGE_RX_COPY_ALL:
35286f45ec7bSml29623 rbrp->rbr_threshold_lo = 0;
35296f45ec7bSml29623 break;
35306f45ec7bSml29623 }
35316f45ec7bSml29623
35326f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
35336f45ec7bSml29623 "nxge_map_rxdma_channel_cfg_ring: channel %d "
35346f45ec7bSml29623 "rbb_max %d "
35356f45ec7bSml29623 "rbrp->rbr_bufsize_type %d "
35366f45ec7bSml29623 "rbb_threshold_hi %d "
35376f45ec7bSml29623 "rbb_threshold_lo %d",
35386f45ec7bSml29623 dma_channel,
35396f45ec7bSml29623 rbrp->rbb_max,
35406f45ec7bSml29623 rbrp->rbr_bufsize_type,
35416f45ec7bSml29623 rbrp->rbr_threshold_hi,
35426f45ec7bSml29623 rbrp->rbr_threshold_lo));
35436f45ec7bSml29623
35446f45ec7bSml29623 rbrp->page_valid.value = 0;
35456f45ec7bSml29623 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0;
35466f45ec7bSml29623 rbrp->page_value_1.value = rbrp->page_value_2.value = 0;
35476f45ec7bSml29623 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0;
35486f45ec7bSml29623 rbrp->page_hdl.value = 0;
35496f45ec7bSml29623
35506f45ec7bSml29623 rbrp->page_valid.bits.ldw.page0 = 1;
35516f45ec7bSml29623 rbrp->page_valid.bits.ldw.page1 = 1;
35526f45ec7bSml29623
35536f45ec7bSml29623 /* Map in the receive completion ring */
35546f45ec7bSml29623 rcrp = (p_rx_rcr_ring_t)
35556f45ec7bSml29623 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP);
35566f45ec7bSml29623 rcrp->rdc = dma_channel;
35576f45ec7bSml29623
35586f45ec7bSml29623 nxge_port_rcr_size = nxgep->nxge_port_rcr_size;
35596f45ec7bSml29623 rcrp->comp_size = nxge_port_rcr_size;
35606f45ec7bSml29623 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1;
35616f45ec7bSml29623
35626f45ec7bSml29623 rcrp->max_receive_pkts = nxge_max_rx_pkts;
35636f45ec7bSml29623
35646f45ec7bSml29623 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
35656f45ec7bSml29623 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size,
35666f45ec7bSml29623 sizeof (rcr_entry_t));
35676f45ec7bSml29623 rcrp->comp_rd_index = 0;
35686f45ec7bSml29623 rcrp->comp_wt_index = 0;
35696f45ec7bSml29623 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
35706f45ec7bSml29623 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
357152ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
35726f45ec7bSml29623 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
35736f45ec7bSml29623
35746f45ec7bSml29623 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
35756f45ec7bSml29623 (nxge_port_rcr_size - 1);
35766f45ec7bSml29623 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
35776f45ec7bSml29623 (nxge_port_rcr_size - 1);
35786f45ec7bSml29623
35796f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
35806f45ec7bSml29623 "==> nxge_map_rxdma_channel_cfg_ring: "
35816f45ec7bSml29623 "channel %d "
35826f45ec7bSml29623 "rbr_vaddrp $%p "
35836f45ec7bSml29623 "rcr_desc_rd_head_p $%p "
35846f45ec7bSml29623 "rcr_desc_rd_head_pp $%p "
35856f45ec7bSml29623 "rcr_desc_rd_last_p $%p "
35866f45ec7bSml29623 "rcr_desc_rd_last_pp $%p ",
35876f45ec7bSml29623 dma_channel,
35886f45ec7bSml29623 rbr_vaddrp,
35896f45ec7bSml29623 rcrp->rcr_desc_rd_head_p,
35906f45ec7bSml29623 rcrp->rcr_desc_rd_head_pp,
35916f45ec7bSml29623 rcrp->rcr_desc_last_p,
35926f45ec7bSml29623 rcrp->rcr_desc_last_pp));
35936f45ec7bSml29623
35946f45ec7bSml29623 /*
35956f45ec7bSml29623 * Zero out buffer block ring descriptors.
35966f45ec7bSml29623 */
35976f45ec7bSml29623 bzero((caddr_t)dmap->kaddrp, dmap->alength);
35987b26d9ffSSantwona Behera
35997b26d9ffSSantwona Behera rcrp->intr_timeout = (nxgep->intr_timeout <
36007b26d9ffSSantwona Behera NXGE_RDC_RCR_TIMEOUT_MIN) ? NXGE_RDC_RCR_TIMEOUT_MIN :
36017b26d9ffSSantwona Behera nxgep->intr_timeout;
36027b26d9ffSSantwona Behera
36037b26d9ffSSantwona Behera rcrp->intr_threshold = (nxgep->intr_threshold <
36047b26d9ffSSantwona Behera NXGE_RDC_RCR_THRESHOLD_MIN) ? NXGE_RDC_RCR_THRESHOLD_MIN :
36057b26d9ffSSantwona Behera nxgep->intr_threshold;
36067b26d9ffSSantwona Behera
36076f45ec7bSml29623 rcrp->full_hdr_flag = B_FALSE;
36084df55fdeSJanie Lu
36094df55fdeSJanie Lu rcrp->sw_priv_hdr_len = nxge_rdc_buf_offset;
36104df55fdeSJanie Lu
36116f45ec7bSml29623
36126f45ec7bSml29623 cfga_p = &(rcrp->rcr_cfga);
36136f45ec7bSml29623 cfgb_p = &(rcrp->rcr_cfgb);
36146f45ec7bSml29623 cfga_p->value = 0;
36156f45ec7bSml29623 cfgb_p->value = 0;
36166f45ec7bSml29623 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress;
36176f45ec7bSml29623 cfga_p->value = (rcrp->rcr_addr &
36186f45ec7bSml29623 (RCRCFIG_A_STADDR_MASK |
36196f45ec7bSml29623 RCRCFIG_A_STADDR_BASE_MASK));
36206f45ec7bSml29623
36216f45ec7bSml29623 rcfga_p->value |= ((uint64_t)rcrp->comp_size <<
36226f45ec7bSml29623 RCRCFIG_A_LEN_SHIF);
36236f45ec7bSml29623
36246f45ec7bSml29623 /*
36256f45ec7bSml29623 * Timeout should be set based on the system clock divider.
36267b26d9ffSSantwona Behera * A timeout value of 1 assumes that the
36276f45ec7bSml29623 * granularity (1000) is 3 microseconds running at 300MHz.
36286f45ec7bSml29623 */
36296f45ec7bSml29623 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold;
36306f45ec7bSml29623 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout;
36316f45ec7bSml29623 cfgb_p->bits.ldw.entout = 1;
36326f45ec7bSml29623
36336f45ec7bSml29623 /* Map in the mailbox */
36346f45ec7bSml29623 mboxp = (p_rx_mbox_t)
36356f45ec7bSml29623 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP);
36366f45ec7bSml29623 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox;
36376f45ec7bSml29623 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t));
36386f45ec7bSml29623 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1;
36396f45ec7bSml29623 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2;
36406f45ec7bSml29623 cfig1_p->value = cfig2_p->value = 0;
36416f45ec7bSml29623
36426f45ec7bSml29623 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress;
36436f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
36446f45ec7bSml29623 "==> nxge_map_rxdma_channel_cfg_ring: "
36456f45ec7bSml29623 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx",
36466f45ec7bSml29623 dma_channel, cfig1_p->value, cfig2_p->value,
36476f45ec7bSml29623 mboxp->mbox_addr));
36486f45ec7bSml29623
36496f45ec7bSml29623 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32
36506f45ec7bSml29623 & 0xfff);
36516f45ec7bSml29623 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp;
36526f45ec7bSml29623
36536f45ec7bSml29623
36546f45ec7bSml29623 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff);
36556f45ec7bSml29623 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress &
36566f45ec7bSml29623 RXDMA_CFIG2_MBADDR_L_MASK);
36576f45ec7bSml29623
36586f45ec7bSml29623 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT);
36596f45ec7bSml29623
36606f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
36616f45ec7bSml29623 "==> nxge_map_rxdma_channel_cfg_ring: "
36626f45ec7bSml29623 "channel %d damaddrp $%p "
36636f45ec7bSml29623 "cfg1 0x%016llx cfig2 0x%016llx",
36646f45ec7bSml29623 dma_channel, dmaaddrp,
36656f45ec7bSml29623 cfig1_p->value, cfig2_p->value));
36666f45ec7bSml29623
36676f45ec7bSml29623 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag;
36684df55fdeSJanie Lu if (nxgep->niu_hw_type == NIU_HW_TYPE_RF) {
36694df55fdeSJanie Lu switch (rcrp->sw_priv_hdr_len) {
36704df55fdeSJanie Lu case SW_OFFSET_NO_OFFSET:
36714df55fdeSJanie Lu case SW_OFFSET_64:
36724df55fdeSJanie Lu case SW_OFFSET_128:
36734df55fdeSJanie Lu case SW_OFFSET_192:
36744df55fdeSJanie Lu cfig2_p->bits.ldw.offset =
36754df55fdeSJanie Lu rcrp->sw_priv_hdr_len;
36764df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 0;
36774df55fdeSJanie Lu break;
36784df55fdeSJanie Lu case SW_OFFSET_256:
36794df55fdeSJanie Lu case SW_OFFSET_320:
36804df55fdeSJanie Lu case SW_OFFSET_384:
36814df55fdeSJanie Lu case SW_OFFSET_448:
36824df55fdeSJanie Lu cfig2_p->bits.ldw.offset =
36834df55fdeSJanie Lu rcrp->sw_priv_hdr_len & 0x3;
36844df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 1;
36854df55fdeSJanie Lu break;
36864df55fdeSJanie Lu default:
36874df55fdeSJanie Lu cfig2_p->bits.ldw.offset = SW_OFFSET_NO_OFFSET;
36884df55fdeSJanie Lu cfig2_p->bits.ldw.offset256 = 0;
36894df55fdeSJanie Lu }
36904df55fdeSJanie Lu } else {
36916f45ec7bSml29623 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len;
36924df55fdeSJanie Lu }
36936f45ec7bSml29623
36946f45ec7bSml29623 rbrp->rx_rcr_p = rcrp;
36956f45ec7bSml29623 rcrp->rx_rbr_p = rbrp;
36966f45ec7bSml29623 *rcr_p = rcrp;
36976f45ec7bSml29623 *rx_mbox_p = mboxp;
36986f45ec7bSml29623
36996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37006f45ec7bSml29623 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status));
37016f45ec7bSml29623
37026f45ec7bSml29623 return (status);
37036f45ec7bSml29623 }
37046f45ec7bSml29623
37056f45ec7bSml29623 /*ARGSUSED*/
37066f45ec7bSml29623 static void
nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t rx_mbox_p)37076f45ec7bSml29623 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep,
37086f45ec7bSml29623 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p)
37096f45ec7bSml29623 {
37106f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37116f45ec7bSml29623 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d",
37126f45ec7bSml29623 rcr_p->rdc));
37136f45ec7bSml29623
37146f45ec7bSml29623 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t));
37156f45ec7bSml29623 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t));
37166f45ec7bSml29623
37176f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37186f45ec7bSml29623 "<== nxge_unmap_rxdma_channel_cfg_ring"));
37196f45ec7bSml29623 }
37206f45ec7bSml29623
37216f45ec7bSml29623 static nxge_status_t
nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep,uint16_t channel,p_nxge_dma_common_t * dma_buf_p,p_rx_rbr_ring_t * rbr_p,uint32_t num_chunks)37226f45ec7bSml29623 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel,
37236f45ec7bSml29623 p_nxge_dma_common_t *dma_buf_p,
37246f45ec7bSml29623 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks)
37256f45ec7bSml29623 {
37266f45ec7bSml29623 p_rx_rbr_ring_t rbrp;
37276f45ec7bSml29623 p_nxge_dma_common_t dma_bufp, tmp_bufp;
37286f45ec7bSml29623 p_rx_msg_t *rx_msg_ring;
37296f45ec7bSml29623 p_rx_msg_t rx_msg_p;
37306f45ec7bSml29623 p_mblk_t mblk_p;
37316f45ec7bSml29623
37326f45ec7bSml29623 rxring_info_t *ring_info;
37336f45ec7bSml29623 nxge_status_t status = NXGE_OK;
37346f45ec7bSml29623 int i, j, index;
37356f45ec7bSml29623 uint32_t size, bsize, nblocks, nmsgs;
37366f45ec7bSml29623
37376f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37386f45ec7bSml29623 "==> nxge_map_rxdma_channel_buf_ring: channel %d",
37396f45ec7bSml29623 channel));
37406f45ec7bSml29623
37416f45ec7bSml29623 dma_bufp = tmp_bufp = *dma_buf_p;
37426f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37436f45ec7bSml29623 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d "
37446f45ec7bSml29623 "chunks bufp 0x%016llx",
37456f45ec7bSml29623 channel, num_chunks, dma_bufp));
37466f45ec7bSml29623
37476f45ec7bSml29623 nmsgs = 0;
37486f45ec7bSml29623 for (i = 0; i < num_chunks; i++, tmp_bufp++) {
37496f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
37506f45ec7bSml29623 "==> nxge_map_rxdma_channel_buf_ring: channel %d "
37516f45ec7bSml29623 "bufp 0x%016llx nblocks %d nmsgs %d",
37526f45ec7bSml29623 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs));
37536f45ec7bSml29623 nmsgs += tmp_bufp->nblocks;
37546f45ec7bSml29623 }
37556f45ec7bSml29623 if (!nmsgs) {
375656d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
37576f45ec7bSml29623 "<== nxge_map_rxdma_channel_buf_ring: channel %d "
37586f45ec7bSml29623 "no msg blocks",
37596f45ec7bSml29623 channel));
37606f45ec7bSml29623 status = NXGE_ERROR;
37616f45ec7bSml29623 goto nxge_map_rxdma_channel_buf_ring_exit;
37626f45ec7bSml29623 }
37636f45ec7bSml29623
3764007969e0Stm144005 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP);
37656f45ec7bSml29623
37666f45ec7bSml29623 size = nmsgs * sizeof (p_rx_msg_t);
37676f45ec7bSml29623 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP);
37686f45ec7bSml29623 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t),
37696f45ec7bSml29623 KM_SLEEP);
37706f45ec7bSml29623
37716f45ec7bSml29623 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER,
37726f45ec7bSml29623 (void *)nxgep->interrupt_cookie);
37736f45ec7bSml29623 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER,
37746f45ec7bSml29623 (void *)nxgep->interrupt_cookie);
37756f45ec7bSml29623 rbrp->rdc = channel;
37766f45ec7bSml29623 rbrp->num_blocks = num_chunks;
37776f45ec7bSml29623 rbrp->tnblocks = nmsgs;
37786f45ec7bSml29623 rbrp->rbb_max = nmsgs;
37796f45ec7bSml29623 rbrp->rbr_max_size = nmsgs;
37806f45ec7bSml29623 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1);
37816f45ec7bSml29623
37826f45ec7bSml29623 /*
37836f45ec7bSml29623 * Buffer sizes suggested by NIU architect.
37846f45ec7bSml29623 * 256, 512 and 2K.
37856f45ec7bSml29623 */
37866f45ec7bSml29623
37876f45ec7bSml29623 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B;
37886f45ec7bSml29623 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES;
37896f45ec7bSml29623 rbrp->npi_pkt_buf_size0 = SIZE_256B;
37906f45ec7bSml29623
37916f45ec7bSml29623 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K;
37926f45ec7bSml29623 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES;
37936f45ec7bSml29623 rbrp->npi_pkt_buf_size1 = SIZE_1KB;
37946f45ec7bSml29623
37956f45ec7bSml29623 rbrp->block_size = nxgep->rx_default_block_size;
37966f45ec7bSml29623
379748056c53SMichael Speer if (!nxgep->mac.is_jumbo) {
37986f45ec7bSml29623 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K;
37996f45ec7bSml29623 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES;
38006f45ec7bSml29623 rbrp->npi_pkt_buf_size2 = SIZE_2KB;
38016f45ec7bSml29623 } else {
38026f45ec7bSml29623 if (rbrp->block_size >= 0x2000) {
38036f45ec7bSml29623 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K;
38046f45ec7bSml29623 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES;
38056f45ec7bSml29623 rbrp->npi_pkt_buf_size2 = SIZE_8KB;
38066f45ec7bSml29623 } else {
38076f45ec7bSml29623 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K;
38086f45ec7bSml29623 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES;
38096f45ec7bSml29623 rbrp->npi_pkt_buf_size2 = SIZE_4KB;
38106f45ec7bSml29623 }
38116f45ec7bSml29623 }
38126f45ec7bSml29623
38136f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
38146f45ec7bSml29623 "==> nxge_map_rxdma_channel_buf_ring: channel %d "
38156f45ec7bSml29623 "actual rbr max %d rbb_max %d nmsgs %d "
38166f45ec7bSml29623 "rbrp->block_size %d default_block_size %d "
38176f45ec7bSml29623 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)",
38186f45ec7bSml29623 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs,
38196f45ec7bSml29623 rbrp->block_size, nxgep->rx_default_block_size,
38206f45ec7bSml29623 nxge_rbr_size, nxge_rbr_spare_size));
38216f45ec7bSml29623
38226f45ec7bSml29623 /* Map in buffers from the buffer pool. */
38236f45ec7bSml29623 index = 0;
38246f45ec7bSml29623 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) {
38256f45ec7bSml29623 bsize = dma_bufp->block_size;
38266f45ec7bSml29623 nblocks = dma_bufp->nblocks;
38276f45ec7bSml29623 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp;
38286f45ec7bSml29623 ring_info->buffer[i].buf_index = i;
38296f45ec7bSml29623 ring_info->buffer[i].buf_size = dma_bufp->alength;
38306f45ec7bSml29623 ring_info->buffer[i].start_index = index;
38316f45ec7bSml29623 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp;
38326f45ec7bSml29623
38336f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
38346f45ec7bSml29623 " nxge_map_rxdma_channel_buf_ring: map channel %d "
38356f45ec7bSml29623 "chunk %d"
38366f45ec7bSml29623 " nblocks %d chunk_size %x block_size 0x%x "
38376f45ec7bSml29623 "dma_bufp $%p", channel, i,
38386f45ec7bSml29623 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize,
38396f45ec7bSml29623 dma_bufp));
38406f45ec7bSml29623
38416f45ec7bSml29623 for (j = 0; j < nblocks; j++) {
38426f45ec7bSml29623 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO,
38436f45ec7bSml29623 dma_bufp)) == NULL) {
384456d930aeSspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
384556d930aeSspeer "allocb failed (index %d i %d j %d)",
384656d930aeSspeer index, i, j));
384756d930aeSspeer goto nxge_map_rxdma_channel_buf_ring_fail1;
38486f45ec7bSml29623 }
38496f45ec7bSml29623 rx_msg_ring[index] = rx_msg_p;
38506f45ec7bSml29623 rx_msg_p->block_index = index;
38516f45ec7bSml29623 rx_msg_p->shifted_addr = (uint32_t)
38526f45ec7bSml29623 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >>
38536f45ec7bSml29623 RBR_BKADDR_SHIFT));
38546f45ec7bSml29623
38556f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
385656d930aeSspeer "index %d j %d rx_msg_p $%p mblk %p",
385756d930aeSspeer index, j, rx_msg_p, rx_msg_p->rx_mblk_p));
38586f45ec7bSml29623
38596f45ec7bSml29623 mblk_p = rx_msg_p->rx_mblk_p;
38606f45ec7bSml29623 mblk_p->b_wptr = mblk_p->b_rptr + bsize;
3861007969e0Stm144005
3862007969e0Stm144005 rbrp->rbr_ref_cnt++;
38636f45ec7bSml29623 index++;
38646f45ec7bSml29623 rx_msg_p->buf_dma.dma_channel = channel;
38656f45ec7bSml29623 }
3866678453a8Sspeer
3867678453a8Sspeer rbrp->rbr_alloc_type = DDI_MEM_ALLOC;
3868678453a8Sspeer if (dma_bufp->contig_alloc_type) {
3869678453a8Sspeer rbrp->rbr_alloc_type = CONTIG_MEM_ALLOC;
3870678453a8Sspeer }
3871678453a8Sspeer
3872678453a8Sspeer if (dma_bufp->kmem_alloc_type) {
3873678453a8Sspeer rbrp->rbr_alloc_type = KMEM_ALLOC;
3874678453a8Sspeer }
3875678453a8Sspeer
3876678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
3877678453a8Sspeer " nxge_map_rxdma_channel_buf_ring: map channel %d "
3878678453a8Sspeer "chunk %d"
3879678453a8Sspeer " nblocks %d chunk_size %x block_size 0x%x "
3880678453a8Sspeer "dma_bufp $%p",
3881678453a8Sspeer channel, i,
3882678453a8Sspeer dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize,
3883678453a8Sspeer dma_bufp));
38846f45ec7bSml29623 }
38856f45ec7bSml29623 if (i < rbrp->num_blocks) {
38866f45ec7bSml29623 goto nxge_map_rxdma_channel_buf_ring_fail1;
38876f45ec7bSml29623 }
38886f45ec7bSml29623
38896f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
38906f45ec7bSml29623 "nxge_map_rxdma_channel_buf_ring: done buf init "
38916f45ec7bSml29623 "channel %d msg block entries %d",
38926f45ec7bSml29623 channel, index));
38936f45ec7bSml29623 ring_info->block_size_mask = bsize - 1;
38946f45ec7bSml29623 rbrp->rx_msg_ring = rx_msg_ring;
38956f45ec7bSml29623 rbrp->dma_bufp = dma_buf_p;
38966f45ec7bSml29623 rbrp->ring_info = ring_info;
38976f45ec7bSml29623
38986f45ec7bSml29623 status = nxge_rxbuf_index_info_init(nxgep, rbrp);
38996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39006f45ec7bSml29623 " nxge_map_rxdma_channel_buf_ring: "
39016f45ec7bSml29623 "channel %d done buf info init", channel));
39026f45ec7bSml29623
3903007969e0Stm144005 /*
3904007969e0Stm144005 * Finally, permit nxge_freeb() to call nxge_post_page().
3905007969e0Stm144005 */
3906007969e0Stm144005 rbrp->rbr_state = RBR_POSTING;
3907007969e0Stm144005
39086f45ec7bSml29623 *rbr_p = rbrp;
39096f45ec7bSml29623 goto nxge_map_rxdma_channel_buf_ring_exit;
39106f45ec7bSml29623
39116f45ec7bSml29623 nxge_map_rxdma_channel_buf_ring_fail1:
39126f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39136f45ec7bSml29623 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)",
39146f45ec7bSml29623 channel, status));
39156f45ec7bSml29623
39166f45ec7bSml29623 index--;
39176f45ec7bSml29623 for (; index >= 0; index--) {
39186f45ec7bSml29623 rx_msg_p = rx_msg_ring[index];
39196f45ec7bSml29623 if (rx_msg_p != NULL) {
39206f45ec7bSml29623 freeb(rx_msg_p->rx_mblk_p);
39216f45ec7bSml29623 rx_msg_ring[index] = NULL;
39226f45ec7bSml29623 }
39236f45ec7bSml29623 }
39246f45ec7bSml29623 nxge_map_rxdma_channel_buf_ring_fail:
39256f45ec7bSml29623 MUTEX_DESTROY(&rbrp->post_lock);
39266f45ec7bSml29623 MUTEX_DESTROY(&rbrp->lock);
39276f45ec7bSml29623 KMEM_FREE(ring_info, sizeof (rxring_info_t));
39286f45ec7bSml29623 KMEM_FREE(rx_msg_ring, size);
39296f45ec7bSml29623 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t));
39306f45ec7bSml29623
393156d930aeSspeer status = NXGE_ERROR;
393256d930aeSspeer
39336f45ec7bSml29623 nxge_map_rxdma_channel_buf_ring_exit:
39346f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39356f45ec7bSml29623 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status));
39366f45ec7bSml29623
39376f45ec7bSml29623 return (status);
39386f45ec7bSml29623 }
39396f45ec7bSml29623
39406f45ec7bSml29623 /*ARGSUSED*/
39416f45ec7bSml29623 static void
nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep,p_rx_rbr_ring_t rbr_p)39426f45ec7bSml29623 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep,
39436f45ec7bSml29623 p_rx_rbr_ring_t rbr_p)
39446f45ec7bSml29623 {
39456f45ec7bSml29623 p_rx_msg_t *rx_msg_ring;
39466f45ec7bSml29623 p_rx_msg_t rx_msg_p;
39476f45ec7bSml29623 rxring_info_t *ring_info;
39486f45ec7bSml29623 int i;
39496f45ec7bSml29623 uint32_t size;
39506f45ec7bSml29623 #ifdef NXGE_DEBUG
39516f45ec7bSml29623 int num_chunks;
39526f45ec7bSml29623 #endif
39536f45ec7bSml29623
39546f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39556f45ec7bSml29623 "==> nxge_unmap_rxdma_channel_buf_ring"));
39566f45ec7bSml29623 if (rbr_p == NULL) {
39576f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
39586f45ec7bSml29623 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp"));
39596f45ec7bSml29623 return;
39606f45ec7bSml29623 }
39616f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39626f45ec7bSml29623 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d",
39636f45ec7bSml29623 rbr_p->rdc));
39646f45ec7bSml29623
39656f45ec7bSml29623 rx_msg_ring = rbr_p->rx_msg_ring;
39666f45ec7bSml29623 ring_info = rbr_p->ring_info;
39676f45ec7bSml29623
39686f45ec7bSml29623 if (rx_msg_ring == NULL || ring_info == NULL) {
39696f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39706f45ec7bSml29623 "<== nxge_unmap_rxdma_channel_buf_ring: "
39716f45ec7bSml29623 "rx_msg_ring $%p ring_info $%p",
39726f45ec7bSml29623 rx_msg_p, ring_info));
39736f45ec7bSml29623 return;
39746f45ec7bSml29623 }
39756f45ec7bSml29623
39766f45ec7bSml29623 #ifdef NXGE_DEBUG
39776f45ec7bSml29623 num_chunks = rbr_p->num_blocks;
39786f45ec7bSml29623 #endif
39796f45ec7bSml29623 size = rbr_p->tnblocks * sizeof (p_rx_msg_t);
39806f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39816f45ec7bSml29623 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d "
39826f45ec7bSml29623 "tnblocks %d (max %d) size ptrs %d ",
39836f45ec7bSml29623 rbr_p->rdc, num_chunks,
39846f45ec7bSml29623 rbr_p->tnblocks, rbr_p->rbr_max_size, size));
39856f45ec7bSml29623
39866f45ec7bSml29623 for (i = 0; i < rbr_p->tnblocks; i++) {
39876f45ec7bSml29623 rx_msg_p = rx_msg_ring[i];
39886f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
39896f45ec7bSml29623 " nxge_unmap_rxdma_channel_buf_ring: "
39906f45ec7bSml29623 "rx_msg_p $%p",
39916f45ec7bSml29623 rx_msg_p));
39926f45ec7bSml29623 if (rx_msg_p != NULL) {
39936f45ec7bSml29623 freeb(rx_msg_p->rx_mblk_p);
39946f45ec7bSml29623 rx_msg_ring[i] = NULL;
39956f45ec7bSml29623 }
39966f45ec7bSml29623 }
39976f45ec7bSml29623
3998007969e0Stm144005 /*
3999007969e0Stm144005 * We no longer may use the mutex <post_lock>. By setting
4000007969e0Stm144005 * <rbr_state> to anything but POSTING, we prevent
4001007969e0Stm144005 * nxge_post_page() from accessing a dead mutex.
4002007969e0Stm144005 */
4003007969e0Stm144005 rbr_p->rbr_state = RBR_UNMAPPING;
40046f45ec7bSml29623 MUTEX_DESTROY(&rbr_p->post_lock);
4005007969e0Stm144005
40066f45ec7bSml29623 MUTEX_DESTROY(&rbr_p->lock);
4007007969e0Stm144005
4008007969e0Stm144005 if (rbr_p->rbr_ref_cnt == 0) {
4009678453a8Sspeer /*
4010678453a8Sspeer * This is the normal state of affairs.
4011678453a8Sspeer * Need to free the following buffers:
4012678453a8Sspeer * - data buffers
4013678453a8Sspeer * - rx_msg ring
4014678453a8Sspeer * - ring_info
4015678453a8Sspeer * - rbr ring
4016678453a8Sspeer */
4017678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL,
4018678453a8Sspeer "unmap_rxdma_buf_ring: No outstanding - freeing "));
4019678453a8Sspeer nxge_rxdma_databuf_free(rbr_p);
4020678453a8Sspeer KMEM_FREE(ring_info, sizeof (rxring_info_t));
4021678453a8Sspeer KMEM_FREE(rx_msg_ring, size);
4022007969e0Stm144005 KMEM_FREE(rbr_p, sizeof (*rbr_p));
4023007969e0Stm144005 } else {
4024007969e0Stm144005 /*
4025007969e0Stm144005 * Some of our buffers are still being used.
4026007969e0Stm144005 * Therefore, tell nxge_freeb() this ring is
4027007969e0Stm144005 * unmapped, so it may free <rbr_p> for us.
4028007969e0Stm144005 */
4029007969e0Stm144005 rbr_p->rbr_state = RBR_UNMAPPED;
4030007969e0Stm144005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4031007969e0Stm144005 "unmap_rxdma_buf_ring: %d %s outstanding.",
4032007969e0Stm144005 rbr_p->rbr_ref_cnt,
4033007969e0Stm144005 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs"));
4034007969e0Stm144005 }
40356f45ec7bSml29623
40366f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
40376f45ec7bSml29623 "<== nxge_unmap_rxdma_channel_buf_ring"));
40386f45ec7bSml29623 }
40396f45ec7bSml29623
4040678453a8Sspeer /*
4041678453a8Sspeer * nxge_rxdma_hw_start_common
4042678453a8Sspeer *
4043678453a8Sspeer * Arguments:
4044678453a8Sspeer * nxgep
4045678453a8Sspeer *
4046678453a8Sspeer * Notes:
4047678453a8Sspeer *
4048678453a8Sspeer * NPI/NXGE function calls:
4049678453a8Sspeer * nxge_init_fzc_rx_common();
4050678453a8Sspeer * nxge_init_fzc_rxdma_port();
4051678453a8Sspeer *
4052678453a8Sspeer * Registers accessed:
4053678453a8Sspeer *
4054678453a8Sspeer * Context:
4055678453a8Sspeer * Service domain
4056678453a8Sspeer */
40576f45ec7bSml29623 static nxge_status_t
nxge_rxdma_hw_start_common(p_nxge_t nxgep)40586f45ec7bSml29623 nxge_rxdma_hw_start_common(p_nxge_t nxgep)
40596f45ec7bSml29623 {
40606f45ec7bSml29623 nxge_status_t status = NXGE_OK;
40616f45ec7bSml29623
40626f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common"));
40636f45ec7bSml29623
40646f45ec7bSml29623 /*
40656f45ec7bSml29623 * Load the sharable parameters by writing to the
40666f45ec7bSml29623 * function zero control registers. These FZC registers
40676f45ec7bSml29623 * should be initialized only once for the entire chip.
40686f45ec7bSml29623 */
40696f45ec7bSml29623 (void) nxge_init_fzc_rx_common(nxgep);
40706f45ec7bSml29623
40716f45ec7bSml29623 /*
40726f45ec7bSml29623 * Initialize the RXDMA port specific FZC control configurations.
40736f45ec7bSml29623 * These FZC registers are pertaining to each port.
40746f45ec7bSml29623 */
40756f45ec7bSml29623 (void) nxge_init_fzc_rxdma_port(nxgep);
40766f45ec7bSml29623
40776f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common"));
40786f45ec7bSml29623
40796f45ec7bSml29623 return (status);
40806f45ec7bSml29623 }
40816f45ec7bSml29623
40826f45ec7bSml29623 static nxge_status_t
nxge_rxdma_hw_start(p_nxge_t nxgep,int channel)4083678453a8Sspeer nxge_rxdma_hw_start(p_nxge_t nxgep, int channel)
40846f45ec7bSml29623 {
40856f45ec7bSml29623 int i, ndmas;
40866f45ec7bSml29623 p_rx_rbr_rings_t rx_rbr_rings;
40876f45ec7bSml29623 p_rx_rbr_ring_t *rbr_rings;
40886f45ec7bSml29623 p_rx_rcr_rings_t rx_rcr_rings;
40896f45ec7bSml29623 p_rx_rcr_ring_t *rcr_rings;
40906f45ec7bSml29623 p_rx_mbox_areas_t rx_mbox_areas_p;
40916f45ec7bSml29623 p_rx_mbox_t *rx_mbox_p;
40926f45ec7bSml29623 nxge_status_t status = NXGE_OK;
40936f45ec7bSml29623
40946f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start"));
40956f45ec7bSml29623
40966f45ec7bSml29623 rx_rbr_rings = nxgep->rx_rbr_rings;
40976f45ec7bSml29623 rx_rcr_rings = nxgep->rx_rcr_rings;
40986f45ec7bSml29623 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) {
40996f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
41006f45ec7bSml29623 "<== nxge_rxdma_hw_start: NULL ring pointers"));
41016f45ec7bSml29623 return (NXGE_ERROR);
41026f45ec7bSml29623 }
41036f45ec7bSml29623 ndmas = rx_rbr_rings->ndmas;
41046f45ec7bSml29623 if (ndmas == 0) {
41056f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
41066f45ec7bSml29623 "<== nxge_rxdma_hw_start: no dma channel allocated"));
41076f45ec7bSml29623 return (NXGE_ERROR);
41086f45ec7bSml29623 }
41096f45ec7bSml29623
41106f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
41116f45ec7bSml29623 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas));
41126f45ec7bSml29623
41136f45ec7bSml29623 rbr_rings = rx_rbr_rings->rbr_rings;
41146f45ec7bSml29623 rcr_rings = rx_rcr_rings->rcr_rings;
41156f45ec7bSml29623 rx_mbox_areas_p = nxgep->rx_mbox_areas_p;
41166f45ec7bSml29623 if (rx_mbox_areas_p) {
41176f45ec7bSml29623 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas;
4118*e3d11eeeSToomas Soome } else {
4119*e3d11eeeSToomas Soome rx_mbox_p = NULL;
41206f45ec7bSml29623 }
41216f45ec7bSml29623
4122678453a8Sspeer i = channel;
41236f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
41246f45ec7bSml29623 "==> nxge_rxdma_hw_start (ndmas %d) channel %d",
41256f45ec7bSml29623 ndmas, channel));
41266f45ec7bSml29623 status = nxge_rxdma_start_channel(nxgep, channel,
41276f45ec7bSml29623 (p_rx_rbr_ring_t)rbr_rings[i],
41286f45ec7bSml29623 (p_rx_rcr_ring_t)rcr_rings[i],
41296f45ec7bSml29623 (p_rx_mbox_t)rx_mbox_p[i]);
41306f45ec7bSml29623 if (status != NXGE_OK) {
4131678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4132678453a8Sspeer "==> nxge_rxdma_hw_start: disable "
4133678453a8Sspeer "(status 0x%x channel %d)", status, channel));
4134678453a8Sspeer return (status);
41356f45ec7bSml29623 }
41366f45ec7bSml29623
41376f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: "
41386f45ec7bSml29623 "rx_rbr_rings 0x%016llx rings 0x%016llx",
41396f45ec7bSml29623 rx_rbr_rings, rx_rcr_rings));
41406f45ec7bSml29623
41416f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
41426f45ec7bSml29623 "==> nxge_rxdma_hw_start: (status 0x%x)", status));
41436f45ec7bSml29623
41446f45ec7bSml29623 return (status);
41456f45ec7bSml29623 }
41466f45ec7bSml29623
41476f45ec7bSml29623 static void
nxge_rxdma_hw_stop(p_nxge_t nxgep,int channel)4148678453a8Sspeer nxge_rxdma_hw_stop(p_nxge_t nxgep, int channel)
41496f45ec7bSml29623 {
41506f45ec7bSml29623 p_rx_rbr_rings_t rx_rbr_rings;
41516f45ec7bSml29623 p_rx_rcr_rings_t rx_rcr_rings;
41526f45ec7bSml29623
41536f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop"));
41546f45ec7bSml29623
41556f45ec7bSml29623 rx_rbr_rings = nxgep->rx_rbr_rings;
41566f45ec7bSml29623 rx_rcr_rings = nxgep->rx_rcr_rings;
41576f45ec7bSml29623 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) {
41586f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
41596f45ec7bSml29623 "<== nxge_rxdma_hw_stop: NULL ring pointers"));
41606f45ec7bSml29623 return;
41616f45ec7bSml29623 }
41626f45ec7bSml29623
41636f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4164678453a8Sspeer "==> nxge_rxdma_hw_stop(channel %d)",
4165678453a8Sspeer channel));
41666f45ec7bSml29623 (void) nxge_rxdma_stop_channel(nxgep, channel);
41676f45ec7bSml29623
41686f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: "
41696f45ec7bSml29623 "rx_rbr_rings 0x%016llx rings 0x%016llx",
41706f45ec7bSml29623 rx_rbr_rings, rx_rcr_rings));
41716f45ec7bSml29623
41726f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop"));
41736f45ec7bSml29623 }
41746f45ec7bSml29623
41756f45ec7bSml29623
41766f45ec7bSml29623 static nxge_status_t
nxge_rxdma_start_channel(p_nxge_t nxgep,uint16_t channel,p_rx_rbr_ring_t rbr_p,p_rx_rcr_ring_t rcr_p,p_rx_mbox_t mbox_p)41776f45ec7bSml29623 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel,
41786f45ec7bSml29623 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p)
41796f45ec7bSml29623 {
41806f45ec7bSml29623 npi_handle_t handle;
41816f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
41826f45ec7bSml29623 rx_dma_ctl_stat_t cs;
41836f45ec7bSml29623 rx_dma_ent_msk_t ent_mask;
41846f45ec7bSml29623 nxge_status_t status = NXGE_OK;
41856f45ec7bSml29623
41866f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel"));
41876f45ec7bSml29623
41886f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
41896f45ec7bSml29623
41906f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: "
41916f45ec7bSml29623 "npi handle addr $%p acc $%p",
41926f45ec7bSml29623 nxgep->npi_handle.regp, nxgep->npi_handle.regh));
41936f45ec7bSml29623
4194678453a8Sspeer /* Reset RXDMA channel, but not if you're a guest. */
4195678453a8Sspeer if (!isLDOMguest(nxgep)) {
41966f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_reset(handle, channel);
41976f45ec7bSml29623 if (rs != NPI_SUCCESS) {
41986f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4199678453a8Sspeer "==> nxge_init_fzc_rdc: "
4200678453a8Sspeer "npi_rxdma_cfg_rdc_reset(%d) returned 0x%08x",
4201678453a8Sspeer channel, rs));
42026f45ec7bSml29623 return (NXGE_ERROR | rs);
42036f45ec7bSml29623 }
42046f45ec7bSml29623
42056f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
42066f45ec7bSml29623 "==> nxge_rxdma_start_channel: reset done: channel %d",
42076f45ec7bSml29623 channel));
4208678453a8Sspeer }
4209678453a8Sspeer
4210678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
4211678453a8Sspeer if (isLDOMguest(nxgep))
4212678453a8Sspeer (void) nxge_rdc_lp_conf(nxgep, channel);
4213678453a8Sspeer #endif
42146f45ec7bSml29623
42156f45ec7bSml29623 /*
42166f45ec7bSml29623 * Initialize the RXDMA channel specific FZC control
42176f45ec7bSml29623 * configurations. These FZC registers are pertaining
42186f45ec7bSml29623 * to each RX channel (logical pages).
42196f45ec7bSml29623 */
4220678453a8Sspeer if (!isLDOMguest(nxgep)) {
4221678453a8Sspeer status = nxge_init_fzc_rxdma_channel(nxgep, channel);
42226f45ec7bSml29623 if (status != NXGE_OK) {
42236f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
42246f45ec7bSml29623 "==> nxge_rxdma_start_channel: "
42256f45ec7bSml29623 "init fzc rxdma failed (0x%08x channel %d)",
42266f45ec7bSml29623 status, channel));
42276f45ec7bSml29623 return (status);
42286f45ec7bSml29623 }
42296f45ec7bSml29623
42306f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
42316f45ec7bSml29623 "==> nxge_rxdma_start_channel: fzc done"));
4232678453a8Sspeer }
42336f45ec7bSml29623
42346f45ec7bSml29623 /* Set up the interrupt event masks. */
42356f45ec7bSml29623 ent_mask.value = 0;
42366f45ec7bSml29623 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK;
42376f45ec7bSml29623 rs = npi_rxdma_event_mask(handle, OP_SET, channel,
42386f45ec7bSml29623 &ent_mask);
42396f45ec7bSml29623 if (rs != NPI_SUCCESS) {
42406f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
42416f45ec7bSml29623 "==> nxge_rxdma_start_channel: "
4242678453a8Sspeer "init rxdma event masks failed "
4243678453a8Sspeer "(0x%08x channel %d)",
42446f45ec7bSml29623 status, channel));
42456f45ec7bSml29623 return (NXGE_ERROR | rs);
42466f45ec7bSml29623 }
42476f45ec7bSml29623
4248678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4249678453a8Sspeer "==> nxge_rxdma_start_channel: "
42506f45ec7bSml29623 "event done: channel %d (mask 0x%016llx)",
42516f45ec7bSml29623 channel, ent_mask.value));
42526f45ec7bSml29623
42536f45ec7bSml29623 /* Initialize the receive DMA control and status register */
42546f45ec7bSml29623 cs.value = 0;
42556f45ec7bSml29623 cs.bits.hdw.mex = 1;
42566f45ec7bSml29623 cs.bits.hdw.rcrthres = 1;
42576f45ec7bSml29623 cs.bits.hdw.rcrto = 1;
42586f45ec7bSml29623 cs.bits.hdw.rbr_empty = 1;
42596f45ec7bSml29623 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs);
42606f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
42616f45ec7bSml29623 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value));
42626f45ec7bSml29623 if (status != NXGE_OK) {
42636f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
42646f45ec7bSml29623 "==> nxge_rxdma_start_channel: "
42656f45ec7bSml29623 "init rxdma control register failed (0x%08x channel %d",
42666f45ec7bSml29623 status, channel));
42676f45ec7bSml29623 return (status);
42686f45ec7bSml29623 }
42696f45ec7bSml29623
42706f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
42716f45ec7bSml29623 "control done - channel %d cs 0x%016llx", channel, cs.value));
42726f45ec7bSml29623
42736f45ec7bSml29623 /*
42746f45ec7bSml29623 * Load RXDMA descriptors, buffers, mailbox,
42756f45ec7bSml29623 * initialise the receive DMA channels and
42766f45ec7bSml29623 * enable each DMA channel.
42776f45ec7bSml29623 */
42786f45ec7bSml29623 status = nxge_enable_rxdma_channel(nxgep,
42796f45ec7bSml29623 channel, rbr_p, rcr_p, mbox_p);
42806f45ec7bSml29623
42816f45ec7bSml29623 if (status != NXGE_OK) {
42826f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
42836f45ec7bSml29623 " nxge_rxdma_start_channel: "
4284678453a8Sspeer " enable rxdma failed (0x%08x channel %d)",
42856f45ec7bSml29623 status, channel));
42866f45ec7bSml29623 return (status);
42876f45ec7bSml29623 }
42886f45ec7bSml29623
4289678453a8Sspeer NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
4290678453a8Sspeer "==> nxge_rxdma_start_channel: enabled channel %d"));
4291678453a8Sspeer
4292678453a8Sspeer if (isLDOMguest(nxgep)) {
4293678453a8Sspeer /* Add interrupt handler for this channel. */
4294ef523517SMichael Speer status = nxge_hio_intr_add(nxgep, VP_BOUND_RX, channel);
4295ef523517SMichael Speer if (status != NXGE_OK) {
4296678453a8Sspeer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4297678453a8Sspeer " nxge_rxdma_start_channel: "
4298678453a8Sspeer " nxge_hio_intr_add failed (0x%08x channel %d)",
4299678453a8Sspeer status, channel));
4300ef523517SMichael Speer return (status);
4301678453a8Sspeer }
4302678453a8Sspeer }
4303678453a8Sspeer
43046f45ec7bSml29623 ent_mask.value = 0;
43056f45ec7bSml29623 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK |
43066f45ec7bSml29623 RX_DMA_ENT_MSK_PTDROP_PKT_MASK);
43076f45ec7bSml29623 rs = npi_rxdma_event_mask(handle, OP_SET, channel,
43086f45ec7bSml29623 &ent_mask);
43096f45ec7bSml29623 if (rs != NPI_SUCCESS) {
43106f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL,
43116f45ec7bSml29623 "==> nxge_rxdma_start_channel: "
43126f45ec7bSml29623 "init rxdma event masks failed (0x%08x channel %d)",
43136f45ec7bSml29623 status, channel));
43146f45ec7bSml29623 return (NXGE_ERROR | rs);
43156f45ec7bSml29623 }
43166f45ec7bSml29623
43176f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: "
43186f45ec7bSml29623 "control done - channel %d cs 0x%016llx", channel, cs.value));
43196f45ec7bSml29623
43206f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel"));
43216f45ec7bSml29623
43226f45ec7bSml29623 return (NXGE_OK);
43236f45ec7bSml29623 }
43246f45ec7bSml29623
43256f45ec7bSml29623 static nxge_status_t
nxge_rxdma_stop_channel(p_nxge_t nxgep,uint16_t channel)43266f45ec7bSml29623 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel)
43276f45ec7bSml29623 {
43286f45ec7bSml29623 npi_handle_t handle;
43296f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
43306f45ec7bSml29623 rx_dma_ctl_stat_t cs;
43316f45ec7bSml29623 rx_dma_ent_msk_t ent_mask;
43326f45ec7bSml29623 nxge_status_t status = NXGE_OK;
43336f45ec7bSml29623
43346f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel"));
43356f45ec7bSml29623
43366f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
43376f45ec7bSml29623
43386f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: "
43396f45ec7bSml29623 "npi handle addr $%p acc $%p",
43406f45ec7bSml29623 nxgep->npi_handle.regp, nxgep->npi_handle.regh));
43416f45ec7bSml29623
4342330cd344SMichael Speer if (!isLDOMguest(nxgep)) {
4343330cd344SMichael Speer /*
4344330cd344SMichael Speer * Stop RxMAC = A.9.2.6
4345330cd344SMichael Speer */
4346330cd344SMichael Speer if (nxge_rx_mac_disable(nxgep) != NXGE_OK) {
4347330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4348330cd344SMichael Speer "nxge_rxdma_stop_channel: "
4349330cd344SMichael Speer "Failed to disable RxMAC"));
4350330cd344SMichael Speer }
4351330cd344SMichael Speer
4352330cd344SMichael Speer /*
4353330cd344SMichael Speer * Drain IPP Port = A.9.3.6
4354330cd344SMichael Speer */
4355330cd344SMichael Speer (void) nxge_ipp_drain(nxgep);
4356330cd344SMichael Speer }
4357330cd344SMichael Speer
43586f45ec7bSml29623 /* Reset RXDMA channel */
43596f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_reset(handle, channel);
43606f45ec7bSml29623 if (rs != NPI_SUCCESS) {
43616f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
43626f45ec7bSml29623 " nxge_rxdma_stop_channel: "
43636f45ec7bSml29623 " reset rxdma failed (0x%08x channel %d)",
43646f45ec7bSml29623 rs, channel));
43656f45ec7bSml29623 return (NXGE_ERROR | rs);
43666f45ec7bSml29623 }
43676f45ec7bSml29623
43686f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
43696f45ec7bSml29623 "==> nxge_rxdma_stop_channel: reset done"));
43706f45ec7bSml29623
43716f45ec7bSml29623 /* Set up the interrupt event masks. */
43726f45ec7bSml29623 ent_mask.value = RX_DMA_ENT_MSK_ALL;
43736f45ec7bSml29623 rs = npi_rxdma_event_mask(handle, OP_SET, channel,
43746f45ec7bSml29623 &ent_mask);
43756f45ec7bSml29623 if (rs != NPI_SUCCESS) {
43766f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
43776f45ec7bSml29623 "==> nxge_rxdma_stop_channel: "
43786f45ec7bSml29623 "set rxdma event masks failed (0x%08x channel %d)",
43796f45ec7bSml29623 rs, channel));
43806f45ec7bSml29623 return (NXGE_ERROR | rs);
43816f45ec7bSml29623 }
43826f45ec7bSml29623
43836f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
43846f45ec7bSml29623 "==> nxge_rxdma_stop_channel: event done"));
43856f45ec7bSml29623
4386330cd344SMichael Speer /*
4387330cd344SMichael Speer * Initialize the receive DMA control and status register
4388330cd344SMichael Speer */
43896f45ec7bSml29623 cs.value = 0;
4390330cd344SMichael Speer status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs);
43916f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control "
43926f45ec7bSml29623 " to default (all 0s) 0x%08x", cs.value));
43936f45ec7bSml29623 if (status != NXGE_OK) {
43946f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
43956f45ec7bSml29623 " nxge_rxdma_stop_channel: init rxdma"
43966f45ec7bSml29623 " control register failed (0x%08x channel %d",
43976f45ec7bSml29623 status, channel));
43986f45ec7bSml29623 return (status);
43996f45ec7bSml29623 }
44006f45ec7bSml29623
44016f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL,
44026f45ec7bSml29623 "==> nxge_rxdma_stop_channel: control done"));
44036f45ec7bSml29623
4404330cd344SMichael Speer /*
4405330cd344SMichael Speer * Make sure channel is disabled.
4406330cd344SMichael Speer */
44076f45ec7bSml29623 status = nxge_disable_rxdma_channel(nxgep, channel);
4408da14cebeSEric Cheng
44096f45ec7bSml29623 if (status != NXGE_OK) {
44106f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
44116f45ec7bSml29623 " nxge_rxdma_stop_channel: "
44126f45ec7bSml29623 " init enable rxdma failed (0x%08x channel %d)",
44136f45ec7bSml29623 status, channel));
44146f45ec7bSml29623 return (status);
44156f45ec7bSml29623 }
44166f45ec7bSml29623
4417330cd344SMichael Speer if (!isLDOMguest(nxgep)) {
4418330cd344SMichael Speer /*
4419330cd344SMichael Speer * Enable RxMAC = A.9.2.10
4420330cd344SMichael Speer */
4421330cd344SMichael Speer if (nxge_rx_mac_enable(nxgep) != NXGE_OK) {
4422330cd344SMichael Speer NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4423330cd344SMichael Speer "nxge_rxdma_stop_channel: Rx MAC still disabled"));
4424330cd344SMichael Speer }
4425330cd344SMichael Speer }
4426330cd344SMichael Speer
44276f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep,
44286f45ec7bSml29623 RX_CTL, "==> nxge_rxdma_stop_channel: disable done"));
44296f45ec7bSml29623
44306f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel"));
44316f45ec7bSml29623
44326f45ec7bSml29623 return (NXGE_OK);
44336f45ec7bSml29623 }
44346f45ec7bSml29623
44356f45ec7bSml29623 nxge_status_t
nxge_rxdma_handle_sys_errors(p_nxge_t nxgep)44366f45ec7bSml29623 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep)
44376f45ec7bSml29623 {
44386f45ec7bSml29623 npi_handle_t handle;
44396f45ec7bSml29623 p_nxge_rdc_sys_stats_t statsp;
44406f45ec7bSml29623 rx_ctl_dat_fifo_stat_t stat;
44416f45ec7bSml29623 uint32_t zcp_err_status;
44426f45ec7bSml29623 uint32_t ipp_err_status;
44436f45ec7bSml29623 nxge_status_t status = NXGE_OK;
44446f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
44456f45ec7bSml29623 boolean_t my_err = B_FALSE;
44466f45ec7bSml29623
44476f45ec7bSml29623 handle = nxgep->npi_handle;
44486f45ec7bSml29623 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats;
44496f45ec7bSml29623
44506f45ec7bSml29623 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat);
44516f45ec7bSml29623
44526f45ec7bSml29623 if (rs != NPI_SUCCESS)
44536f45ec7bSml29623 return (NXGE_ERROR | rs);
44546f45ec7bSml29623
44556f45ec7bSml29623 if (stat.bits.ldw.id_mismatch) {
44566f45ec7bSml29623 statsp->id_mismatch++;
4457b37cc459SToomas Soome NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, 0,
44586f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_ID_MISMATCH);
44596f45ec7bSml29623 /* Global fatal error encountered */
44606f45ec7bSml29623 }
44616f45ec7bSml29623
44626f45ec7bSml29623 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) {
44636f45ec7bSml29623 switch (nxgep->mac.portnum) {
44646f45ec7bSml29623 case 0:
44656f45ec7bSml29623 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) ||
44666f45ec7bSml29623 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) {
44676f45ec7bSml29623 my_err = B_TRUE;
44686f45ec7bSml29623 zcp_err_status = stat.bits.ldw.zcp_eop_err;
44696f45ec7bSml29623 ipp_err_status = stat.bits.ldw.ipp_eop_err;
44706f45ec7bSml29623 }
44716f45ec7bSml29623 break;
44726f45ec7bSml29623 case 1:
44736f45ec7bSml29623 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) ||
44746f45ec7bSml29623 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) {
44756f45ec7bSml29623 my_err = B_TRUE;
44766f45ec7bSml29623 zcp_err_status = stat.bits.ldw.zcp_eop_err;
44776f45ec7bSml29623 ipp_err_status = stat.bits.ldw.ipp_eop_err;
44786f45ec7bSml29623 }
44796f45ec7bSml29623 break;
44806f45ec7bSml29623 case 2:
44816f45ec7bSml29623 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) ||
44826f45ec7bSml29623 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) {
44836f45ec7bSml29623 my_err = B_TRUE;
44846f45ec7bSml29623 zcp_err_status = stat.bits.ldw.zcp_eop_err;
44856f45ec7bSml29623 ipp_err_status = stat.bits.ldw.ipp_eop_err;
44866f45ec7bSml29623 }
44876f45ec7bSml29623 break;
44886f45ec7bSml29623 case 3:
44896f45ec7bSml29623 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) ||
44906f45ec7bSml29623 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) {
44916f45ec7bSml29623 my_err = B_TRUE;
44926f45ec7bSml29623 zcp_err_status = stat.bits.ldw.zcp_eop_err;
44936f45ec7bSml29623 ipp_err_status = stat.bits.ldw.ipp_eop_err;
44946f45ec7bSml29623 }
44956f45ec7bSml29623 break;
44966f45ec7bSml29623 default:
44976f45ec7bSml29623 return (NXGE_ERROR);
44986f45ec7bSml29623 }
44996f45ec7bSml29623 }
45006f45ec7bSml29623
45016f45ec7bSml29623 if (my_err) {
45026f45ec7bSml29623 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status,
45036f45ec7bSml29623 zcp_err_status);
45046f45ec7bSml29623 if (status != NXGE_OK)
45056f45ec7bSml29623 return (status);
45066f45ec7bSml29623 }
45076f45ec7bSml29623
45086f45ec7bSml29623 return (NXGE_OK);
45096f45ec7bSml29623 }
45106f45ec7bSml29623
45116f45ec7bSml29623 static nxge_status_t
nxge_rxdma_handle_port_errors(p_nxge_t nxgep,uint32_t ipp_status,uint32_t zcp_status)45126f45ec7bSml29623 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status,
45136f45ec7bSml29623 uint32_t zcp_status)
45146f45ec7bSml29623 {
45156f45ec7bSml29623 boolean_t rxport_fatal = B_FALSE;
45166f45ec7bSml29623 p_nxge_rdc_sys_stats_t statsp;
45176f45ec7bSml29623 nxge_status_t status = NXGE_OK;
45186f45ec7bSml29623 uint8_t portn;
45196f45ec7bSml29623
45206f45ec7bSml29623 portn = nxgep->mac.portnum;
45216f45ec7bSml29623 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats;
45226f45ec7bSml29623
45236f45ec7bSml29623 if (ipp_status & (0x1 << portn)) {
45246f45ec7bSml29623 statsp->ipp_eop_err++;
4525b37cc459SToomas Soome NXGE_FM_REPORT_ERROR(nxgep, portn, 0,
45266f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR);
45276f45ec7bSml29623 rxport_fatal = B_TRUE;
45286f45ec7bSml29623 }
45296f45ec7bSml29623
45306f45ec7bSml29623 if (zcp_status & (0x1 << portn)) {
45316f45ec7bSml29623 statsp->zcp_eop_err++;
4532b37cc459SToomas Soome NXGE_FM_REPORT_ERROR(nxgep, portn, 0,
45336f45ec7bSml29623 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR);
45346f45ec7bSml29623 rxport_fatal = B_TRUE;
45356f45ec7bSml29623 }
45366f45ec7bSml29623
45376f45ec7bSml29623 if (rxport_fatal) {
45386f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
45396f45ec7bSml29623 " nxge_rxdma_handle_port_error: "
45406f45ec7bSml29623 " fatal error on Port #%d\n",
45416f45ec7bSml29623 portn));
45426f45ec7bSml29623 status = nxge_rx_port_fatal_err_recover(nxgep);
45436f45ec7bSml29623 if (status == NXGE_OK) {
45446f45ec7bSml29623 FM_SERVICE_RESTORED(nxgep);
45456f45ec7bSml29623 }
45466f45ec7bSml29623 }
45476f45ec7bSml29623
45486f45ec7bSml29623 return (status);
45496f45ec7bSml29623 }
45506f45ec7bSml29623
45516f45ec7bSml29623 static nxge_status_t
nxge_rxdma_fatal_err_recover(p_nxge_t nxgep,uint16_t channel)45526f45ec7bSml29623 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel)
45536f45ec7bSml29623 {
45546f45ec7bSml29623 npi_handle_t handle;
45556f45ec7bSml29623 npi_status_t rs = NPI_SUCCESS;
45566f45ec7bSml29623 nxge_status_t status = NXGE_OK;
45576f45ec7bSml29623 p_rx_rbr_ring_t rbrp;
45586f45ec7bSml29623 p_rx_rcr_ring_t rcrp;
45596f45ec7bSml29623 p_rx_mbox_t mboxp;
45606f45ec7bSml29623 rx_dma_ent_msk_t ent_mask;
45616f45ec7bSml29623 p_nxge_dma_common_t dmap;
45626f45ec7bSml29623 uint32_t ref_cnt;
45636f45ec7bSml29623 p_rx_msg_t rx_msg_p;
45646f45ec7bSml29623 int i;
45656f45ec7bSml29623 uint32_t nxge_port_rcr_size;
45666f45ec7bSml29623
45676f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover"));
45686f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
45696f45ec7bSml29623 "Recovering from RxDMAChannel#%d error...", channel));
45706f45ec7bSml29623
45716f45ec7bSml29623 /*
45726f45ec7bSml29623 * Stop the dma channel waits for the stop done.
45736f45ec7bSml29623 * If the stop done bit is not set, then create
45746f45ec7bSml29623 * an error.
45756f45ec7bSml29623 */
45766f45ec7bSml29623
45776f45ec7bSml29623 handle = NXGE_DEV_NPI_HANDLE(nxgep);
45786f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop..."));
45796f45ec7bSml29623
45803587e8e2SMichael Speer rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[channel];
45813587e8e2SMichael Speer rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[channel];
45826f45ec7bSml29623
45836f45ec7bSml29623 MUTEX_ENTER(&rbrp->lock);
45846f45ec7bSml29623 MUTEX_ENTER(&rbrp->post_lock);
45856f45ec7bSml29623
45866f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel..."));
45876f45ec7bSml29623
45886f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_disable(handle, channel);
45896f45ec7bSml29623 if (rs != NPI_SUCCESS) {
45906f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
45916f45ec7bSml29623 "nxge_disable_rxdma_channel:failed"));
45926f45ec7bSml29623 goto fail;
45936f45ec7bSml29623 }
45946f45ec7bSml29623
45956f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt..."));
45966f45ec7bSml29623
45976f45ec7bSml29623 /* Disable interrupt */
45986f45ec7bSml29623 ent_mask.value = RX_DMA_ENT_MSK_ALL;
45996f45ec7bSml29623 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask);
46006f45ec7bSml29623 if (rs != NPI_SUCCESS) {
46016f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46026f45ec7bSml29623 "nxge_rxdma_stop_channel: "
46036f45ec7bSml29623 "set rxdma event masks failed (channel %d)",
46046f45ec7bSml29623 channel));
46056f45ec7bSml29623 }
46066f45ec7bSml29623
46076f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset..."));
46086f45ec7bSml29623
46096f45ec7bSml29623 /* Reset RXDMA channel */
46106f45ec7bSml29623 rs = npi_rxdma_cfg_rdc_reset(handle, channel);
46116f45ec7bSml29623 if (rs != NPI_SUCCESS) {
46126f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46136f45ec7bSml29623 "nxge_rxdma_fatal_err_recover: "
46146f45ec7bSml29623 " reset rxdma failed (channel %d)", channel));
46156f45ec7bSml29623 goto fail;
46166f45ec7bSml29623 }
46176f45ec7bSml29623
46186f45ec7bSml29623 nxge_port_rcr_size = nxgep->nxge_port_rcr_size;
46196f45ec7bSml29623
46203587e8e2SMichael Speer mboxp = (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[channel];
46216f45ec7bSml29623
46226f45ec7bSml29623 rbrp->rbr_wr_index = (rbrp->rbb_max - 1);
46236f45ec7bSml29623 rbrp->rbr_rd_index = 0;
46246f45ec7bSml29623
46256f45ec7bSml29623 rcrp->comp_rd_index = 0;
46266f45ec7bSml29623 rcrp->comp_wt_index = 0;
46276f45ec7bSml29623 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p =
46286f45ec7bSml29623 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc);
462952ccf843Smisaki rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp =
46306f45ec7bSml29623 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc);
46316f45ec7bSml29623
46326f45ec7bSml29623 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p +
46336f45ec7bSml29623 (nxge_port_rcr_size - 1);
46346f45ec7bSml29623 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp +
46356f45ec7bSml29623 (nxge_port_rcr_size - 1);
46366f45ec7bSml29623
46376f45ec7bSml29623 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc;
46386f45ec7bSml29623 bzero((caddr_t)dmap->kaddrp, dmap->alength);
46396f45ec7bSml29623
46406f45ec7bSml29623 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size);
46416f45ec7bSml29623
46426f45ec7bSml29623 for (i = 0; i < rbrp->rbr_max_size; i++) {
46436f45ec7bSml29623 rx_msg_p = rbrp->rx_msg_ring[i];
46446f45ec7bSml29623 ref_cnt = rx_msg_p->ref_cnt;
46456f45ec7bSml29623 if (ref_cnt != 1) {
46466f45ec7bSml29623 if (rx_msg_p->cur_usage_cnt !=
46476f45ec7bSml29623 rx_msg_p->max_usage_cnt) {
46486f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46496f45ec7bSml29623 "buf[%d]: cur_usage_cnt = %d "
46506f45ec7bSml29623 "max_usage_cnt = %d\n", i,
46516f45ec7bSml29623 rx_msg_p->cur_usage_cnt,
46526f45ec7bSml29623 rx_msg_p->max_usage_cnt));
46536f45ec7bSml29623 } else {
46546f45ec7bSml29623 /* Buffer can be re-posted */
46556f45ec7bSml29623 rx_msg_p->free = B_TRUE;
46566f45ec7bSml29623 rx_msg_p->cur_usage_cnt = 0;
46576f45ec7bSml29623 rx_msg_p->max_usage_cnt = 0xbaddcafe;
46586f45ec7bSml29623 rx_msg_p->pkt_buf_size = 0;
46596f45ec7bSml29623 }
46606f45ec7bSml29623 }
46616f45ec7bSml29623 }
46626f45ec7bSml29623
46636f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start..."));
46646f45ec7bSml29623
46656f45ec7bSml29623 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp);
46666f45ec7bSml29623 if (status != NXGE_OK) {
46676f45ec7bSml29623 goto fail;
46686f45ec7bSml29623 }
46696f45ec7bSml29623
46706f45ec7bSml29623 MUTEX_EXIT(&rbrp->post_lock);
46716f45ec7bSml29623 MUTEX_EXIT(&rbrp->lock);
46726f45ec7bSml29623
46736f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46746f45ec7bSml29623 "Recovery Successful, RxDMAChannel#%d Restored",
46756f45ec7bSml29623 channel));
46766f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover"));
46776f45ec7bSml29623 return (NXGE_OK);
4678ef523517SMichael Speer
46796f45ec7bSml29623 fail:
46806f45ec7bSml29623 MUTEX_EXIT(&rbrp->post_lock);
46816f45ec7bSml29623 MUTEX_EXIT(&rbrp->lock);
46826f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed"));
46836f45ec7bSml29623 return (NXGE_ERROR | rs);
46846f45ec7bSml29623 }
46856f45ec7bSml29623
46866f45ec7bSml29623 nxge_status_t
nxge_rx_port_fatal_err_recover(p_nxge_t nxgep)46876f45ec7bSml29623 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep)
46886f45ec7bSml29623 {
4689678453a8Sspeer nxge_grp_set_t *set = &nxgep->rx_set;
46906f45ec7bSml29623 nxge_status_t status = NXGE_OK;
4691ef523517SMichael Speer p_rx_rcr_ring_t rcrp;
4692678453a8Sspeer int rdc;
46936f45ec7bSml29623
46946f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover"));
46956f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
46966f45ec7bSml29623 "Recovering from RxPort error..."));
4697678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disabling RxMAC...\n"));
46986f45ec7bSml29623
46996f45ec7bSml29623 if (nxge_rx_mac_disable(nxgep) != NXGE_OK)
47006f45ec7bSml29623 goto fail;
47016f45ec7bSml29623
47026f45ec7bSml29623 NXGE_DELAY(1000);
47036f45ec7bSml29623
4704678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stopping all RxDMA channels..."));
47056f45ec7bSml29623
4706678453a8Sspeer for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) {
4707678453a8Sspeer if ((1 << rdc) & set->owned.map) {
4708ef523517SMichael Speer rcrp = nxgep->rx_rcr_rings->rcr_rings[rdc];
4709ef523517SMichael Speer if (rcrp != NULL) {
4710ef523517SMichael Speer MUTEX_ENTER(&rcrp->lock);
4711ef523517SMichael Speer if (nxge_rxdma_fatal_err_recover(nxgep,
4712ef523517SMichael Speer rdc) != NXGE_OK) {
47136f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
4714ef523517SMichael Speer "Could not recover "
4715ef523517SMichael Speer "channel %d", rdc));
4716ef523517SMichael Speer }
4717ef523517SMichael Speer MUTEX_EXIT(&rcrp->lock);
4718678453a8Sspeer }
47196f45ec7bSml29623 }
47206f45ec7bSml29623 }
47216f45ec7bSml29623
4722678453a8Sspeer NXGE_DEBUG_MSG((nxgep, RX_CTL, "Resetting IPP..."));
47236f45ec7bSml29623
47246f45ec7bSml29623 /* Reset IPP */
47256f45ec7bSml29623 if (nxge_ipp_reset(nxgep) != NXGE_OK) {
47266f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47276f45ec7bSml29623 "nxge_rx_port_fatal_err_recover: "
47286f45ec7bSml29623 "Failed to reset IPP"));
47296f45ec7bSml29623 goto fail;
47306f45ec7bSml29623 }
47316f45ec7bSml29623
47326f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC..."));
47336f45ec7bSml29623
47346f45ec7bSml29623 /* Reset RxMAC */
47356f45ec7bSml29623 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) {
47366f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47376f45ec7bSml29623 "nxge_rx_port_fatal_err_recover: "
47386f45ec7bSml29623 "Failed to reset RxMAC"));
47396f45ec7bSml29623 goto fail;
47406f45ec7bSml29623 }
47416f45ec7bSml29623
47426f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP..."));
47436f45ec7bSml29623
47446f45ec7bSml29623 /* Re-Initialize IPP */
47456f45ec7bSml29623 if (nxge_ipp_init(nxgep) != NXGE_OK) {
47466f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47476f45ec7bSml29623 "nxge_rx_port_fatal_err_recover: "
47486f45ec7bSml29623 "Failed to init IPP"));
47496f45ec7bSml29623 goto fail;
47506f45ec7bSml29623 }
47516f45ec7bSml29623
47526f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC..."));
47536f45ec7bSml29623
47546f45ec7bSml29623 /* Re-Initialize RxMAC */
47556f45ec7bSml29623 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) {
47566f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47576f45ec7bSml29623 "nxge_rx_port_fatal_err_recover: "
47586f45ec7bSml29623 "Failed to reset RxMAC"));
47596f45ec7bSml29623 goto fail;
47606f45ec7bSml29623 }
47616f45ec7bSml29623
47626f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC..."));
47636f45ec7bSml29623
47646f45ec7bSml29623 /* Re-enable RxMAC */
47656f45ec7bSml29623 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) {
47666f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47676f45ec7bSml29623 "nxge_rx_port_fatal_err_recover: "
47686f45ec7bSml29623 "Failed to enable RxMAC"));
47696f45ec7bSml29623 goto fail;
47706f45ec7bSml29623 }
47716f45ec7bSml29623
47726f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
47736f45ec7bSml29623 "Recovery Successful, RxPort Restored"));
47746f45ec7bSml29623
47756f45ec7bSml29623 return (NXGE_OK);
47766f45ec7bSml29623 fail:
47776f45ec7bSml29623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed"));
47786f45ec7bSml29623 return (status);
47796f45ec7bSml29623 }
47806f45ec7bSml29623
47816f45ec7bSml29623 void
nxge_rxdma_inject_err(p_nxge_t nxgep,uint32_t err_id,uint8_t chan)47826f45ec7bSml29623 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan)
47836f45ec7bSml29623 {
47846f45ec7bSml29623 rx_dma_ctl_stat_t cs;
47856f45ec7bSml29623 rx_ctl_dat_fifo_stat_t cdfs;
47866f45ec7bSml29623
47876f45ec7bSml29623 switch (err_id) {
47886f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR:
47896f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR:
47906f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR:
47916f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR:
47926f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT:
47936f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR:
47946f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS:
47956f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR:
47966f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RCRINCON:
47976f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RCRFULL:
47986f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RBRFULL:
47996f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE:
48006f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE:
48016f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR:
48026f45ec7bSml29623 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG,
48036f45ec7bSml29623 chan, &cs.value);
48046f45ec7bSml29623 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR)
48056f45ec7bSml29623 cs.bits.hdw.rcr_ack_err = 1;
48066f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR)
48076f45ec7bSml29623 cs.bits.hdw.dc_fifo_err = 1;
48086f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR)
48096f45ec7bSml29623 cs.bits.hdw.rcr_sha_par = 1;
48106f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR)
48116f45ec7bSml29623 cs.bits.hdw.rbr_pre_par = 1;
48126f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT)
48136f45ec7bSml29623 cs.bits.hdw.rbr_tmout = 1;
48146f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR)
48156f45ec7bSml29623 cs.bits.hdw.rsp_cnt_err = 1;
48166f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS)
48176f45ec7bSml29623 cs.bits.hdw.byte_en_bus = 1;
48186f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR)
48196f45ec7bSml29623 cs.bits.hdw.rsp_dat_err = 1;
48206f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR)
48216f45ec7bSml29623 cs.bits.hdw.config_err = 1;
48226f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON)
48236f45ec7bSml29623 cs.bits.hdw.rcrincon = 1;
48246f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL)
48256f45ec7bSml29623 cs.bits.hdw.rcrfull = 1;
48266f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL)
48276f45ec7bSml29623 cs.bits.hdw.rbrfull = 1;
48286f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE)
48296f45ec7bSml29623 cs.bits.hdw.rbrlogpage = 1;
48306f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE)
48316f45ec7bSml29623 cs.bits.hdw.cfiglogpage = 1;
48326f45ec7bSml29623 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n",
48336f45ec7bSml29623 cs.value);
48346f45ec7bSml29623 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG,
48356f45ec7bSml29623 chan, cs.value);
48366f45ec7bSml29623 break;
48376f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH:
48386f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR:
48396f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR:
48406f45ec7bSml29623 cdfs.value = 0;
48416f45ec7bSml29623 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH)
48426f45ec7bSml29623 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum);
48436f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR)
48446f45ec7bSml29623 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum);
48456f45ec7bSml29623 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR)
48466f45ec7bSml29623 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum);
48476f45ec7bSml29623 cmn_err(CE_NOTE,
48486f45ec7bSml29623 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n",
48496f45ec7bSml29623 cdfs.value);
4850678453a8Sspeer NXGE_REG_WR64(nxgep->npi_handle,
4851678453a8Sspeer RX_CTL_DAT_FIFO_STAT_DBG_REG, cdfs.value);
48526f45ec7bSml29623 break;
48536f45ec7bSml29623 case NXGE_FM_EREPORT_RDMC_DCF_ERR:
48546f45ec7bSml29623 break;
485553f3d8ecSyc148097 case NXGE_FM_EREPORT_RDMC_RCR_ERR:
48566f45ec7bSml29623 break;
48576f45ec7bSml29623 }
48586f45ec7bSml29623 }
4859678453a8Sspeer
4860678453a8Sspeer static void
nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p)4861678453a8Sspeer nxge_rxdma_databuf_free(p_rx_rbr_ring_t rbr_p)
4862678453a8Sspeer {
4863678453a8Sspeer rxring_info_t *ring_info;
4864678453a8Sspeer int index;
4865678453a8Sspeer uint32_t chunk_size;
4866678453a8Sspeer uint64_t kaddr;
4867678453a8Sspeer uint_t num_blocks;
4868678453a8Sspeer
4869678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_rxdma_databuf_free"));
4870678453a8Sspeer
4871678453a8Sspeer if (rbr_p == NULL) {
4872678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
4873678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL rbr pointer"));
4874678453a8Sspeer return;
4875678453a8Sspeer }
4876678453a8Sspeer
4877678453a8Sspeer if (rbr_p->rbr_alloc_type == DDI_MEM_ALLOC) {
4878e759c33aSMichael Speer NXGE_DEBUG_MSG((NULL, DMA_CTL,
4879e759c33aSMichael Speer "<== nxge_rxdma_databuf_free: DDI"));
4880678453a8Sspeer return;
4881678453a8Sspeer }
4882678453a8Sspeer
4883678453a8Sspeer ring_info = rbr_p->ring_info;
4884678453a8Sspeer if (ring_info == NULL) {
4885678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
4886678453a8Sspeer "==> nxge_rxdma_databuf_free: NULL ring info"));
4887678453a8Sspeer return;
4888678453a8Sspeer }
4889678453a8Sspeer num_blocks = rbr_p->num_blocks;
4890678453a8Sspeer for (index = 0; index < num_blocks; index++) {
4891678453a8Sspeer kaddr = ring_info->buffer[index].kaddr;
4892678453a8Sspeer chunk_size = ring_info->buffer[index].buf_size;
4893678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL,
4894678453a8Sspeer "==> nxge_rxdma_databuf_free: free chunk %d "
4895678453a8Sspeer "kaddrp $%p chunk size %d",
4896678453a8Sspeer index, kaddr, chunk_size));
4897b37cc459SToomas Soome if (kaddr == 0)
4898b37cc459SToomas Soome continue;
4899678453a8Sspeer nxge_free_buf(rbr_p->rbr_alloc_type, kaddr, chunk_size);
4900b37cc459SToomas Soome ring_info->buffer[index].kaddr = 0;
4901678453a8Sspeer }
4902678453a8Sspeer
4903678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_databuf_free"));
4904678453a8Sspeer }
4905678453a8Sspeer
4906678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
4907678453a8Sspeer extern void contig_mem_free(void *, size_t);
4908678453a8Sspeer #endif
4909678453a8Sspeer
4910678453a8Sspeer void
nxge_free_buf(buf_alloc_type_t alloc_type,uint64_t kaddr,uint32_t buf_size)4911678453a8Sspeer nxge_free_buf(buf_alloc_type_t alloc_type, uint64_t kaddr, uint32_t buf_size)
4912678453a8Sspeer {
4913678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_free_buf"));
4914678453a8Sspeer
4915b37cc459SToomas Soome if (kaddr == 0 || !buf_size) {
4916678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
4917678453a8Sspeer "==> nxge_free_buf: invalid kaddr $%p size to free %d",
4918678453a8Sspeer kaddr, buf_size));
4919678453a8Sspeer return;
4920678453a8Sspeer }
4921678453a8Sspeer
4922678453a8Sspeer switch (alloc_type) {
4923678453a8Sspeer case KMEM_ALLOC:
4924678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL,
4925678453a8Sspeer "==> nxge_free_buf: freeing kmem $%p size %d",
4926678453a8Sspeer kaddr, buf_size));
4927678453a8Sspeer KMEM_FREE((void *)kaddr, buf_size);
4928678453a8Sspeer break;
4929678453a8Sspeer
4930678453a8Sspeer #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
4931678453a8Sspeer case CONTIG_MEM_ALLOC:
4932678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL,
4933678453a8Sspeer "==> nxge_free_buf: freeing contig_mem kaddr $%p size %d",
4934678453a8Sspeer kaddr, buf_size));
4935678453a8Sspeer contig_mem_free((void *)kaddr, buf_size);
4936678453a8Sspeer break;
4937678453a8Sspeer #endif
4938678453a8Sspeer
4939678453a8Sspeer default:
4940678453a8Sspeer NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
4941678453a8Sspeer "<== nxge_free_buf: unsupported alloc type %d",
4942678453a8Sspeer alloc_type));
4943678453a8Sspeer return;
4944678453a8Sspeer }
4945678453a8Sspeer
4946678453a8Sspeer NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_free_buf"));
4947678453a8Sspeer }
4948