1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Racktop Systems, Inc. 14 */ 15 #ifndef _LMRC_REG_H 16 #define _LMRC_REG_H 17 18 #include <sys/bitext.h> 19 #include <sys/debug.h> 20 #include <sys/stddef.h> 21 22 typedef struct lmrc_raid_mfa_io_req_desc lmrc_raid_mfa_io_req_desc_t; 23 typedef union lmrc_atomic_req_desc lmrc_atomic_req_desc_t; 24 typedef union lmrc_req_desc lmrc_req_desc_t; 25 26 typedef union lmrc_mfi_cap lmrc_mfi_cap_t; 27 typedef union lmrc_mfi_sgl lmrc_mfi_sgl_t; 28 typedef struct lmrc_mfi_header lmrc_mfi_header_t; 29 typedef struct lmrc_mfi_init_payload lmrc_mfi_init_payload_t; 30 typedef struct lmrc_mfi_io_payload lmrc_mfi_io_payload_t; 31 typedef struct lmrc_mfi_pthru_payload lmrc_mfi_pthru_payload_t; 32 typedef struct lmrc_mfi_dcmd_payload lmrc_mfi_dcmd_payload_t; 33 typedef struct lmrc_mfi_abort_payload lmrc_mfi_abort_payload_t; 34 typedef struct lmrc_mfi_frame lmrc_mfi_frame_t; 35 36 typedef struct lmrc_aen lmrc_aen_t; 37 typedef union lmrc_evt_class_locale lmrc_evt_class_locale_t; 38 typedef struct lmrc_evt_log_info lmrc_evt_log_info_t; 39 typedef struct lmrc_evtarg_ld lmrc_evtarg_ld_t; 40 typedef struct lmrc_evtarg_pd lmrc_evtarg_pd_t; 41 typedef struct lmrc_evt lmrc_evt_t; 42 43 typedef struct lmrc_ctrl_prop lmrc_ctrl_prop_t; 44 typedef struct lmrc_image_comp lmrc_image_comp_t; 45 typedef struct lmrc_ctrl_info lmrc_ctrl_info_t; 46 47 #include "lmrc_raid.h" 48 49 /* PCI device IDs of Gen 3.5 Controllers */ 50 #define LMRC_VENTURA 0x0014 51 #define LMRC_CRUSADER 0x0015 52 #define LMRC_HARPOON 0x0016 53 #define LMRC_TOMCAT 0x0017 54 #define LMRC_VENTURA_4PORT 0x001B 55 #define LMRC_CRUSADER_4PORT 0x001C 56 #define LMRC_AERO_10E0 0x10E0 57 #define LMRC_AERO_10E1 0x10E1 58 #define LMRC_AERO_10E2 0x10E2 59 #define LMRC_AERO_10E3 0x10E3 60 #define LMRC_AERO_10E4 0x10E4 61 #define LMRC_AERO_10E5 0x10E5 62 #define LMRC_AERO_10E6 0x10E6 63 #define LMRC_AERO_10E7 0x10E7 64 65 /* 66 * Message Frame Defines 67 */ 68 #define LMRC_SENSE_LEN 96 69 70 #define MFI_FUSION_ENABLE_INTERRUPT_MASK 0x00000009 71 72 73 #define LMRC_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 74 75 #define LMRC_SPECIFIC_MPI2_FUNCTION(x) \ 76 (MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC + (x)) 77 #define LMRC_MPI2_FUNCTION_PASSTHRU_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(0) 78 #define LMRC_MPI2_FUNCTION_LD_IO_REQUEST LMRC_SPECIFIC_MPI2_FUNCTION(1) 79 80 81 #define LMRC_MAX_MFI_CMDS 16 82 #define LMRC_MAX_IOCTL_CMDS 3 83 84 /* 85 * Firmware Status Register 86 * For Ventura and Aero controllers, this is outbound scratch pad register 0. 87 */ 88 #define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0) 89 #define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0) 90 #define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0) 91 #define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0) 92 #define LMRC_FW_STATE(reg) bitx32((reg), 31, 28) 93 94 /* outbound scratch pad register 1 */ 95 #define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5) 96 #define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14) 97 #define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0) 98 #define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0) 99 #define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 100 #define LMRC_ATOMIC_DESCRIPTOR_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) 101 #define LMRC_64BIT_DMA_SUPPORT(reg) (bitx32((reg), 25, 25) != 0) 102 #define LMRC_INTR_COALESCING_SUPPORT(reg) (bitx32((reg), 26, 26) != 0) 103 104 #define LMRC_256K_IO 128 105 #define LMRC_1MB_IO (LMRC_256K_IO * 4) 106 107 /* outbound scratch pad register 2 */ 108 #define LMRC_MAX_RAID_MAP_SZ(reg) bitx32((reg), 24, 16) 109 110 /* outbound scratch pad register 3 */ 111 #define LMRC_NVME_PAGE_SHIFT(reg) bitx32((reg), 7, 0) 112 #define LMRC_DEFAULT_NVME_PAGE_SHIFT 12 113 114 /* 115 * Firmware Interface 116 * 117 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 118 * for the protocol between the software and the firmware. Commands are 119 * issued using "message frames". 120 */ 121 /* 122 * FW posts its state in the upper 4 bits of the status register, extracted 123 * with LMRC_FW_STATE(reg). 124 */ 125 #define LMRC_FW_STATE_UNDEFINED 0x0 126 #define LMRC_FW_STATE_BB_INIT 0x1 127 #define LMRC_FW_STATE_FW_INIT 0x4 128 #define LMRC_FW_STATE_WAIT_HANDSHAKE 0x6 129 #define LMRC_FW_STATE_FW_INIT_2 0x7 130 #define LMRC_FW_STATE_DEVICE_SCAN 0x8 131 #define LMRC_FW_STATE_BOOT_MSG_PENDING 0x9 132 #define LMRC_FW_STATE_FLUSH_CACHE 0xa 133 #define LMRC_FW_STATE_READY 0xb 134 #define LMRC_FW_STATE_OPERATIONAL 0xc 135 #define LMRC_FW_STATE_FAULT 0xf 136 137 /* 138 * During FW init, clear pending cmds & reset state using the doorbell register 139 * 140 * ABORT: Abort all pending cmds 141 * READY: Move from OPERATIONAL to READY state; discard queue info 142 * MFIMODE: Discard (possible) low MFA posted in 64-bit mode (??) 143 * CLEAR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 144 * HOTPLUG: Resume from Hotplug 145 * MFI_STOP_ADP: Send signal to FW to stop processing 146 */ 147 #define MFI_INIT_ABORT 0x00000001 148 #define MFI_INIT_READY 0x00000002 149 #define MFI_INIT_MFIMODE 0x00000004 150 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 151 #define MFI_INIT_HOTPLUG 0x00000010 152 #define MFI_STOP_ADP 0x00000020 153 #define MFI_RESET_FLAGS (MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT) 154 155 /* 156 * MFI frame flags 157 */ 158 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 159 #define MFI_FRAME_SGL64 0x0002 160 #define MFI_FRAME_SENSE64 0x0004 161 #define MFI_FRAME_DIR_NONE 0 162 #define MFI_FRAME_DIR_WRITE 0x0008 163 #define MFI_FRAME_DIR_READ 0x0010 164 #define MFI_FRAME_DIR_BOTH 0x0018 165 #define MFI_FRAME_IEEE 0x0020 166 167 /* 168 * MFI command opcodes 169 */ 170 #define MFI_CMD_INIT 0x00 171 #define MFI_CMD_LD_READ 0x01 172 #define MFI_CMD_LD_WRITE 0x02 173 #define MFI_CMD_LD_SCSI_IO 0x03 174 #define MFI_CMD_PD_SCSI_IO 0x04 175 #define MFI_CMD_DCMD 0x05 176 #define MFI_CMD_ABORT 0x06 177 #define MFI_CMD_SMP 0x07 178 #define MFI_CMD_STP 0x08 179 #define MFI_CMD_INVALID 0xff 180 181 /* 182 * MFI command status completion codes 183 */ 184 #define MFI_STAT_OK 0x00 185 #define MFI_STAT_INVALID_CMD 0x01 186 #define MFI_STAT_INVALID_DCMD 0x02 187 #define MFI_STAT_INVALID_PARAMETER 0x03 188 #define MFI_STAT_INVALID_SEQUENCE_NUMBER 0x04 189 #define MFI_STAT_ABORT_NOT_POSSIBLE 0x05 190 #define MFI_STAT_APP_HOST_CODE_NOT_FOUND 0x06 191 #define MFI_STAT_APP_IN_USE 0x07 192 #define MFI_STAT_APP_NOT_INITIALIZED 0x08 193 #define MFI_STAT_ARRAY_INDEX_INVALID 0x09 194 #define MFI_STAT_ARRAY_ROW_NOT_EMPTY 0x0a 195 #define MFI_STAT_CONFIG_RESOURCE_CONFLICT 0x0b 196 #define MFI_STAT_DEVICE_NOT_FOUND 0x0c 197 #define MFI_STAT_DRIVE_TOO_SMALL 0x0d 198 #define MFI_STAT_FLASH_ALLOC_FAIL 0x0e 199 #define MFI_STAT_FLASH_BUSY 0x0f 200 #define MFI_STAT_FLASH_ERROR 0x10 201 #define MFI_STAT_FLASH_IMAGE_BAD 0x11 202 #define MFI_STAT_FLASH_IMAGE_INCOMPLETE 0x12 203 #define MFI_STAT_FLASH_NOT_OPEN 0x13 204 #define MFI_STAT_FLASH_NOT_STARTED 0x14 205 #define MFI_STAT_FLUSH_FAILED 0x15 206 #define MFI_STAT_HOST_CODE_NOT_FOUNT 0x16 207 #define MFI_STAT_LD_CC_IN_PROGRESS 0x17 208 #define MFI_STAT_LD_INIT_IN_PROGRESS 0x18 209 #define MFI_STAT_LD_LBA_OUT_OF_RANGE 0x19 210 #define MFI_STAT_LD_MAX_CONFIGURED 0x1a 211 #define MFI_STAT_LD_NOT_OPTIMAL 0x1b 212 #define MFI_STAT_LD_RBLD_IN_PROGRESS 0x1c 213 #define MFI_STAT_LD_RECON_IN_PROGRESS 0x1d 214 #define MFI_STAT_LD_WRONG_RAID_LEVEL 0x1e 215 #define MFI_STAT_MAX_SPARES_EXCEEDED 0x1f 216 #define MFI_STAT_MEMORY_NOT_AVAILABLE 0x20 217 #define MFI_STAT_MFC_HW_ERROR 0x21 218 #define MFI_STAT_NO_HW_PRESENT 0x22 219 #define MFI_STAT_NOT_FOUND 0x23 220 #define MFI_STAT_NOT_IN_ENCL 0x24 221 #define MFI_STAT_PD_CLEAR_IN_PROGRESS 0x25 222 #define MFI_STAT_PD_TYPE_WRONG 0x26 223 #define MFI_STAT_PR_DISABLED 0x27 224 #define MFI_STAT_ROW_INDEX_INVALID 0x28 225 #define MFI_STAT_SAS_CONFIG_INVALID_ACTION 0x29 226 #define MFI_STAT_SAS_CONFIG_INVALID_DATA 0x2a 227 #define MFI_STAT_SAS_CONFIG_INVALID_PAGE 0x2b 228 #define MFI_STAT_SAS_CONFIG_INVALID_TYPE 0x2c 229 #define MFI_STAT_SCSI_DONE_WITH_ERROR 0x2d 230 #define MFI_STAT_SCSI_IO_FAILED 0x2e 231 #define MFI_STAT_SCSI_RESERVATION_CONFLICT 0x2f 232 #define MFI_STAT_SHUTDOWN_FAILED 0x30 233 #define MFI_STAT_TIME_NOT_SET 0x31 234 #define MFI_STAT_WRONG_STATE 0x32 235 #define MFI_STAT_LD_OFFLINE 0x33 236 #define MFI_STAT_PEER_NOTIFICATION_REJECTED 0x34 237 #define MFI_STAT_PEER_NOTIFICATION_FAILED 0x35 238 #define MFI_STAT_RESERVATION_IN_PROGRESS 0x36 239 #define MFI_STAT_I2C_ERRORS_DETECTED 0x37 240 #define MFI_STAT_PCI_ERRORS_DETECTED 0x38 241 #define MFI_STAT_CONFIG_SEQ_MISMATCH 0x67 242 243 #define MFI_STAT_INVALID_STATUS 0xFF 244 245 /* 246 * MFI DCMDs 247 */ 248 #define LMRC_DCMD_CTRL_GET_INFO 0x01010000 249 #define LMRC_DCMD_CTRL_EVENT_GET_INFO 0x01040100 250 #define LMRC_DCMD_CTRL_EVENT_WAIT 0x01040500 251 #define LMRC_DCMD_CTRL_SHUTDOWN 0x01050000 252 #define LMRC_DCMD_PD_GET_INFO 0x02020000 253 #define LMRC_DCMD_PD_LIST_QUERY 0x02010100 254 #define LMRC_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 255 #define LMRC_DCMD_LD_MAP_GET_INFO 0x0300e101 256 #define LMRC_DCMD_LD_GET_LIST 0x03010000 257 #define LMRC_DCMD_LD_LIST_QUERY 0x03010100 258 259 #define LMRC_PD_QUERY_TYPE_ALL 0 260 #define LMRC_PD_QUERY_TYPE_STATE 1 261 #define LMRC_PD_QUERY_TYPE_POWER_STATE 2 262 #define LMRC_PD_QUERY_TYPE_MEDIA_TYPE 3 263 #define LMRC_PD_QUERY_TYPE_SPEED 4 264 #define LMRC_PD_QUERY_TYPE_EXPOSED_TO_HOST 5 265 266 #define LMRC_LD_QUERY_TYPE_ALL 0 267 #define LMRC_LD_QUERY_TYPE_EXPOSED_TO_HOST 1 268 #define LMRC_LD_QUERY_TYPE_USED_TGT_IDS 2 269 #define LMRC_LD_QUERY_TYPE_CLUSTER_ACCESS 3 270 #define LMRC_LD_QUERY_TYPE_CLUSTER_LOCALE 4 271 272 #define LMRC_DCMD_MBOX_PEND_FLAG 0x01 273 274 #define LMRC_MAX_PD_CHANNELS 1 275 #define LMRC_MAX_LD_CHANNELS 1 276 #define LMRC_MAX_DEV_PER_CHANNEL 256 277 #define LMRC_MAX_PD \ 278 (LMRC_MAX_PD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 279 #define LMRC_MAX_LD \ 280 (LMRC_MAX_LD_CHANNELS * LMRC_MAX_DEV_PER_CHANNEL) 281 #define LMRC_MAX_TM_TARGETS (LMRC_MAX_PD + LMRC_MAX_LD) 282 283 #define LMRC_DEFAULT_INIT_ID -1 284 #define LMRC_MAX_LUN 8 285 #define LMRC_DEFAULT_CMD_PER_LUN 256 286 287 /* 288 * Register offsets 289 */ 290 #define LMRC_DOORBELL 0x0000 291 #define LMRC_WRITE_SEQUENCE 0x0004 292 #define LMRC_HOST_DIAG 0x0008 293 294 #define LMRC_IB_MSG0 0x0010 295 #define LMRC_IB_MSG1 0x0014 296 #define LMRC_OB_MSG0 0x0018 297 #define LMRC_OB_MSG1 0x001C 298 299 #define LMRC_IB_DOORBELL 0x0020 300 #define LMRC_IB_INTR_STATUS 0x0024 301 #define LMRC_IB_INTR_MASK 0x0028 302 303 #define LMRC_OB_DOORBELL 0x002C 304 #define LMRC_OB_INTR_STATUS 0x0030 305 #define LMRC_OB_INTR_MASK 0x0034 306 307 #define LMRC_IB_QUEUE_PORT 0x0040 308 #define LMRC_OB_QUEUE_PORT 0x0044 309 310 #define LMRC_REPLY_POST_HOST_INDEX 0x006C 311 312 #define LMRC_OB_DOORBELL_CLR 0x00A0 313 314 #define LMRC_OB_SCRATCH_PAD(x) (0x00B0 + (x) * 4) 315 316 #define LMRC_IB_LO_QUEUE_PORT 0x00C0 317 #define LMRC_IB_HI_QUEUE_PORT 0x00C4 318 #define LMRC_IB_SINGLE_QUEUE_PORT 0x00C8 319 320 #define LMRC_SUP_REPLY_POST_HOST_INDEX 0x030C 321 322 #define LMRC_MAX_REPLY_POST_HOST_INDEX 16 323 324 325 /* By default, the firmware programs for 8k of memory */ 326 #define LMRC_MFI_MIN_MEM 4096 327 #define LMRC_MFI_DEF_MEM 8192 328 #define LMRC_MFI_MAX_CMD 16 329 330 #define LMRC_MAX_SGE_CNT 0x50 331 332 333 #pragma pack(1) 334 335 /* 336 * MPT RAID MFA IO Descriptor. 337 * 338 * Note: The use of the lowest 8 bits for flags implies that an alignment 339 * of 256 bytes is required for the physical address. 340 */ 341 struct lmrc_raid_mfa_io_req_desc { 342 uint32_t RequestFlags:8; 343 uint32_t MessageAddress1:24; /* bits 31:8 */ 344 uint32_t MessageAddress2; /* bits 61:32 */ 345 }; 346 347 /* 348 * unions of Request Descriptors 349 */ 350 union lmrc_atomic_req_desc { 351 Mpi26AtomicRequestDescriptor_t rd_atomic; 352 uint32_t rd_reg; 353 }; 354 355 union lmrc_req_desc { 356 uint64_t rd_reg; 357 358 struct { 359 uint32_t rd_reg_lo; 360 uint32_t rd_reg_hi; 361 }; 362 363 lmrc_atomic_req_desc_t rd_atomic; 364 lmrc_raid_mfa_io_req_desc_t rd_mfa_io; 365 }; 366 367 368 union lmrc_mfi_cap { 369 struct { 370 uint32_t mc_support_fp_remote_lun:1; 371 uint32_t mc_support_additional_msix:1; 372 uint32_t mc_support_fastpath_wb:1; 373 uint32_t mc_support_max_255lds:1; 374 uint32_t mc_support_ndrive_r1_lb:1; 375 uint32_t mc_support_core_affinity:1; 376 uint32_t mc_support_security_protocol_cmds_fw:1; 377 uint32_t mc_support_ext_queue_depth:1; 378 uint32_t mc_support_ext_io_size:1; 379 uint32_t mc_reserved:23; 380 }; 381 uint32_t mc_reg; 382 }; 383 CTASSERT(sizeof (lmrc_mfi_cap_t) == 4); 384 385 union lmrc_mfi_sgl { 386 struct { 387 uint32_t ms32_phys_addr; 388 uint32_t ms32_length; 389 }; 390 struct { 391 uint64_t ms64_phys_addr; 392 uint32_t ms64_length; 393 }; 394 }; 395 396 struct lmrc_mfi_header { 397 uint8_t mh_cmd; /* 0x00 */ 398 uint8_t mh_sense_len; /* 0x01 */ 399 uint8_t mh_cmd_status; /* 0x02 */ 400 uint8_t mh_scsi_status; /* 0x03 */ 401 402 union { 403 lmrc_mfi_cap_t mh_drv_opts; /* 0x04 */ 404 struct { 405 uint8_t mh_target_id; /* 0x04 */ 406 union { 407 uint8_t mh_lun; /* 0x05 */ 408 uint8_t mh_access_byte; /* 0x05 */ 409 }; 410 uint8_t mh_cdb_len; /* 0x06 */ 411 uint8_t mh_sge_count; /* 0x07 */ 412 }; 413 }; 414 415 uint32_t mh_context; /* 0x08 */ 416 uint32_t mh_pad_0; /* 0x0c */ 417 418 uint16_t mh_flags; /* 0x10 */ 419 uint16_t mh_timeout; /* 0x12 */ 420 union { 421 uint32_t mh_data_xfer_len; /* 0x14 */ 422 uint32_t mh_lba_count; /* 0x14 */ 423 }; 424 }; 425 426 struct lmrc_mfi_init_payload { 427 uint64_t mi_queue_info_new_phys_addr; /* 0x18 */ 428 uint64_t mi_queue_info_old_phys_addr; /* 0x20 */ 429 uint64_t mi_driver_ver_phys_addr; /* 0x28 */ 430 }; 431 432 struct lmrc_mfi_io_payload { 433 uint64_t mio_sense_buf_phys_addr; /* 0x18 */ 434 uint64_t mio_start_lba; /* 0x20 */ 435 lmrc_mfi_sgl_t mio_sgl; /* 0x28 */ 436 }; 437 438 struct lmrc_mfi_pthru_payload { 439 uint64_t mp_sense_buf_phys_addr; /* 0x18 */ 440 uint8_t mp_cdb[16]; /* 0x20 */ 441 lmrc_mfi_sgl_t mp_sgl; /* 0x30 */ 442 }; 443 444 struct lmrc_mfi_dcmd_payload { 445 uint32_t md_opcode; /* 0x18 */ 446 447 union { /* 0x1c */ 448 uint8_t md_mbox_8[12]; 449 uint16_t md_mbox_16[6]; 450 uint32_t md_mbox_32[3]; 451 }; 452 453 lmrc_mfi_sgl_t md_sgl; /* 0x28 */ 454 }; 455 456 struct lmrc_mfi_abort_payload { 457 uint32_t ma_abort_context; /* 0x18 */ 458 uint32_t ma_pad_1; /* 0x1c */ 459 uint64_t ma_abort_mfi_phys_addr; /* 0x20 */ 460 }; 461 462 struct lmrc_mfi_frame { 463 lmrc_mfi_header_t mf_hdr; 464 union { 465 lmrc_mfi_init_payload_t mf_init; 466 lmrc_mfi_io_payload_t mf_io; 467 lmrc_mfi_pthru_payload_t mf_pthru; 468 lmrc_mfi_dcmd_payload_t mf_dcmd; 469 lmrc_mfi_abort_payload_t mf_abort; 470 uint8_t mf_raw[64 - sizeof (lmrc_mfi_header_t)]; 471 }; 472 }; 473 CTASSERT(offsetof(lmrc_mfi_frame_t, mf_init) == 0x18); 474 CTASSERT(sizeof (lmrc_mfi_frame_t) == 64); 475 476 struct lmrc_aen { 477 uint16_t aen_host_no; 478 uint16_t aen_cmd_status; 479 uint32_t aen_seqnum; 480 uint32_t aen_class_locale_word; 481 }; 482 483 /* 484 * Asynchronous Event Notifications 485 */ 486 #define LMRC_EVT_CFG_CLEARED 0x0004 487 #define LMRC_EVT_CTRL_PATROL_READ_COMPLETE 0x0023 488 #define LMRC_EVT_CTRL_PATROL_READ_RESUMED 0x0026 489 #define LMRC_EVT_CTRL_PATROL_READ_START 0x0027 490 #define LMRC_EVT_LD_BG_INIT_PROGRESS 0x0034 491 #define LMRC_EVT_LD_CC_COMPLETE 0x003a 492 #define LMRC_EVT_LD_CC_PROGRESS 0x0041 493 #define LMRC_EVT_LD_CC_STARTED 0x0042 494 #define LMRC_EVT_LD_INIT_ABORTED 0x0043 495 #define LMRC_EVT_LD_INIT_PROGRESS 0x0045 496 #define LMRC_EVT_LD_FAST_INIT_STARTED 0x0046 497 #define LMRC_EVT_LD_FULL_INIT_STARTED 0x0047 498 #define LMRC_EVT_LD_INIT_COMPLETE 0x0048 499 #define LMRC_EVT_LD_PROP_CHANGED 0x0049 500 #define LMRC_EVT_LD_STATE_CHANGE 0x0051 501 #define LMRC_EVT_PD_INSERTED 0x005b 502 #define LMRC_EVT_PD_PATROL_READ_PROGRESS 0x005e 503 #define LMRC_EVT_PD_REMOVED 0x0070 504 #define LMRC_EVT_PD_CHANGED 0x0072 505 #define LMRC_EVT_LD_CREATED 0x008a 506 #define LMRC_EVT_LD_DELETED 0x008b 507 #define LMRC_EVT_FOREIGN_CFG_IMPORTED 0x00db 508 #define LMRC_EVT_LD_OPTIMAL 0x00f9 509 #define LMRC_EVT_LD_OFFLINE 0x00fc 510 #define LMRC_EVT_PD_RESET 0x010c 511 #define LMRC_EVT_CTRL_PATROL_READ_CANT_START 0x0124 512 #define LMRC_EVT_CTRL_PROP_CHANGED 0x012f 513 #define LMRC_EVT_LD_BBT_CLEARED 0x014f 514 #define LMRC_EVT_CTRL_HOST_BUS_SCAN_REQD 0x0152 515 #define LMRC_EVT_LD_AVAILABLE 0x0172 516 #define LMRC_EVT_CTRL_PERF_COLLECTION 0x017e 517 #define LMRC_EVT_CTRL_BOOTDEV_SET 0x01ec 518 #define LMRC_EVT_CTRL_BOOTDEV_RESET 0x01f3 519 #define LMRC_EVT_CTRL_PERSONALITY_CHANGE 0x0206 520 #define LMRC_EVT_CTRL_PERSONALITY_CHANGE_PEND 0x0222 521 #define LMRC_EVT_CTRL_NR_OF_VALID_SNAPDUMP 0x024e 522 523 #define LMRC_EVT_CLASS_DEBUG -2 524 #define LMRC_EVT_CLASS_PROGRESS -1 525 #define LMRC_EVT_CLASS_INFO 0 526 #define LMRC_EVT_CLASS_WARNING 1 527 #define LMRC_EVT_CLASS_CRITICAL 2 528 #define LMRC_EVT_CLASS_FATAL 3 529 #define LMRC_EVT_CLASS_DEAD 4 530 531 #define LMRC_EVT_LOCALE_LD 0x0001 532 #define LMRC_EVT_LOCALE_PD 0x0002 533 #define LMRC_EVT_LOCALE_ENCL 0x0004 534 #define LMRC_EVT_LOCALE_BBU 0x0008 535 #define LMRC_EVT_LOCALE_SAS 0x0010 536 #define LMRC_EVT_LOCALE_CTRL 0x0020 537 #define LMRC_EVT_LOCALE_CONFIG 0x0040 538 #define LMRC_EVT_LOCALE_CLUSTER 0x0080 539 #define LMRC_EVT_LOCALE_ALL 0xffff 540 541 union lmrc_evt_class_locale { 542 struct { 543 uint16_t ecl_locale; 544 uint8_t ecl_rsvd; 545 int8_t ecl_class; 546 }; 547 uint32_t ecl_word; 548 }; 549 550 struct lmrc_evt_log_info { 551 uint32_t eli_newest_seqnum; 552 uint32_t eli_oldest_seqnum; 553 uint32_t eli_clear_seqnum; 554 uint32_t eli_shutdown_seqnum; 555 uint32_t eli_boot_seqnum; 556 }; 557 558 struct lmrc_evtarg_ld { 559 uint16_t el_tgtid; 560 uint8_t el_ld_id; 561 uint8_t el_rsvd; 562 }; 563 564 struct lmrc_evtarg_pd { 565 uint16_t ep_dev_id; 566 uint8_t ep_enc_id; 567 uint8_t ep_slot; 568 }; 569 570 struct lmrc_evt { 571 uint32_t evt_seqnum; 572 uint32_t evt_timestamp; 573 uint32_t evt_code; 574 uint16_t evt_locale; 575 uint8_t evt_rsvd; 576 int8_t evt_class; 577 uint8_t evt_argtype; 578 uint8_t evt_rsvd2[15]; 579 union { 580 lmrc_evtarg_ld_t evt_ld; 581 lmrc_evtarg_pd_t evt_pd; 582 char evt_str[96]; 583 }; 584 char evt_descr[128]; 585 }; 586 CTASSERT(sizeof (lmrc_evt_t) == 256); 587 588 /* 589 * SAS controller properties 590 */ 591 struct lmrc_ctrl_prop { 592 uint16_t cp_seq_num; 593 uint16_t cp_pred_fail_poll_interval; 594 uint16_t cp_intr_throttle_count; 595 uint16_t cp_intr_throttle_timeouts; 596 uint8_t cp_rebuild_rate; 597 uint8_t cp_patrol_read_rate; 598 uint8_t cp_bgi_rate; 599 uint8_t cp_cc_rate; 600 uint8_t cp_recon_rate; 601 uint8_t cp_cache_flush_interval; 602 uint8_t cp_spinup_drv_count; 603 uint8_t cp_spinup_delay; 604 uint8_t cp_cluster_enable; 605 uint8_t cp_coercion_mode; 606 uint8_t cp_alarm_enable; 607 uint8_t cp_disable_auto_rebuild; 608 uint8_t cp_disable_battery_warn; 609 uint8_t cp_ecc_bucket_size; 610 uint16_t cp_ecc_bucket_leak_rate; 611 uint8_t cp_restore_hotspare_on_insertion; 612 uint8_t cp_expose_encl_devices; 613 uint8_t cp_maintain_pd_fail_history; 614 uint8_t cp_disallow_host_request_reordering; 615 uint8_t cp_abort_cc_on_error; 616 uint8_t cp_load_balance_mode; 617 uint8_t cp_disable_auto_detect_backplane; 618 uint8_t cp_snap_vd_space; 619 620 struct { 621 uint32_t cp_copy_back_disabled:1; 622 uint32_t cp_smarter_enabled:1; 623 uint32_t cp_pr_correct_unconfigured_areas:1; 624 uint32_t cp_use_FDE_only:1; 625 uint32_t cp_disable_NCQ:1; 626 uint32_t cp_SSD_smarter_enabled:1; 627 uint32_t cp_SSD_patrol_read_enabled:1; 628 uint32_t cp_enable_spin_down_unconfigured:1; 629 uint32_t cp_auto_enhanced_import:1; 630 uint32_t cp_enable_secret_key_control:1; 631 uint32_t cp_disable_online_ctrl_reset:1; 632 uint32_t cp_allow_boot_with_pinned_cache:1; 633 uint32_t cp_disable_spin_down_HS:1; 634 uint32_t cp_enable_JBOD:1; 635 uint32_t cp_disable_cache_bypass:1; 636 uint32_t cp_use_disk_activity_for_locate:1; 637 uint32_t cp_enable_PI:1; 638 uint32_t cp_prevent_PI_import:1; 639 uint32_t cp_use_global_spares_for_emergency:1; 640 uint32_t cp_use_unconf_good_for_emergency:1; 641 uint32_t cp_use_emergency_spares_for_smarter:1; 642 uint32_t cp_force_sgpio_for_quad_only:1; 643 uint32_t cp_enable_config_auto_balance:1; 644 uint32_t cp_enable_virtual_cache:1; 645 uint32_t cp_enable_auto_lock_recovery:1; 646 uint32_t cp_disable_immediate_io:1; 647 uint32_t cp_disable_T10_rebuild_assist:1; 648 uint32_t cp_ignore64_ld_restriction:1; 649 uint32_t cp_enable_sw_zone:1; 650 uint32_t cp_limit_max_rate_SATA_3G:1; 651 uint32_t cp_reserved:2; 652 }; 653 uint8_t cp_auto_snap_vd_space; 654 uint8_t cp_view_space; 655 uint16_t cp_spin_down_time; 656 uint8_t cp_reserved2[24]; 657 }; 658 659 struct lmrc_image_comp { 660 char ic_name[8]; 661 char ic_version[32]; 662 char ic_build_date[16]; 663 char ic_built_time[16]; 664 }; 665 666 /* 667 * SAS controller information 668 */ 669 struct lmrc_ctrl_info { 670 /* PCI device information */ 671 struct { 672 uint16_t pci_vendor_id; 673 uint16_t pci_device_id; 674 uint16_t pci_sub_vendor_id; 675 uint16_t pci_sub_device_id; 676 uint8_t pci_reserved[24]; 677 } ci_pci; 678 679 /* Host interface information */ 680 struct { 681 uint8_t hi_PCIX:1; 682 uint8_t hi_PCIE:1; 683 uint8_t hi_iSCSI:1; 684 uint8_t hi_SAS_3G:1; 685 uint8_t hi_reserved_0:4; 686 uint8_t hi_reserved_1[6]; 687 uint8_t hi_port_count; 688 uint64_t hi_port_addr[8]; 689 } ci_host_interface; 690 691 /* Target interface information */ 692 struct { 693 uint8_t di_SPI:1; 694 uint8_t di_SAS_3G:1; 695 uint8_t di_SATA_1_5G:1; 696 uint8_t di_SATA_3G:1; 697 uint8_t di_reserved_0:4; 698 uint8_t di_reserved_1[6]; 699 uint8_t di_port_count; 700 uint64_t di_port_addr[8]; 701 } ci_device_interface; 702 703 uint32_t ci_image_check_word; 704 705 uint32_t ci_image_component_count; 706 lmrc_image_comp_t ci_image_component[8]; 707 708 uint32_t ci_pending_image_component_count; 709 lmrc_image_comp_t ci_pending_image_component[8]; 710 711 uint8_t ci_max_arms; 712 uint8_t ci_max_spans; 713 uint8_t ci_max_arrays; 714 uint8_t ci_max_lds; 715 char ci_product_name[80]; 716 char ci_serial_no[32]; 717 718 /* 719 * Hardware features 720 */ 721 struct { 722 uint32_t hw_bbu:1; 723 uint32_t hw_alarm:1; 724 uint32_t hw_nvram:1; 725 uint32_t hw_uart:1; 726 uint32_t hw_reserved:28; 727 } ci_hw_present; 728 729 uint32_t current_fw_time; 730 731 /* Maximum data transfer sizes */ 732 uint16_t ci_max_concurrent_cmds; 733 uint16_t ci_max_sge_count; 734 uint32_t ci_max_request_size; 735 736 /* Logical and physical device counts */ 737 uint16_t ci_ld_present_count; 738 uint16_t ci_ld_degraded_count; 739 uint16_t ci_ld_offline_count; 740 741 uint16_t ci_pd_present_count; 742 uint16_t ci_pd_disk_present_count; 743 uint16_t ci_pd_disk_pred_failure_count; 744 uint16_t ci_pd_disk_failed_count; 745 746 /* Memory size information */ 747 uint16_t ci_nvram_size; 748 uint16_t ci_memory_size; 749 uint16_t ci_flash_size; 750 751 /* Error counters */ 752 uint16_t ci_mem_correctable_error_count; 753 uint16_t ci_mem_uncorrectable_error_count; 754 755 /* Cluster information */ 756 uint8_t ci_cluster_permitted; 757 uint8_t ci_cluster_active; 758 759 /* Additional max data transfer sizes */ 760 uint16_t ci_max_stripes_per_io; 761 762 /* Controller capabilities structures */ 763 struct { 764 uint32_t rl_raid_level_0:1; 765 uint32_t rl_raid_level_1:1; 766 uint32_t rl_raid_level_5:1; 767 uint32_t rl_raid_level_1E:1; 768 uint32_t rl_raid_level_6:1; 769 uint32_t rl_reserved:27; 770 } ci_raid_levels; 771 772 struct { 773 uint32_t ao_rbld_rate:1; 774 uint32_t ao_cc_rate:1; 775 uint32_t ao_bgi_rate:1; 776 uint32_t ao_recon_rate:1; 777 uint32_t ao_patrol_rate:1; 778 uint32_t ao_alarm_control:1; 779 uint32_t ao_cluster_supported:1; 780 uint32_t ao_bbu:1; 781 uint32_t ao_spanning_allowed:1; 782 uint32_t ao_dedicated_hotspares:1; 783 uint32_t ao_revertible_hotspares:1; 784 uint32_t ao_foreign_config_import:1; 785 uint32_t ao_self_diagnostic:1; 786 uint32_t ao_mixed_redundancy_arr:1; 787 uint32_t ao_global_hot_spares:1; 788 uint32_t ao_reserved:17; 789 } ci_adapter_opts; 790 791 struct { 792 uint32_t ld_read_policy:1; 793 uint32_t ld_write_policy:1; 794 uint32_t ld_io_policy:1; 795 uint32_t ld_access_policy:1; 796 uint32_t ld_disk_cache_policy:1; 797 uint32_t ld_reserved:27; 798 } ci_ld_opts; 799 800 struct { 801 uint8_t raid_stripe_sz_min; 802 uint8_t raid_stripe_sz_max; 803 uint8_t raid_reserved[2]; 804 } ci_raid_opts; 805 806 struct { 807 uint32_t pd_force_online:1; 808 uint32_t pd_force_offline:1; 809 uint32_t pd_force_rebuild:1; 810 uint32_t pd_reserved:29; 811 } ci_pd_opts; 812 813 struct { 814 uint32_t pd_ctrl_supports_sas:1; 815 uint32_t pd_ctrl_supports_sata:1; 816 uint32_t pd_allow_mix_in_encl:1; 817 uint32_t pd_allow_mix_in_ld:1; 818 uint32_t pd_allow_sata_in_cluster:1; 819 uint32_t pd_reserved:27; 820 } ci_pd_mix_support; 821 822 /* ECC single-bit error bucket information */ 823 uint8_t ci_ecc_bucket_count; 824 uint8_t ci_reserved_2[11]; 825 826 /* Controller properties */ 827 lmrc_ctrl_prop_t ci_prop; 828 829 char ci_package_version[0x60]; 830 831 uint64_t ci_device_interface_port_addr2[8]; 832 uint8_t ci_reserved3[128]; 833 834 struct { 835 uint16_t pd_min_pd_raid_level_0:4; 836 uint16_t pd_max_pd_raid_level_0:12; 837 838 uint16_t pd_min_pd_raid_level_1:4; 839 uint16_t pd_max_pd_raid_level_1:12; 840 841 uint16_t pd_min_pd_raid_level_5:4; 842 uint16_t pd_max_pd_raid_level_5:12; 843 844 uint16_t pd_min_pd_raid_level_1E:4; 845 uint16_t pd_max_pd_raid_level_1E:12; 846 847 uint16_t pd_min_pd_raid_level_6:4; 848 uint16_t pd_max_pd_raid_level_6:12; 849 850 uint16_t pd_min_pd_raid_level_10:4; 851 uint16_t pd_max_pd_raid_level_10:12; 852 853 uint16_t pd_min_pd_raid_level_50:4; 854 uint16_t pd_max_pd_raid_level_50:12; 855 856 uint16_t pd_min_pd_raid_level_60:4; 857 uint16_t pd_max_pd_raid_level_60:12; 858 859 uint16_t pd_min_pd_raid_level_1E_RLQ0:4; 860 uint16_t pd_max_pd_raid_level_1E_RLQ0:12; 861 862 uint16_t pd_min_pd_raid_level_1E0_RLQ0:4; 863 uint16_t pd_max_pd_raid_level_1E0_RLQ0:12; 864 865 uint16_t pd_reserved[6]; 866 } ci_pds_for_raid_levels; 867 868 uint16_t ci_max_pds; /* 0x780 */ 869 uint16_t ci_max_ded_HSPs; /* 0x782 */ 870 uint16_t ci_max_global_HSPs; /* 0x784 */ 871 uint16_t ci_ddf_size; /* 0x786 */ 872 uint8_t ci_max_lds_per_array; /* 0x788 */ 873 uint8_t ci_partitions_in_DDF; /* 0x789 */ 874 uint8_t ci_lock_key_binding; /* 0x78a */ 875 uint8_t ci_max_PITs_per_ld; /* 0x78b */ 876 uint8_t ci_max_views_per_ld; /* 0x78c */ 877 uint8_t ci_max_target_id; /* 0x78d */ 878 uint16_t ci_max_bvl_vd_size; /* 0x78e */ 879 880 uint16_t ci_max_configurable_SSC_size; /* 0x790 */ 881 uint16_t ci_current_SSC_size; /* 0x792 */ 882 883 char ci_expander_fw_version[12]; /* 0x794 */ 884 885 uint16_t ci_PFK_trial_time_remaining; /* 0x7A0 */ 886 887 uint16_t ci_cache_memory_size; /* 0x7A2 */ 888 889 struct { /* 0x7A4 */ 890 uint32_t ao2_support_PI_controller:1; 891 uint32_t ao2_support_ld_PI_type1:1; 892 uint32_t ao2_support_ld_PI_type2:1; 893 uint32_t ao2_support_ld_PI_type3:1; 894 uint32_t ao2_support_ld_BBM_info:1; 895 uint32_t ao2_support_shield_state:1; 896 uint32_t ao2_block_SSD_write_cache_change:1; 897 uint32_t ao2_support_suspend_resume_b_Gops:1; 898 uint32_t ao2_support_emergency_spares:1; 899 uint32_t ao2_support_set_link_speed:1; 900 uint32_t ao2_support_boot_time_PFK_change:1; 901 uint32_t ao2_support_JBOD:1; 902 uint32_t ao2_disable_online_PFK_change:1; 903 uint32_t ao2_support_perf_tuning:1; 904 uint32_t ao2_support_SSD_patrol_read:1; 905 uint32_t ao2_real_time_scheduler:1; 906 907 uint32_t ao2_support_reset_now:1; 908 uint32_t ao2_support_emulated_drives:1; 909 uint32_t ao2_headless_mode:1; 910 uint32_t ao2_dedicated_hot_spares_limited:1; 911 912 uint32_t ao2_support_uneven_spans:1; 913 uint32_t ao2_reserved:11; 914 } ci_adapter_opts2; 915 916 uint8_t ci_driver_version[32]; /* 0x7A8 */ 917 uint8_t ci_max_DAP_d_count_spinup60; /* 0x7C8 */ 918 uint8_t ci_temperature_ROC; /* 0x7C9 */ 919 uint8_t ci_temperature_ctrl; /* 0x7CA */ 920 uint8_t ci_reserved4; /* 0x7CB */ 921 uint16_t ci_max_configurable_pds; /* 0x7CC */ 922 923 uint8_t ci_reserved5[2]; /* 0x7CD reserved */ 924 925 struct { 926 uint32_t cl_peer_is_present:1; 927 uint32_t cl_peer_is_incompatible:1; 928 929 uint32_t cl_hw_incompatible:1; 930 uint32_t cl_fw_version_mismatch:1; 931 uint32_t cl_ctrl_prop_incompatible:1; 932 uint32_t cl_premium_feature_mismatch:1; 933 uint32_t cl_reserved:26; 934 } ci_cluster; 935 936 char ci_cluster_id[16]; /* 0x7D4 */ 937 938 char ci_reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 939 940 struct { /* 0x7E8 */ 941 uint32_t ao3_support_personality_change:2; 942 uint32_t ao3_support_thermal_poll_interval:1; 943 uint32_t ao3_support_disable_immediate_IO:1; 944 uint32_t ao3_support_T10_rebuild_assist:1; 945 uint32_t ao3_support_max_ext_lds:1; 946 uint32_t ao3_support_crash_dump:1; 947 uint32_t ao3_support_sw_zone:1; 948 uint32_t ao3_support_debug_queue:1; 949 uint32_t ao3_support_NV_cache_erase:1; 950 uint32_t ao3_support_force_to_512e:1; 951 uint32_t ao3_support_HOQ_rebuild:1; 952 uint32_t ao3_support_allowed_opsfor_drv_removal:1; 953 uint32_t ao3_support_drv_activity_LED_setting:1; 954 uint32_t ao3_support_NVDRAM:1; 955 uint32_t ao3_support_force_flash:1; 956 uint32_t ao3_support_disable_SES_monitoring:1; 957 uint32_t ao3_support_cache_bypass_modes:1; 958 uint32_t ao3_support_securityon_JBOD:1; 959 uint32_t ao3_discard_cache_during_ld_delete:1; 960 uint32_t ao3_support_TTY_log_compression:1; 961 uint32_t ao3_support_CPLD_update:1; 962 uint32_t ao3_support_disk_cache_setting_for_sys_pds:1; 963 uint32_t ao3_support_extended_SSC_size:1; 964 uint32_t ao3_use_seq_num_jbod_FP:1; 965 uint32_t ao3_reserved:7; 966 } ci_adapter_opts3; 967 968 uint8_t ci_pad_cpld[16]; 969 970 struct { 971 uint16_t ao4_ctrl_info_ext_supported:1; 972 uint16_t ao4_support_ibutton_less:1; 973 uint16_t ao4_supported_enc_algo:1; 974 uint16_t ao4_support_encrypted_mfc:1; 975 uint16_t ao4_image_upload_supported:1; 976 uint16_t ao4_support_SES_ctrl_in_multipath_cfg:1; 977 uint16_t ao4_support_pd_map_target_id:1; 978 uint16_t ao4_fw_swaps_bbu_vpd_info:1; 979 uint16_t ao4_reserved:8; 980 } ci_adapter_opts4; 981 982 uint8_t ci_pad[0x800 - 0x7FE]; /* 0x7FE */ 983 }; 984 985 #pragma pack(0) 986 987 /* 988 * Request descriptor types, in addition to those defined by mpi2.h 989 * 990 * FreeBSD and Linux drivers shift these, while mpi2.h defines them 991 * pre-shifted. The latter seems more sensible. 992 * 993 * XXX: LMRC_REQ_DESCRIPT_FLAGS_MFA has the same value as 994 * MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET. Why? 995 */ 996 #define LMRC_REQ_DESCRIPT_FLAGS_MFA 0x02 997 #define LMRC_REQ_DESCRIPT_FLAGS_NO_LOCK 0x04 998 #define LMRC_REQ_DESCRIPT_FLAGS_LD_IO 0x0e 999 1000 #define MPI2_TYPE_CUDA 0x2 1001 1002 #endif /* _LMRC_REG_H */ 1003