15cff7825Smh27603 /* 25cff7825Smh27603 * CDDL HEADER START 35cff7825Smh27603 * 45cff7825Smh27603 * The contents of this file are subject to the terms of the 55cff7825Smh27603 * Common Development and Distribution License (the "License"). 65cff7825Smh27603 * You may not use this file except in compliance with the License. 75cff7825Smh27603 * 85cff7825Smh27603 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 95cff7825Smh27603 * or http://www.opensolaris.org/os/licensing. 105cff7825Smh27603 * See the License for the specific language governing permissions 115cff7825Smh27603 * and limitations under the License. 125cff7825Smh27603 * 135cff7825Smh27603 * When distributing Covered Code, include this CDDL HEADER in each 145cff7825Smh27603 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 155cff7825Smh27603 * If applicable, add the following below this CDDL HEADER, with the 165cff7825Smh27603 * fields enclosed by brackets "[]" replaced with your own identifying 175cff7825Smh27603 * information: Portions Copyright [yyyy] [name of copyright owner] 185cff7825Smh27603 * 195cff7825Smh27603 * CDDL HEADER END 205cff7825Smh27603 */ 215cff7825Smh27603 /* 22fcddbe1fSMark Haywood * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 235cff7825Smh27603 * Use is subject to license terms. 245cff7825Smh27603 */ 25444f66e7SMark Haywood /* 26444f66e7SMark Haywood * Copyright (c) 2009, Intel Corporation. 27444f66e7SMark Haywood * All Rights Reserved. 28444f66e7SMark Haywood */ 295cff7825Smh27603 305cff7825Smh27603 #ifndef _SYS_CPUDRV_H 315cff7825Smh27603 #define _SYS_CPUDRV_H 325cff7825Smh27603 335cff7825Smh27603 #include <sys/promif.h> 345cff7825Smh27603 #include <sys/cpuvar.h> 355cff7825Smh27603 #include <sys/taskq.h> 365cff7825Smh27603 375cff7825Smh27603 #ifdef __cplusplus 385cff7825Smh27603 extern "C" { 395cff7825Smh27603 #endif 405cff7825Smh27603 415cff7825Smh27603 #ifdef _KERNEL 425cff7825Smh27603 435cff7825Smh27603 /* 445cff7825Smh27603 * CPU power management data 455cff7825Smh27603 */ 465cff7825Smh27603 /* 475cff7825Smh27603 * Data related to a particular speed. 485cff7825Smh27603 * 495cff7825Smh27603 * All per speed data nodes for a CPU are linked together using down_spd. 505cff7825Smh27603 * The link list is ordered with first node containing data for 515cff7825Smh27603 * normal (maximum) speed. up_spd points to the next speed up. Currently 525cff7825Smh27603 * all up_spd's point to the normal speed but this can be changed in future. 535cff7825Smh27603 * quant_cnt is the number of ticks when monitoring system will be called 545cff7825Smh27603 * next. There are different quant_cnt for different speeds. 555cff7825Smh27603 * 565cff7825Smh27603 * Note that 'speed' has different meaning depending upon the platform. 575cff7825Smh27603 * On SPARC, the speed is really a divisor of the maximum speed (e.g., a speed 585cff7825Smh27603 * of 2 means that it's 1/2 the maximum speed). On x86, speed is a processor 595cff7825Smh27603 * frequency. 605cff7825Smh27603 */ 615cff7825Smh27603 typedef struct cpudrv_pm_spd { 625cff7825Smh27603 uint_t speed; /* platform dependent notion */ 635cff7825Smh27603 uint_t quant_cnt; /* quantum count in ticks */ 645cff7825Smh27603 struct cpudrv_pm_spd *down_spd; /* ptr to next speed down */ 655cff7825Smh27603 struct cpudrv_pm_spd *up_spd; /* ptr to next speed up */ 665cff7825Smh27603 uint_t idle_hwm; /* down if idle thread >= hwm */ 675cff7825Smh27603 uint_t idle_lwm; /* up if idle thread < lwm */ 685cff7825Smh27603 uint_t idle_bhwm_cnt; /* # of iters idle is < hwm */ 695cff7825Smh27603 uint_t idle_blwm_cnt; /* # of iters idle is < lwm */ 705cff7825Smh27603 uint_t user_hwm; /* up if user thread > hwm */ 715cff7825Smh27603 int user_lwm; /* down if user thread <= lwm */ 725cff7825Smh27603 int pm_level; /* power level for framework */ 735cff7825Smh27603 } cpudrv_pm_spd_t; 745cff7825Smh27603 755cff7825Smh27603 /* 765cff7825Smh27603 * Power management data 775cff7825Smh27603 */ 785cff7825Smh27603 typedef struct cpudrv_pm { 795cff7825Smh27603 cpudrv_pm_spd_t *head_spd; /* ptr to head of speed */ 805cff7825Smh27603 cpudrv_pm_spd_t *cur_spd; /* ptr to current speed */ 815cff7825Smh27603 uint_t num_spd; /* number of speeds */ 825cff7825Smh27603 hrtime_t lastquan_mstate[NCMSTATES]; /* last quantum's mstate */ 83fcddbe1fSMark Haywood clock_t lastquan_ticks; /* last quantum's clock tick */ 845cff7825Smh27603 int pm_busycnt; /* pm_busy_component() count */ 85444f66e7SMark Haywood ddi_taskq_t *tq; /* taskq handler for CPU monitor */ 860e751525SEric Saxe timeout_id_t timeout_id; /* cpudrv_monitor()'s timeout_id */ 875cff7825Smh27603 int timeout_count; /* count dispatched timeouts */ 885cff7825Smh27603 kmutex_t timeout_lock; /* protect timeout_count */ 895cff7825Smh27603 kcondvar_t timeout_cv; /* wait on timeout_count change */ 905cff7825Smh27603 #if defined(__x86) 917f606aceSMark Haywood kthread_t *pm_governor_thread; /* governor thread */ 9217353130SMark Haywood cpudrv_pm_spd_t *top_spd; /* ptr to effective head speed */ 935cff7825Smh27603 #endif 9468afbec1Smh27603 boolean_t pm_started; /* PM really started */ 955cff7825Smh27603 } cpudrv_pm_t; 965cff7825Smh27603 975cff7825Smh27603 /* 985cff7825Smh27603 * Idle & user threads water marks in percentage 995cff7825Smh27603 */ 1005cff7825Smh27603 #if defined(__x86) 1010e751525SEric Saxe #define CPUDRV_IDLE_HWM 85 /* idle high water mark */ 1020e751525SEric Saxe #define CPUDRV_IDLE_LWM 70 /* idle low water mark */ 1030e751525SEric Saxe #define CPUDRV_IDLE_BLWM_CNT_MAX 1 /* # of iters idle can be < lwm */ 1040e751525SEric Saxe #define CPUDRV_IDLE_BHWM_CNT_MAX 1 /* # of iters idle can be < hwm */ 1055cff7825Smh27603 #else 1060e751525SEric Saxe #define CPUDRV_IDLE_HWM 98 /* idle high water mark */ 1070e751525SEric Saxe #define CPUDRV_IDLE_LWM 8 /* idle low water mark */ 1080e751525SEric Saxe #define CPUDRV_IDLE_BLWM_CNT_MAX 2 /* # of iters idle can be < lwm */ 1090e751525SEric Saxe #define CPUDRV_IDLE_BHWM_CNT_MAX 2 /* # of iters idle can be < hwm */ 1105cff7825Smh27603 #endif 1110e751525SEric Saxe #define CPUDRV_USER_HWM 20 /* user high water mark */ 1120e751525SEric Saxe #define CPUDRV_IDLE_BUF_ZONE 4 /* buffer zone when going down */ 1135cff7825Smh27603 1145cff7825Smh27603 1155cff7825Smh27603 /* 1165cff7825Smh27603 * Maximums for creating 'pm-components' property 1175cff7825Smh27603 */ 1180e751525SEric Saxe #define CPUDRV_COMP_MAX_DIG 4 /* max digits in power level */ 1195cff7825Smh27603 /* or divisor */ 1200e751525SEric Saxe #define CPUDRV_COMP_MAX_VAL 9999 /* max value in above digits */ 1215cff7825Smh27603 1225cff7825Smh27603 /* 1235cff7825Smh27603 * Component number for calls to PM framework 1245cff7825Smh27603 */ 1250e751525SEric Saxe #define CPUDRV_COMP_NUM 0 /* first component is 0 */ 1265cff7825Smh27603 1275cff7825Smh27603 /* 1285cff7825Smh27603 * Quantum counts for normal and other clock speeds in terms of ticks. 1295cff7825Smh27603 * 1305cff7825Smh27603 * In determining the quantum count, we need to balance two opposing factors: 1315cff7825Smh27603 * 1325cff7825Smh27603 * 1) Minimal delay when user start using the CPU that is in low 1335cff7825Smh27603 * power mode -- requires that we monitor more frequently, 1345cff7825Smh27603 * 1355cff7825Smh27603 * 2) Extra code executed because of frequent monitoring -- requires 1365cff7825Smh27603 * that we monitor less frequently. 1375cff7825Smh27603 * 1385cff7825Smh27603 * We reach a tradeoff between these two requirements by monitoring 1390e751525SEric Saxe * more frequently when we are in low speed mode (CPUDRV_QUANT_CNT_OTHR) 1405cff7825Smh27603 * so we can bring the CPU up without user noticing it. Moreover, at low 1415cff7825Smh27603 * speed we are not using CPU much so extra code execution should be fine. 1425cff7825Smh27603 * Since we are in no hurry to bring CPU down and at normal speed and we 1435cff7825Smh27603 * might really be using the CPU fully, we monitor less frequently 1440e751525SEric Saxe * (CPUDRV_QUANT_CNT_NORMAL). 1455cff7825Smh27603 */ 146fc68e77cSmh27603 #if defined(__x86) 1470e751525SEric Saxe #define CPUDRV_QUANT_CNT_NORMAL (hz * 1) /* 1 sec */ 148fc68e77cSmh27603 #else 1490e751525SEric Saxe #define CPUDRV_QUANT_CNT_NORMAL (hz * 5) /* 5 sec */ 150fc68e77cSmh27603 #endif 1510e751525SEric Saxe #define CPUDRV_QUANT_CNT_OTHR (hz * 1) /* 1 sec */ 1525cff7825Smh27603 1535cff7825Smh27603 /* 1545cff7825Smh27603 * Taskq parameters 1555cff7825Smh27603 */ 1560e751525SEric Saxe #define CPUDRV_TASKQ_THREADS 1 /* # threads to run CPU monitor */ 1570e751525SEric Saxe #define CPUDRV_TASKQ_MIN 2 /* min # of taskq entries */ 1580e751525SEric Saxe #define CPUDRV_TASKQ_MAX 2 /* max # of taskq entries */ 1595cff7825Smh27603 1605cff7825Smh27603 1615cff7825Smh27603 /* 1625cff7825Smh27603 * Device driver state structure 1635cff7825Smh27603 */ 1645cff7825Smh27603 typedef struct cpudrv_devstate { 1655cff7825Smh27603 dev_info_t *dip; /* devinfo handle */ 1660e751525SEric Saxe cpu_t *cp; /* CPU data for this node */ 1675cff7825Smh27603 processorid_t cpu_id; /* CPU number for this node */ 1685cff7825Smh27603 cpudrv_pm_t cpudrv_pm; /* power management data */ 1695cff7825Smh27603 kmutex_t lock; /* protects state struct */ 1705cff7825Smh27603 } cpudrv_devstate_t; 1715cff7825Smh27603 1725cff7825Smh27603 extern void *cpudrv_state; 1730e751525SEric Saxe extern boolean_t cpudrv_enabled; 1745cff7825Smh27603 1755cff7825Smh27603 /* 1765cff7825Smh27603 * Debugging definitions 1775cff7825Smh27603 */ 1785cff7825Smh27603 #ifdef DEBUG 1795cff7825Smh27603 #define D_INIT 0x00000001 1805cff7825Smh27603 #define D_FINI 0x00000002 1815cff7825Smh27603 #define D_ATTACH 0x00000004 1825cff7825Smh27603 #define D_DETACH 0x00000008 1835cff7825Smh27603 #define D_POWER 0x00000010 1845cff7825Smh27603 #define D_PM_INIT 0x00000020 1855cff7825Smh27603 #define D_PM_FREE 0x00000040 1865cff7825Smh27603 #define D_PM_COMP_CREATE 0x00000080 1875cff7825Smh27603 #define D_PM_MONITOR 0x00000100 1885cff7825Smh27603 #define D_PM_MONITOR_VERBOSE 0x00000200 1895cff7825Smh27603 #define D_PM_MONITOR_DELAY 0x00000400 1905cff7825Smh27603 1915cff7825Smh27603 extern uint_t cpudrv_debug; 1925cff7825Smh27603 1935cff7825Smh27603 #define _PRINTF prom_printf 1945cff7825Smh27603 #define DPRINTF(flag, args) if (cpudrv_debug & flag) _PRINTF args; 1955cff7825Smh27603 #else 1965cff7825Smh27603 #define DPRINTF(flag, args) 1975cff7825Smh27603 #endif /* DEBUG */ 1985cff7825Smh27603 1990e751525SEric Saxe extern int cpudrv_change_speed(cpudrv_devstate_t *, cpudrv_pm_spd_t *); 2000e751525SEric Saxe extern boolean_t cpudrv_get_cpu_id(dev_info_t *, processorid_t *); 2010e751525SEric Saxe extern boolean_t cpudrv_is_governor_thread(cpudrv_pm_t *); 2020e751525SEric Saxe extern boolean_t cpudrv_mach_init(cpudrv_devstate_t *); 203444f66e7SMark Haywood extern boolean_t cpudrv_mach_fini(cpudrv_devstate_t *); 204444f66e7SMark Haywood extern boolean_t cpudrv_power_ready(cpu_t *); 2050e751525SEric Saxe extern boolean_t cpudrv_is_enabled(cpudrv_devstate_t *); 2060e751525SEric Saxe extern void cpudrv_set_supp_freqs(cpudrv_devstate_t *); 207*6af9d452Saubrey.li@intel.com extern int cpudrv_get_cpu(cpudrv_devstate_t *); 2085cff7825Smh27603 2095cff7825Smh27603 #endif /* _KERNEL */ 2105cff7825Smh27603 2115cff7825Smh27603 #ifdef __cplusplus 2125cff7825Smh27603 } 2135cff7825Smh27603 #endif 2145cff7825Smh27603 2155cff7825Smh27603 #endif /* _SYS_CPUDRV_H */ 216