1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 1992-2002 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #ifndef _SYS_ECPPREG_H 28*7c478bd9Sstevel@tonic-gate #define _SYS_ECPPREG_H 29*7c478bd9Sstevel@tonic-gate 30*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 31*7c478bd9Sstevel@tonic-gate extern "C" { 32*7c478bd9Sstevel@tonic-gate #endif 33*7c478bd9Sstevel@tonic-gate 34*7c478bd9Sstevel@tonic-gate /* 35*7c478bd9Sstevel@tonic-gate * Register definitions for the National Semiconductor PC87332VLJ 36*7c478bd9Sstevel@tonic-gate * SuperI/O chip. 37*7c478bd9Sstevel@tonic-gate */ 38*7c478bd9Sstevel@tonic-gate 39*7c478bd9Sstevel@tonic-gate /* 40*7c478bd9Sstevel@tonic-gate * configuration registers 41*7c478bd9Sstevel@tonic-gate */ 42*7c478bd9Sstevel@tonic-gate struct config_reg { 43*7c478bd9Sstevel@tonic-gate uint8_t index; 44*7c478bd9Sstevel@tonic-gate uint8_t data; 45*7c478bd9Sstevel@tonic-gate }; 46*7c478bd9Sstevel@tonic-gate 47*7c478bd9Sstevel@tonic-gate /* index values for the configuration registers */ 48*7c478bd9Sstevel@tonic-gate #define FER 0x0 /* Function Enable Register */ 49*7c478bd9Sstevel@tonic-gate #define FAR 0x1 /* Function Address Register */ 50*7c478bd9Sstevel@tonic-gate #define PTR 0x2 /* Power and Test Register */ 51*7c478bd9Sstevel@tonic-gate #define FCR 0x3 /* Function Control Register */ 52*7c478bd9Sstevel@tonic-gate #define PCR 0x4 /* Printer Control Register */ 53*7c478bd9Sstevel@tonic-gate #define KRR 0x5 /* Keyboard and RTC control Register */ 54*7c478bd9Sstevel@tonic-gate #define PMC 0x6 /* Power Management Control register */ 55*7c478bd9Sstevel@tonic-gate #define TUP 0x7 /* Tape, UART, and Parallel port register */ 56*7c478bd9Sstevel@tonic-gate #define SID 0x8 /* Super I/O Identification register */ 57*7c478bd9Sstevel@tonic-gate 58*7c478bd9Sstevel@tonic-gate #define SIO_LITE 0x40 59*7c478bd9Sstevel@tonic-gate #define SIO_LITE_B 0x90 60*7c478bd9Sstevel@tonic-gate #define SIO_REVA 0x1a 61*7c478bd9Sstevel@tonic-gate #define SIO_REVB 0x1b 62*7c478bd9Sstevel@tonic-gate 63*7c478bd9Sstevel@tonic-gate /* bit definitions for the FCR register */ 64*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_MSD_SEL 0x01 65*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_RESERVED 0x02 66*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_PPM_EN 0x04 67*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_PPM_FLOAT_CTL 0x08 68*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_LDX 0x10 69*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_ZWS_EN 0x20 70*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_ZWS_SEL 0x40 71*7c478bd9Sstevel@tonic-gate #define PC87332_FCR_IOCHRDY_SEL 0x80 72*7c478bd9Sstevel@tonic-gate 73*7c478bd9Sstevel@tonic-gate /* bit definitions for the PCR register */ 74*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_EPP_EN 0x01 75*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_EPP_VER 0x02 76*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_ECP_EN 0x04 77*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_ECP_CLK_FZ 0x08 78*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_INTR_LEVL 0x10 79*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_INTR_POL 0x20 80*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_INTR_DRAIN 0x40 81*7c478bd9Sstevel@tonic-gate #define PC87332_PCR_RESERVED 0x80 82*7c478bd9Sstevel@tonic-gate 83*7c478bd9Sstevel@tonic-gate /* bit definitions for the PMC register */ 84*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_IDE_TRISTATE 0x01 85*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_FDC_TRISTATE 0x02 86*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_UART_TRISTATE 0x04 87*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_ECP_DMA_CONFIG 0x08 88*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_FDC_PD 0x10 89*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_SLB 0x20 90*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_PP_TRISTATE 0x40 91*7c478bd9Sstevel@tonic-gate #define PC87332_PMC_RESERVED 0x80 92*7c478bd9Sstevel@tonic-gate 93*7c478bd9Sstevel@tonic-gate /* 94*7c478bd9Sstevel@tonic-gate * National 97317 superio registers 95*7c478bd9Sstevel@tonic-gate */ 96*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_DEV_NO 0x07 97*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_ACTIVATE 0x30 98*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_IO_RANGE 0x31 99*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_BASE_ADDR_MSB 0x60 100*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_BASE_ADDR_LSB 0x61 101*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_INTR_SEL 0x70 102*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_INTR_TYPE 0x71 103*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_DMA0_CHAN 0x74 104*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_DMA1_CHAN 0x75 105*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG_PP_CONFIG 0xF0 106*7c478bd9Sstevel@tonic-gate 107*7c478bd9Sstevel@tonic-gate /* 108*7c478bd9Sstevel@tonic-gate * Plug N Play configuration superio registers 109*7c478bd9Sstevel@tonic-gate * used in PC97317 & M1553 110*7c478bd9Sstevel@tonic-gate */ 111*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_DEV_NO 0x07 112*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_ACTIVATE 0x30 113*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_IO_RANGE 0x31 114*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_BASE_ADDR_MSB 0x60 115*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_BASE_ADDR_LSB 0x61 116*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_INTR_SEL 0x70 117*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_INTR_TYPE 0x71 118*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_DMA0_CHAN 0x74 119*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_DMA1_CHAN 0x75 120*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_PP_CONFIG0 0xF0 121*7c478bd9Sstevel@tonic-gate #define PnP_CONFIG_PP_CONFIG1 0xF1 122*7c478bd9Sstevel@tonic-gate 123*7c478bd9Sstevel@tonic-gate 124*7c478bd9Sstevel@tonic-gate /* 125*7c478bd9Sstevel@tonic-gate * parallel port interface registers - same for all 1284 modes. 126*7c478bd9Sstevel@tonic-gate */ 127*7c478bd9Sstevel@tonic-gate struct info_reg { 128*7c478bd9Sstevel@tonic-gate union { 129*7c478bd9Sstevel@tonic-gate uint8_t datar; 130*7c478bd9Sstevel@tonic-gate uint8_t afifo; 131*7c478bd9Sstevel@tonic-gate } ir; 132*7c478bd9Sstevel@tonic-gate uint8_t dsr; 133*7c478bd9Sstevel@tonic-gate uint8_t dcr; 134*7c478bd9Sstevel@tonic-gate uint8_t epp_addr; 135*7c478bd9Sstevel@tonic-gate uint8_t epp_data; 136*7c478bd9Sstevel@tonic-gate uint8_t epp_data32[3]; 137*7c478bd9Sstevel@tonic-gate }; 138*7c478bd9Sstevel@tonic-gate 139*7c478bd9Sstevel@tonic-gate /* 140*7c478bd9Sstevel@tonic-gate * additional ECP mode registers. 141*7c478bd9Sstevel@tonic-gate */ 142*7c478bd9Sstevel@tonic-gate struct fifo_reg { 143*7c478bd9Sstevel@tonic-gate union { 144*7c478bd9Sstevel@tonic-gate uint8_t cfifo; 145*7c478bd9Sstevel@tonic-gate uint8_t dfifo; 146*7c478bd9Sstevel@tonic-gate uint8_t tfifo; 147*7c478bd9Sstevel@tonic-gate uint8_t config_a; 148*7c478bd9Sstevel@tonic-gate } fr; 149*7c478bd9Sstevel@tonic-gate uint8_t config_b; 150*7c478bd9Sstevel@tonic-gate uint8_t ecr; 151*7c478bd9Sstevel@tonic-gate }; 152*7c478bd9Sstevel@tonic-gate 153*7c478bd9Sstevel@tonic-gate /* 154*7c478bd9Sstevel@tonic-gate * Values for the ECR field 155*7c478bd9Sstevel@tonic-gate * 156*7c478bd9Sstevel@tonic-gate * The ECR has 3 read-only bits - bits 0,1,2. Bits 3,4,5,6,7 are read/write. 157*7c478bd9Sstevel@tonic-gate * While writing to this register (ECPPIOC_SETREGS), bits 0,1,2 must be 0. 158*7c478bd9Sstevel@tonic-gate * If not, ECPPIOC_SETREGS will return EINVAL. 159*7c478bd9Sstevel@tonic-gate */ 160*7c478bd9Sstevel@tonic-gate 161*7c478bd9Sstevel@tonic-gate #define ECPP_FIFO_EMPTY 0x01 /* 1 when FIFO empty */ 162*7c478bd9Sstevel@tonic-gate #define ECPP_FIFO_FULL 0x02 /* 1 when FIFO full */ 163*7c478bd9Sstevel@tonic-gate #define ECPP_INTR_SRV 0x04 164*7c478bd9Sstevel@tonic-gate 165*7c478bd9Sstevel@tonic-gate /* 166*7c478bd9Sstevel@tonic-gate * When bit is 0, bit will be set to 1 167*7c478bd9Sstevel@tonic-gate * and interrupt will be generated if 168*7c478bd9Sstevel@tonic-gate * any of the three events occur: 169*7c478bd9Sstevel@tonic-gate * (a) TC is reached while DMA enabled 170*7c478bd9Sstevel@tonic-gate * (b) If DMA disabled & DCR5 = 0, 8 or more bytes free in FIFO, 171*7c478bd9Sstevel@tonic-gate * (c) IF DMA disable & DCR5 = 1, 8 or more bytes to be read in FIFO. 172*7c478bd9Sstevel@tonic-gate * 173*7c478bd9Sstevel@tonic-gate * When this bit is 1, DMA & (a), (b), (c) 174*7c478bd9Sstevel@tonic-gate * interrupts are disabled. 175*7c478bd9Sstevel@tonic-gate */ 176*7c478bd9Sstevel@tonic-gate 177*7c478bd9Sstevel@tonic-gate #define ECPP_DMA_ENABLE 0x08 /* DMA enable =1 */ 178*7c478bd9Sstevel@tonic-gate #define ECPP_INTR_MASK 0x10 /* intr-enable nErr mask=1 */ 179*7c478bd9Sstevel@tonic-gate #define ECR_mode_000 0x00 /* PIO CENTRONICS */ 180*7c478bd9Sstevel@tonic-gate #define ECR_mode_001 0x20 /* PIO NIBBLE */ 181*7c478bd9Sstevel@tonic-gate #define ECR_mode_010 0x40 /* DMA CENTRONICS */ 182*7c478bd9Sstevel@tonic-gate #define ECR_mode_011 0x60 /* DMA ECP */ 183*7c478bd9Sstevel@tonic-gate #define ECR_mode_100 0x80 /* PIO EPP */ 184*7c478bd9Sstevel@tonic-gate #define ECR_mode_110 0xc0 /* TDMA (TFIFO) */ 185*7c478bd9Sstevel@tonic-gate #define ECR_mode_111 0xe0 /* Config Mode */ 186*7c478bd9Sstevel@tonic-gate 187*7c478bd9Sstevel@tonic-gate /* 188*7c478bd9Sstevel@tonic-gate * 97317 second level configuration registers 189*7c478bd9Sstevel@tonic-gate */ 190*7c478bd9Sstevel@tonic-gate struct config2_reg { 191*7c478bd9Sstevel@tonic-gate uint8_t eir; /* Extended Index Register */ 192*7c478bd9Sstevel@tonic-gate uint8_t edr; /* Extended Data Register */ 193*7c478bd9Sstevel@tonic-gate }; 194*7c478bd9Sstevel@tonic-gate 195*7c478bd9Sstevel@tonic-gate /* 196*7c478bd9Sstevel@tonic-gate * Second level offset 197*7c478bd9Sstevel@tonic-gate */ 198*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG2_CONTROL0 0x00 199*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG2_CONTROL2 0x02 200*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG2_CONTROL4 0x04 201*7c478bd9Sstevel@tonic-gate #define PC97317_CONFIG2_PPCONFG0 0x05 202*7c478bd9Sstevel@tonic-gate 203*7c478bd9Sstevel@tonic-gate /* Cheerio Ebus DMAC */ 204*7c478bd9Sstevel@tonic-gate 205*7c478bd9Sstevel@tonic-gate struct cheerio_dma_reg { 206*7c478bd9Sstevel@tonic-gate uint32_t csr; /* Data Control Status Register */ 207*7c478bd9Sstevel@tonic-gate uint32_t acr; /* DMA Address Count Registers */ 208*7c478bd9Sstevel@tonic-gate uint32_t bcr; /* DMA Byte Count Register */ 209*7c478bd9Sstevel@tonic-gate }; 210*7c478bd9Sstevel@tonic-gate 211*7c478bd9Sstevel@tonic-gate /* 212*7c478bd9Sstevel@tonic-gate * DMA Control and Status Register(DCSR) definitions. See Cheerio spec 213*7c478bd9Sstevel@tonic-gate * for more details 214*7c478bd9Sstevel@tonic-gate */ 215*7c478bd9Sstevel@tonic-gate #define DCSR_INT_PEND 0x00000001 /* 1= pport or dma interrupts */ 216*7c478bd9Sstevel@tonic-gate #define DCSR_ERR_PEND 0x00000002 /* 1= host bus error detected */ 217*7c478bd9Sstevel@tonic-gate #define DCSR_INT_EN 0x00000010 /* 1= enable sidewinder/ebus intr */ 218*7c478bd9Sstevel@tonic-gate #define DCSR_RESET 0x00000080 /* 1= resets the DCSR */ 219*7c478bd9Sstevel@tonic-gate #define DCSR_WRITE 0x00000100 /* DMA direction; 1 = memory */ 220*7c478bd9Sstevel@tonic-gate #define DCSR_EN_DMA 0x00000200 /* 1= enable DMA */ 221*7c478bd9Sstevel@tonic-gate #define DCSR_CYC_PEND 0x00000400 /* 1 = DMA pending */ 222*7c478bd9Sstevel@tonic-gate #define DCSR_EN_CNT 0x00002000 /* 1= enables byte counter */ 223*7c478bd9Sstevel@tonic-gate #define DCSR_TC 0x00004000 /* 1= Terminal Count occurred */ 224*7c478bd9Sstevel@tonic-gate #define DCSR_CSR_DRAIN 0x00000000 /* 1= disable draining */ 225*7c478bd9Sstevel@tonic-gate #define DCSR_BURST_0 0x00040000 /* Burst Size bit 0 */ 226*7c478bd9Sstevel@tonic-gate #define DCSR_BURST_1 0x00080000 /* Burst Size bit 1 */ 227*7c478bd9Sstevel@tonic-gate #define DCSR_DIAG 0x00000000 /* 1= diag enable */ 228*7c478bd9Sstevel@tonic-gate #define DCSR_TCI_DIS 0x00800000 /* 1= TC won't cause interrupt */ 229*7c478bd9Sstevel@tonic-gate 230*7c478bd9Sstevel@tonic-gate 231*7c478bd9Sstevel@tonic-gate /* Southbridge support */ 232*7c478bd9Sstevel@tonic-gate struct isaspace { 233*7c478bd9Sstevel@tonic-gate uchar_t isa_reg[0x500]; /* 0x500 regs from isa config space */ 234*7c478bd9Sstevel@tonic-gate }; 235*7c478bd9Sstevel@tonic-gate 236*7c478bd9Sstevel@tonic-gate 237*7c478bd9Sstevel@tonic-gate #ifdef __cplusplus 238*7c478bd9Sstevel@tonic-gate } 239*7c478bd9Sstevel@tonic-gate #endif 240*7c478bd9Sstevel@tonic-gate 241*7c478bd9Sstevel@tonic-gate #endif /* _SYS_ECPPREG_H */ 242