1da14cebeSEric Cheng /* 2da14cebeSEric Cheng * CDDL HEADER START 3da14cebeSEric Cheng * 4da14cebeSEric Cheng * The contents of this file are subject to the terms of the 5da14cebeSEric Cheng * Common Development and Distribution License (the "License"). 6da14cebeSEric Cheng * You may not use this file except in compliance with the License. 7da14cebeSEric Cheng * 8da14cebeSEric Cheng * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9da14cebeSEric Cheng * or http://www.opensolaris.org/os/licensing. 10da14cebeSEric Cheng * See the License for the specific language governing permissions 11da14cebeSEric Cheng * and limitations under the License. 12da14cebeSEric Cheng * 13da14cebeSEric Cheng * When distributing Covered Code, include this CDDL HEADER in each 14da14cebeSEric Cheng * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15da14cebeSEric Cheng * If applicable, add the following below this CDDL HEADER, with the 16da14cebeSEric Cheng * fields enclosed by brackets "[]" replaced with your own identifying 17da14cebeSEric Cheng * information: Portions Copyright [yyyy] [name of copyright owner] 18da14cebeSEric Cheng * 19da14cebeSEric Cheng * CDDL HEADER END 20da14cebeSEric Cheng */ 21da14cebeSEric Cheng 22da14cebeSEric Cheng /* 230dc2366fSVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24da14cebeSEric Cheng * Use is subject to license terms. 25e03914f9SRobert Mustacchi * Copyright 2013 Joyent, Inc. All rights reserved. 26*3714f7beSPaul Winder * Copyright 2020 RackTop Systems, Inc. 27da14cebeSEric Cheng */ 28da14cebeSEric Cheng 29da14cebeSEric Cheng #ifndef _MAC_FLOW_H 30da14cebeSEric Cheng #define _MAC_FLOW_H 31da14cebeSEric Cheng 32da14cebeSEric Cheng /* 33da14cebeSEric Cheng * Main structure describing a flow of packets, for classification use 34da14cebeSEric Cheng */ 35da14cebeSEric Cheng 36da14cebeSEric Cheng #ifdef __cplusplus 37da14cebeSEric Cheng extern "C" { 38da14cebeSEric Cheng #endif 39da14cebeSEric Cheng 40da14cebeSEric Cheng #include <sys/types.h> 4133697085SGordon Ross #include <sys/param.h> /* for MAXPATHLEN */ 42da14cebeSEric Cheng #include <netinet/in.h> /* for IPPROTO_* constants */ 43da14cebeSEric Cheng #include <sys/ethernet.h> 44da14cebeSEric Cheng 450dc2366fSVenugopal Iyer #define MAX_RINGS_PER_GROUP 128 460dc2366fSVenugopal Iyer 47da000602SGirish Moodalbail /* 48da000602SGirish Moodalbail * MAXFLOWNAMELEN defines the longest possible permitted flow name, 49da000602SGirish Moodalbail * including the terminating NUL. 50da000602SGirish Moodalbail */ 51da000602SGirish Moodalbail #define MAXFLOWNAMELEN 128 52da14cebeSEric Cheng 53da14cebeSEric Cheng /* need to use MAXMACADDRLEN from dld.h instead of this one */ 54da14cebeSEric Cheng #define MAXMACADDR 20 55da14cebeSEric Cheng 56da14cebeSEric Cheng /* Bit-mask for the selectors carried in the flow descriptor */ 57da14cebeSEric Cheng typedef uint64_t flow_mask_t; 58da14cebeSEric Cheng 59da14cebeSEric Cheng #define FLOW_LINK_DST 0x00000001 /* Destination MAC addr */ 60da14cebeSEric Cheng #define FLOW_LINK_SRC 0x00000002 /* Source MAC address */ 61da14cebeSEric Cheng #define FLOW_LINK_VID 0x00000004 /* VLAN ID */ 62da14cebeSEric Cheng #define FLOW_LINK_SAP 0x00000008 /* SAP value */ 63da14cebeSEric Cheng 64da14cebeSEric Cheng #define FLOW_IP_VERSION 0x00000010 /* V4 or V6 */ 65da14cebeSEric Cheng #define FLOW_IP_PROTOCOL 0x00000020 /* Protocol type */ 66da14cebeSEric Cheng #define FLOW_IP_LOCAL 0x00000040 /* Local address */ 67da14cebeSEric Cheng #define FLOW_IP_REMOTE 0x00000080 /* Remote address */ 68da14cebeSEric Cheng #define FLOW_IP_DSFIELD 0x00000100 /* DSfield value */ 69da14cebeSEric Cheng 70da14cebeSEric Cheng #define FLOW_ULP_PORT_LOCAL 0x00001000 /* ULP local port */ 71da14cebeSEric Cheng #define FLOW_ULP_PORT_REMOTE 0x00002000 /* ULP remote port */ 72da14cebeSEric Cheng 73da14cebeSEric Cheng #if _LONG_LONG_ALIGNMENT == 8 && _LONG_LONG_ALIGNMENT_32 == 4 74da14cebeSEric Cheng #pragma pack(4) 75da14cebeSEric Cheng #endif 76da14cebeSEric Cheng 77da14cebeSEric Cheng typedef struct flow_desc_s { 78da14cebeSEric Cheng flow_mask_t fd_mask; 79da14cebeSEric Cheng uint32_t fd_mac_len; 80da14cebeSEric Cheng uint8_t fd_dst_mac[MAXMACADDR]; 81da14cebeSEric Cheng uint8_t fd_src_mac[MAXMACADDR]; 82da14cebeSEric Cheng uint16_t fd_vid; 83da14cebeSEric Cheng uint32_t fd_sap; 84da14cebeSEric Cheng uint8_t fd_ipversion; 85da14cebeSEric Cheng uint8_t fd_protocol; 86da14cebeSEric Cheng in6_addr_t fd_local_addr; 87da14cebeSEric Cheng in6_addr_t fd_local_netmask; 88da14cebeSEric Cheng in6_addr_t fd_remote_addr; 89da14cebeSEric Cheng in6_addr_t fd_remote_netmask; 90da14cebeSEric Cheng in_port_t fd_local_port; 91da14cebeSEric Cheng in_port_t fd_remote_port; 92da14cebeSEric Cheng uint8_t fd_dsfield; 93da14cebeSEric Cheng uint8_t fd_dsfield_mask; 94da14cebeSEric Cheng } flow_desc_t; 95da14cebeSEric Cheng 96*3714f7beSPaul Winder #define MRP_NCPUS 256 97da14cebeSEric Cheng 98da14cebeSEric Cheng /* 99da14cebeSEric Cheng * In MCM_CPUS mode, cpu bindings is user specified. In MCM_FANOUT mode, 100da14cebeSEric Cheng * user only specifies a fanout count. 1010dc2366fSVenugopal Iyer * mc_rx_fanout_cnt gives the number of CPUs used for fanout soft rings. 1020dc2366fSVenugopal Iyer * mc_rx_fanout_cpus[] array stores the CPUs used for fanout soft rings. 103da14cebeSEric Cheng */ 104da14cebeSEric Cheng typedef enum { 105da14cebeSEric Cheng MCM_FANOUT = 1, 106da14cebeSEric Cheng MCM_CPUS 107da14cebeSEric Cheng } mac_cpu_mode_t; 108da14cebeSEric Cheng 1090dc2366fSVenugopal Iyer /* 1100dc2366fSVenugopal Iyer * Structure to store the value of the CPUs to be used to re-target 1110dc2366fSVenugopal Iyer * Tx interrupt. 1120dc2366fSVenugopal Iyer */ 1130dc2366fSVenugopal Iyer typedef struct mac_tx_intr_cpus_s { 1140dc2366fSVenugopal Iyer /* cpu value to re-target intr to */ 1150dc2366fSVenugopal Iyer int32_t mtc_intr_cpu[MRP_NCPUS]; 1160dc2366fSVenugopal Iyer /* re-targeted CPU or -1 if failed */ 1170dc2366fSVenugopal Iyer int32_t mtc_retargeted_cpu[MRP_NCPUS]; 1180dc2366fSVenugopal Iyer } mac_tx_intr_cpu_t; 1190dc2366fSVenugopal Iyer 120da14cebeSEric Cheng typedef struct mac_cpus_props_s { 121da14cebeSEric Cheng uint32_t mc_ncpus; /* num of cpus */ 122da14cebeSEric Cheng uint32_t mc_cpus[MRP_NCPUS]; /* cpu list */ 1230dc2366fSVenugopal Iyer uint32_t mc_rx_fanout_cnt; /* soft ring cpu cnt */ 1240dc2366fSVenugopal Iyer uint32_t mc_rx_fanout_cpus[MRP_NCPUS]; /* SR cpu list */ 1250dc2366fSVenugopal Iyer uint32_t mc_rx_pollid; /* poll thr binding */ 1260dc2366fSVenugopal Iyer uint32_t mc_rx_workerid; /* worker thr binding */ 127da14cebeSEric Cheng /* 128da14cebeSEric Cheng * interrupt cpu: mrp_intr_cpu less than 0 implies platform limitation 129da14cebeSEric Cheng * in retargetting the interrupt assignment. 130da14cebeSEric Cheng */ 1310dc2366fSVenugopal Iyer int32_t mc_rx_intr_cpu; 1320dc2366fSVenugopal Iyer int32_t mc_tx_fanout_cpus[MRP_NCPUS]; 1330dc2366fSVenugopal Iyer mac_tx_intr_cpu_t mc_tx_intr_cpus; 134da14cebeSEric Cheng mac_cpu_mode_t mc_fanout_mode; /* fanout mode */ 135da14cebeSEric Cheng } mac_cpus_t; 136da14cebeSEric Cheng 1370dc2366fSVenugopal Iyer #define mc_tx_intr_cpu mc_tx_intr_cpus.mtc_intr_cpu 1380dc2366fSVenugopal Iyer #define mc_tx_retargeted_cpu mc_tx_intr_cpus.mtc_retargeted_cpu 1390dc2366fSVenugopal Iyer 140da14cebeSEric Cheng /* Priority values */ 141da14cebeSEric Cheng typedef enum { 142da14cebeSEric Cheng MPL_LOW, 143da14cebeSEric Cheng MPL_MEDIUM, 144da14cebeSEric Cheng MPL_HIGH, 145da14cebeSEric Cheng MPL_RESET 146da14cebeSEric Cheng } mac_priority_level_t; 147da14cebeSEric Cheng 14825ec3e3dSEric Cheng /* Protection types */ 14925ec3e3dSEric Cheng #define MPT_MACNOSPOOF 0x00000001 1500dc2366fSVenugopal Iyer #define MPT_RESTRICTED 0x00000002 1510dc2366fSVenugopal Iyer #define MPT_IPNOSPOOF 0x00000004 1520dc2366fSVenugopal Iyer #define MPT_DHCPNOSPOOF 0x00000008 1530dc2366fSVenugopal Iyer #define MPT_ALL 0x0000000f 15425ec3e3dSEric Cheng #define MPT_RESET 0xffffffff 1550dc2366fSVenugopal Iyer #define MPT_MAXCNT 32 1560dc2366fSVenugopal Iyer #define MPT_MAXIPADDR MPT_MAXCNT 1570dc2366fSVenugopal Iyer #define MPT_MAXCID MPT_MAXCNT 1580dc2366fSVenugopal Iyer #define MPT_MAXCIDLEN 256 1590dc2366fSVenugopal Iyer 1600dc2366fSVenugopal Iyer typedef struct mac_ipaddr_s { 1610dc2366fSVenugopal Iyer uint32_t ip_version; 1620dc2366fSVenugopal Iyer in6_addr_t ip_addr; 163e03914f9SRobert Mustacchi uint8_t ip_netmask; 1640dc2366fSVenugopal Iyer } mac_ipaddr_t; 1650dc2366fSVenugopal Iyer 1660dc2366fSVenugopal Iyer typedef enum { 1670dc2366fSVenugopal Iyer CIDFORM_TYPED = 1, 1680dc2366fSVenugopal Iyer CIDFORM_HEX, 1690dc2366fSVenugopal Iyer CIDFORM_STR 1700dc2366fSVenugopal Iyer } mac_dhcpcid_form_t; 1710dc2366fSVenugopal Iyer 1720dc2366fSVenugopal Iyer typedef struct mac_dhcpcid_s { 1730dc2366fSVenugopal Iyer uchar_t dc_id[MPT_MAXCIDLEN]; 1740dc2366fSVenugopal Iyer uint32_t dc_len; 1750dc2366fSVenugopal Iyer mac_dhcpcid_form_t dc_form; 1760dc2366fSVenugopal Iyer } mac_dhcpcid_t; 17725ec3e3dSEric Cheng 17825ec3e3dSEric Cheng typedef struct mac_protect_s { 17925ec3e3dSEric Cheng uint32_t mp_types; 18025ec3e3dSEric Cheng uint32_t mp_ipaddrcnt; 1810dc2366fSVenugopal Iyer mac_ipaddr_t mp_ipaddrs[MPT_MAXIPADDR]; 1820dc2366fSVenugopal Iyer uint32_t mp_cidcnt; 1830dc2366fSVenugopal Iyer mac_dhcpcid_t mp_cids[MPT_MAXCID]; 18425ec3e3dSEric Cheng } mac_protect_t; 18525ec3e3dSEric Cheng 186da14cebeSEric Cheng /* The default priority for links */ 187da14cebeSEric Cheng #define MPL_LINK_DEFAULT MPL_HIGH 188da14cebeSEric Cheng 189da14cebeSEric Cheng /* The default priority for flows */ 190da14cebeSEric Cheng #define MPL_SUBFLOW_DEFAULT MPL_MEDIUM 191da14cebeSEric Cheng 192da14cebeSEric Cheng #define MRP_MAXBW 0x00000001 /* Limit set */ 193da14cebeSEric Cheng #define MRP_CPUS 0x00000002 /* CPU/fanout set */ 194da14cebeSEric Cheng #define MRP_CPUS_USERSPEC 0x00000004 /* CPU/fanout from user */ 195da14cebeSEric Cheng #define MRP_PRIORITY 0x00000008 /* Priority set */ 19625ec3e3dSEric Cheng #define MRP_PROTECT 0x00000010 /* Protection set */ 1970dc2366fSVenugopal Iyer #define MRP_RX_RINGS 0x00000020 /* Rx rings */ 1980dc2366fSVenugopal Iyer #define MRP_TX_RINGS 0x00000040 /* Tx rings */ 1990dc2366fSVenugopal Iyer #define MRP_RXRINGS_UNSPEC 0x00000080 /* unspecified rings */ 2000dc2366fSVenugopal Iyer #define MRP_TXRINGS_UNSPEC 0x00000100 /* unspecified rings */ 2010dc2366fSVenugopal Iyer #define MRP_RINGS_RESET 0x00000200 /* resetting rings */ 2020dc2366fSVenugopal Iyer #define MRP_POOL 0x00000400 /* CPU pool */ 203da14cebeSEric Cheng 204da14cebeSEric Cheng #define MRP_THROTTLE MRP_MAXBW 205da14cebeSEric Cheng 206da14cebeSEric Cheng /* 3 levels - low, medium, high */ 207da14cebeSEric Cheng #define MRP_PRIORITY_LEVELS 3 208da14cebeSEric Cheng 209da14cebeSEric Cheng /* Special value denoting no bandwidth control */ 210da14cebeSEric Cheng #define MRP_MAXBW_RESETVAL -1ULL 211da14cebeSEric Cheng 212da14cebeSEric Cheng /* 213da14cebeSEric Cheng * Until sub-megabit limit is implemented, 214da14cebeSEric Cheng * reject values lower than 1 MTU per tick or 1.2Mbps 215da14cebeSEric Cheng */ 216da14cebeSEric Cheng #define MRP_MAXBW_MINVAL 1200000 217da14cebeSEric Cheng 218da14cebeSEric Cheng typedef struct mac_resource_props_s { 219da14cebeSEric Cheng /* 220da14cebeSEric Cheng * Bit-mask for the network resource control types types 221da14cebeSEric Cheng */ 222da14cebeSEric Cheng uint32_t mrp_mask; 223da14cebeSEric Cheng uint64_t mrp_maxbw; /* bandwidth limit in bps */ 224da14cebeSEric Cheng mac_priority_level_t mrp_priority; /* relative flow priority */ 225da14cebeSEric Cheng mac_cpus_t mrp_cpus; 22625ec3e3dSEric Cheng mac_protect_t mrp_protect; 2270dc2366fSVenugopal Iyer uint32_t mrp_nrxrings; 2280dc2366fSVenugopal Iyer uint32_t mrp_ntxrings; 2290dc2366fSVenugopal Iyer char mrp_pool[MAXPATHLEN]; /* CPU pool */ 230da14cebeSEric Cheng } mac_resource_props_t; 231da14cebeSEric Cheng 232da14cebeSEric Cheng #define mrp_ncpus mrp_cpus.mc_ncpus 233da14cebeSEric Cheng #define mrp_cpu mrp_cpus.mc_cpus 2340dc2366fSVenugopal Iyer #define mrp_rx_fanout_cnt mrp_cpus.mc_rx_fanout_cnt 2350dc2366fSVenugopal Iyer #define mrp_rx_pollid mrp_cpus.mc_rx_pollid 2360dc2366fSVenugopal Iyer #define mrp_rx_workerid mrp_cpus.mc_rx_workerid 2370dc2366fSVenugopal Iyer #define mrp_rx_intr_cpu mrp_cpus.mc_rx_intr_cpu 238da14cebeSEric Cheng #define mrp_fanout_mode mrp_cpus.mc_fanout_mode 239da14cebeSEric Cheng 240da14cebeSEric Cheng #define MAC_COPY_CPUS(mrp, fmrp) { \ 241da14cebeSEric Cheng int ncpus; \ 242da14cebeSEric Cheng (fmrp)->mrp_ncpus = (mrp)->mrp_ncpus; \ 2430dc2366fSVenugopal Iyer (fmrp)->mrp_rx_fanout_cnt = (mrp)->mrp_rx_fanout_cnt; \ 2440dc2366fSVenugopal Iyer (fmrp)->mrp_rx_intr_cpu = (mrp)->mrp_rx_intr_cpu; \ 245da14cebeSEric Cheng (fmrp)->mrp_fanout_mode = (mrp)->mrp_fanout_mode; \ 246da14cebeSEric Cheng if ((mrp)->mrp_ncpus == 0) { \ 247da14cebeSEric Cheng (fmrp)->mrp_mask &= ~MRP_CPUS; \ 248da14cebeSEric Cheng (fmrp)->mrp_mask &= ~MRP_CPUS_USERSPEC; \ 249da14cebeSEric Cheng } else { \ 250da14cebeSEric Cheng for (ncpus = 0; ncpus < (fmrp)->mrp_ncpus; ncpus++) \ 251da14cebeSEric Cheng (fmrp)->mrp_cpu[ncpus] = (mrp)->mrp_cpu[ncpus];\ 252da14cebeSEric Cheng (fmrp)->mrp_mask |= MRP_CPUS; \ 253da14cebeSEric Cheng if ((mrp)->mrp_mask & MRP_CPUS_USERSPEC) \ 254da14cebeSEric Cheng (fmrp)->mrp_mask |= MRP_CPUS_USERSPEC; \ 255da14cebeSEric Cheng } \ 256da14cebeSEric Cheng } 257da14cebeSEric Cheng 258da14cebeSEric Cheng #if _LONG_LONG_ALIGNMENT == 8 && _LONG_LONG_ALIGNMENT_32 == 4 259da14cebeSEric Cheng #pragma pack() 260da14cebeSEric Cheng #endif 261da14cebeSEric Cheng 262da14cebeSEric Cheng #ifdef __cplusplus 263da14cebeSEric Cheng } 264da14cebeSEric Cheng #endif 265da14cebeSEric Cheng 266da14cebeSEric Cheng #endif /* _MAC_FLOW_H */ 267