16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 22*4df55fdeSJanie Lu * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _SYS_NXGE_NXGE_FFLP_HW_H 276f45ec7bSml29623 #define _SYS_NXGE_NXGE_FFLP_HW_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 #include <nxge_defs.h> 346f45ec7bSml29623 35da14cebeSEric Cheng 366f45ec7bSml29623 /* FZC_FFLP Offsets */ 376f45ec7bSml29623 #define FFLP_ENET_VLAN_TBL_REG (FZC_FFLP + 0x00000) 386f45ec7bSml29623 396f45ec7bSml29623 /* defines for FFLP_ENET_VLAN_TBL */ 406f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN0_MASK 0x0000000000000003ULL 416f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN0_SHIFT 0 426f45ec7bSml29623 #define ENET_VLAN_TBL_VPR0_MASK 0x00000000000000008ULL 436f45ec7bSml29623 #define ENET_VLAN_TBL_VPR0_SHIFT 3 446f45ec7bSml29623 456f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN1_MASK 0x0000000000000030ULL 466f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN1_SHIFT 4 476f45ec7bSml29623 #define ENET_VLAN_TBL_VPR1_MASK 0x00000000000000080ULL 486f45ec7bSml29623 #define ENET_VLAN_TBL_VPR1_SHIFT 7 496f45ec7bSml29623 506f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN2_MASK 0x0000000000000300ULL 516f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN2_SHIFT 8 526f45ec7bSml29623 #define ENET_VLAN_TBL_VPR2_MASK 0x00000000000000800ULL 536f45ec7bSml29623 #define ENET_VLAN_TBL_VPR2_SHIFT 11 546f45ec7bSml29623 556f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN3_MASK 0x0000000000003000ULL 566f45ec7bSml29623 #define ENET_VLAN_TBL_VLANRDCTBLN3_SHIFT 12 576f45ec7bSml29623 #define ENET_VLAN_TBL_VPR3_MASK 0x0000000000008000ULL 586f45ec7bSml29623 #define ENET_VLAN_TBL_VPR3_SHIFT 15 596f45ec7bSml29623 606f45ec7bSml29623 #define ENET_VLAN_TBL_PARITY0_MASK 0x0000000000010000ULL 616f45ec7bSml29623 #define ENET_VLAN_TBL_PARITY0_SHIFT 16 626f45ec7bSml29623 #define ENET_VLAN_TBL_PARITY1_MASK 0x0000000000020000ULL 636f45ec7bSml29623 #define ENET_VLAN_TBL_PARITY1_SHIFT 17 646f45ec7bSml29623 656f45ec7bSml29623 typedef union _fflp_enet_vlan_tbl_t { 666f45ec7bSml29623 uint64_t value; 676f45ec7bSml29623 struct { 686f45ec7bSml29623 #if defined(_BIG_ENDIAN) 696f45ec7bSml29623 uint32_t hdw; 706f45ec7bSml29623 #endif 716f45ec7bSml29623 struct { 726f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 736f45ec7bSml29623 uint32_t rsrvd:14; 746f45ec7bSml29623 uint32_t parity1:1; 756f45ec7bSml29623 uint32_t parity0:1; 766f45ec7bSml29623 uint32_t vpr3:1; 776f45ec7bSml29623 uint32_t vlanrdctbln3:3; 786f45ec7bSml29623 uint32_t vpr2:1; 796f45ec7bSml29623 uint32_t vlanrdctbln2:3; 806f45ec7bSml29623 uint32_t vpr1:1; 816f45ec7bSml29623 uint32_t vlanrdctbln1:3; 826f45ec7bSml29623 uint32_t vpr0:1; 836f45ec7bSml29623 uint32_t vlanrdctbln0:3; 846f45ec7bSml29623 #else 856f45ec7bSml29623 uint32_t vlanrdctbln0:3; 866f45ec7bSml29623 uint32_t vpr0:1; 876f45ec7bSml29623 uint32_t vlanrdctbln1:3; 886f45ec7bSml29623 uint32_t vpr1:1; 896f45ec7bSml29623 uint32_t vlanrdctbln2:3; 906f45ec7bSml29623 uint32_t vpr2:1; 916f45ec7bSml29623 uint32_t vlanrdctbln3:3; 926f45ec7bSml29623 uint32_t vpr3:1; 936f45ec7bSml29623 uint32_t parity0:1; 946f45ec7bSml29623 uint32_t parity1:1; 956f45ec7bSml29623 uint32_t rsrvd:14; 966f45ec7bSml29623 #endif 976f45ec7bSml29623 } ldw; 986f45ec7bSml29623 #ifndef _BIG_ENDIAN 996f45ec7bSml29623 uint32_t hdw; 1006f45ec7bSml29623 #endif 1016f45ec7bSml29623 } bits; 1026f45ec7bSml29623 } fflp_enet_vlan_tbl_t, *p_fflp_enet_vlan_tbl_t; 1036f45ec7bSml29623 1046f45ec7bSml29623 #define FFLP_TCAM_CLS_BASE_OFFSET (FZC_FFLP + 0x20000) 1056f45ec7bSml29623 #define FFLP_L2_CLS_ENET1_REG (FZC_FFLP + 0x20000) 1066f45ec7bSml29623 #define FFLP_L2_CLS_ENET2_REG (FZC_FFLP + 0x20008) 1076f45ec7bSml29623 1086f45ec7bSml29623 typedef union _tcam_class_prg_ether_t { 1096f45ec7bSml29623 #define TCAM_ENET_USR_CLASS_ENABLE 0x1 1106f45ec7bSml29623 #define TCAM_ENET_USR_CLASS_DISABLE 0x0 1116f45ec7bSml29623 1126f45ec7bSml29623 uint64_t value; 1136f45ec7bSml29623 struct { 1146f45ec7bSml29623 #ifdef _BIG_ENDIAN 1156f45ec7bSml29623 uint32_t hdw; 1166f45ec7bSml29623 #endif 1176f45ec7bSml29623 struct { 1186f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 1196f45ec7bSml29623 uint32_t rsrvd:15; 1206f45ec7bSml29623 uint32_t valid:1; 1216f45ec7bSml29623 uint32_t etype:16; 1226f45ec7bSml29623 #else 1236f45ec7bSml29623 uint32_t etype:16; 1246f45ec7bSml29623 uint32_t valid:1; 1256f45ec7bSml29623 uint32_t rsrvd:15; 1266f45ec7bSml29623 #endif 1276f45ec7bSml29623 } ldw; 1286f45ec7bSml29623 #ifndef _BIG_ENDIAN 1296f45ec7bSml29623 uint32_t hdw; 1306f45ec7bSml29623 #endif 1316f45ec7bSml29623 } bits; 1326f45ec7bSml29623 } tcam_class_prg_ether_t, *p_tcam_class_prg_ether_t; 1336f45ec7bSml29623 1346f45ec7bSml29623 #define FFLP_L3_CLS_IP_U4_REG (FZC_FFLP + 0x20010) 1356f45ec7bSml29623 #define FFLP_L3_CLS_IP_U5_REG (FZC_FFLP + 0x20018) 1366f45ec7bSml29623 #define FFLP_L3_CLS_IP_U6_REG (FZC_FFLP + 0x20020) 1376f45ec7bSml29623 #define FFLP_L3_CLS_IP_U7_REG (FZC_FFLP + 0x20028) 1386f45ec7bSml29623 1396f45ec7bSml29623 typedef union _tcam_class_prg_ip_t { 1406f45ec7bSml29623 #define TCAM_IP_USR_CLASS_ENABLE 0x1 1416f45ec7bSml29623 #define TCAM_IP_USR_CLASS_DISABLE 0x0 1426f45ec7bSml29623 1436f45ec7bSml29623 uint64_t value; 1446f45ec7bSml29623 struct { 1456f45ec7bSml29623 #if defined(_BIG_ENDIAN) 1466f45ec7bSml29623 uint32_t hdw; 1476f45ec7bSml29623 #endif 1486f45ec7bSml29623 struct { 1496f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 1506f45ec7bSml29623 uint32_t rsrvd:6; 1516f45ec7bSml29623 uint32_t valid:1; 1526f45ec7bSml29623 uint32_t ipver:1; 1536f45ec7bSml29623 uint32_t pid:8; 1546f45ec7bSml29623 uint32_t tosmask:8; 1556f45ec7bSml29623 uint32_t tos:8; 1566f45ec7bSml29623 #else 1576f45ec7bSml29623 uint32_t tos:8; 1586f45ec7bSml29623 uint32_t tosmask:8; 1596f45ec7bSml29623 uint32_t pid:8; 1606f45ec7bSml29623 uint32_t ipver:1; 1616f45ec7bSml29623 uint32_t valid:1; 1626f45ec7bSml29623 uint32_t rsrvd:6; 1636f45ec7bSml29623 #endif 1646f45ec7bSml29623 } ldw; 1656f45ec7bSml29623 #ifndef _BIG_ENDIAN 1666f45ec7bSml29623 uint32_t hdw; 1676f45ec7bSml29623 #endif 1686f45ec7bSml29623 } bits; 1696f45ec7bSml29623 } tcam_class_prg_ip_t, *p_tcam_class_prg_ip_t; 170*4df55fdeSJanie Lu 171*4df55fdeSJanie Lu /* 172*4df55fdeSJanie Lu * New fields added to the L3 programmable class register for RF-NIU 173*4df55fdeSJanie Lu * and Neptune-L. 174*4df55fdeSJanie Lu */ 175*4df55fdeSJanie Lu #define L3_UCLS_TOS_SH 0 176*4df55fdeSJanie Lu #define L3_UCLS_TOS_MSK 0xff 177*4df55fdeSJanie Lu #define L3_UCLS_TOSM_SH 8 178*4df55fdeSJanie Lu #define L3_UCLS_TOSM_MSK 0xff 179*4df55fdeSJanie Lu #define L3_UCLS_PID_SH 16 180*4df55fdeSJanie Lu #define L3_UCLS_PID_MSK 0xff 181*4df55fdeSJanie Lu #define L3_UCLS_VALID_SH 25 182*4df55fdeSJanie Lu #define L3_UCLS_VALID_MSK 0x01 183*4df55fdeSJanie Lu #define L3_UCLS_L4B23_SEL_SH 26 184*4df55fdeSJanie Lu #define L3_UCLS_L4B23_SEL_MSK 0x01 185*4df55fdeSJanie Lu #define L3_UCLS_L4B23_VAL_SH 27 186*4df55fdeSJanie Lu #define L3_UCLS_L4B23_VAL_MSK 0xffff 187*4df55fdeSJanie Lu #define L3_UCLS_L4B0_MASK_SH 43 188*4df55fdeSJanie Lu #define L3_UCLS_L4B0_MASK_MSK 0xff 189*4df55fdeSJanie Lu #define L3_UCLS_L4B0_VAL_SH 51 190*4df55fdeSJanie Lu #define L3_UCLS_L4B0_VAL_MSK 0xff 191*4df55fdeSJanie Lu #define L3_UCLS_L4_MODE_SH 59 192*4df55fdeSJanie Lu #define L3_UCLS_L4_MODE_MSK 0x01 1936f45ec7bSml29623 /* define the classes which use the above structure */ 1946f45ec7bSml29623 1956f45ec7bSml29623 typedef enum fflp_tcam_class { 1966f45ec7bSml29623 TCAM_CLASS_INVALID = 0, 1976f45ec7bSml29623 TCAM_CLASS_DUMMY = 1, 1986f45ec7bSml29623 TCAM_CLASS_ETYPE_1 = 2, 1996f45ec7bSml29623 TCAM_CLASS_ETYPE_2, 2006f45ec7bSml29623 TCAM_CLASS_IP_USER_4, 2016f45ec7bSml29623 TCAM_CLASS_IP_USER_5, 2026f45ec7bSml29623 TCAM_CLASS_IP_USER_6, 2036f45ec7bSml29623 TCAM_CLASS_IP_USER_7, 2046f45ec7bSml29623 TCAM_CLASS_TCP_IPV4, 2056f45ec7bSml29623 TCAM_CLASS_UDP_IPV4, 2066f45ec7bSml29623 TCAM_CLASS_AH_ESP_IPV4, 2076f45ec7bSml29623 TCAM_CLASS_SCTP_IPV4, 2086f45ec7bSml29623 TCAM_CLASS_TCP_IPV6, 2096f45ec7bSml29623 TCAM_CLASS_UDP_IPV6, 2106f45ec7bSml29623 TCAM_CLASS_AH_ESP_IPV6, 2116f45ec7bSml29623 TCAM_CLASS_SCTP_IPV6, 2126f45ec7bSml29623 TCAM_CLASS_ARP, 2136f45ec7bSml29623 TCAM_CLASS_RARP, 2146f45ec7bSml29623 TCAM_CLASS_DUMMY_12, 2156f45ec7bSml29623 TCAM_CLASS_DUMMY_13, 2166f45ec7bSml29623 TCAM_CLASS_DUMMY_14, 2176f45ec7bSml29623 TCAM_CLASS_DUMMY_15, 218*4df55fdeSJanie Lu TCAM_CLASS_IPV6_FRAG = 0x1F 2196f45ec7bSml29623 } tcam_class_t; 2206f45ec7bSml29623 221*4df55fdeSJanie Lu #define TCAM_CLASS_MAX TCAM_CLASS_IPV6_FRAG 222*4df55fdeSJanie Lu 2236f45ec7bSml29623 /* 2246f45ec7bSml29623 * Specify how to build TCAM key for L3 2256f45ec7bSml29623 * IP Classes. Both User configured and 2266f45ec7bSml29623 * hardwired IP services are included. 2276f45ec7bSml29623 * These are the supported 12 classes. 2286f45ec7bSml29623 */ 2296f45ec7bSml29623 #define FFLP_TCAM_KEY_BASE_OFFSET (FZC_FFLP + 0x20030) 2306f45ec7bSml29623 #define FFLP_TCAM_KEY_IP_USR4_REG (FZC_FFLP + 0x20030) 2316f45ec7bSml29623 #define FFLP_TCAM_KEY_IP_USR5_REG (FZC_FFLP + 0x20038) 2326f45ec7bSml29623 #define FFLP_TCAM_KEY_IP_USR6_REG (FZC_FFLP + 0x20040) 2336f45ec7bSml29623 #define FFLP_TCAM_KEY_IP_USR7_REG (FZC_FFLP + 0x20048) 2346f45ec7bSml29623 #define FFLP_TCAM_KEY_IP4_TCP_REG (FZC_FFLP + 0x20050) 2356f45ec7bSml29623 #define FFLP_TCAM_KEY_IP4_UDP_REG (FZC_FFLP + 0x20058) 2366f45ec7bSml29623 #define FFLP_TCAM_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x20060) 2376f45ec7bSml29623 #define FFLP_TCAM_KEY_IP4_SCTP_REG (FZC_FFLP + 0x20068) 2386f45ec7bSml29623 #define FFLP_TCAM_KEY_IP6_TCP_REG (FZC_FFLP + 0x20070) 2396f45ec7bSml29623 #define FFLP_TCAM_KEY_IP6_UDP_REG (FZC_FFLP + 0x20078) 2406f45ec7bSml29623 #define FFLP_TCAM_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x20080) 2416f45ec7bSml29623 #define FFLP_TCAM_KEY_IP6_SCTP_REG (FZC_FFLP + 0x20088) 2426f45ec7bSml29623 2436f45ec7bSml29623 2446f45ec7bSml29623 typedef union _tcam_class_key_ip_t { 2456f45ec7bSml29623 uint64_t value; 2466f45ec7bSml29623 struct { 2476f45ec7bSml29623 #if defined(_BIG_ENDIAN) 2486f45ec7bSml29623 uint32_t hdw; 2496f45ec7bSml29623 #endif 2506f45ec7bSml29623 struct { 2516f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 2526f45ec7bSml29623 uint32_t rsrvd2:28; 2536f45ec7bSml29623 uint32_t discard:1; 2546f45ec7bSml29623 uint32_t tsel:1; 2556f45ec7bSml29623 uint32_t rsrvd:1; 2566f45ec7bSml29623 uint32_t ipaddr:1; 2576f45ec7bSml29623 #else 2586f45ec7bSml29623 uint32_t ipaddr:1; 2596f45ec7bSml29623 uint32_t rsrvd:1; 2606f45ec7bSml29623 uint32_t tsel:1; 2616f45ec7bSml29623 uint32_t discard:1; 2626f45ec7bSml29623 uint32_t rsrvd2:28; 2636f45ec7bSml29623 #endif 2646f45ec7bSml29623 } ldw; 2656f45ec7bSml29623 #ifndef _BIG_ENDIAN 2666f45ec7bSml29623 uint32_t hdw; 2676f45ec7bSml29623 #endif 2686f45ec7bSml29623 } bits; 2696f45ec7bSml29623 } tcam_class_key_ip_t, *p_tcam_class_key_ip_t; 2706f45ec7bSml29623 2716f45ec7bSml29623 2726f45ec7bSml29623 2736f45ec7bSml29623 #define FFLP_TCAM_KEY_0_REG (FZC_FFLP + 0x20090) 2746f45ec7bSml29623 #define FFLP_TCAM_KEY_1_REG (FZC_FFLP + 0x20098) 2756f45ec7bSml29623 #define FFLP_TCAM_KEY_2_REG (FZC_FFLP + 0x200A0) 2766f45ec7bSml29623 #define FFLP_TCAM_KEY_3_REG (FZC_FFLP + 0x200A8) 2776f45ec7bSml29623 #define FFLP_TCAM_MASK_0_REG (FZC_FFLP + 0x200B0) 2786f45ec7bSml29623 #define FFLP_TCAM_MASK_1_REG (FZC_FFLP + 0x200B8) 2796f45ec7bSml29623 #define FFLP_TCAM_MASK_2_REG (FZC_FFLP + 0x200C0) 2806f45ec7bSml29623 #define FFLP_TCAM_MASK_3_REG (FZC_FFLP + 0x200C8) 2816f45ec7bSml29623 2826f45ec7bSml29623 #define FFLP_TCAM_CTL_REG (FZC_FFLP + 0x200D0) 2836f45ec7bSml29623 2846f45ec7bSml29623 /* bit defines for FFLP_TCAM_CTL register */ 2856f45ec7bSml29623 #define TCAM_CTL_TCAM_WR 0x0ULL 2866f45ec7bSml29623 #define TCAM_CTL_TCAM_RD 0x040000ULL 2876f45ec7bSml29623 #define TCAM_CTL_TCAM_CMP 0x080000ULL 2886f45ec7bSml29623 #define TCAM_CTL_RAM_WR 0x100000ULL 2896f45ec7bSml29623 #define TCAM_CTL_RAM_RD 0x140000ULL 2906f45ec7bSml29623 #define TCAM_CTL_RWC_STAT 0x0020000ULL 2916f45ec7bSml29623 #define TCAM_CTL_RWC_MATCH 0x0010000ULL 2926f45ec7bSml29623 2936f45ec7bSml29623 2946f45ec7bSml29623 typedef union _tcam_ctl_t { 2956f45ec7bSml29623 #define TCAM_CTL_RWC_TCAM_WR 0x0 2966f45ec7bSml29623 #define TCAM_CTL_RWC_TCAM_RD 0x1 2976f45ec7bSml29623 #define TCAM_CTL_RWC_TCAM_CMP 0x2 2986f45ec7bSml29623 #define TCAM_CTL_RWC_RAM_WR 0x4 2996f45ec7bSml29623 #define TCAM_CTL_RWC_RAM_RD 0x5 3006f45ec7bSml29623 #define TCAM_CTL_RWC_RWC_STAT 0x1 3016f45ec7bSml29623 #define TCAM_CTL_RWC_RWC_MATCH 0x1 3026f45ec7bSml29623 3036f45ec7bSml29623 uint64_t value; 3046f45ec7bSml29623 struct { 3056f45ec7bSml29623 #if defined(_BIG_ENDIAN) 3066f45ec7bSml29623 uint32_t hdw; 3076f45ec7bSml29623 #endif 3086f45ec7bSml29623 struct { 3096f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 3106f45ec7bSml29623 uint32_t rsrvd2:11; 3116f45ec7bSml29623 uint32_t rwc:3; 3126f45ec7bSml29623 uint32_t stat:1; 3136f45ec7bSml29623 uint32_t match:1; 3146f45ec7bSml29623 uint32_t rsrvd:6; 3156f45ec7bSml29623 uint32_t location:10; 3166f45ec7bSml29623 #else 3176f45ec7bSml29623 uint32_t location:10; 3186f45ec7bSml29623 uint32_t rsrvd:6; 3196f45ec7bSml29623 uint32_t match:1; 3206f45ec7bSml29623 uint32_t stat:1; 3216f45ec7bSml29623 uint32_t rwc:3; 3226f45ec7bSml29623 uint32_t rsrvd2:11; 3236f45ec7bSml29623 #endif 3246f45ec7bSml29623 } ldw; 3256f45ec7bSml29623 #ifndef _BIG_ENDIAN 3266f45ec7bSml29623 uint32_t hdw; 3276f45ec7bSml29623 #endif 3286f45ec7bSml29623 } bits; 3296f45ec7bSml29623 } tcam_ctl_t, *p_tcam_ctl_t; 3306f45ec7bSml29623 3316f45ec7bSml29623 3326f45ec7bSml29623 3336f45ec7bSml29623 /* Bit defines for TCAM ASC RAM */ 3346f45ec7bSml29623 3356f45ec7bSml29623 3366f45ec7bSml29623 typedef union _tcam_res_t { 3376f45ec7bSml29623 uint64_t value; 3386f45ec7bSml29623 struct { 3396f45ec7bSml29623 #if defined(_BIG_ENDIAN) 3406f45ec7bSml29623 struct { 3416f45ec7bSml29623 uint32_t rsrvd:22; 3426f45ec7bSml29623 uint32_t syndrome:10; 3436f45ec7bSml29623 } hdw; 3446f45ec7bSml29623 #endif 3456f45ec7bSml29623 struct { 3466f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 3476f45ec7bSml29623 uint32_t syndrome:6; 3486f45ec7bSml29623 uint32_t zfid:12; 3496f45ec7bSml29623 uint32_t v4_ecc_ck:1; 3506f45ec7bSml29623 uint32_t disc:1; 3516f45ec7bSml29623 uint32_t tres:2; 3526f45ec7bSml29623 uint32_t rdctbl:3; 3536f45ec7bSml29623 uint32_t offset:5; 3546f45ec7bSml29623 uint32_t zfld:1; 3556f45ec7bSml29623 uint32_t age:1; 3566f45ec7bSml29623 #else 3576f45ec7bSml29623 uint32_t age:1; 3586f45ec7bSml29623 uint32_t zfld:1; 3596f45ec7bSml29623 uint32_t offset:5; 3606f45ec7bSml29623 uint32_t rdctbl:3; 3616f45ec7bSml29623 uint32_t tres:2; 3626f45ec7bSml29623 uint32_t disc:1; 3636f45ec7bSml29623 uint32_t v4_ecc_ck:1; 3646f45ec7bSml29623 uint32_t zfid:12; 3656f45ec7bSml29623 uint32_t syndrome:6; 3666f45ec7bSml29623 #endif 3676f45ec7bSml29623 } ldw; 3686f45ec7bSml29623 #ifndef _BIG_ENDIAN 3696f45ec7bSml29623 struct { 3706f45ec7bSml29623 uint32_t syndrome:10; 3716f45ec7bSml29623 uint32_t rsrvd:22; 3726f45ec7bSml29623 } hdw; 3736f45ec7bSml29623 #endif 3746f45ec7bSml29623 } bits; 3756f45ec7bSml29623 } tcam_res_t, *p_tcam_res_t; 3766f45ec7bSml29623 3776f45ec7bSml29623 3786f45ec7bSml29623 3796f45ec7bSml29623 #define TCAM_ASC_DATA_AGE 0x0000000000000001ULL 3806f45ec7bSml29623 #define TCAM_ASC_DATA_AGE_SHIFT 0x0 3816f45ec7bSml29623 #define TCAM_ASC_DATA_ZFVLD 0x0000000000000002ULL 3826f45ec7bSml29623 #define TCAM_ASC_DATA_ZFVLD_SHIFT 1 3836f45ec7bSml29623 3846f45ec7bSml29623 #define TCAM_ASC_DATA_OFFSET_MASK 0x000000000000007CULL 3856f45ec7bSml29623 #define TCAM_ASC_DATA_OFFSET_SHIFT 2 3866f45ec7bSml29623 3876f45ec7bSml29623 #define TCAM_ASC_DATA_RDCTBL_MASK 0x0000000000000038ULL 3886f45ec7bSml29623 #define TCAM_ASC_DATA_RDCTBL_SHIFT 7 3896f45ec7bSml29623 #define TCAM_ASC_DATA_TRES_MASK 0x0000000000000C00ULL 3906f45ec7bSml29623 #define TRES_CONT_USE_L2RDC 0x00 3916f45ec7bSml29623 #define TRES_TERM_USE_OFFSET 0x01 3926f45ec7bSml29623 #define TRES_CONT_OVRD_L2RDC 0x02 3936f45ec7bSml29623 #define TRES_TERM_OVRD_L2RDC 0x03 3946f45ec7bSml29623 3956f45ec7bSml29623 #define TCAM_ASC_DATA_TRES_SHIFT 10 3966f45ec7bSml29623 #define TCAM_TRES_CONT_USE_L2RDC \ 3976f45ec7bSml29623 (0x0000000000000000ULL << TCAM_ASC_DATA_TRES_SHIFT) 3986f45ec7bSml29623 #define TCAM_TRES_TERM_USE_OFFSET \ 3996f45ec7bSml29623 (0x0000000000000001ULL << TCAM_ASC_DATA_TRES_SHIFT) 4006f45ec7bSml29623 #define TCAM_TRES_CONT_OVRD_L2RDC \ 4016f45ec7bSml29623 (0x0000000000000002ULL << TCAM_ASC_DATA_TRES_SHIFT) 4026f45ec7bSml29623 #define TCAM_TRES_TERM_OVRD_L2RDC \ 4036f45ec7bSml29623 (0x0000000000000003ULL << TCAM_ASC_DATA_TRES_SHIFT) 4046f45ec7bSml29623 4056f45ec7bSml29623 #define TCAM_ASC_DATA_DISC_MASK 0x0000000000001000ULL 4066f45ec7bSml29623 #define TCAM_ASC_DATA_DISC_SHIFT 12 4076f45ec7bSml29623 #define TCAM_ASC_DATA_V4_ECC_OK_MASK 0x0000000000002000ULL 4086f45ec7bSml29623 #define TCAM_ASC_DATA_V4_ECC_OK_SHIFT 13 4096f45ec7bSml29623 #define TCAM_ASC_DATA_V4_ECC_OK \ 4106f45ec7bSml29623 (0x0000000000000001ULL << TCAM_ASC_DATA_V4_ECC_OK_MASK_SHIFT) 4116f45ec7bSml29623 4126f45ec7bSml29623 #define TCAM_ASC_DATA_ZFID_MASK 0x0000000003FF3000ULL 4136f45ec7bSml29623 #define TCAM_ASC_DATA_ZFID_SHIFT 14 4146f45ec7bSml29623 #define TCAM_ASC_DATA_ZFID(value) \ 4156f45ec7bSml29623 ((value & TCAM_ASC_DATA_ZFID_MASK) >> TCAM_ASC_DATA_ZFID_SHIFT) 4166f45ec7bSml29623 4176f45ec7bSml29623 #define TCAM_ASC_DATA_SYNDR_MASK 0x000003FFF3000000ULL 4186f45ec7bSml29623 #define TCAM_ASC_DATA_SYNDR_SHIFT 26 4196f45ec7bSml29623 #define TCAM_ASC_DATA_SYNDR(value) \ 4206f45ec7bSml29623 ((value & TCAM_ASC_DATA_SYNDR_MASK) >> TCAM_ASC_DATA_SYNDR_SHIFT) 4216f45ec7bSml29623 4226f45ec7bSml29623 4236f45ec7bSml29623 /* error registers */ 4246f45ec7bSml29623 4256f45ec7bSml29623 #define FFLP_VLAN_PAR_ERR_REG (FZC_FFLP + 0x08000) 4266f45ec7bSml29623 4276f45ec7bSml29623 typedef union _vlan_par_err_t { 4286f45ec7bSml29623 uint64_t value; 4296f45ec7bSml29623 struct { 4306f45ec7bSml29623 #if defined(_BIG_ENDIAN) 4316f45ec7bSml29623 uint32_t hdw; 4326f45ec7bSml29623 #endif 4336f45ec7bSml29623 struct { 4346f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 4356f45ec7bSml29623 uint32_t err:1; 4366f45ec7bSml29623 uint32_t m_err:1; 4376f45ec7bSml29623 uint32_t addr:12; 4386f45ec7bSml29623 uint32_t data:18; 4396f45ec7bSml29623 #else 4406f45ec7bSml29623 uint32_t data:18; 4416f45ec7bSml29623 uint32_t addr:12; 4426f45ec7bSml29623 uint32_t m_err:1; 4436f45ec7bSml29623 uint32_t err:1; 4446f45ec7bSml29623 #endif 4456f45ec7bSml29623 } ldw; 4466f45ec7bSml29623 #ifndef _BIG_ENDIAN 4476f45ec7bSml29623 uint32_t hdw; 4486f45ec7bSml29623 #endif 4496f45ec7bSml29623 } bits; 4506f45ec7bSml29623 } vlan_par_err_t, *p_vlan_par_err_t; 4516f45ec7bSml29623 4526f45ec7bSml29623 4536f45ec7bSml29623 #define FFLP_TCAM_ERR_REG (FZC_FFLP + 0x200D8) 4546f45ec7bSml29623 4556f45ec7bSml29623 typedef union _tcam_err_t { 4566f45ec7bSml29623 uint64_t value; 4576f45ec7bSml29623 struct { 4586f45ec7bSml29623 #if defined(_BIG_ENDIAN) 4596f45ec7bSml29623 uint32_t hdw; 4606f45ec7bSml29623 #endif 4616f45ec7bSml29623 struct { 4626f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 4636f45ec7bSml29623 uint32_t err:1; 4646f45ec7bSml29623 uint32_t p_ecc:1; 4656f45ec7bSml29623 uint32_t mult:1; 4666f45ec7bSml29623 uint32_t rsrvd:5; 4676f45ec7bSml29623 uint32_t addr:8; 4686f45ec7bSml29623 uint32_t syndrome:16; 4696f45ec7bSml29623 #else 4706f45ec7bSml29623 uint32_t syndrome:16; 4716f45ec7bSml29623 uint32_t addr:8; 4726f45ec7bSml29623 uint32_t rsrvd:5; 4736f45ec7bSml29623 uint32_t mult:1; 4746f45ec7bSml29623 uint32_t p_ecc:1; 4756f45ec7bSml29623 uint32_t err:1; 4766f45ec7bSml29623 #endif 4776f45ec7bSml29623 } ldw; 4786f45ec7bSml29623 #ifndef _BIG_ENDIAN 4796f45ec7bSml29623 uint32_t hdw; 4806f45ec7bSml29623 #endif 4816f45ec7bSml29623 } bits; 4826f45ec7bSml29623 } tcam_err_t, *p_tcam_err_t; 4836f45ec7bSml29623 4846f45ec7bSml29623 4856f45ec7bSml29623 #define TCAM_ERR_SYNDROME_MASK 0x000000000000FFFFULL 4866f45ec7bSml29623 #define TCAM_ERR_MULT_SHIFT 29 4876f45ec7bSml29623 #define TCAM_ERR_MULT 0x0000000020000000ULL 4886f45ec7bSml29623 #define TCAM_ERR_P_ECC 0x0000000040000000ULL 4896f45ec7bSml29623 #define TCAM_ERR_ERR 0x0000000080000000ULL 4906f45ec7bSml29623 4916f45ec7bSml29623 #define HASH_LKUP_ERR_LOG1_REG (FZC_FFLP + 0x200E0) 4926f45ec7bSml29623 #define HASH_LKUP_ERR_LOG2_REG (FZC_FFLP + 0x200E8) 4936f45ec7bSml29623 4946f45ec7bSml29623 4956f45ec7bSml29623 4966f45ec7bSml29623 typedef union _hash_lookup_err_log1_t { 4976f45ec7bSml29623 uint64_t value; 4986f45ec7bSml29623 struct { 4996f45ec7bSml29623 #if defined(_BIG_ENDIAN) 5006f45ec7bSml29623 uint32_t hdw; 5016f45ec7bSml29623 #endif 5026f45ec7bSml29623 struct { 5036f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 5046f45ec7bSml29623 uint32_t rsrvd:28; 5056f45ec7bSml29623 uint32_t ecc_err:1; 5066f45ec7bSml29623 uint32_t mult_lk:1; 5076f45ec7bSml29623 uint32_t cu:1; 5086f45ec7bSml29623 uint32_t mult_bit:1; 5096f45ec7bSml29623 #else 5106f45ec7bSml29623 uint32_t mult_bit:1; 5116f45ec7bSml29623 uint32_t cu:1; 5126f45ec7bSml29623 uint32_t mult_lk:1; 5136f45ec7bSml29623 uint32_t ecc_err:1; 5146f45ec7bSml29623 uint32_t rsrvd:28; 5156f45ec7bSml29623 #endif 5166f45ec7bSml29623 } ldw; 5176f45ec7bSml29623 #ifndef _BIG_ENDIAN 5186f45ec7bSml29623 uint32_t hdw; 5196f45ec7bSml29623 #endif 5206f45ec7bSml29623 } bits; 5216f45ec7bSml29623 } hash_lookup_err_log1_t, *p_hash_lookup_err_log1_t; 5226f45ec7bSml29623 5236f45ec7bSml29623 5246f45ec7bSml29623 5256f45ec7bSml29623 typedef union _hash_lookup_err_log2_t { 5266f45ec7bSml29623 uint64_t value; 5276f45ec7bSml29623 struct { 5286f45ec7bSml29623 #if defined(_BIG_ENDIAN) 5296f45ec7bSml29623 uint32_t hdw; 5306f45ec7bSml29623 #endif 5316f45ec7bSml29623 struct { 5326f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 5336f45ec7bSml29623 uint32_t rsrvd:1; 5346f45ec7bSml29623 uint32_t h1:20; 5356f45ec7bSml29623 uint32_t subarea:3; 5366f45ec7bSml29623 uint32_t syndrome:8; 5376f45ec7bSml29623 #else 5386f45ec7bSml29623 uint32_t syndrome:8; 5396f45ec7bSml29623 uint32_t subarea:3; 5406f45ec7bSml29623 uint32_t h1:20; 5416f45ec7bSml29623 uint32_t rsrvd:1; 5426f45ec7bSml29623 #endif 5436f45ec7bSml29623 } ldw; 5446f45ec7bSml29623 #ifndef _BIG_ENDIAN 5456f45ec7bSml29623 uint32_t hdw; 5466f45ec7bSml29623 #endif 5476f45ec7bSml29623 } bits; 5486f45ec7bSml29623 } hash_lookup_err_log2_t, *p_hash_lookup_err_log2_t; 5496f45ec7bSml29623 5506f45ec7bSml29623 5516f45ec7bSml29623 5526f45ec7bSml29623 #define FFLP_FCRAM_ERR_TST0_REG (FZC_FFLP + 0x20128) 5536f45ec7bSml29623 5546f45ec7bSml29623 typedef union _fcram_err_tst0_t { 5556f45ec7bSml29623 uint64_t value; 5566f45ec7bSml29623 struct { 5576f45ec7bSml29623 #if defined(_BIG_ENDIAN) 5586f45ec7bSml29623 uint32_t hdw; 5596f45ec7bSml29623 #endif 5606f45ec7bSml29623 struct { 5616f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 5626f45ec7bSml29623 uint32_t rsrvd:24; 5636f45ec7bSml29623 uint32_t syndrome_mask:8; 5646f45ec7bSml29623 #else 5656f45ec7bSml29623 uint32_t syndrome_mask:10; 5666f45ec7bSml29623 uint32_t rsrvd:24; 5676f45ec7bSml29623 #endif 5686f45ec7bSml29623 } ldw; 5696f45ec7bSml29623 #ifndef _BIG_ENDIAN 5706f45ec7bSml29623 uint32_t hdw; 5716f45ec7bSml29623 #endif 5726f45ec7bSml29623 } bits; 5736f45ec7bSml29623 } fcram_err_tst0_t, *p_fcram_err_tst0_t; 5746f45ec7bSml29623 5756f45ec7bSml29623 5766f45ec7bSml29623 #define FFLP_FCRAM_ERR_TST1_REG (FZC_FFLP + 0x20130) 5776f45ec7bSml29623 #define FFLP_FCRAM_ERR_TST2_REG (FZC_FFLP + 0x20138) 5786f45ec7bSml29623 5796f45ec7bSml29623 typedef union _fcram_err_tst_t { 5806f45ec7bSml29623 uint64_t value; 5816f45ec7bSml29623 struct { 5826f45ec7bSml29623 #if defined(_BIG_ENDIAN) 5836f45ec7bSml29623 struct { 5846f45ec7bSml29623 uint32_t dat; 5856f45ec7bSml29623 } hdw; 5866f45ec7bSml29623 #endif 5876f45ec7bSml29623 struct { 5886f45ec7bSml29623 uint32_t dat; 5896f45ec7bSml29623 } ldw; 5906f45ec7bSml29623 #ifndef _BIG_ENDIAN 5916f45ec7bSml29623 struct { 5926f45ec7bSml29623 uint32_t dat; 5936f45ec7bSml29623 } hdw; 5946f45ec7bSml29623 #endif 5956f45ec7bSml29623 } bits; 5966f45ec7bSml29623 } fcram_err_tst1_t, *p_fcram_err_tst1_t, 5976f45ec7bSml29623 fcram_err_tst2_t, *p_fcram_err_tst2_t, 5986f45ec7bSml29623 fcram_err_data_t, *p_fcram_err_data_t; 5996f45ec7bSml29623 6006f45ec7bSml29623 6016f45ec7bSml29623 6026f45ec7bSml29623 #define FFLP_ERR_MSK_REG (FZC_FFLP + 0x20140) 6036f45ec7bSml29623 6046f45ec7bSml29623 typedef union _fflp_err_mask_t { 6056f45ec7bSml29623 uint64_t value; 6066f45ec7bSml29623 struct { 6076f45ec7bSml29623 #if defined(_BIG_ENDIAN) 6086f45ec7bSml29623 uint32_t hdw; 6096f45ec7bSml29623 #endif 6106f45ec7bSml29623 struct { 6116f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 6126f45ec7bSml29623 uint32_t rsrvd:21; 6136f45ec7bSml29623 uint32_t hash_tbl_dat:8; 6146f45ec7bSml29623 uint32_t hash_tbl_lkup:1; 6156f45ec7bSml29623 uint32_t tcam:1; 6166f45ec7bSml29623 uint32_t vlan:1; 6176f45ec7bSml29623 #else 6186f45ec7bSml29623 uint32_t vlan:1; 6196f45ec7bSml29623 uint32_t tcam:1; 6206f45ec7bSml29623 uint32_t hash_tbl_lkup:1; 6216f45ec7bSml29623 uint32_t hash_tbl_dat:8; 6226f45ec7bSml29623 uint32_t rsrvd:21; 6236f45ec7bSml29623 #endif 6246f45ec7bSml29623 } ldw; 6256f45ec7bSml29623 #ifndef _BIG_ENDIAN 6266f45ec7bSml29623 uint32_t hdw; 6276f45ec7bSml29623 #endif 6286f45ec7bSml29623 } bits; 6296f45ec7bSml29623 } fflp_err_mask_t, *p_fflp_err_mask_t; 6306f45ec7bSml29623 6316f45ec7bSml29623 #define FFLP_ERR_VLAN_MASK 0x00000001ULL 6326f45ec7bSml29623 #define FFLP_ERR_VLAN 0x00000001ULL 6336f45ec7bSml29623 #define FFLP_ERR_VLAN_SHIFT 0x0 6346f45ec7bSml29623 6356f45ec7bSml29623 #define FFLP_ERR_TCAM_MASK 0x00000002ULL 6366f45ec7bSml29623 #define FFLP_ERR_TCAM 0x00000001ULL 6376f45ec7bSml29623 #define FFLP_ERR_TCAM_SHIFT 0x1 6386f45ec7bSml29623 6396f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_LKUP_MASK 0x00000004ULL 6406f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_LKUP 0x00000001ULL 6416f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_LKUP_SHIFT 0x2 6426f45ec7bSml29623 6436f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_DAT_MASK 0x00000007F8ULL 6446f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_DAT 0x0000000FFULL 6456f45ec7bSml29623 #define FFLP_ERR_HASH_TBL_DAT_SHIFT 0x3 6466f45ec7bSml29623 6476f45ec7bSml29623 #define FFLP_ERR_MASK_ALL (FFLP_ERR_VLAN_MASK | FFLP_ERR_TCAM_MASK | \ 6486f45ec7bSml29623 FFLP_ERR_HASH_TBL_LKUP_MASK | \ 6496f45ec7bSml29623 FFLP_ERR_HASH_TBL_DAT_MASK) 6506f45ec7bSml29623 6516f45ec7bSml29623 6526f45ec7bSml29623 #define FFLP_CFG_1_REG (FZC_FFLP + 0x20100) 6536f45ec7bSml29623 6546f45ec7bSml29623 typedef union _fflp_cfg_1_t { 6556f45ec7bSml29623 uint64_t value; 6566f45ec7bSml29623 struct { 6576f45ec7bSml29623 #if defined(_BIG_ENDIAN) 6586f45ec7bSml29623 uint32_t hdw; 6596f45ec7bSml29623 #endif 6606f45ec7bSml29623 struct { 6616f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 6626f45ec7bSml29623 uint32_t rsrvd:5; 6636f45ec7bSml29623 uint32_t tcam_disable:1; 6646f45ec7bSml29623 uint32_t pio_dbg_sel:3; 6656f45ec7bSml29623 uint32_t pio_fio_rst:1; 6666f45ec7bSml29623 uint32_t pio_fio_lat:2; 6676f45ec7bSml29623 uint32_t camlatency:4; 6686f45ec7bSml29623 uint32_t camratio:4; 6696f45ec7bSml29623 uint32_t fcramratio:4; 6706f45ec7bSml29623 uint32_t fcramoutdr:4; 6716f45ec7bSml29623 uint32_t fcramqs:1; 6726f45ec7bSml29623 uint32_t errordis:1; 6736f45ec7bSml29623 uint32_t fflpinitdone:1; 6746f45ec7bSml29623 uint32_t llcsnap:1; 6756f45ec7bSml29623 #else 6766f45ec7bSml29623 uint32_t llcsnap:1; 6776f45ec7bSml29623 uint32_t fflpinitdone:1; 6786f45ec7bSml29623 uint32_t errordis:1; 6796f45ec7bSml29623 uint32_t fcramqs:1; 6806f45ec7bSml29623 uint32_t fcramoutdr:4; 6816f45ec7bSml29623 uint32_t fcramratio:4; 6826f45ec7bSml29623 uint32_t camratio:4; 6836f45ec7bSml29623 uint32_t camlatency:4; 6846f45ec7bSml29623 uint32_t pio_fio_lat:2; 6856f45ec7bSml29623 uint32_t pio_fio_rst:1; 6866f45ec7bSml29623 uint32_t pio_dbg_sel:3; 6876f45ec7bSml29623 uint32_t tcam_disable:1; 6886f45ec7bSml29623 uint32_t rsrvd:5; 6896f45ec7bSml29623 #endif 6906f45ec7bSml29623 } ldw; 6916f45ec7bSml29623 #ifndef _BIG_ENDIAN 6926f45ec7bSml29623 uint32_t hdw; 6936f45ec7bSml29623 #endif 6946f45ec7bSml29623 } bits; 6956f45ec7bSml29623 } fflp_cfg_1_t, *p_fflp_cfg_1_t; 6966f45ec7bSml29623 6976f45ec7bSml29623 6986f45ec7bSml29623 typedef enum fflp_fcram_output_drive { 6996f45ec7bSml29623 FCRAM_OUTDR_NORMAL = 0x0, 7006f45ec7bSml29623 FCRAM_OUTDR_STRONG = 0x5, 7016f45ec7bSml29623 FCRAM_OUTDR_WEAK = 0xa 7026f45ec7bSml29623 } fflp_fcram_output_drive_t; 7036f45ec7bSml29623 7046f45ec7bSml29623 7056f45ec7bSml29623 typedef enum fflp_fcram_qs { 7066f45ec7bSml29623 FCRAM_QS_MODE_QS = 0x0, 7076f45ec7bSml29623 FCRAM_QS_MODE_FREE = 0x1 7086f45ec7bSml29623 } fflp_fcram_qs_t; 7096f45ec7bSml29623 7106f45ec7bSml29623 #define FCRAM_PIO_HIGH_PRI 0xf 7116f45ec7bSml29623 #define FCRAM_PIO_MED_PRI 0xa 7126f45ec7bSml29623 #define FCRAM_LOOKUP_HIGH_PRI 0x0 7136f45ec7bSml29623 #define FCRAM_LOOKUP_HIGH_PRI 0x0 7146f45ec7bSml29623 #define FCRAM_IO_DEFAULT_PRI FCRAM_PIO_MED_PRI 7156f45ec7bSml29623 7166f45ec7bSml29623 #define TCAM_PIO_HIGH_PRI 0xf 7176f45ec7bSml29623 #define TCAM_PIO_MED_PRI 0xa 7186f45ec7bSml29623 #define TCAM_LOOKUP_HIGH_PRI 0x0 7196f45ec7bSml29623 #define TCAM_LOOKUP_HIGH_PRI 0x0 7206f45ec7bSml29623 #define TCAM_IO_DEFAULT_PRI TCAM_PIO_MED_PRI 7216f45ec7bSml29623 7226f45ec7bSml29623 #define TCAM_DEFAULT_LATENCY 0x4 7236f45ec7bSml29623 7246f45ec7bSml29623 7256f45ec7bSml29623 #define FFLP_DBG_TRAIN_VCT_REG (FZC_FFLP + 0x20148) 7266f45ec7bSml29623 7276f45ec7bSml29623 typedef union _fflp_dbg_train_vct_t { 7286f45ec7bSml29623 uint64_t value; 7296f45ec7bSml29623 struct { 7306f45ec7bSml29623 #if defined(_BIG_ENDIAN) 7316f45ec7bSml29623 uint32_t hdw; 7326f45ec7bSml29623 #endif 7336f45ec7bSml29623 struct { 7346f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 7356f45ec7bSml29623 uint32_t vector; 7366f45ec7bSml29623 #else 7376f45ec7bSml29623 uint32_t vector; 7386f45ec7bSml29623 #endif 7396f45ec7bSml29623 } ldw; 7406f45ec7bSml29623 #ifndef _BIG_ENDIAN 7416f45ec7bSml29623 uint32_t hdw; 7426f45ec7bSml29623 #endif 7436f45ec7bSml29623 } bits; 7446f45ec7bSml29623 } fflp_dbg_train_vct_t, *p_fflp_dbg_train_vct_t; 7456f45ec7bSml29623 7466f45ec7bSml29623 7476f45ec7bSml29623 7486f45ec7bSml29623 #define FFLP_TCP_CFLAG_MSK_REG (FZC_FFLP + 0x20108) 7496f45ec7bSml29623 7506f45ec7bSml29623 typedef union _tcp_cflag_mask_t { 7516f45ec7bSml29623 uint64_t value; 7526f45ec7bSml29623 struct { 7536f45ec7bSml29623 #if defined(_BIG_ENDIAN) 7546f45ec7bSml29623 uint32_t hdw; 7556f45ec7bSml29623 #endif 7566f45ec7bSml29623 struct { 7576f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 7586f45ec7bSml29623 uint32_t rsrvd:20; 7596f45ec7bSml29623 uint32_t mask:12; 7606f45ec7bSml29623 #else 7616f45ec7bSml29623 uint32_t mask:12; 7626f45ec7bSml29623 uint32_t rsrvd:20; 7636f45ec7bSml29623 #endif 7646f45ec7bSml29623 } ldw; 7656f45ec7bSml29623 #ifndef _BIG_ENDIAN 7666f45ec7bSml29623 uint32_t hdw; 7676f45ec7bSml29623 #endif 7686f45ec7bSml29623 } bits; 7696f45ec7bSml29623 } tcp_cflag_mask_t, *p_tcp_cflag_mask_t; 7706f45ec7bSml29623 7716f45ec7bSml29623 7726f45ec7bSml29623 7736f45ec7bSml29623 #define FFLP_FCRAM_REF_TMR_REG (FZC_FFLP + 0x20110) 7746f45ec7bSml29623 7756f45ec7bSml29623 7766f45ec7bSml29623 typedef union _fcram_ref_tmr_t { 7776f45ec7bSml29623 #define FCRAM_REFRESH_DEFAULT_MAX_TIME 0x200 7786f45ec7bSml29623 #define FCRAM_REFRESH_DEFAULT_MIN_TIME 0x200 7796f45ec7bSml29623 #define FCRAM_REFRESH_DEFAULT_SYS_TIME 0x200 7806f45ec7bSml29623 #define FCRAM_REFRESH_MAX_TICK 39 /* usecs */ 7816f45ec7bSml29623 #define FCRAM_REFRESH_MIN_TICK 400 /* nsecs */ 7826f45ec7bSml29623 7836f45ec7bSml29623 uint64_t value; 7846f45ec7bSml29623 struct { 7856f45ec7bSml29623 #if defined(_BIG_ENDIAN) 7866f45ec7bSml29623 uint32_t hdw; 7876f45ec7bSml29623 #endif 7886f45ec7bSml29623 struct { 7896f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 7906f45ec7bSml29623 uint32_t max:16; 7916f45ec7bSml29623 uint32_t min:16; 7926f45ec7bSml29623 #else 7936f45ec7bSml29623 uint32_t min:16; 7946f45ec7bSml29623 uint32_t max:16; 7956f45ec7bSml29623 #endif 7966f45ec7bSml29623 } ldw; 7976f45ec7bSml29623 #ifndef _BIG_ENDIAN 7986f45ec7bSml29623 uint32_t hdw; 7996f45ec7bSml29623 #endif 8006f45ec7bSml29623 } bits; 8016f45ec7bSml29623 } fcram_ref_tmr_t, *p_fcram_ref_tmr_t; 8026f45ec7bSml29623 8036f45ec7bSml29623 8046f45ec7bSml29623 8056f45ec7bSml29623 8066f45ec7bSml29623 #define FFLP_FCRAM_FIO_ADDR_REG (FZC_FFLP + 0x20118) 8076f45ec7bSml29623 8086f45ec7bSml29623 typedef union _fcram_fio_addr_t { 8096f45ec7bSml29623 uint64_t value; 8106f45ec7bSml29623 struct { 8116f45ec7bSml29623 #if defined(_BIG_ENDIAN) 8126f45ec7bSml29623 uint32_t hdw; 8136f45ec7bSml29623 #endif 8146f45ec7bSml29623 struct { 8156f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 8166f45ec7bSml29623 uint32_t rsrvd:22; 8176f45ec7bSml29623 uint32_t addr:10; 8186f45ec7bSml29623 #else 8196f45ec7bSml29623 uint32_t addr:10; 8206f45ec7bSml29623 uint32_t rsrvd:22; 8216f45ec7bSml29623 #endif 8226f45ec7bSml29623 } ldw; 8236f45ec7bSml29623 #ifndef _BIG_ENDIAN 8246f45ec7bSml29623 uint32_t hdw; 8256f45ec7bSml29623 #endif 8266f45ec7bSml29623 } bits; 8276f45ec7bSml29623 } fcram_fio_addr_t, *p_fcram_fio_addr_t; 8286f45ec7bSml29623 8296f45ec7bSml29623 8306f45ec7bSml29623 #define FFLP_FCRAM_FIO_DAT_REG (FZC_FFLP + 0x20120) 8316f45ec7bSml29623 8326f45ec7bSml29623 typedef union _fcram_fio_dat_t { 8336f45ec7bSml29623 uint64_t value; 8346f45ec7bSml29623 struct { 8356f45ec7bSml29623 #if defined(_BIG_ENDIAN) 8366f45ec7bSml29623 uint32_t hdw; 8376f45ec7bSml29623 #endif 8386f45ec7bSml29623 struct { 8396f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 8406f45ec7bSml29623 uint32_t rsrvd:22; 8416f45ec7bSml29623 uint32_t addr:10; 8426f45ec7bSml29623 #else 8436f45ec7bSml29623 uint32_t addr:10; 8446f45ec7bSml29623 uint32_t rsrvd:22; 8456f45ec7bSml29623 #endif 8466f45ec7bSml29623 } ldw; 8476f45ec7bSml29623 #ifndef _BIG_ENDIAN 8486f45ec7bSml29623 uint32_t hdw; 8496f45ec7bSml29623 #endif 8506f45ec7bSml29623 } bits; 8516f45ec7bSml29623 } fcram_fio_dat_t, *p_fcram_fio_dat_t; 8526f45ec7bSml29623 8536f45ec7bSml29623 8546f45ec7bSml29623 #define FFLP_FCRAM_PHY_RD_LAT_REG (FZC_FFLP + 0x20150) 8556f45ec7bSml29623 8566f45ec7bSml29623 typedef union _fcram_phy_rd_lat_t { 8576f45ec7bSml29623 uint64_t value; 8586f45ec7bSml29623 struct { 8596f45ec7bSml29623 #if defined(_BIG_ENDIAN) 8606f45ec7bSml29623 uint32_t hdw; 8616f45ec7bSml29623 #endif 8626f45ec7bSml29623 struct { 8636f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 8646f45ec7bSml29623 uint32_t rsrvd:24; 8656f45ec7bSml29623 uint32_t lat:8; 8666f45ec7bSml29623 #else 8676f45ec7bSml29623 uint32_t lat:8; 8686f45ec7bSml29623 uint32_t rsrvd:24; 8696f45ec7bSml29623 #endif 8706f45ec7bSml29623 } ldw; 8716f45ec7bSml29623 #ifndef _BIG_ENDIAN 8726f45ec7bSml29623 uint32_t hdw; 8736f45ec7bSml29623 #endif 8746f45ec7bSml29623 } bits; 8756f45ec7bSml29623 } fcram_phy_rd_lat_t, *p_fcram_phy_rd_lat_t; 8766f45ec7bSml29623 8776f45ec7bSml29623 8786f45ec7bSml29623 /* 8796f45ec7bSml29623 * Specify how to build a flow key for IP 8806f45ec7bSml29623 * classes, both programmable and hardwired 8816f45ec7bSml29623 */ 8826f45ec7bSml29623 #define FFLP_FLOW_KEY_BASE_OFFSET (FZC_FFLP + 0x40000) 8836f45ec7bSml29623 #define FFLP_FLOW_KEY_IP_USR4_REG (FZC_FFLP + 0x40000) 8846f45ec7bSml29623 #define FFLP_FLOW_KEY_IP_USR5_REG (FZC_FFLP + 0x40008) 8856f45ec7bSml29623 #define FFLP_FLOW_KEY_IP_USR6_REG (FZC_FFLP + 0x40010) 8866f45ec7bSml29623 #define FFLP_FLOW_KEY_IP_USR7_REG (FZC_FFLP + 0x40018) 8876f45ec7bSml29623 #define FFLP_FLOW_KEY_IP4_TCP_REG (FZC_FFLP + 0x40020) 8886f45ec7bSml29623 #define FFLP_FLOW_KEY_IP4_UDP_REG (FZC_FFLP + 0x40028) 8896f45ec7bSml29623 #define FFLP_FLOW_KEY_IP4_AH_ESP_REG (FZC_FFLP + 0x40030) 8906f45ec7bSml29623 #define FFLP_FLOW_KEY_IP4_SCTP_REG (FZC_FFLP + 0x40038) 8916f45ec7bSml29623 #define FFLP_FLOW_KEY_IP6_TCP_REG (FZC_FFLP + 0x40040) 8926f45ec7bSml29623 #define FFLP_FLOW_KEY_IP6_UDP_REG (FZC_FFLP + 0x40048) 8936f45ec7bSml29623 #define FFLP_FLOW_KEY_IP6_AH_ESP_REG (FZC_FFLP + 0x40050) 8946f45ec7bSml29623 #define FFLP_FLOW_KEY_IP6_SCTP_REG (FZC_FFLP + 0x40058) 895*4df55fdeSJanie Lu /* 896*4df55fdeSJanie Lu * New FLOW KEY register added for IPV6 Fragments for RF-NIU 897*4df55fdeSJanie Lu * and Neptune-L. 898*4df55fdeSJanie Lu */ 899*4df55fdeSJanie Lu #define FFLP_FLOW_KEY_IP6_FRAG_REG (FZC_FFLP + 0x400B0) 900*4df55fdeSJanie Lu 901*4df55fdeSJanie Lu #define FL_KEY_USR_L4XOR_MSK 0x03ff 9026f45ec7bSml29623 9036f45ec7bSml29623 typedef union _flow_class_key_ip_t { 9046f45ec7bSml29623 uint64_t value; 9056f45ec7bSml29623 struct { 9066f45ec7bSml29623 #if defined(_BIG_ENDIAN) 9076f45ec7bSml29623 uint32_t hdw; 9086f45ec7bSml29623 #endif 9096f45ec7bSml29623 struct { 9106f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 911*4df55fdeSJanie Lu uint32_t rsrvd2:10; 912*4df55fdeSJanie Lu /* These bits added for L3 programmable classes in RF-NIU and Neptune-L */ 913*4df55fdeSJanie Lu uint32_t l4_xor:10; 914*4df55fdeSJanie Lu uint32_t l4_mode:1; 915*4df55fdeSJanie Lu /* This bit added for SNORT support in RF-NIU and Neptune-L */ 916*4df55fdeSJanie Lu uint32_t sym:1; 9176f45ec7bSml29623 uint32_t port:1; 9186f45ec7bSml29623 uint32_t l2da:1; 9196f45ec7bSml29623 uint32_t vlan:1; 9206f45ec7bSml29623 uint32_t ipsa:1; 9216f45ec7bSml29623 uint32_t ipda:1; 9226f45ec7bSml29623 uint32_t proto:1; 9236f45ec7bSml29623 uint32_t l4_0:2; 9246f45ec7bSml29623 uint32_t l4_1:2; 9256f45ec7bSml29623 #else 9266f45ec7bSml29623 uint32_t l4_1:2; 9276f45ec7bSml29623 uint32_t l4_0:2; 9286f45ec7bSml29623 uint32_t proto:1; 9296f45ec7bSml29623 uint32_t ipda:1; 9306f45ec7bSml29623 uint32_t ipsa:1; 9316f45ec7bSml29623 uint32_t vlan:1; 9326f45ec7bSml29623 uint32_t l2da:1; 9336f45ec7bSml29623 uint32_t port:1; 934*4df55fdeSJanie Lu uint32_t sym:1; 935*4df55fdeSJanie Lu uint32_t l4_mode:1; 936*4df55fdeSJanie Lu uint32_t l4_xor:10; 937*4df55fdeSJanie Lu uint32_t rsrvd2:10; 9386f45ec7bSml29623 #endif 9396f45ec7bSml29623 } ldw; 9406f45ec7bSml29623 #ifndef _BIG_ENDIAN 9416f45ec7bSml29623 uint32_t hdw; 9426f45ec7bSml29623 #endif 9436f45ec7bSml29623 } bits; 9446f45ec7bSml29623 } flow_class_key_ip_t, *p_flow_class_key_ip_t; 9456f45ec7bSml29623 9466f45ec7bSml29623 #define FFLP_H1POLY_REG (FZC_FFLP + 0x40060) 9476f45ec7bSml29623 9486f45ec7bSml29623 9496f45ec7bSml29623 typedef union _hash_h1poly_t { 9506f45ec7bSml29623 uint64_t value; 9516f45ec7bSml29623 struct { 9526f45ec7bSml29623 #if defined(_BIG_ENDIAN) 9536f45ec7bSml29623 uint32_t hdw; 9546f45ec7bSml29623 #endif 9556f45ec7bSml29623 struct { 9566f45ec7bSml29623 uint32_t init_value; 9576f45ec7bSml29623 } ldw; 9586f45ec7bSml29623 #ifndef _BIG_ENDIAN 9596f45ec7bSml29623 uint32_t hdw; 9606f45ec7bSml29623 #endif 9616f45ec7bSml29623 } bits; 9626f45ec7bSml29623 } hash_h1poly_t, *p_hash_h1poly_t; 9636f45ec7bSml29623 9646f45ec7bSml29623 #define FFLP_H2POLY_REG (FZC_FFLP + 0x40068) 9656f45ec7bSml29623 9666f45ec7bSml29623 typedef union _hash_h2poly_t { 9676f45ec7bSml29623 uint64_t value; 9686f45ec7bSml29623 struct { 9696f45ec7bSml29623 #if defined(_BIG_ENDIAN) 9706f45ec7bSml29623 uint32_t hdw; 9716f45ec7bSml29623 #endif 9726f45ec7bSml29623 struct { 9736f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 9746f45ec7bSml29623 uint32_t rsrvd:16; 9756f45ec7bSml29623 uint32_t init_value:16; 9766f45ec7bSml29623 #else 9776f45ec7bSml29623 uint32_t init_value:16; 9786f45ec7bSml29623 uint32_t rsrvd:16; 9796f45ec7bSml29623 #endif 9806f45ec7bSml29623 } ldw; 9816f45ec7bSml29623 #ifndef _BIG_ENDIAN 9826f45ec7bSml29623 uint32_t hdw; 9836f45ec7bSml29623 #endif 9846f45ec7bSml29623 } bits; 9856f45ec7bSml29623 } hash_h2poly_t, *p_hash_h2poly_t; 9866f45ec7bSml29623 9876f45ec7bSml29623 #define FFLP_FLW_PRT_SEL_REG (FZC_FFLP + 0x40070) 9886f45ec7bSml29623 9896f45ec7bSml29623 9906f45ec7bSml29623 typedef union _flow_prt_sel_t { 9916f45ec7bSml29623 #define FFLP_FCRAM_MAX_PARTITION 8 9926f45ec7bSml29623 uint64_t value; 9936f45ec7bSml29623 struct { 9946f45ec7bSml29623 #if defined(_BIG_ENDIAN) 9956f45ec7bSml29623 uint32_t hdw; 9966f45ec7bSml29623 #endif 9976f45ec7bSml29623 struct { 9986f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 9996f45ec7bSml29623 uint32_t rsrvd3:15; 10006f45ec7bSml29623 uint32_t ext:1; 10016f45ec7bSml29623 uint32_t rsrvd2:3; 10026f45ec7bSml29623 uint32_t mask:5; 10036f45ec7bSml29623 uint32_t rsrvd:3; 10046f45ec7bSml29623 uint32_t base:5; 10056f45ec7bSml29623 #else 10066f45ec7bSml29623 uint32_t base:5; 10076f45ec7bSml29623 uint32_t rsrvd:3; 10086f45ec7bSml29623 uint32_t mask:5; 10096f45ec7bSml29623 uint32_t rsrvd2:3; 10106f45ec7bSml29623 uint32_t ext:1; 10116f45ec7bSml29623 uint32_t rsrvd3:15; 10126f45ec7bSml29623 #endif 10136f45ec7bSml29623 } ldw; 10146f45ec7bSml29623 #ifndef _BIG_ENDIAN 10156f45ec7bSml29623 uint32_t hdw; 10166f45ec7bSml29623 #endif 10176f45ec7bSml29623 } bits; 10186f45ec7bSml29623 } flow_prt_sel_t, *p_flow_prt_sel_t; 10196f45ec7bSml29623 10206f45ec7bSml29623 10216f45ec7bSml29623 10226f45ec7bSml29623 /* FFLP Offsets */ 10236f45ec7bSml29623 10246f45ec7bSml29623 10256f45ec7bSml29623 #define FFLP_HASH_TBL_ADDR_REG (FFLP + 0x00000) 10266f45ec7bSml29623 10276f45ec7bSml29623 typedef union _hash_tbl_addr_t { 10286f45ec7bSml29623 uint64_t value; 10296f45ec7bSml29623 struct { 10306f45ec7bSml29623 #if defined(_BIG_ENDIAN) 10316f45ec7bSml29623 uint32_t hdw; 10326f45ec7bSml29623 #endif 10336f45ec7bSml29623 struct { 10346f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 10356f45ec7bSml29623 uint32_t rsrvd:8; 10366f45ec7bSml29623 uint32_t autoinc:1; 10376f45ec7bSml29623 uint32_t addr:23; 10386f45ec7bSml29623 #else 10396f45ec7bSml29623 uint32_t addr:23; 10406f45ec7bSml29623 uint32_t autoinc:1; 10416f45ec7bSml29623 uint32_t rsrvd:8; 10426f45ec7bSml29623 #endif 10436f45ec7bSml29623 } ldw; 10446f45ec7bSml29623 #ifndef _BIG_ENDIAN 10456f45ec7bSml29623 uint32_t hdw; 10466f45ec7bSml29623 #endif 10476f45ec7bSml29623 } bits; 10486f45ec7bSml29623 } hash_tbl_addr_t, *p_hash_tbl_addr_t; 10496f45ec7bSml29623 10506f45ec7bSml29623 10516f45ec7bSml29623 #define FFLP_HASH_TBL_DATA_REG (FFLP + 0x00008) 10526f45ec7bSml29623 10536f45ec7bSml29623 typedef union _hash_tbl_data_t { 10546f45ec7bSml29623 uint64_t value; 10556f45ec7bSml29623 struct { 10566f45ec7bSml29623 #ifdef _BIG_ENDIAN 10576f45ec7bSml29623 uint32_t hdw; 10586f45ec7bSml29623 uint32_t ldw; 10596f45ec7bSml29623 #else 10606f45ec7bSml29623 uint32_t ldw; 10616f45ec7bSml29623 uint32_t hdw; 10626f45ec7bSml29623 #endif 10636f45ec7bSml29623 } bits; 10646f45ec7bSml29623 } hash_tbl_data_t, *p_hash_tbl_data_t; 10656f45ec7bSml29623 10666f45ec7bSml29623 10676f45ec7bSml29623 #define FFLP_HASH_TBL_DATA_LOG_REG (FFLP + 0x00010) 10686f45ec7bSml29623 10696f45ec7bSml29623 10706f45ec7bSml29623 typedef union _hash_tbl_data_log_t { 10716f45ec7bSml29623 uint64_t value; 10726f45ec7bSml29623 struct { 10736f45ec7bSml29623 #if defined(_BIG_ENDIAN) 10746f45ec7bSml29623 uint32_t hdw; 10756f45ec7bSml29623 #endif 10766f45ec7bSml29623 struct { 10776f45ec7bSml29623 #ifdef _BIT_FIELDS_HTOL 10786f45ec7bSml29623 uint32_t pio_err:1; 10796f45ec7bSml29623 uint32_t fcram_addr:23; 10806f45ec7bSml29623 uint32_t syndrome:8; 10816f45ec7bSml29623 #else 10826f45ec7bSml29623 uint32_t syndrome:8; 10836f45ec7bSml29623 uint32_t fcram_addr:23; 10846f45ec7bSml29623 uint32_t pio_err:1; 10856f45ec7bSml29623 #endif 10866f45ec7bSml29623 } ldw; 10876f45ec7bSml29623 #ifndef _BIG_ENDIAN 10886f45ec7bSml29623 uint32_t hdw; 10896f45ec7bSml29623 #endif 10906f45ec7bSml29623 } bits; 10916f45ec7bSml29623 } hash_tbl_data_log_t, *p_hash_tbl_data_log_t; 10926f45ec7bSml29623 10936f45ec7bSml29623 10946f45ec7bSml29623 10956f45ec7bSml29623 #define REG_PIO_WRITE64(handle, offset, value) \ 10966f45ec7bSml29623 NXGE_REG_WR64((handle), (offset), (value)) 10976f45ec7bSml29623 #define REG_PIO_READ64(handle, offset, val_p) \ 10986f45ec7bSml29623 NXGE_REG_RD64((handle), (offset), (val_p)) 10996f45ec7bSml29623 11006f45ec7bSml29623 11016f45ec7bSml29623 #define WRITE_TCAM_REG_CTL(handle, ctl) \ 11026f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_CTL_REG, ctl) 11036f45ec7bSml29623 11046f45ec7bSml29623 #define READ_TCAM_REG_CTL(handle, val_p) \ 11056f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_CTL_REG, val_p) 11066f45ec7bSml29623 11076f45ec7bSml29623 11086f45ec7bSml29623 #define WRITE_TCAM_REG_KEY0(handle, key) \ 11096f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_0_REG, key) 11106f45ec7bSml29623 #define WRITE_TCAM_REG_KEY1(handle, key) \ 11116f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_1_REG, key) 11126f45ec7bSml29623 #define WRITE_TCAM_REG_KEY2(handle, key) \ 11136f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_2_REG, key) 11146f45ec7bSml29623 #define WRITE_TCAM_REG_KEY3(handle, key) \ 11156f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_KEY_3_REG, key) 11166f45ec7bSml29623 #define WRITE_TCAM_REG_MASK0(handle, mask) \ 11176f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_0_REG, mask) 11186f45ec7bSml29623 #define WRITE_TCAM_REG_MASK1(handle, mask) \ 11196f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_1_REG, mask) 11206f45ec7bSml29623 #define WRITE_TCAM_REG_MASK2(handle, mask) \ 11216f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_2_REG, mask) 11226f45ec7bSml29623 #define WRITE_TCAM_REG_MASK3(handle, mask) \ 11236f45ec7bSml29623 REG_PIO_WRITE64(handle, FFLP_TCAM_MASK_3_REG, mask) 11246f45ec7bSml29623 11256f45ec7bSml29623 #define READ_TCAM_REG_KEY0(handle, val_p) \ 11266f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_KEY_0_REG, val_p) 11276f45ec7bSml29623 #define READ_TCAM_REG_KEY1(handle, val_p) \ 11286f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_KEY_1_REG, val_p) 11296f45ec7bSml29623 #define READ_TCAM_REG_KEY2(handle, val_p) \ 11306f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_KEY_2_REG, val_p) 11316f45ec7bSml29623 #define READ_TCAM_REG_KEY3(handle, val_p) \ 11326f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_KEY_3_REG, val_p) 11336f45ec7bSml29623 #define READ_TCAM_REG_MASK0(handle, val_p) \ 11346f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_MASK_0_REG, val_p) 11356f45ec7bSml29623 #define READ_TCAM_REG_MASK1(handle, val_p) \ 11366f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_MASK_1_REG, val_p) 11376f45ec7bSml29623 #define READ_TCAM_REG_MASK2(handle, val_p) \ 11386f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_MASK_2_REG, val_p) 11396f45ec7bSml29623 #define READ_TCAM_REG_MASK3(handle, val_p) \ 11406f45ec7bSml29623 REG_PIO_READ64(handle, FFLP_TCAM_MASK_3_REG, val_p) 11416f45ec7bSml29623 11426f45ec7bSml29623 11436f45ec7bSml29623 11446f45ec7bSml29623 11456f45ec7bSml29623 typedef struct tcam_ipv4 { 11466f45ec7bSml29623 #if defined(_BIG_ENDIAN) 11476f45ec7bSml29623 uint32_t reserved6; /* 255 : 224 */ 11486f45ec7bSml29623 uint32_t reserved5 : 24; /* 223 : 200 */ 11496f45ec7bSml29623 uint32_t cls_code : 5; /* 199 : 195 */ 11506f45ec7bSml29623 uint32_t reserved4 : 3; /* 194 : 192 */ 11516f45ec7bSml29623 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 11526f45ec7bSml29623 uint32_t noport : 1; /* 186 */ 11536f45ec7bSml29623 uint32_t reserved3 : 26; /* 185: 160 */ 11546f45ec7bSml29623 uint32_t reserved2; /* 159: 128 */ 11556f45ec7bSml29623 uint32_t reserved : 16; /* 127 : 112 */ 11566f45ec7bSml29623 uint32_t tos : 8; /* 111 : 104 */ 11576f45ec7bSml29623 uint32_t proto : 8; /* 103 : 96 */ 11586f45ec7bSml29623 uint32_t l4_port_spi; /* 95 : 64 */ 11596f45ec7bSml29623 uint32_t ip_src; /* 63 : 32 */ 11606f45ec7bSml29623 uint32_t ip_dest; /* 31 : 0 */ 11616f45ec7bSml29623 #else 11626f45ec7bSml29623 uint32_t ip_dest; /* 31 : 0 */ 11636f45ec7bSml29623 uint32_t ip_src; /* 63 : 32 */ 11646f45ec7bSml29623 uint32_t l4_port_spi; /* 95 : 64 */ 11656f45ec7bSml29623 uint32_t proto : 8; /* 103 : 96 */ 11666f45ec7bSml29623 uint32_t tos : 8; /* 111 : 104 */ 11676f45ec7bSml29623 uint32_t reserved : 16; /* 127 : 112 */ 11686f45ec7bSml29623 uint32_t reserved2; /* 159: 128 */ 11696f45ec7bSml29623 uint32_t reserved3 : 26; /* 185: 160 */ 11706f45ec7bSml29623 uint32_t noport : 1; /* 186 */ 11716f45ec7bSml29623 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 11726f45ec7bSml29623 uint32_t reserved4 : 3; /* 194 : 192 */ 11736f45ec7bSml29623 uint32_t cls_code : 5; /* 199 : 195 */ 11746f45ec7bSml29623 uint32_t reserved5 : 24; /* 223 : 200 */ 11756f45ec7bSml29623 uint32_t reserved6; /* 255 : 224 */ 11766f45ec7bSml29623 #endif 11776f45ec7bSml29623 } tcam_ipv4_t; 11786f45ec7bSml29623 11796f45ec7bSml29623 11806f45ec7bSml29623 11816f45ec7bSml29623 typedef struct tcam_reg { 11826f45ec7bSml29623 #if defined(_BIG_ENDIAN) 11836f45ec7bSml29623 uint64_t reg0; 11846f45ec7bSml29623 uint64_t reg1; 11856f45ec7bSml29623 uint64_t reg2; 11866f45ec7bSml29623 uint64_t reg3; 11876f45ec7bSml29623 #else 11886f45ec7bSml29623 uint64_t reg3; 11896f45ec7bSml29623 uint64_t reg2; 11906f45ec7bSml29623 uint64_t reg1; 11916f45ec7bSml29623 uint64_t reg0; 11926f45ec7bSml29623 #endif 11936f45ec7bSml29623 } tcam_reg_t; 11946f45ec7bSml29623 11956f45ec7bSml29623 11966f45ec7bSml29623 typedef struct tcam_ether { 11976f45ec7bSml29623 #if defined(_BIG_ENDIAN) 11986f45ec7bSml29623 uint8_t reserved3[7]; /* 255 : 200 */ 11996f45ec7bSml29623 uint8_t cls_code : 5; /* 199 : 195 */ 12006f45ec7bSml29623 uint8_t reserved2 : 3; /* 194 : 192 */ 12016f45ec7bSml29623 uint8_t ethframe[11]; /* 191 : 104 */ 12026f45ec7bSml29623 uint8_t reserved[13]; /* 103 : 0 */ 12036f45ec7bSml29623 #else 12046f45ec7bSml29623 uint8_t reserved[13]; /* 103 : 0 */ 12056f45ec7bSml29623 uint8_t ethframe[11]; /* 191 : 104 */ 12066f45ec7bSml29623 uint8_t reserved2 : 3; /* 194 : 192 */ 12076f45ec7bSml29623 uint8_t cls_code : 5; /* 199 : 195 */ 12086f45ec7bSml29623 uint8_t reserved3[7]; /* 255 : 200 */ 12096f45ec7bSml29623 #endif 12106f45ec7bSml29623 } tcam_ether_t; 12116f45ec7bSml29623 12126f45ec7bSml29623 12136f45ec7bSml29623 typedef struct tcam_ipv6 { 12146f45ec7bSml29623 #if defined(_BIG_ENDIAN) 12156f45ec7bSml29623 uint32_t reserved4; /* 255 : 224 */ 12166f45ec7bSml29623 uint32_t reserved3 : 24; /* 223 : 200 */ 12176f45ec7bSml29623 uint32_t cls_code : 5; /* 199 : 195 */ 12186f45ec7bSml29623 uint32_t reserved2 : 3; /* 194 : 192 */ 12196f45ec7bSml29623 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 12206f45ec7bSml29623 uint32_t noport : 1; /* 186 */ 12216f45ec7bSml29623 uint32_t reserved : 10; /* 185 : 176 */ 12226f45ec7bSml29623 uint32_t tos : 8; /* 175 : 168 */ 12236f45ec7bSml29623 uint32_t nxt_hdr : 8; /* 167 : 160 */ 12246f45ec7bSml29623 uint32_t l4_port_spi; /* 159 : 128 */ 12256f45ec7bSml29623 uint32_t ip_addr[4]; /* 127 : 0 */ 12266f45ec7bSml29623 #else 12276f45ec7bSml29623 uint32_t ip_addr[4]; /* 127 : 0 */ 12286f45ec7bSml29623 uint32_t l4_port_spi; /* 159 : 128 */ 12296f45ec7bSml29623 uint32_t nxt_hdr : 8; /* 167 : 160 */ 12306f45ec7bSml29623 uint32_t tos : 8; /* 175 : 168 */ 12316f45ec7bSml29623 uint32_t reserved : 10; /* 185 : 176 */ 12326f45ec7bSml29623 uint32_t noport : 1; /* 186 */ 12336f45ec7bSml29623 uint32_t l2rd_tbl_num : 5; /* 191: 187 */ 12346f45ec7bSml29623 uint32_t reserved2 : 3; /* 194 : 192 */ 12356f45ec7bSml29623 uint32_t cls_code : 5; /* 199 : 195 */ 12366f45ec7bSml29623 uint32_t reserved3 : 24; /* 223 : 200 */ 12376f45ec7bSml29623 uint32_t reserved4; /* 255 : 224 */ 12386f45ec7bSml29623 #endif 12396f45ec7bSml29623 } tcam_ipv6_t; 12406f45ec7bSml29623 12416f45ec7bSml29623 12426f45ec7bSml29623 typedef struct tcam_entry { 12436f45ec7bSml29623 union _tcam_entry { 12446f45ec7bSml29623 tcam_reg_t regs_e; 12456f45ec7bSml29623 tcam_ether_t ether_e; 12466f45ec7bSml29623 tcam_ipv4_t ipv4_e; 12476f45ec7bSml29623 tcam_ipv6_t ipv6_e; 12486f45ec7bSml29623 } key, mask; 12496f45ec7bSml29623 tcam_res_t match_action; 12506f45ec7bSml29623 } tcam_entry_t; 12516f45ec7bSml29623 12526f45ec7bSml29623 12536f45ec7bSml29623 #define key_reg0 key.regs_e.reg0 12546f45ec7bSml29623 #define key_reg1 key.regs_e.reg1 12556f45ec7bSml29623 #define key_reg2 key.regs_e.reg2 12566f45ec7bSml29623 #define key_reg3 key.regs_e.reg3 12576f45ec7bSml29623 #define mask_reg0 mask.regs_e.reg0 12586f45ec7bSml29623 #define mask_reg1 mask.regs_e.reg1 12596f45ec7bSml29623 #define mask_reg2 mask.regs_e.reg2 12606f45ec7bSml29623 #define mask_reg3 mask.regs_e.reg3 12616f45ec7bSml29623 12626f45ec7bSml29623 12636f45ec7bSml29623 #define key0 key.regs_e.reg0 12646f45ec7bSml29623 #define key1 key.regs_e.reg1 12656f45ec7bSml29623 #define key2 key.regs_e.reg2 12666f45ec7bSml29623 #define key3 key.regs_e.reg3 12676f45ec7bSml29623 #define mask0 mask.regs_e.reg0 12686f45ec7bSml29623 #define mask1 mask.regs_e.reg1 12696f45ec7bSml29623 #define mask2 mask.regs_e.reg2 12706f45ec7bSml29623 #define mask3 mask.regs_e.reg3 12716f45ec7bSml29623 12726f45ec7bSml29623 12736f45ec7bSml29623 #define ip4_src_key key.ipv4_e.ip_src 12746f45ec7bSml29623 #define ip4_dest_key key.ipv4_e.ip_dest 12756f45ec7bSml29623 #define ip4_proto_key key.ipv4_e.proto 12766f45ec7bSml29623 #define ip4_port_key key.ipv4_e.l4_port_spi 12776f45ec7bSml29623 #define ip4_tos_key key.ipv4_e.tos 12786f45ec7bSml29623 #define ip4_noport_key key.ipv4_e.noport 12796f45ec7bSml29623 #define ip4_nrdc_key key.ipv4_e.l2rdc_tbl_num 12806f45ec7bSml29623 #define ip4_class_key key.ipv4_e.cls_code 12816f45ec7bSml29623 12826f45ec7bSml29623 #define ip4_src_mask mask.ipv4_e.ip_src 12836f45ec7bSml29623 #define ip4_dest_mask mask.ipv4_e.ip_dest 12846f45ec7bSml29623 #define ip4_proto_mask mask.ipv4_e.proto 12856f45ec7bSml29623 #define ip4_port_mask mask.ipv4_e.l4_port_spi 12866f45ec7bSml29623 #define ip4_tos_mask mask.ipv4_e.tos 12876f45ec7bSml29623 #define ip4_nrdc_mask mask.ipv4_e.l2rdc_tbl_num 12886f45ec7bSml29623 #define ip4_noport_mask mask.ipv4_e.noport 12896f45ec7bSml29623 #define ip4_class_mask mask.ipv4_e.cls_code 12906f45ec7bSml29623 12916f45ec7bSml29623 12926f45ec7bSml29623 #define ip6_ip_addr_key key.ipv6_e.ip_addr 12936f45ec7bSml29623 #define ip6_port_key key.ipv6_e.l4_port_spi 12946f45ec7bSml29623 #define ip6_nxt_hdr_key key.ipv6_e.nxt_hdr 12956f45ec7bSml29623 #define ip6_tos_key key.ipv6_e.tos 12966f45ec7bSml29623 #define ip6_nrdc_key key.ipv6_e.l2rdc_tbl_num 12976f45ec7bSml29623 #define ip6_noport_key key.ipv6_e.noport 12986f45ec7bSml29623 #define ip6_class_key key.ipv6_e.cls_code 12996f45ec7bSml29623 13006f45ec7bSml29623 13016f45ec7bSml29623 #define ip6_ip_addr_mask mask.ipv6_e.ip_addr 13026f45ec7bSml29623 #define ip6_port_mask mask.ipv6_e.l4_port_spi 13036f45ec7bSml29623 #define ip6_nxt_hdr_mask mask.ipv6_e.nxt_hdr 13046f45ec7bSml29623 #define ip6_tos_mask mask.ipv6_e.tos 13056f45ec7bSml29623 #define ip6_nrdc_mask mask.ipv6_e.l2rdc_tbl_num 13066f45ec7bSml29623 #define ip6_noport_mask mask.ipv6_e.noport 13076f45ec7bSml29623 #define ip6_class_mask mask.ipv6_e.cls_code 13086f45ec7bSml29623 13096f45ec7bSml29623 #define ether_class_key key.ether_e.cls_code 13106f45ec7bSml29623 #define ether_ethframe_key key.ether_e.ethframe 13116f45ec7bSml29623 #define ether_class_mask mask.ether_e.cls_code 13126f45ec7bSml29623 #define ether_ethframe_mask mask.ether_e.ethframe 13136f45ec7bSml29623 13146f45ec7bSml29623 13156f45ec7bSml29623 /* 13166f45ec7bSml29623 * flow template structure 13176f45ec7bSml29623 * The flow header is passed through the hash function 13186f45ec7bSml29623 * which generates the H1 (and the H2 ) hash value. 13196f45ec7bSml29623 * Hash computation is started at the 22 zeros. 13206f45ec7bSml29623 * 13216f45ec7bSml29623 * Since this structure uses the ip address fields, 13226f45ec7bSml29623 * /usr/include/netinet/in.h has to be included 13236f45ec7bSml29623 * before this header file. 13246f45ec7bSml29623 * Need to move these includes to impl files ... 13256f45ec7bSml29623 */ 1326da14cebeSEric Cheng 13276f45ec7bSml29623 #include <netinet/in.h> 13286f45ec7bSml29623 13296f45ec7bSml29623 typedef union flow_template { 13306f45ec7bSml29623 13316f45ec7bSml29623 struct { 13326f45ec7bSml29623 #if defined(_BIG_ENDIAN) 13336f45ec7bSml29623 uint32_t l4_0:16; /* src port */ 13346f45ec7bSml29623 uint32_t l4_1:16; /* dest Port */ 13356f45ec7bSml29623 13366f45ec7bSml29623 uint32_t pid:8; 13376f45ec7bSml29623 uint32_t port:2; 13386f45ec7bSml29623 uint32_t zeros:22; /* 0 */ 13396f45ec7bSml29623 13406f45ec7bSml29623 union { 13416f45ec7bSml29623 struct { 13426f45ec7bSml29623 struct in6_addr daddr; 13436f45ec7bSml29623 struct in6_addr saddr; 13446f45ec7bSml29623 } ip6_addr; 13456f45ec7bSml29623 13466f45ec7bSml29623 struct { 13476f45ec7bSml29623 uint32_t rsrvd1; 13486f45ec7bSml29623 struct in_addr daddr; 13496f45ec7bSml29623 uint32_t rsrvd2[3]; 13506f45ec7bSml29623 struct in_addr saddr; 13516f45ec7bSml29623 uint32_t rsrvd5[2]; 13526f45ec7bSml29623 } ip4_addr; 13536f45ec7bSml29623 } ipaddr; 13546f45ec7bSml29623 13556f45ec7bSml29623 union { 13566f45ec7bSml29623 uint64_t l2_info; 13576f45ec7bSml29623 struct { 13586f45ec7bSml29623 uint32_t vlan_valid : 4; 13596f45ec7bSml29623 uint32_t l2da_1 : 28; 13606f45ec7bSml29623 uint32_t l2da_0 : 20; 13616f45ec7bSml29623 uint32_t vlanid : 12; 13626f45ec7bSml29623 13636f45ec7bSml29623 }l2_bits; 13646f45ec7bSml29623 }l2; 13656f45ec7bSml29623 #else 13666f45ec7bSml29623 13676f45ec7bSml29623 uint32_t l4_1:16; /* dest Port */ 13686f45ec7bSml29623 uint32_t l4_0:16; /* src port */ 13696f45ec7bSml29623 13706f45ec7bSml29623 uint32_t zeros:22; /* 0 */ 13716f45ec7bSml29623 uint32_t port:2; 13726f45ec7bSml29623 uint32_t pid:8; 13736f45ec7bSml29623 13746f45ec7bSml29623 union { 13756f45ec7bSml29623 struct { 13766f45ec7bSml29623 struct in6_addr daddr; 13776f45ec7bSml29623 struct in6_addr saddr; 13786f45ec7bSml29623 } ip6_addr; 13796f45ec7bSml29623 13806f45ec7bSml29623 struct { 13816f45ec7bSml29623 uint32_t rsrvd1; 13826f45ec7bSml29623 struct in_addr daddr; 13836f45ec7bSml29623 uint32_t rsrvd2[3]; 13846f45ec7bSml29623 struct in_addr saddr; 13856f45ec7bSml29623 uint32_t rsrvd5[2]; 13866f45ec7bSml29623 } ip4_addr; 13876f45ec7bSml29623 } ipaddr; 13886f45ec7bSml29623 13896f45ec7bSml29623 union { 13906f45ec7bSml29623 uint64_t l2_info; 13916f45ec7bSml29623 struct { 13926f45ec7bSml29623 13936f45ec7bSml29623 uint32_t l2da_1 : 28; 13946f45ec7bSml29623 uint32_t vlan_valid : 4; 13956f45ec7bSml29623 13966f45ec7bSml29623 uint32_t vlanid : 12; 13976f45ec7bSml29623 uint32_t l2da_0 : 20; 13986f45ec7bSml29623 }l2_bits; 13996f45ec7bSml29623 }l2; 14006f45ec7bSml29623 #endif 14016f45ec7bSml29623 } bits; 14026f45ec7bSml29623 14036f45ec7bSml29623 } flow_template_t; 14046f45ec7bSml29623 14056f45ec7bSml29623 14066f45ec7bSml29623 14076f45ec7bSml29623 #define ip4_saddr bits.ipaddr.ip4_addr.saddr.s_addr 14086f45ec7bSml29623 #define ip4_daddr bits.ipaddr.ip4_addr.daddr.s_addr 14096f45ec7bSml29623 14106f45ec7bSml29623 #define ip_src_port bits.l4_0 14116f45ec7bSml29623 #define ip_dst_port bits.l4_1 14126f45ec7bSml29623 #define ip_proto bits.pid 14136f45ec7bSml29623 14146f45ec7bSml29623 #define ip6_saddr bits.ipaddr.ip6_addr.saddr 14156f45ec7bSml29623 #define ip6_daddr bits.ipaddr.ip6_addr.daddr 14166f45ec7bSml29623 14176f45ec7bSml29623 14186f45ec7bSml29623 14196f45ec7bSml29623 14206f45ec7bSml29623 typedef struct _flow_key_cfg_t { 1421*4df55fdeSJanie Lu uint32_t rsrvd:11; 1422*4df55fdeSJanie Lu /* The following 3 bit fields added for RF-NIU and Neptune-L */ 1423*4df55fdeSJanie Lu uint32_t l4_xor_sel:10; 1424*4df55fdeSJanie Lu uint32_t use_l4_md:1; 1425*4df55fdeSJanie Lu uint32_t use_sym:1; 14266f45ec7bSml29623 uint32_t use_portnum:1; 14276f45ec7bSml29623 uint32_t use_l2da:1; 14286f45ec7bSml29623 uint32_t use_vlan:1; 14296f45ec7bSml29623 uint32_t use_saddr:1; 14306f45ec7bSml29623 uint32_t use_daddr:1; 14316f45ec7bSml29623 uint32_t use_sport:1; 14326f45ec7bSml29623 uint32_t use_dport:1; 14336f45ec7bSml29623 uint32_t use_proto:1; 14346f45ec7bSml29623 uint32_t ip_opts_exist:1; 14356f45ec7bSml29623 } flow_key_cfg_t; 14366f45ec7bSml29623 14376f45ec7bSml29623 14386f45ec7bSml29623 typedef struct _tcam_key_cfg_t { 14396f45ec7bSml29623 uint32_t rsrvd:28; 14406f45ec7bSml29623 uint32_t use_ip_daddr:1; 14416f45ec7bSml29623 uint32_t use_ip_saddr:1; 14426f45ec7bSml29623 uint32_t lookup_enable:1; 14436f45ec7bSml29623 uint32_t discard:1; 14446f45ec7bSml29623 } tcam_key_cfg_t; 14456f45ec7bSml29623 14466f45ec7bSml29623 14476f45ec7bSml29623 14486f45ec7bSml29623 /* 14496f45ec7bSml29623 * FCRAM Entry Formats 14506f45ec7bSml29623 * 14516f45ec7bSml29623 * ip6 and ip4 entries, the first 64 bits layouts are identical 14526f45ec7bSml29623 * optimistic entry has only 64 bit layout 14536f45ec7bSml29623 * The first three bits, fmt, ext and valid are the same 14546f45ec7bSml29623 * accoross all the entries 14556f45ec7bSml29623 */ 14566f45ec7bSml29623 14576f45ec7bSml29623 typedef union hash_optim { 14586f45ec7bSml29623 uint64_t value; 14596f45ec7bSml29623 struct _bits { 14606f45ec7bSml29623 #if defined(_BIG_ENDIAN) 14616f45ec7bSml29623 uint32_t fmt : 1; /* 63 set to zero */ 14626f45ec7bSml29623 uint32_t ext : 1; /* 62 set to zero */ 14636f45ec7bSml29623 uint32_t valid : 1; /* 61 */ 14646f45ec7bSml29623 uint32_t rdc_offset : 5; /* 60 : 56 */ 14656f45ec7bSml29623 uint32_t h2 : 16; /* 55 : 40 */ 14666f45ec7bSml29623 uint32_t rsrvd : 8; /* 32 : 32 */ 14676f45ec7bSml29623 uint32_t usr_info; /* 31 : 0 */ 14686f45ec7bSml29623 #else 14696f45ec7bSml29623 uint32_t usr_info; /* 31 : 0 */ 14706f45ec7bSml29623 uint32_t rsrvd : 8; /* 39 : 32 */ 14716f45ec7bSml29623 uint32_t h2 : 16; /* 55 : 40 */ 14726f45ec7bSml29623 uint32_t rdc_offset : 5; /* 60 : 56 */ 14736f45ec7bSml29623 uint32_t valid : 1; /* 61 */ 14746f45ec7bSml29623 uint32_t ext : 1; /* 62 set to zero */ 14756f45ec7bSml29623 uint32_t fmt : 1; /* 63 set to zero */ 14766f45ec7bSml29623 #endif 14776f45ec7bSml29623 } bits; 14786f45ec7bSml29623 } hash_optim_t; 14796f45ec7bSml29623 14806f45ec7bSml29623 14816f45ec7bSml29623 typedef union _hash_hdr { 14826f45ec7bSml29623 uint64_t value; 14836f45ec7bSml29623 struct _exact_hdr { 14846f45ec7bSml29623 #if defined(_BIG_ENDIAN) 14856f45ec7bSml29623 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 14866f45ec7bSml29623 uint32_t ext : 1; /* 62 set to 1 */ 14876f45ec7bSml29623 uint32_t valid : 1; /* 61 */ 14886f45ec7bSml29623 uint32_t rsrvd : 1; /* 60 */ 14896f45ec7bSml29623 uint32_t l2da_1 : 28; /* 59 : 32 */ 14906f45ec7bSml29623 uint32_t l2da_0 : 20; /* 31 : 12 */ 14916f45ec7bSml29623 uint32_t vlan : 12; /* 12 : 0 */ 14926f45ec7bSml29623 #else 14936f45ec7bSml29623 uint32_t vlan : 12; /* 12 : 0 */ 14946f45ec7bSml29623 uint32_t l2da_0 : 20; /* 31 : 12 */ 14956f45ec7bSml29623 uint32_t l2da_1 : 28; /* 59 : 32 */ 14966f45ec7bSml29623 uint32_t rsrvd : 1; /* 60 */ 14976f45ec7bSml29623 uint32_t valid : 1; /* 61 */ 14986f45ec7bSml29623 uint32_t ext : 1; /* 62 set to 1 */ 14996f45ec7bSml29623 uint32_t fmt : 1; /* 63 1 for ipv6, 0 for ipv4 */ 15006f45ec7bSml29623 #endif 15016f45ec7bSml29623 } exact_hdr; 15026f45ec7bSml29623 hash_optim_t optim_hdr; 15036f45ec7bSml29623 } hash_hdr_t; 15046f45ec7bSml29623 15056f45ec7bSml29623 15066f45ec7bSml29623 15076f45ec7bSml29623 typedef union _hash_ports { 15086f45ec7bSml29623 uint64_t value; 15096f45ec7bSml29623 struct _ports_bits { 15106f45ec7bSml29623 #if defined(_BIG_ENDIAN) 15116f45ec7bSml29623 uint32_t ip_dport : 16; /* 63 : 48 */ 15126f45ec7bSml29623 uint32_t ip_sport : 16; /* 47 : 32 */ 15136f45ec7bSml29623 uint32_t proto : 8; /* 31 : 24 */ 15146f45ec7bSml29623 uint32_t port : 2; /* 23 : 22 */ 15156f45ec7bSml29623 uint32_t rsrvd : 22; /* 21 : 0 */ 15166f45ec7bSml29623 #else 15176f45ec7bSml29623 uint32_t rsrvd : 22; /* 21 : 0 */ 15186f45ec7bSml29623 uint32_t port : 2; /* 23 : 22 */ 15196f45ec7bSml29623 uint32_t proto : 8; /* 31 : 24 */ 15206f45ec7bSml29623 uint32_t ip_sport : 16; /* 47 : 32 */ 15216f45ec7bSml29623 uint32_t ip_dport : 16; /* 63 : 48 */ 15226f45ec7bSml29623 #endif 15236f45ec7bSml29623 } ports_bits; 15246f45ec7bSml29623 } hash_ports_t; 15256f45ec7bSml29623 15266f45ec7bSml29623 15276f45ec7bSml29623 15286f45ec7bSml29623 typedef union _hash_match_action { 15296f45ec7bSml29623 uint64_t value; 15306f45ec7bSml29623 struct _action_bits { 15316f45ec7bSml29623 #if defined(_BIG_ENDIAN) 15326f45ec7bSml29623 uint32_t rsrvd2 : 3; /* 63 : 61 */ 15336f45ec7bSml29623 uint32_t rdc_offset : 5; /* 60 : 56 */ 15346f45ec7bSml29623 uint32_t zfvld : 1; /* 55 */ 15356f45ec7bSml29623 uint32_t rsrvd : 3; /* 54 : 52 */ 15366f45ec7bSml29623 uint32_t zfid : 12; /* 51 : 40 */ 15376f45ec7bSml29623 uint32_t _rsrvd : 8; /* 39 : 32 */ 15386f45ec7bSml29623 uint32_t usr_info; /* 31 : 0 */ 15396f45ec7bSml29623 #else 15406f45ec7bSml29623 uint32_t usr_info; /* 31 : 0 */ 15416f45ec7bSml29623 uint32_t _rsrvd : 8; /* 39 : 32 */ 15426f45ec7bSml29623 uint32_t zfid : 12; /* 51 : 40 */ 15436f45ec7bSml29623 uint32_t rsrvd : 3; /* 54 : 52 */ 15446f45ec7bSml29623 uint32_t zfvld : 1; /* 55 */ 15456f45ec7bSml29623 uint32_t rdc_offset : 5; /* 60 : 56 */ 15466f45ec7bSml29623 uint32_t rsrvd2 : 1; /* 63 : 61 */ 15476f45ec7bSml29623 #endif 15486f45ec7bSml29623 } action_bits; 15496f45ec7bSml29623 } hash_match_action_t; 15506f45ec7bSml29623 15516f45ec7bSml29623 15526f45ec7bSml29623 typedef struct _ipaddr6 { 15536f45ec7bSml29623 struct in6_addr saddr; 15546f45ec7bSml29623 struct in6_addr daddr; 15556f45ec7bSml29623 } ip6_addr_t; 15566f45ec7bSml29623 15576f45ec7bSml29623 15586f45ec7bSml29623 typedef struct _ipaddr4 { 15596f45ec7bSml29623 #if defined(_BIG_ENDIAN) 15606f45ec7bSml29623 struct in_addr saddr; 15616f45ec7bSml29623 struct in_addr daddr; 15626f45ec7bSml29623 #else 15636f45ec7bSml29623 struct in_addr daddr; 15646f45ec7bSml29623 struct in_addr saddr; 15656f45ec7bSml29623 #endif 15666f45ec7bSml29623 } ip4_addr_t; 15676f45ec7bSml29623 15686f45ec7bSml29623 15696f45ec7bSml29623 /* ipv4 has 32 byte layout */ 15706f45ec7bSml29623 15716f45ec7bSml29623 typedef struct hash_ipv4 { 15726f45ec7bSml29623 hash_hdr_t hdr; 15736f45ec7bSml29623 ip4_addr_t ip_addr; 15746f45ec7bSml29623 hash_ports_t proto_ports; 15756f45ec7bSml29623 hash_match_action_t action; 15766f45ec7bSml29623 } hash_ipv4_t; 15776f45ec7bSml29623 15786f45ec7bSml29623 15796f45ec7bSml29623 /* ipv4 has 56 byte layout */ 15806f45ec7bSml29623 typedef struct hash_ipv6 { 15816f45ec7bSml29623 hash_hdr_t hdr; 15826f45ec7bSml29623 ip6_addr_t ip_addr; 15836f45ec7bSml29623 hash_ports_t proto_ports; 15846f45ec7bSml29623 hash_match_action_t action; 15856f45ec7bSml29623 } hash_ipv6_t; 15866f45ec7bSml29623 15876f45ec7bSml29623 15886f45ec7bSml29623 15896f45ec7bSml29623 typedef union fcram_entry { 15906f45ec7bSml29623 uint64_t value[8]; 15916f45ec7bSml29623 hash_tbl_data_t dreg[8]; 15926f45ec7bSml29623 hash_ipv6_t ipv6_entry; 15936f45ec7bSml29623 hash_ipv4_t ipv4_entry; 15946f45ec7bSml29623 hash_optim_t optim_entry; 15956f45ec7bSml29623 } fcram_entry_t; 15966f45ec7bSml29623 15976f45ec7bSml29623 15986f45ec7bSml29623 15996f45ec7bSml29623 #define hash_hdr_fmt ipv4_entry.hdr.exact_hdr.fmt 16006f45ec7bSml29623 #define hash_hdr_ext ipv4_entry.hdr.exact_hdr.ext 16016f45ec7bSml29623 #define hash_hdr_valid ipv4_entry.hdr.exact_hdr.valid 16026f45ec7bSml29623 16036f45ec7bSml29623 #define HASH_ENTRY_EXACT(fc) \ 16046f45ec7bSml29623 (fc->ipv4_entry.hdr.exact_hdr.ext == 1) 16056f45ec7bSml29623 #define HASH_ENTRY_OPTIM(fc) \ 16066f45ec7bSml29623 ((fc->ipv4_entry.hdr.exact_hdr.ext == 0) && \ 16076f45ec7bSml29623 (fc->ipv6_entry.hdr.exact_hdr.fmt == 0)) 16086f45ec7bSml29623 #define HASH_ENTRY_EXACT_IP6(fc) \ 16096f45ec7bSml29623 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 1) && \ 16106f45ec7bSml29623 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 16116f45ec7bSml29623 16126f45ec7bSml29623 #define HASH_ENTRY_EXACT_IP4(fc) \ 16136f45ec7bSml29623 ((fc->ipv6_entry.hdr.exact_hdr.fmt == 0) && \ 16146f45ec7bSml29623 (fc->ipv4_entry.hdr.exact_hdr.ext == 1)) 16156f45ec7bSml29623 16166f45ec7bSml29623 #define HASH_ENTRY_TYPE(fc) \ 16176f45ec7bSml29623 (fc->ipv4_entry.hdr.exact_hdr.ext | \ 16186f45ec7bSml29623 (fc->ipv4_entry.hdr.exact_hdr.fmt << 1)) 16196f45ec7bSml29623 16206f45ec7bSml29623 16216f45ec7bSml29623 16226f45ec7bSml29623 typedef enum fcram_entry_format { 16236f45ec7bSml29623 FCRAM_ENTRY_OPTIM = 0x0, 16246f45ec7bSml29623 FCRAM_ENTRY_EX_IP4 = 0x2, 16256f45ec7bSml29623 FCRAM_ENTRY_EX_IP6 = 0x3, 16266f45ec7bSml29623 FCRAM_ENTRY_UNKOWN = 0x1 16276f45ec7bSml29623 } fcram_entry_format_t; 16286f45ec7bSml29623 16296f45ec7bSml29623 16306f45ec7bSml29623 #define HASH_ENTRY_TYPE_OPTIM FCRAM_ENTRY_OPTIM 16316f45ec7bSml29623 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 16326f45ec7bSml29623 #define HASH_ENTRY_TYPE_OPTIM_IP4 FCRAM_ENTRY_OPTIM 16336f45ec7bSml29623 #define HASH_ENTRY_TYPE_EX_IP4 FCRAM_ENTRY_EX_IP4 16346f45ec7bSml29623 #define HASH_ENTRY_TYPE_EX_IP6 FCRAM_ENTRY_EX_IP6 16356f45ec7bSml29623 16366f45ec7bSml29623 16376f45ec7bSml29623 16386f45ec7bSml29623 16396f45ec7bSml29623 /* error xxx formats */ 16406f45ec7bSml29623 16416f45ec7bSml29623 16426f45ec7bSml29623 typedef struct _hash_lookup_err_log { 16436f45ec7bSml29623 uint32_t rsrvd:28; 16446f45ec7bSml29623 uint32_t lookup_err:1; 16456f45ec7bSml29623 uint32_t ecc_err:1; 16466f45ec7bSml29623 uint32_t uncor_err:1; 16476f45ec7bSml29623 uint32_t multi_lkup:1; 16486f45ec7bSml29623 uint32_t multi_bit:1; 16496f45ec7bSml29623 uint32_t subarea:3; 16506f45ec7bSml29623 uint32_t syndrome:8; 16516f45ec7bSml29623 uint32_t h1:20; 16526f45ec7bSml29623 } hash_lookup_err_log_t, *p_hash_lookup_err_log_t; 16536f45ec7bSml29623 16546f45ec7bSml29623 16556f45ec7bSml29623 16566f45ec7bSml29623 typedef struct _hash_pio_err_log { 16576f45ec7bSml29623 uint32_t rsrvd:32; 16586f45ec7bSml29623 uint32_t pio_err:1; 16596f45ec7bSml29623 uint32_t syndrome:8; 16606f45ec7bSml29623 uint32_t addr:23; 16616f45ec7bSml29623 } hash_pio_err_log_t, *p_hash_pio_err_log_t; 16626f45ec7bSml29623 16636f45ec7bSml29623 16646f45ec7bSml29623 16656f45ec7bSml29623 typedef struct _tcam_err_log { 16666f45ec7bSml29623 uint32_t rsrvd:2; 16676f45ec7bSml29623 uint32_t tcam_err:1; 16686f45ec7bSml29623 uint32_t parity_err:1; 16696f45ec7bSml29623 uint32_t ecc_err:1; 16706f45ec7bSml29623 uint32_t multi_lkup:1; 16716f45ec7bSml29623 uint32_t location:8; 16726f45ec7bSml29623 uint32_t syndrome:16; 16736f45ec7bSml29623 } tcam_err_log_t, *p_tcam_err_log_t; 16746f45ec7bSml29623 16756f45ec7bSml29623 16766f45ec7bSml29623 typedef struct _vlan_tbl_err_log { 16776f45ec7bSml29623 uint32_t rsrvd:32; 16786f45ec7bSml29623 uint32_t err:1; 16796f45ec7bSml29623 uint32_t multi:1; 16806f45ec7bSml29623 uint32_t addr:12; 16816f45ec7bSml29623 uint32_t data:18; 16826f45ec7bSml29623 } vlan_tbl_err_log_t, *p_vlan_tbl_err_log_t; 16836f45ec7bSml29623 16846f45ec7bSml29623 16856f45ec7bSml29623 #define NEPTUNE_TCAM_SIZE 0x100 16866f45ec7bSml29623 #define NIU_TCAM_SIZE 0x80 16876f45ec7bSml29623 #define FCRAM_SIZE 0x100000 16886f45ec7bSml29623 16896f45ec7bSml29623 #ifdef __cplusplus 16906f45ec7bSml29623 } 16916f45ec7bSml29623 #endif 16926f45ec7bSml29623 16936f45ec7bSml29623 #endif /* _SYS_NXGE_NXGE_FFLP_HW_H */ 1694