100d0963fSdilpreet /* 200d0963fSdilpreet * CDDL HEADER START 300d0963fSdilpreet * 400d0963fSdilpreet * The contents of this file are subject to the terms of the 500d0963fSdilpreet * Common Development and Distribution License (the "License"). 600d0963fSdilpreet * You may not use this file except in compliance with the License. 700d0963fSdilpreet * 800d0963fSdilpreet * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 900d0963fSdilpreet * or http://www.opensolaris.org/os/licensing. 1000d0963fSdilpreet * See the License for the specific language governing permissions 1100d0963fSdilpreet * and limitations under the License. 1200d0963fSdilpreet * 1300d0963fSdilpreet * When distributing Covered Code, include this CDDL HEADER in each 1400d0963fSdilpreet * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1500d0963fSdilpreet * If applicable, add the following below this CDDL HEADER, with the 1600d0963fSdilpreet * fields enclosed by brackets "[]" replaced with your own identifying 1700d0963fSdilpreet * information: Portions Copyright [yyyy] [name of copyright owner] 1800d0963fSdilpreet * 1900d0963fSdilpreet * CDDL HEADER END 2000d0963fSdilpreet */ 2100d0963fSdilpreet /* 22*49fbdd30SErwin T Tsaur * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 2300d0963fSdilpreet * Use is subject to license terms. 2400d0963fSdilpreet */ 2500d0963fSdilpreet 2600d0963fSdilpreet #ifndef _SYS_PCIFM_H 2700d0963fSdilpreet #define _SYS_PCIFM_H 2800d0963fSdilpreet 2900d0963fSdilpreet #include <sys/dditypes.h> /* for ddi_acc_handle_t */ 3000d0963fSdilpreet 3100d0963fSdilpreet #ifdef __cplusplus 3200d0963fSdilpreet extern "C" { 3300d0963fSdilpreet #endif 3400d0963fSdilpreet 3500d0963fSdilpreet 3600d0963fSdilpreet /* 3700d0963fSdilpreet * PCI device type defines. 3800d0963fSdilpreet */ 3900d0963fSdilpreet #define PCI_BRIDGE_DEV 0x02 4000d0963fSdilpreet #define PCIX_DEV 0x04 4100d0963fSdilpreet 4200d0963fSdilpreet /* 4300d0963fSdilpreet * PCI and PCI-X valid flags 4400d0963fSdilpreet */ 4500d0963fSdilpreet #define PCI_ERR_STATUS_VALID 0x1 4600d0963fSdilpreet #define PCI_BDG_SEC_STAT_VALID 0x2 4700d0963fSdilpreet #define PCI_BDG_CTRL_VALID 0x4 4800d0963fSdilpreet #define PCIX_ERR_STATUS_VALID 0x8 4900d0963fSdilpreet #define PCIX_ERR_ECC_STS_VALID 0x10 5000d0963fSdilpreet #define PCIX_ERR_S_ECC_STS_VALID 0x20 5100d0963fSdilpreet #define PCIX_BDG_STATUS_VALID 0x40 5200d0963fSdilpreet #define PCIX_BDG_SEC_STATUS_VALID 0x80 5300d0963fSdilpreet 5400d0963fSdilpreet 5500d0963fSdilpreet /* 5600d0963fSdilpreet * PCI(-X) structures used (by pci_ereport_setup, pci_ereport_post, and 5700d0963fSdilpreet * pci_ereport_teardown) to gather and report errors detected by PCI(-X) 5800d0963fSdilpreet * compliant devices. 5900d0963fSdilpreet */ 6000d0963fSdilpreet typedef struct pci_bdg_error_regs { 6100d0963fSdilpreet uint16_t pci_bdg_vflags; /* status valid bits */ 6200d0963fSdilpreet uint16_t pci_bdg_sec_stat; /* PCI secondary status reg */ 6300d0963fSdilpreet uint16_t pci_bdg_ctrl; /* PCI bridge control reg */ 6400d0963fSdilpreet } pci_bdg_error_regs_t; 6500d0963fSdilpreet 6600d0963fSdilpreet typedef struct pci_error_regs { 6700d0963fSdilpreet uint16_t pci_vflags; /* status valid bits */ 6800d0963fSdilpreet uint8_t pci_cap_ptr; /* PCI Capability pointer */ 6900d0963fSdilpreet uint16_t pci_err_status; /* pci status register */ 7000d0963fSdilpreet uint16_t pci_cfg_comm; /* pci command register */ 7100d0963fSdilpreet pci_bdg_error_regs_t *pci_bdg_regs; 7200d0963fSdilpreet } pci_error_regs_t; 7300d0963fSdilpreet 7400d0963fSdilpreet typedef struct pci_erpt { 7500d0963fSdilpreet ddi_acc_handle_t pe_hdl; /* Config space access handle */ 7600d0963fSdilpreet uint64_t pe_dflags; /* Device type flags */ 7700d0963fSdilpreet uint16_t pe_bdf; /* bus/device/function of device */ 7800d0963fSdilpreet pci_error_regs_t *pe_pci_regs; /* PCI generic error registers */ 7900d0963fSdilpreet void *pe_regs; /* Pointer to extended error regs */ 8000d0963fSdilpreet } pci_erpt_t; 8100d0963fSdilpreet 8200d0963fSdilpreet typedef struct pcix_ecc_regs { 8300d0963fSdilpreet uint16_t pcix_ecc_vflags; /* pcix ecc valid flags */ 8400d0963fSdilpreet uint16_t pcix_ecc_bdf; /* pcix ecc bdf */ 8500d0963fSdilpreet uint32_t pcix_ecc_ctlstat; /* pcix ecc control status reg */ 8600d0963fSdilpreet uint32_t pcix_ecc_fstaddr; /* pcix ecc first address reg */ 8700d0963fSdilpreet uint32_t pcix_ecc_secaddr; /* pcix ecc second address reg */ 8800d0963fSdilpreet uint32_t pcix_ecc_attr; /* pcix ecc attributes reg */ 8900d0963fSdilpreet } pcix_ecc_regs_t; 9000d0963fSdilpreet 9100d0963fSdilpreet typedef struct pcix_error_regs { 9200d0963fSdilpreet uint16_t pcix_vflags; /* pcix valid flags */ 9300d0963fSdilpreet uint8_t pcix_cap_ptr; /* pcix capability pointer */ 9400d0963fSdilpreet uint16_t pcix_ver; /* pcix version */ 9500d0963fSdilpreet uint16_t pcix_command; /* pcix command register */ 9600d0963fSdilpreet uint32_t pcix_status; /* pcix status register */ 9700d0963fSdilpreet pcix_ecc_regs_t *pcix_ecc_regs; /* pcix ecc registers */ 9800d0963fSdilpreet } pcix_error_regs_t; 9900d0963fSdilpreet 10000d0963fSdilpreet typedef struct pcix_bdg_error_regs { 10100d0963fSdilpreet uint16_t pcix_bdg_vflags; /* pcix valid flags */ 10200d0963fSdilpreet uint8_t pcix_bdg_cap_ptr; /* pcix bridge capability pointer */ 10300d0963fSdilpreet uint16_t pcix_bdg_ver; /* pcix version */ 10400d0963fSdilpreet uint16_t pcix_bdg_sec_stat; /* pcix bridge secondary status reg */ 10500d0963fSdilpreet uint32_t pcix_bdg_stat; /* pcix bridge status reg */ 10600d0963fSdilpreet pcix_ecc_regs_t *pcix_bdg_ecc_regs[2]; /* pcix ecc registers */ 10700d0963fSdilpreet } pcix_bdg_error_regs_t; 10800d0963fSdilpreet 10900d0963fSdilpreet /* 1108aec9182Sstephh * pcie bus specific structure 1118aec9182Sstephh */ 1128aec9182Sstephh 1138aec9182Sstephh typedef struct pci_fme_bus_specific { 1148aec9182Sstephh int pci_bs_type; 1158aec9182Sstephh uint64_t pci_bs_addr; 1168aec9182Sstephh uint16_t pci_bs_bdf; 1178aec9182Sstephh int pci_bs_flags; 1188aec9182Sstephh } pci_fme_bus_specific_t; 1198aec9182Sstephh 1208aec9182Sstephh #define PCI_BS_ADDR_VALID 1 1218aec9182Sstephh #define PCI_BS_BDF_VALID 2 1228aec9182Sstephh 1238aec9182Sstephh /* 12400d0963fSdilpreet * target error queue defines 12500d0963fSdilpreet */ 12600d0963fSdilpreet #define TARGET_MAX_ERRS 6 12700d0963fSdilpreet #define TGT_PCI_SPACE_UNKNOWN 4 12800d0963fSdilpreet 12900d0963fSdilpreet typedef struct pci_target_err { 13000d0963fSdilpreet uint64_t tgt_err_addr; 13100d0963fSdilpreet uint64_t tgt_err_ena; 13200d0963fSdilpreet uint64_t tgt_pci_addr; 13300d0963fSdilpreet uint32_t tgt_pci_space; 13400d0963fSdilpreet dev_info_t *tgt_dip; 13500d0963fSdilpreet char *tgt_err_class; 13600d0963fSdilpreet char *tgt_bridge_type; 13700d0963fSdilpreet } pci_target_err_t; 13800d0963fSdilpreet 13900d0963fSdilpreet #define PCI_FM_SEV_INC(x) ((x) == DDI_FM_FATAL) ? fatal++ :\ 14000d0963fSdilpreet (((x) == DDI_FM_NONFATAL) ? nonfatal++ :\ 14100d0963fSdilpreet (((x) == DDI_FM_UNKNOWN) ? unknown++ : ok++)); 14200d0963fSdilpreet 14300d0963fSdilpreet #ifdef __cplusplus 14400d0963fSdilpreet } 14500d0963fSdilpreet #endif 14600d0963fSdilpreet 14700d0963fSdilpreet #endif /* _SYS_PCIFM_H */ 148