15cff7825Smh27603 /* 25cff7825Smh27603 * CDDL HEADER START 35cff7825Smh27603 * 45cff7825Smh27603 * The contents of this file are subject to the terms of the 55cff7825Smh27603 * Common Development and Distribution License (the "License"). 65cff7825Smh27603 * You may not use this file except in compliance with the License. 75cff7825Smh27603 * 85cff7825Smh27603 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 95cff7825Smh27603 * or http://www.opensolaris.org/os/licensing. 105cff7825Smh27603 * See the License for the specific language governing permissions 115cff7825Smh27603 * and limitations under the License. 125cff7825Smh27603 * 135cff7825Smh27603 * When distributing Covered Code, include this CDDL HEADER in each 145cff7825Smh27603 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 155cff7825Smh27603 * If applicable, add the following below this CDDL HEADER, with the 165cff7825Smh27603 * fields enclosed by brackets "[]" replaced with your own identifying 175cff7825Smh27603 * information: Portions Copyright [yyyy] [name of copyright owner] 185cff7825Smh27603 * 195cff7825Smh27603 * CDDL HEADER END 205cff7825Smh27603 */ 215cff7825Smh27603 /* 22*444f66e7SMark Haywood * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 235cff7825Smh27603 * Use is subject to license terms. 245cff7825Smh27603 */ 25*444f66e7SMark Haywood /* 26*444f66e7SMark Haywood * Copyright (c) 2009, Intel Corporation. 27*444f66e7SMark Haywood * All Rights Reserved. 28*444f66e7SMark Haywood */ 295cff7825Smh27603 305cff7825Smh27603 #ifndef _SYS_PPMVAR_H 315cff7825Smh27603 #define _SYS_PPMVAR_H 325cff7825Smh27603 335cff7825Smh27603 #include <sys/epm.h> 345cff7825Smh27603 #include <sys/sunldi.h> 355cff7825Smh27603 365cff7825Smh27603 #ifdef __cplusplus 375cff7825Smh27603 extern "C" { 385cff7825Smh27603 #endif 395cff7825Smh27603 405cff7825Smh27603 415cff7825Smh27603 typedef struct ppm_unit { 425cff7825Smh27603 dev_info_t *dip; /* node dev info */ 435cff7825Smh27603 kmutex_t lock; /* global driver lock */ 445cff7825Smh27603 uint_t states; /* driver states */ 455cff7825Smh27603 timeout_id_t led_tid; /* timeout id for LED */ 465cff7825Smh27603 } ppm_unit_t; 475cff7825Smh27603 485cff7825Smh27603 /* 495cff7825Smh27603 * driver states 505cff7825Smh27603 */ 515cff7825Smh27603 #define PPM_STATE_SUSPENDED 0x1 /* driver is suspended */ 525cff7825Smh27603 535cff7825Smh27603 /* 545cff7825Smh27603 * Check for domain operational 555cff7825Smh27603 */ 565cff7825Smh27603 #define PPM_DOMAIN_UP(domp) (!(domp->dflags & PPMD_OFFLINE)) 575cff7825Smh27603 585cff7825Smh27603 /* 595cff7825Smh27603 * LED constants 605cff7825Smh27603 */ 615cff7825Smh27603 #define PPM_LED_PULSE (drv_usectohz(250000)) /* 0.25 seconds */ 625cff7825Smh27603 #define PPM_LEDON_INTERVAL (1 * PPM_LED_PULSE) 635cff7825Smh27603 #define PPM_LEDOFF_INTERVAL (8 * PPM_LED_PULSE) 645cff7825Smh27603 #define PPM_LEDON 1 /* (s10) */ 655cff7825Smh27603 #define PPM_LEDOFF 0 /* (s10) */ 665cff7825Smh27603 675cff7825Smh27603 /* 685cff7825Smh27603 * internal form of "ppm.conf" data 695cff7825Smh27603 */ 705cff7825Smh27603 struct ppm_db { 715cff7825Smh27603 struct ppm_db *next; 725cff7825Smh27603 char *name; /* device name */ 735cff7825Smh27603 int plen; /* strlen before wildcard(s10) */ 745cff7825Smh27603 int wccnt; /* upto 2 '*' allowed */ 755cff7825Smh27603 int wcpos[2]; /* '*' location in pathname */ 765cff7825Smh27603 }; 775cff7825Smh27603 typedef struct ppm_db ppm_db_t; 785cff7825Smh27603 795cff7825Smh27603 struct ppm_cdata { 805cff7825Smh27603 char *name; /* property name */ 815cff7825Smh27603 char **strings; /* string array */ 825cff7825Smh27603 uint_t cnt; /* property count */ 835cff7825Smh27603 }; 845cff7825Smh27603 855cff7825Smh27603 /* 865cff7825Smh27603 * ppm device info 875cff7825Smh27603 */ 885cff7825Smh27603 struct ppm_dev { 895cff7825Smh27603 struct ppm_dev *next; 905cff7825Smh27603 struct ppm_domain *domp; 915cff7825Smh27603 dev_info_t *dip; 925cff7825Smh27603 char *path; /* OBP device pathname */ 935cff7825Smh27603 int cmpt; /* component number */ 945cff7825Smh27603 int rplvl; /* last requested power level */ 955cff7825Smh27603 int level; /* actual current power level */ 965cff7825Smh27603 int lowest; /* lowest power level for device */ 975cff7825Smh27603 int highest; /* highest power level for device */ 985cff7825Smh27603 uint_t flags; 995cff7825Smh27603 }; 1005cff7825Smh27603 typedef struct ppm_dev ppm_dev_t; 1015cff7825Smh27603 1025cff7825Smh27603 /* 1035cff7825Smh27603 * ppm_dev.flags field 1045cff7825Smh27603 */ 1055cff7825Smh27603 #define PPMDEV_PCI66_D2 0x1 /* device support D2 at pci 66mhz */ 1065cff7825Smh27603 #define PPMDEV_PCI_PROP_CLKPM 0x2 /* clock can be power managed */ 1075cff7825Smh27603 #define PPM_PM_POWEROP 0x10 /* power level change, initiated */ 1085cff7825Smh27603 /* from PM is in progress. */ 1095cff7825Smh27603 #define PPM_PHC_WHILE_SET_POWER 0x20 /* power level of a device is */ 1105cff7825Smh27603 /* changed through */ 1115cff7825Smh27603 /* pm_power_has_changed path */ 1125cff7825Smh27603 /* while power level change, */ 1135cff7825Smh27603 /* initiated from PM is in */ 1145cff7825Smh27603 /* progress. */ 1155cff7825Smh27603 1165cff7825Smh27603 1175cff7825Smh27603 /* 1185cff7825Smh27603 * per domain record of device _ever_ managed by ppm 1195cff7825Smh27603 */ 1205cff7825Smh27603 struct ppm_owned { 1215cff7825Smh27603 struct ppm_owned *next; 1225cff7825Smh27603 char *path; /* device pathname */ 1235cff7825Smh27603 int initializing; /* initializing flag */ 1245cff7825Smh27603 }; 1255cff7825Smh27603 typedef struct ppm_owned ppm_owned_t; 1265cff7825Smh27603 1275cff7825Smh27603 1285cff7825Smh27603 /* 1295cff7825Smh27603 * domain control data structure - 1305cff7825Smh27603 * when you need to do an op for a domain, look up the op in the 1315cff7825Smh27603 * cmd member of the struct, and then perform the method on the 1325cff7825Smh27603 * path using iowr cmd with the args specified in val or val and 1335cff7825Smh27603 * mask or the speed index. 1345cff7825Smh27603 */ 1355cff7825Smh27603 struct ppm_dc { 1365cff7825Smh27603 struct ppm_dc *next; 1375cff7825Smh27603 ldi_handle_t lh; /* layered (ldi) handle */ 1385cff7825Smh27603 char *path; /* control device prom pathname */ 1395cff7825Smh27603 uint_t cmd; /* search key: op to be performed */ 1402df1fe9cSrandyf /* one of: PPMDC_CPU_NEXT */ 1412df1fe9cSrandyf /* PPMDC_CPU_GO, PPMDC_FET_ON, */ 1422df1fe9cSrandyf /* PPMDC_FET_OFF, PPMDC_LED_ON, */ 1432df1fe9cSrandyf /* PPMDC_LED_OFF, PPMDC_PCI_ON, */ 1442df1fe9cSrandyf /* PPMDC_ENTER_S3, PPMDC_PCI_OFF */ 1452df1fe9cSrandyf /* PPMDC_EXIT_S3 commands */ 1465cff7825Smh27603 uint_t method; /* control method / union selector */ 1475cff7825Smh27603 /* one of PPMDC_KIO, PPMDC_I2CKIO, */ 1485cff7825Smh27603 /* PPMDC_CPUSPEEDKIO */ 1495cff7825Smh27603 1505cff7825Smh27603 union { 1515cff7825Smh27603 /* In each sub struct in union, the first three fields */ 1525cff7825Smh27603 /* must be .iord, .iowr and .val and in such order. */ 1535cff7825Smh27603 /* The .method field above selects a union sub struct */ 1545cff7825Smh27603 /* for a particular .cmd operation. */ 1555cff7825Smh27603 /* The association between .method and .cmd is platform */ 1565cff7825Smh27603 /* specific, therefore described in ppm.conf file. */ 1575cff7825Smh27603 1585cff7825Smh27603 /* PPMDC_KIO: simple KIO */ 1595cff7825Smh27603 struct m_kio { 1605cff7825Smh27603 uint_t iord; /* IOCTL read cmd */ 1615cff7825Smh27603 uint_t iowr; /* IOCTL write cmd */ 1625cff7825Smh27603 uint_t val; /* ioctl arg */ 1635cff7825Smh27603 uint_t delay; /* total delay before this */ 1645cff7825Smh27603 /* operation can be carried out */ 1655cff7825Smh27603 uint_t post_delay; /* post delay, if any */ 1665cff7825Smh27603 } kio; 1675cff7825Smh27603 1682df1fe9cSrandyf #ifdef sun4u 1695cff7825Smh27603 /* PPMDC_I2CKIO: KIO requires 'arg' as struct i2c_gpio */ 1705cff7825Smh27603 /* (defined in i2c_client.h) */ 1715cff7825Smh27603 struct m_i2ckio { 1725cff7825Smh27603 uint_t iord; /* IOCTL read cmd */ 1735cff7825Smh27603 uint_t iowr; /* IOCTL write cmd */ 1745cff7825Smh27603 uint_t val; /* register content */ 1755cff7825Smh27603 uint_t mask; /* mask to select relevant bits */ 1765cff7825Smh27603 /* of register content */ 1775cff7825Smh27603 uint_t delay; /* total delay before this */ 1785cff7825Smh27603 /* operation can be carried out */ 1795cff7825Smh27603 uint_t post_delay; /* post delay, if any */ 1805cff7825Smh27603 } i2c; 1812df1fe9cSrandyf #endif 1825cff7825Smh27603 1835cff7825Smh27603 /* PPMDC_CPUSPEEDKIO, PPMDC_VCORE: cpu estar related */ 1845cff7825Smh27603 /* simple KIO */ 1855cff7825Smh27603 struct m_cpu { 1865cff7825Smh27603 uint_t iord; /* IOCTL read cmd */ 1875cff7825Smh27603 uint_t iowr; /* IOCTL write cmd */ 1885cff7825Smh27603 int val; /* new register value */ 1895cff7825Smh27603 uint_t speeds; /* number of speeds cpu supports */ 1905cff7825Smh27603 uint_t delay; /* microseconds post op delay */ 1915cff7825Smh27603 } cpu; 1925cff7825Smh27603 } m_un; 1935cff7825Smh27603 }; 1945cff7825Smh27603 typedef struct ppm_dc ppm_dc_t; 1955cff7825Smh27603 1965cff7825Smh27603 /* 1975cff7825Smh27603 * ppm_dc.cmd field - 1985cff7825Smh27603 */ 1995cff7825Smh27603 #define PPMDC_CPU_NEXT 2 2005cff7825Smh27603 #define PPMDC_PRE_CHNG 3 2015cff7825Smh27603 #define PPMDC_CPU_GO 4 2025cff7825Smh27603 #define PPMDC_POST_CHNG 5 2035cff7825Smh27603 #define PPMDC_FET_ON 6 2045cff7825Smh27603 #define PPMDC_FET_OFF 7 2055cff7825Smh27603 #define PPMDC_LED_ON 8 2065cff7825Smh27603 #define PPMDC_LED_OFF 9 2075cff7825Smh27603 #define PPMDC_CLK_ON 10 2085cff7825Smh27603 #define PPMDC_CLK_OFF 11 2095cff7825Smh27603 #define PPMDC_PRE_PWR_OFF 12 2105cff7825Smh27603 #define PPMDC_PRE_PWR_ON 13 2115cff7825Smh27603 #define PPMDC_POST_PWR_ON 14 2125cff7825Smh27603 #define PPMDC_PWR_OFF 15 2135cff7825Smh27603 #define PPMDC_PWR_ON 16 2145cff7825Smh27603 #define PPMDC_RESET_OFF 17 2155cff7825Smh27603 #define PPMDC_RESET_ON 18 2162df1fe9cSrandyf #define PPMDC_ENTER_S3 19 2172df1fe9cSrandyf #define PPMDC_EXIT_S3 20 2185cff7825Smh27603 2195cff7825Smh27603 /* 2205cff7825Smh27603 * ppm_dc.method field - select union element 2215cff7825Smh27603 */ 2225cff7825Smh27603 #define PPMDC_KIO 1 /* simple ioctl with val as arg */ 2235cff7825Smh27603 #define PPMDC_CPUSPEEDKIO 2 /* ioctl with speed index arg */ 2245cff7825Smh27603 #define PPMDC_VCORE 3 /* CPU Vcore change operation */ 2252df1fe9cSrandyf #ifdef sun4u 2265cff7825Smh27603 #define PPMDC_I2CKIO 4 /* ioctl with i2c_gpio_t as arg */ 2272df1fe9cSrandyf #endif 2285cff7825Smh27603 2295cff7825Smh27603 /* 2305cff7825Smh27603 * devices that are powered by the same source 2315cff7825Smh27603 * are grouped by this struct as a "power domain" 2325cff7825Smh27603 */ 2335cff7825Smh27603 struct ppm_domain { 2345cff7825Smh27603 char *name; /* domain name */ 2355cff7825Smh27603 int dflags; /* domain flags */ 2365cff7825Smh27603 int pwr_cnt; /* number of powered up devices */ 2375cff7825Smh27603 ppm_db_t *conflist; /* all devices from ppm.conf file */ 2385cff7825Smh27603 ppm_dev_t *devlist; /* current attached devices */ 2395cff7825Smh27603 char *propname; /* domain property name */ 2405cff7825Smh27603 kmutex_t lock; /* domain lock */ 2415cff7825Smh27603 int refcnt; /* domain lock ref count */ 2425cff7825Smh27603 int model; /* pm model, CPU, FET or LED */ 2435cff7825Smh27603 int status; /* domain specific status */ 244*444f66e7SMark Haywood int sub_domain; /* sub-domain */ 2455cff7825Smh27603 ppm_dc_t *dc; /* domain control method */ 2465cff7825Smh27603 ppm_owned_t *owned; /* list of ever owned devices */ 2475cff7825Smh27603 struct ppm_domain *next; /* a linked list */ 2485cff7825Smh27603 clock_t last_off_time; /* last time domain was off */ 2495cff7825Smh27603 2505cff7825Smh27603 }; 2515cff7825Smh27603 typedef struct ppm_domain ppm_domain_t; 2525cff7825Smh27603 2535cff7825Smh27603 2545cff7825Smh27603 /* 2555cff7825Smh27603 * ppm_domain.model field - 2565cff7825Smh27603 */ 2575cff7825Smh27603 #define PPMD_CPU 1 /* cpu PM model */ 2585cff7825Smh27603 #define PPMD_FET 2 /* power FET pm model */ 2595cff7825Smh27603 #define PPMD_LED 3 /* LED pm model */ 2605cff7825Smh27603 #define PPMD_PCI 4 /* PCI pm model */ 2615cff7825Smh27603 #define PPMD_PCI_PROP 5 /* PCI_PROP pm model */ 2625cff7825Smh27603 #define PPMD_PCIE 6 /* PCI Express pm model */ 2632df1fe9cSrandyf #define PPMD_SX 7 /* ACPI Sx pm model */ 2645cff7825Smh27603 2655cff7825Smh27603 #define PPMD_IS_PCI(model) \ 2665cff7825Smh27603 ((model) == PPMD_PCI || (model) == PPMD_PCI_PROP) 2675cff7825Smh27603 2685cff7825Smh27603 /* 2695cff7825Smh27603 * ppm_domain.status field - 2705cff7825Smh27603 */ 2715cff7825Smh27603 #define PPMD_OFF 0x0 /* FET/LED/PCI clock: off */ 2725cff7825Smh27603 #define PPMD_ON 0x1 /* FET/LED/PCI clock: on */ 2735cff7825Smh27603 2745cff7825Smh27603 /* 2755cff7825Smh27603 * ppm_domain.dflags field - 2765cff7825Smh27603 */ 2775cff7825Smh27603 #define PPMD_LOCK_ONE 0x1 2785cff7825Smh27603 #define PPMD_LOCK_ALL 0x4 2795cff7825Smh27603 #define PPMD_PCI33MHZ 0x1000 /* 33mhz PCI slot */ 2805cff7825Smh27603 #define PPMD_PCI66MHZ 0x2000 /* 66mhz PCI slot */ 2815cff7825Smh27603 #define PPMD_INITCHILD_CLKON 0x4000 /* clk turned on in init_child */ 2825cff7825Smh27603 #define PPMD_OFFLINE 0x10000 /* domain is not functional */ 2835cff7825Smh27603 #define PPMD_CPU_READY 0x20000 /* CPU domain can process power call */ 2845cff7825Smh27603 2855cff7825Smh27603 struct ppm_domit { 2865cff7825Smh27603 char *name; 2875cff7825Smh27603 int model; 2885cff7825Smh27603 int dflags; 2895cff7825Smh27603 int status; 2905cff7825Smh27603 }; 2915cff7825Smh27603 extern struct ppm_domit ppm_domit_data[]; 2925cff7825Smh27603 2935cff7825Smh27603 /* 2945cff7825Smh27603 * XXppm driver-specific routines called from common code (s10) 2955cff7825Smh27603 */ 2965cff7825Smh27603 struct ppm_funcs { 2975cff7825Smh27603 void (*dev_init)(ppm_dev_t *); 2985cff7825Smh27603 void (*dev_fini)(ppm_dev_t *); 2995cff7825Smh27603 void (*iocset)(uint8_t); 3005cff7825Smh27603 uint8_t (*iocget)(void); 3015cff7825Smh27603 }; 3025cff7825Smh27603 3035cff7825Smh27603 extern ppm_domain_t *ppm_domain_p; 3045cff7825Smh27603 extern void *ppm_statep; 3055cff7825Smh27603 extern int ppm_inst; 3065cff7825Smh27603 extern ppm_domain_t *ppm_domains[]; /* (s10) */ 3075cff7825Smh27603 extern struct ppm_funcs ppmf; /* (s10) */ 3085cff7825Smh27603 3095cff7825Smh27603 extern void ppm_dev_init(ppm_dev_t *); 3105cff7825Smh27603 extern void ppm_dev_fini(ppm_dev_t *); 3115cff7825Smh27603 extern int ppm_create_db(dev_info_t *); 3125cff7825Smh27603 extern int ppm_claim_dev(dev_info_t *); 3135cff7825Smh27603 extern void ppm_rem_dev(dev_info_t *); 3145cff7825Smh27603 extern ppm_dev_t *ppm_get_dev(dev_info_t *, ppm_domain_t *); 3155cff7825Smh27603 extern void ppm_init_cb(dev_info_t *); 3165cff7825Smh27603 extern int ppm_init_lyr(ppm_dc_t *, dev_info_t *); 3175cff7825Smh27603 extern ppm_domain_t *ppm_lookup_dev(dev_info_t *); 3185cff7825Smh27603 extern ppm_domain_t *ppm_lookup_domain(char *); 3195cff7825Smh27603 extern ppm_dc_t *ppm_lookup_dc(ppm_domain_t *, int); 3205cff7825Smh27603 extern ppm_dc_t *ppm_lookup_hndl(int, ppm_dc_t *); 3215cff7825Smh27603 extern ppm_domain_t *ppm_get_domain_by_dev(const char *); 3225cff7825Smh27603 extern boolean_t ppm_none_else_holds_power(ppm_domain_t *); 3235cff7825Smh27603 extern ppm_owned_t *ppm_add_owned(dev_info_t *, ppm_domain_t *); 3245cff7825Smh27603 extern void ppm_lock_one(ppm_dev_t *, power_req_t *, int *); 3255cff7825Smh27603 extern void ppm_lock_all(ppm_domain_t *, power_req_t *, int *); 3265cff7825Smh27603 extern boolean_t ppm_manage_early_cpus(dev_info_t *, int, int *); 3275cff7825Smh27603 extern int ppm_change_cpu_power(ppm_dev_t *, int); 3285cff7825Smh27603 extern int ppm_revert_cpu_power(ppm_dev_t *, int); 3295cff7825Smh27603 extern ppm_dev_t *ppm_add_dev(dev_info_t *, ppm_domain_t *); 3305cff7825Smh27603 3315cff7825Smh27603 #define PPM_GET_PRIVATE(dip) \ 3325cff7825Smh27603 DEVI(dip)->devi_pm_ppm_private 3335cff7825Smh27603 #define PPM_SET_PRIVATE(dip, datap) \ 3345cff7825Smh27603 DEVI(dip)->devi_pm_ppm_private = datap 3355cff7825Smh27603 3365cff7825Smh27603 #define PPM_LOCK_DOMAIN(domp) { \ 3375cff7825Smh27603 if (!MUTEX_HELD(&(domp)->lock)) \ 3385cff7825Smh27603 mutex_enter(&(domp)->lock); \ 3395cff7825Smh27603 (domp)->refcnt++; \ 3405cff7825Smh27603 } 3415cff7825Smh27603 3425cff7825Smh27603 #define PPM_UNLOCK_DOMAIN(domp) { \ 3435cff7825Smh27603 ASSERT(MUTEX_HELD(&(domp)->lock) && \ 3445cff7825Smh27603 (domp)->refcnt > 0); \ 3455cff7825Smh27603 if (--(domp)->refcnt == 0) \ 3465cff7825Smh27603 mutex_exit(&(domp)->lock); \ 3475cff7825Smh27603 } 3485cff7825Smh27603 3495cff7825Smh27603 /* 3505cff7825Smh27603 * debug support 3515cff7825Smh27603 */ 3525cff7825Smh27603 #ifdef DEBUG 3535cff7825Smh27603 #include <sys/promif.h> 3545cff7825Smh27603 3555cff7825Smh27603 extern char *ppm_get_ctlstr(int, uint_t); 3565cff7825Smh27603 extern void ppm_print_dc(struct ppm_dc *); 3575cff7825Smh27603 3585cff7825Smh27603 extern uint_t ppm_debug; 3595cff7825Smh27603 3605cff7825Smh27603 #define D_CREATEDB 0x00000001 3615cff7825Smh27603 #define D_CLAIMDEV 0x00000002 3625cff7825Smh27603 #define D_ADDDEV 0x00000004 3635cff7825Smh27603 #define D_REMDEV 0x00000008 3645cff7825Smh27603 #define D_LOWEST 0x00000010 3655cff7825Smh27603 #define D_SETLVL 0x00000020 3665cff7825Smh27603 #define D_GPIO 0x00000040 3675cff7825Smh27603 #define D_CPU 0x00000080 3685cff7825Smh27603 #define D_FET 0x00000100 3695cff7825Smh27603 #define D_PCIUPA 0x00000200 3705cff7825Smh27603 #define D_1394 0x00000400 3715cff7825Smh27603 #define D_CTLOPS1 0x00000800 3725cff7825Smh27603 #define D_CTLOPS2 0x00001000 3735cff7825Smh27603 #define D_SOME 0x00002000 3745cff7825Smh27603 #define D_LOCKS 0x00004000 3755cff7825Smh27603 #define D_IOCTL 0x00008000 3765cff7825Smh27603 #define D_ATTACH 0x00010000 3775cff7825Smh27603 #define D_DETACH 0x00020000 3785cff7825Smh27603 #define D_OPEN 0x00040000 3795cff7825Smh27603 #define D_CLOSE 0x00080000 3805cff7825Smh27603 #define D_INIT 0x00100000 3815cff7825Smh27603 #define D_FINI 0x00200000 3825cff7825Smh27603 #define D_ERROR 0x00400000 3835cff7825Smh27603 #define D_SETPWR 0x00800000 3845cff7825Smh27603 #define D_LED 0x01000000 3855cff7825Smh27603 #define D_PCI 0x02000000 3865cff7825Smh27603 #define D_PPMDC 0x04000000 3875cff7825Smh27603 #define D_CPR 0x08000000 3885cff7825Smh27603 3895cff7825Smh27603 #define PPMD(level, arglist) { \ 3905cff7825Smh27603 if (ppm_debug & (level)) { \ 3915cff7825Smh27603 pm_log arglist; \ 3925cff7825Smh27603 } \ 3935cff7825Smh27603 } 3945cff7825Smh27603 /* (s10) */ 3955cff7825Smh27603 #define DPRINTF PPMD 3965cff7825Smh27603 3975cff7825Smh27603 #else /* DEBUG */ 3985cff7825Smh27603 #define PPMD(level, arglist) 3995cff7825Smh27603 #define DPRINTF(flag, args) /* (s10) */ 4005cff7825Smh27603 #endif /* DEBUG */ 4015cff7825Smh27603 4025cff7825Smh27603 #ifdef __cplusplus 4035cff7825Smh27603 } 4045cff7825Smh27603 #endif 4055cff7825Smh27603 4065cff7825Smh27603 #endif /* _SYS_PPMVAR_H */ 407