xref: /illumos-gate/usr/src/uts/common/sys/termiox.h (revision b4203d75)
1*7c478bd9Sstevel@tonic-gate /*
2*7c478bd9Sstevel@tonic-gate  * CDDL HEADER START
3*7c478bd9Sstevel@tonic-gate  *
4*7c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*7c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*7c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*7c478bd9Sstevel@tonic-gate  * with the License.
8*7c478bd9Sstevel@tonic-gate  *
9*7c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*7c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*7c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*7c478bd9Sstevel@tonic-gate  * and limitations under the License.
13*7c478bd9Sstevel@tonic-gate  *
14*7c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*7c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*7c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
17*7c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*7c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
19*7c478bd9Sstevel@tonic-gate  *
20*7c478bd9Sstevel@tonic-gate  * CDDL HEADER END
21*7c478bd9Sstevel@tonic-gate  */
22*7c478bd9Sstevel@tonic-gate /*	Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T	*/
23*7c478bd9Sstevel@tonic-gate /*	  All Rights Reserved	*/
24*7c478bd9Sstevel@tonic-gate 
25*7c478bd9Sstevel@tonic-gate 
26*7c478bd9Sstevel@tonic-gate #ifndef	_SYS_TERMIOX_H
27*7c478bd9Sstevel@tonic-gate #define	_SYS_TERMIOX_H
28*7c478bd9Sstevel@tonic-gate 
29*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
30*7c478bd9Sstevel@tonic-gate extern "C" {
31*7c478bd9Sstevel@tonic-gate #endif
32*7c478bd9Sstevel@tonic-gate 
33*7c478bd9Sstevel@tonic-gate /* This structure provides an extended terminal interface. */
34*7c478bd9Sstevel@tonic-gate /* Features of this interface are optional and may not be */
35*7c478bd9Sstevel@tonic-gate /* implemented on all machines. */
36*7c478bd9Sstevel@tonic-gate 
37*7c478bd9Sstevel@tonic-gate 
38*7c478bd9Sstevel@tonic-gate #define	NFF	5
39*7c478bd9Sstevel@tonic-gate 
40*7c478bd9Sstevel@tonic-gate /* hardware flow control modes */
41*7c478bd9Sstevel@tonic-gate 
42*7c478bd9Sstevel@tonic-gate #define	RTSXOFF	0000001	/* Enable RTS hardware flow control on input */
43*7c478bd9Sstevel@tonic-gate #define	CTSXON	0000002	/* Enable CTS hardware flow control on output */
44*7c478bd9Sstevel@tonic-gate #define	DTRXOFF	0000004	/* Enable DTR hardware flow control on input */
45*7c478bd9Sstevel@tonic-gate #define	CDXON	0000010	/* Enable CD hardware flow control on output */
46*7c478bd9Sstevel@tonic-gate #define	ISXOFF	0000020	/* Enable isochronous hardware flow control on input */
47*7c478bd9Sstevel@tonic-gate 
48*7c478bd9Sstevel@tonic-gate /* clock modes */
49*7c478bd9Sstevel@tonic-gate 
50*7c478bd9Sstevel@tonic-gate #define	XMTCLK		0000007	/* Transmit Clock Source: */
51*7c478bd9Sstevel@tonic-gate #define	XCIBRG		0000000	/* Get transmit clock from */
52*7c478bd9Sstevel@tonic-gate 				/*	internal baud rate generator */
53*7c478bd9Sstevel@tonic-gate #define	XCTSET		0000001	/* Get transmit clock from */
54*7c478bd9Sstevel@tonic-gate 				/*	transmitter signal element */
55*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) lead, */
56*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 114, */
57*7c478bd9Sstevel@tonic-gate 				/*	EIA-232-D pin 15 */
58*7c478bd9Sstevel@tonic-gate #define	XCRSET		0000002	/* Get transmit clock from */
59*7c478bd9Sstevel@tonic-gate 				/*	receiver signal element */
60*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) lead, */
61*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 115, */
62*7c478bd9Sstevel@tonic-gate 				/*	EIA-232-D pin 17 */
63*7c478bd9Sstevel@tonic-gate 
64*7c478bd9Sstevel@tonic-gate #define	RCVCLK		0000070	/* Receive Clock Source: */
65*7c478bd9Sstevel@tonic-gate #define	RCIBRG		0000000	/* get receive clock from internal */
66*7c478bd9Sstevel@tonic-gate 				/*	baud rate generator */
67*7c478bd9Sstevel@tonic-gate #define	RCTSET		0000010	/* Get receive clock from */
68*7c478bd9Sstevel@tonic-gate 				/*	transmitter signal element */
69*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) lead, */
70*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 114, */
71*7c478bd9Sstevel@tonic-gate 				/*	EIA-232-D pin 15 */
72*7c478bd9Sstevel@tonic-gate #define	RCRSET		0000020	/* Get receive clock from */
73*7c478bd9Sstevel@tonic-gate 				/*	receiver signal element */
74*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) lead, */
75*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 115, */
76*7c478bd9Sstevel@tonic-gate 				/*	EIA-232-D pin 17 */
77*7c478bd9Sstevel@tonic-gate 
78*7c478bd9Sstevel@tonic-gate #define	TSETCLK		0000700	/* Transmitter Signal Element */
79*7c478bd9Sstevel@tonic-gate 				/*	timing (DTE source) lead, */
80*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 113, */
81*7c478bd9Sstevel@tonic-gate 				/*	EIA-232-D pin 24, clock source: */
82*7c478bd9Sstevel@tonic-gate #define	TSETCOFF	0000000	/* TSET clock not provided */
83*7c478bd9Sstevel@tonic-gate #define	TSETCRBRG	0000100	/* Output receive baud rate generator */
84*7c478bd9Sstevel@tonic-gate 				/*	on circuit 113 */
85*7c478bd9Sstevel@tonic-gate #define	TSETCTBRG	0000200	/* Output transmit baud rate generator */
86*7c478bd9Sstevel@tonic-gate 				/*	on circuit 113 */
87*7c478bd9Sstevel@tonic-gate #define	TSETCTSET	0000300	/* Output transmitter signal element */
88*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) on circuit 113 */
89*7c478bd9Sstevel@tonic-gate #define	TSETCRSET	0000400	/* Output receiver signal element */
90*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) on circuit 113 */
91*7c478bd9Sstevel@tonic-gate 
92*7c478bd9Sstevel@tonic-gate #define	RSETCLK		0007000	/* Receiver Signal Element */
93*7c478bd9Sstevel@tonic-gate 				/*	timing (DTE source) lead, */
94*7c478bd9Sstevel@tonic-gate 				/*	CCITT V.24 circuit 128, */
95*7c478bd9Sstevel@tonic-gate 				/*	no EIA-232-D pin, clock source: */
96*7c478bd9Sstevel@tonic-gate #define	RSETCOFF	0000000	/* RSET clock not provided */
97*7c478bd9Sstevel@tonic-gate #define	RSETCRBRG	0001000	/* Output receive baud rate generator */
98*7c478bd9Sstevel@tonic-gate 				/*	on circuit 128 */
99*7c478bd9Sstevel@tonic-gate #define	RSETCTBRG	0002000	/* Output transmit baud rate generator */
100*7c478bd9Sstevel@tonic-gate 				/*	on circuit 128 */
101*7c478bd9Sstevel@tonic-gate #define	RSETCTSET	0003000	/* Output transmitter signal element */
102*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) on circuit 128 */
103*7c478bd9Sstevel@tonic-gate #define	RSETCRSET	0004000	/* Output receiver signal element */
104*7c478bd9Sstevel@tonic-gate 				/*	timing (DCE source) on circuit 128 */
105*7c478bd9Sstevel@tonic-gate 
106*7c478bd9Sstevel@tonic-gate 
107*7c478bd9Sstevel@tonic-gate struct termiox {
108*7c478bd9Sstevel@tonic-gate 	unsigned short x_hflag;		/* hardware flow control modes */
109*7c478bd9Sstevel@tonic-gate 	unsigned short x_cflag;		/* clock modes */
110*7c478bd9Sstevel@tonic-gate 	unsigned short x_rflag[NFF];	/* reserved modes */
111*7c478bd9Sstevel@tonic-gate 	unsigned short x_sflag;		/* spare modes */
112*7c478bd9Sstevel@tonic-gate };
113*7c478bd9Sstevel@tonic-gate 
114*7c478bd9Sstevel@tonic-gate #define	XIOC    ('X'<<8)
115*7c478bd9Sstevel@tonic-gate #define	TCGETX  (XIOC|1)
116*7c478bd9Sstevel@tonic-gate #define	TCSETX  (XIOC|2)
117*7c478bd9Sstevel@tonic-gate #define	TCSETXW (XIOC|3)
118*7c478bd9Sstevel@tonic-gate #define	TCSETXF (XIOC|4)
119*7c478bd9Sstevel@tonic-gate 
120*7c478bd9Sstevel@tonic-gate #ifdef	__cplusplus
121*7c478bd9Sstevel@tonic-gate }
122*7c478bd9Sstevel@tonic-gate #endif
123*7c478bd9Sstevel@tonic-gate 
124*7c478bd9Sstevel@tonic-gate #endif	/* _SYS_TERMIOX_H */
125