17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 237c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate #include <sys/types.h> 307c478bd9Sstevel@tonic-gate #include <sys/mkdev.h> 317851eb82Sschwartz #include <sys/stat.h> 327c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 337c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 347c478bd9Sstevel@tonic-gate #include <sys/machparam.h> 357a364d25Sschwartz #include <sys/sunndi.h> 367c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 377a364d25Sschwartz #include <sys/psm.h> 3870025d76Sjohnny #include <sys/pcie.h> 397c478bd9Sstevel@tonic-gate #include <sys/hotplug/pci/pcihp.h> 407c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 417c478bd9Sstevel@tonic-gate #include <sys/pci_tools.h> 42*649d4cceSanish #include <io/pci/pci_tools_ext.h> 437a364d25Sschwartz #include <io/pcplusmp/apic.h> 447a364d25Sschwartz #include <io/pci/pci_var.h> 457c478bd9Sstevel@tonic-gate #include <sys/promif.h> 46*649d4cceSanish #include <sys/x86_archext.h> 477c478bd9Sstevel@tonic-gate 48d4476ccbSschwartz #define PCIEX_BDF_OFFSET_DELTA 4 49d4476ccbSschwartz #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA) 50d4476ccbSschwartz #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA) 51d4476ccbSschwartz #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA) 52d4476ccbSschwartz 537c478bd9Sstevel@tonic-gate #define SUCCESS 0 547c478bd9Sstevel@tonic-gate 557c478bd9Sstevel@tonic-gate int pcitool_debug = 0; 567c478bd9Sstevel@tonic-gate 577c478bd9Sstevel@tonic-gate /* 587c478bd9Sstevel@tonic-gate * Offsets of BARS in config space. First entry of 0 means config space. 597c478bd9Sstevel@tonic-gate * Entries here correlate to pcitool_bars_t enumerated type. 607c478bd9Sstevel@tonic-gate */ 617c478bd9Sstevel@tonic-gate static uint8_t pci_bars[] = { 627c478bd9Sstevel@tonic-gate 0x0, 637c478bd9Sstevel@tonic-gate PCI_CONF_BASE0, 647c478bd9Sstevel@tonic-gate PCI_CONF_BASE1, 657c478bd9Sstevel@tonic-gate PCI_CONF_BASE2, 667c478bd9Sstevel@tonic-gate PCI_CONF_BASE3, 677c478bd9Sstevel@tonic-gate PCI_CONF_BASE4, 687c478bd9Sstevel@tonic-gate PCI_CONF_BASE5, 697c478bd9Sstevel@tonic-gate PCI_CONF_ROM 707c478bd9Sstevel@tonic-gate }; 717c478bd9Sstevel@tonic-gate 72d4476ccbSschwartz /* Max offset allowed into config space for a particular device. */ 73d4476ccbSschwartz static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE; 74d4476ccbSschwartz 757c478bd9Sstevel@tonic-gate static uint64_t pcitool_swap_endian(uint64_t data, int size); 76d4476ccbSschwartz static int pcitool_pciex_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 77d4476ccbSschwartz boolean_t write_flag); 787c478bd9Sstevel@tonic-gate static int pcitool_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 797c478bd9Sstevel@tonic-gate boolean_t write_flag); 807c478bd9Sstevel@tonic-gate static int pcitool_io_access(dev_info_t *dip, pcitool_reg_t *prg, 817c478bd9Sstevel@tonic-gate boolean_t write_flag); 827c478bd9Sstevel@tonic-gate static int pcitool_mem_access(dev_info_t *dip, pcitool_reg_t *prg, 837c478bd9Sstevel@tonic-gate uint64_t virt_addr, boolean_t write_flag); 847c478bd9Sstevel@tonic-gate static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages); 857c478bd9Sstevel@tonic-gate static void pcitool_unmap(uint64_t virt_addr, size_t num_pages); 867c478bd9Sstevel@tonic-gate 877a364d25Sschwartz /* Extern decalrations */ 887a364d25Sschwartz extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 897a364d25Sschwartz psm_intr_op_t, int *); 907a364d25Sschwartz 917851eb82Sschwartz int 92d4476ccbSschwartz pcitool_init(dev_info_t *dip, boolean_t is_pciex) 937851eb82Sschwartz { 947851eb82Sschwartz int instance = ddi_get_instance(dip); 957851eb82Sschwartz 967851eb82Sschwartz /* Create pcitool nodes for register access and interrupt routing. */ 977851eb82Sschwartz 987851eb82Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR, 997851eb82Sschwartz PCIHP_AP_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM), 1007851eb82Sschwartz DDI_NT_REGACC, 0) != DDI_SUCCESS) { 1017851eb82Sschwartz return (DDI_FAILURE); 1027851eb82Sschwartz } 1037851eb82Sschwartz 1047851eb82Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR, 1057851eb82Sschwartz PCIHP_AP_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM), 1067851eb82Sschwartz DDI_NT_INTRCTL, 0) != DDI_SUCCESS) { 1077851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 1087851eb82Sschwartz return (DDI_FAILURE); 1097851eb82Sschwartz } 1107851eb82Sschwartz 111d4476ccbSschwartz if (is_pciex) 112d4476ccbSschwartz max_cfg_size = PCIE_CONF_HDR_SIZE; 113d4476ccbSschwartz 1147851eb82Sschwartz return (DDI_SUCCESS); 1157851eb82Sschwartz } 1167851eb82Sschwartz 1177851eb82Sschwartz void 1187851eb82Sschwartz pcitool_uninit(dev_info_t *dip) 1197851eb82Sschwartz { 1207851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_INTR); 1217851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 1227851eb82Sschwartz } 1237851eb82Sschwartz 1247851eb82Sschwartz 1257a364d25Sschwartz /* Return the number of interrupts on a pci bus. */ 1267a364d25Sschwartz static int 1277a364d25Sschwartz pcitool_intr_get_max_ino(uint32_t *arg, int mode) 1287a364d25Sschwartz { 1297a364d25Sschwartz uint32_t num_intr = APIC_MAX_VECTOR; 1307a364d25Sschwartz 1317a364d25Sschwartz if (ddi_copyout(&num_intr, arg, sizeof (uint32_t), mode) != 1327a364d25Sschwartz DDI_SUCCESS) 1337a364d25Sschwartz return (EFAULT); 1347a364d25Sschwartz else 1357a364d25Sschwartz return (SUCCESS); 1367a364d25Sschwartz } 1377a364d25Sschwartz 1387a364d25Sschwartz 1397a364d25Sschwartz /*ARGSUSED*/ 1407a364d25Sschwartz static int 1417a364d25Sschwartz pcitool_set_intr(dev_info_t *dip, void *arg, int mode) 1427a364d25Sschwartz { 1437a364d25Sschwartz ddi_intr_handle_impl_t info_hdl; 1447a364d25Sschwartz pcitool_intr_set_t iset; 1457a364d25Sschwartz uint32_t old_cpu; 1467a364d25Sschwartz int ret, result; 1477a364d25Sschwartz int rval = SUCCESS; 1487a364d25Sschwartz 1497a364d25Sschwartz if (ddi_copyin(arg, &iset, sizeof (pcitool_intr_set_t), mode) != 1507a364d25Sschwartz DDI_SUCCESS) 1517a364d25Sschwartz return (EFAULT); 1527a364d25Sschwartz 1537a364d25Sschwartz if (iset.ino > APIC_MAX_VECTOR) { 1547a364d25Sschwartz rval = EINVAL; 1557a364d25Sschwartz iset.status = PCITOOL_INVALID_INO; 1567a364d25Sschwartz goto done_set_intr; 1577a364d25Sschwartz } 1587a364d25Sschwartz 1597a364d25Sschwartz iset.status = PCITOOL_SUCCESS; 1607a364d25Sschwartz 1617a364d25Sschwartz if ((old_cpu = pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) { 1627a364d25Sschwartz iset.status = PCITOOL_IO_ERROR; 1637a364d25Sschwartz rval = EINVAL; 1647a364d25Sschwartz goto done_set_intr; 1657a364d25Sschwartz } 1667a364d25Sschwartz 1677a364d25Sschwartz old_cpu &= ~PSMGI_CPU_USER_BOUND; 1687a364d25Sschwartz 1697a364d25Sschwartz /* 1707a364d25Sschwartz * For this locally-declared and used handle, ih_private will contain a 1717a364d25Sschwartz * CPU value, not an ihdl_plat_t as used for global interrupt handling. 1727a364d25Sschwartz */ 1737a364d25Sschwartz info_hdl.ih_vector = iset.ino; 1747a364d25Sschwartz info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id; 1757a364d25Sschwartz ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU, &result); 1767a364d25Sschwartz 1777a364d25Sschwartz iset.drvr_version = PCITOOL_DRVR_VERSION; 1787a364d25Sschwartz if (ret != PSM_SUCCESS) { 1797a364d25Sschwartz switch (result) { 1807a364d25Sschwartz case EIO: /* Error making the change */ 1817a364d25Sschwartz rval = EIO; 1827a364d25Sschwartz iset.status = PCITOOL_IO_ERROR; 1837a364d25Sschwartz break; 1847a364d25Sschwartz case ENXIO: /* Couldn't convert vector to irq */ 1857a364d25Sschwartz rval = EINVAL; 1867a364d25Sschwartz iset.status = PCITOOL_INVALID_INO; 1877a364d25Sschwartz break; 1887a364d25Sschwartz case EINVAL: /* CPU out of range */ 1897a364d25Sschwartz rval = EINVAL; 1907a364d25Sschwartz iset.status = PCITOOL_INVALID_CPUID; 1917a364d25Sschwartz break; 1927a364d25Sschwartz } 1937a364d25Sschwartz } 1947a364d25Sschwartz 1957a364d25Sschwartz /* Return original CPU. */ 1967a364d25Sschwartz iset.cpu_id = old_cpu; 1977a364d25Sschwartz 1987a364d25Sschwartz done_set_intr: 1997a364d25Sschwartz if (ddi_copyout(&iset, arg, sizeof (pcitool_intr_set_t), mode) != 2007a364d25Sschwartz DDI_SUCCESS) 2017a364d25Sschwartz rval = EFAULT; 2027a364d25Sschwartz return (rval); 2037a364d25Sschwartz } 2047a364d25Sschwartz 2057a364d25Sschwartz 2067a364d25Sschwartz /* It is assumed that dip != NULL */ 2077a364d25Sschwartz static void 2087a364d25Sschwartz pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs) 2097a364d25Sschwartz { 2107a364d25Sschwartz (void) strncpy(devs->driver_name, 2117a364d25Sschwartz ddi_driver_name(dip), MAXMODCONFNAME-1); 2127a364d25Sschwartz devs->driver_name[MAXMODCONFNAME] = '\0'; 2137a364d25Sschwartz (void) ddi_pathname(dip, devs->path); 2147a364d25Sschwartz devs->dev_inst = ddi_get_instance(dip); 2157a364d25Sschwartz } 2167a364d25Sschwartz 2177a364d25Sschwartz 2187a364d25Sschwartz /*ARGSUSED*/ 2197a364d25Sschwartz static int 2207a364d25Sschwartz pcitool_get_intr(dev_info_t *dip, void *arg, int mode) 2217a364d25Sschwartz { 2227a364d25Sschwartz /* Array part isn't used here, but oh well... */ 2237a364d25Sschwartz pcitool_intr_get_t partial_iget; 2247a364d25Sschwartz pcitool_intr_get_t *iget = &partial_iget; 2257a364d25Sschwartz size_t iget_kmem_alloc_size = 0; 2267a364d25Sschwartz uint8_t num_devs_ret; 2277a364d25Sschwartz int copyout_rval; 2287a364d25Sschwartz int rval = SUCCESS; 2297a364d25Sschwartz int circ; 2307a364d25Sschwartz int i; 2317a364d25Sschwartz 2327a364d25Sschwartz ddi_intr_handle_impl_t info_hdl; 2337a364d25Sschwartz apic_get_intr_t intr_info; 2347a364d25Sschwartz 2357a364d25Sschwartz /* Read in just the header part, no array section. */ 2367a364d25Sschwartz if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) != 2377a364d25Sschwartz DDI_SUCCESS) 2387a364d25Sschwartz return (EFAULT); 2397a364d25Sschwartz 2407a364d25Sschwartz /* Validate argument. */ 2417a364d25Sschwartz if (partial_iget.ino > APIC_MAX_VECTOR) { 2427a364d25Sschwartz partial_iget.status = PCITOOL_INVALID_INO; 2437a364d25Sschwartz partial_iget.num_devs_ret = 0; 2447a364d25Sschwartz rval = EINVAL; 2457a364d25Sschwartz goto done_get_intr; 2467a364d25Sschwartz } 2477a364d25Sschwartz 2487a364d25Sschwartz num_devs_ret = partial_iget.num_devs_ret; 2497a364d25Sschwartz intr_info.avgi_dip_list = NULL; 2507a364d25Sschwartz intr_info.avgi_req_flags = 2517a364d25Sschwartz PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC; 2527a364d25Sschwartz /* 2537a364d25Sschwartz * For this locally-declared and used handle, ih_private will contain a 2547a364d25Sschwartz * pointer to apic_get_intr_t, not an ihdl_plat_t as used for 2557a364d25Sschwartz * global interrupt handling. 2567a364d25Sschwartz */ 2577a364d25Sschwartz info_hdl.ih_private = &intr_info; 2587a364d25Sschwartz info_hdl.ih_vector = partial_iget.ino; 2597a364d25Sschwartz 2607a364d25Sschwartz /* Caller wants device information returned. */ 2617a364d25Sschwartz if (num_devs_ret > 0) { 2627a364d25Sschwartz 2637a364d25Sschwartz intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS; 2647a364d25Sschwartz 2657a364d25Sschwartz /* 2667a364d25Sschwartz * Allocate room. 2677a364d25Sschwartz * If num_devs_ret == 0 iget remains pointing to partial_iget. 2687a364d25Sschwartz */ 2697a364d25Sschwartz iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret); 2707a364d25Sschwartz iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP); 2717a364d25Sschwartz 2727a364d25Sschwartz /* Read in whole structure to verify there's room. */ 2737a364d25Sschwartz if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) != 2747a364d25Sschwartz SUCCESS) { 2757a364d25Sschwartz 2767a364d25Sschwartz /* Be consistent and just return EFAULT here. */ 2777a364d25Sschwartz kmem_free(iget, iget_kmem_alloc_size); 2787a364d25Sschwartz 2797a364d25Sschwartz return (EFAULT); 2807a364d25Sschwartz } 2817a364d25Sschwartz } 2827a364d25Sschwartz 2837a364d25Sschwartz bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret)); 2847a364d25Sschwartz iget->ino = info_hdl.ih_vector; 2857a364d25Sschwartz 2867a364d25Sschwartz /* 2877a364d25Sschwartz * Lock device tree branch from the pci root nexus on down if info will 2887a364d25Sschwartz * be extracted from dips returned from the tree. 2897a364d25Sschwartz */ 2907a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 2917a364d25Sschwartz ndi_devi_enter(dip, &circ); 2927a364d25Sschwartz } 2937a364d25Sschwartz 2947a364d25Sschwartz /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */ 2957a364d25Sschwartz if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 2967a364d25Sschwartz PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) { 2977a364d25Sschwartz iget->status = PCITOOL_IO_ERROR; 2987a364d25Sschwartz iget->num_devs_ret = 0; 2997a364d25Sschwartz rval = EINVAL; 3007a364d25Sschwartz goto done_get_intr; 3017a364d25Sschwartz } 3027a364d25Sschwartz 3037a364d25Sschwartz /* 3047a364d25Sschwartz * Fill in the pcitool_intr_get_t to be returned, 3057a364d25Sschwartz * with the CPU, num_devs_ret and num_devs. 3067a364d25Sschwartz */ 3077a364d25Sschwartz iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND; 3087a364d25Sschwartz 3097a364d25Sschwartz /* Number of devices returned by apic. */ 3107a364d25Sschwartz iget->num_devs = intr_info.avgi_num_devs; 3117a364d25Sschwartz 3127a364d25Sschwartz /* Device info was returned. */ 3137a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 3147a364d25Sschwartz 3157a364d25Sschwartz /* 3167a364d25Sschwartz * num devs returned is num devs ret by apic, 3177a364d25Sschwartz * space permitting. 3187a364d25Sschwartz */ 3197a364d25Sschwartz iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs); 3207a364d25Sschwartz 3217a364d25Sschwartz /* 3227a364d25Sschwartz * Loop thru list of dips and extract driver, name and instance. 3237a364d25Sschwartz * Fill in the pcitool_intr_dev_t's with this info. 3247a364d25Sschwartz */ 3257a364d25Sschwartz for (i = 0; i < iget->num_devs_ret; i++) 3267a364d25Sschwartz pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i], 3277a364d25Sschwartz &iget->dev[i]); 3287a364d25Sschwartz 3297a364d25Sschwartz /* Free kmem_alloc'ed memory of the apic_get_intr_t */ 3307a364d25Sschwartz kmem_free(intr_info.avgi_dip_list, 3317a364d25Sschwartz intr_info.avgi_num_devs * sizeof (dev_info_t *)); 3327a364d25Sschwartz } 3337a364d25Sschwartz 3347a364d25Sschwartz done_get_intr: 3357a364d25Sschwartz 3367a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 3377a364d25Sschwartz ndi_devi_exit(dip, circ); 3387a364d25Sschwartz } 3397a364d25Sschwartz 3407a364d25Sschwartz iget->drvr_version = PCITOOL_DRVR_VERSION; 3417a364d25Sschwartz copyout_rval = ddi_copyout(iget, arg, 3427a364d25Sschwartz PCITOOL_IGET_SIZE(num_devs_ret), mode); 3437a364d25Sschwartz 3447a364d25Sschwartz if (iget_kmem_alloc_size > 0) 3457a364d25Sschwartz kmem_free(iget, iget_kmem_alloc_size); 3467a364d25Sschwartz 3477a364d25Sschwartz if (copyout_rval != DDI_SUCCESS) 3487a364d25Sschwartz rval = EFAULT; 3497a364d25Sschwartz 3507a364d25Sschwartz return (rval); 3517a364d25Sschwartz } 3527a364d25Sschwartz 3537a364d25Sschwartz 3547a364d25Sschwartz /* 3557a364d25Sschwartz * Main function for handling interrupt CPU binding requests and queries. 3567a364d25Sschwartz * Need to implement later 3577a364d25Sschwartz */ 3587a364d25Sschwartz /*ARGSUSED*/ 3597a364d25Sschwartz int 3607a364d25Sschwartz pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 3617a364d25Sschwartz { 3627a364d25Sschwartz int rval; 3637a364d25Sschwartz 3647a364d25Sschwartz switch (cmd) { 3657a364d25Sschwartz 3667a364d25Sschwartz /* Associate a new CPU with a given vector */ 3677a364d25Sschwartz case PCITOOL_DEVICE_SET_INTR: 3687a364d25Sschwartz rval = pcitool_set_intr(dip, arg, mode); 3697a364d25Sschwartz break; 3707a364d25Sschwartz 3717a364d25Sschwartz case PCITOOL_DEVICE_GET_INTR: 3727a364d25Sschwartz rval = pcitool_get_intr(dip, arg, mode); 3737a364d25Sschwartz break; 3747a364d25Sschwartz 3757a364d25Sschwartz case PCITOOL_DEVICE_NUM_INTR: 3767a364d25Sschwartz rval = pcitool_intr_get_max_ino(arg, mode); 3777a364d25Sschwartz break; 3787a364d25Sschwartz 3797a364d25Sschwartz default: 3807a364d25Sschwartz rval = ENOTSUP; 3817a364d25Sschwartz } 3827a364d25Sschwartz 3837a364d25Sschwartz return (rval); 3847a364d25Sschwartz } 3857a364d25Sschwartz 3867a364d25Sschwartz 3877c478bd9Sstevel@tonic-gate /* 3887c478bd9Sstevel@tonic-gate * A note about ontrap handling: 3897c478bd9Sstevel@tonic-gate * 3907c478bd9Sstevel@tonic-gate * X86 systems on which this module was tested return FFs instead of bus errors 3917c478bd9Sstevel@tonic-gate * when accessing devices with invalid addresses. Ontrap handling, which 3927c478bd9Sstevel@tonic-gate * gracefully handles kernel bus errors, is installed anyway, in case future 3937c478bd9Sstevel@tonic-gate * X86 platforms require it. 3947c478bd9Sstevel@tonic-gate */ 3957c478bd9Sstevel@tonic-gate 3967c478bd9Sstevel@tonic-gate /* 3977c478bd9Sstevel@tonic-gate * Perform register accesses on the nexus device itself. 3987c478bd9Sstevel@tonic-gate * No explicit PCI nexus device for X86, so not applicable. 3997c478bd9Sstevel@tonic-gate */ 4007a364d25Sschwartz 4017c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4027c478bd9Sstevel@tonic-gate int 403d4476ccbSschwartz pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 4047c478bd9Sstevel@tonic-gate { 4057c478bd9Sstevel@tonic-gate return (ENOTSUP); 4067c478bd9Sstevel@tonic-gate } 4077c478bd9Sstevel@tonic-gate 4087c478bd9Sstevel@tonic-gate /* Swap endianness. */ 4097c478bd9Sstevel@tonic-gate static uint64_t 4107c478bd9Sstevel@tonic-gate pcitool_swap_endian(uint64_t data, int size) 4117c478bd9Sstevel@tonic-gate { 4127c478bd9Sstevel@tonic-gate typedef union { 4137c478bd9Sstevel@tonic-gate uint64_t data64; 4147c478bd9Sstevel@tonic-gate uint8_t data8[8]; 4157c478bd9Sstevel@tonic-gate } data_split_t; 4167c478bd9Sstevel@tonic-gate 4177c478bd9Sstevel@tonic-gate data_split_t orig_data; 4187c478bd9Sstevel@tonic-gate data_split_t returned_data; 4197c478bd9Sstevel@tonic-gate int i; 4207c478bd9Sstevel@tonic-gate 4217c478bd9Sstevel@tonic-gate orig_data.data64 = data; 4227c478bd9Sstevel@tonic-gate returned_data.data64 = 0; 4237c478bd9Sstevel@tonic-gate 4247c478bd9Sstevel@tonic-gate for (i = 0; i < size; i++) { 4257c478bd9Sstevel@tonic-gate returned_data.data8[i] = orig_data.data8[size - 1 - i]; 4267c478bd9Sstevel@tonic-gate } 4277c478bd9Sstevel@tonic-gate 4287c478bd9Sstevel@tonic-gate return (returned_data.data64); 4297c478bd9Sstevel@tonic-gate } 4307c478bd9Sstevel@tonic-gate 4317c478bd9Sstevel@tonic-gate 432d4476ccbSschwartz /* 433d4476ccbSschwartz * Access device. prg is modified. 434d4476ccbSschwartz * 435d4476ccbSschwartz * Extended config space is available only through memory-mapped access. 436d4476ccbSschwartz * Standard config space on pci express devices is available either way, 437d4476ccbSschwartz * so do it memory-mapped here too, for simplicity. 438d4476ccbSschwartz */ 439d4476ccbSschwartz /*ARGSUSED*/ 440d4476ccbSschwartz static int 441d4476ccbSschwartz pcitool_pciex_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 442d4476ccbSschwartz boolean_t write_flag) 443d4476ccbSschwartz { 444d4476ccbSschwartz int rval = SUCCESS; 445d4476ccbSschwartz uint64_t virt_addr; 446d4476ccbSschwartz size_t num_virt_pages; 447d4476ccbSschwartz 448d4476ccbSschwartz prg->status = PCITOOL_SUCCESS; 449d4476ccbSschwartz 450d4476ccbSschwartz prg->phys_addr = ddi_prop_get_int64(DDI_DEV_T_ANY, dip, 0, 45170025d76Sjohnny "ecfga-base-address", 0); 452d4476ccbSschwartz if (prg->phys_addr == 0) { 453d4476ccbSschwartz prg->status = PCITOOL_IO_ERROR; 454d4476ccbSschwartz return (EIO); 455d4476ccbSschwartz } 456d4476ccbSschwartz 457d4476ccbSschwartz prg->phys_addr += prg->offset + 458d4476ccbSschwartz ((prg->bus_no << PCIEX_REG_BUS_SHIFT) | 459d4476ccbSschwartz (prg->dev_no << PCIEX_REG_DEV_SHIFT) | 460d4476ccbSschwartz (prg->func_no << PCIEX_REG_FUNC_SHIFT)); 461d4476ccbSschwartz 462d4476ccbSschwartz virt_addr = pcitool_map(prg->phys_addr, 463d4476ccbSschwartz PCITOOL_ACC_ATTR_SIZE(prg->acc_attr), &num_virt_pages); 464d4476ccbSschwartz if (virt_addr == NULL) { 465d4476ccbSschwartz prg->status = PCITOOL_IO_ERROR; 466d4476ccbSschwartz return (EIO); 467d4476ccbSschwartz } 468d4476ccbSschwartz 469d4476ccbSschwartz rval = pcitool_mem_access(dip, prg, virt_addr, write_flag); 470d4476ccbSschwartz pcitool_unmap(virt_addr, num_virt_pages); 471d4476ccbSschwartz return (rval); 472d4476ccbSschwartz } 473d4476ccbSschwartz 4747c478bd9Sstevel@tonic-gate /* Access device. prg is modified. */ 4757c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4767c478bd9Sstevel@tonic-gate static int 4777c478bd9Sstevel@tonic-gate pcitool_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, boolean_t write_flag) 4787c478bd9Sstevel@tonic-gate { 4797c478bd9Sstevel@tonic-gate int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 4807c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 4817c478bd9Sstevel@tonic-gate int rval = SUCCESS; 4827c478bd9Sstevel@tonic-gate uint64_t local_data; 4837c478bd9Sstevel@tonic-gate 4847c478bd9Sstevel@tonic-gate /* 4857c478bd9Sstevel@tonic-gate * NOTE: there is no way to verify whether or not the address is valid. 4867c478bd9Sstevel@tonic-gate * The put functions return void and the get functions return ff on 4877c478bd9Sstevel@tonic-gate * error. 4887c478bd9Sstevel@tonic-gate */ 4897c478bd9Sstevel@tonic-gate prg->status = PCITOOL_SUCCESS; 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate if (write_flag) { 4927c478bd9Sstevel@tonic-gate 4937c478bd9Sstevel@tonic-gate if (big_endian) { 4947c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 4957c478bd9Sstevel@tonic-gate } else { 4967c478bd9Sstevel@tonic-gate local_data = prg->data; 4977c478bd9Sstevel@tonic-gate } 4987c478bd9Sstevel@tonic-gate 4997c478bd9Sstevel@tonic-gate switch (size) { 5007c478bd9Sstevel@tonic-gate case 1: 5017c478bd9Sstevel@tonic-gate (*pci_putb_func)(prg->bus_no, prg->dev_no, 5027c478bd9Sstevel@tonic-gate prg->func_no, prg->offset, local_data); 5037c478bd9Sstevel@tonic-gate break; 5047c478bd9Sstevel@tonic-gate case 2: 5057c478bd9Sstevel@tonic-gate (*pci_putw_func)(prg->bus_no, prg->dev_no, 5067c478bd9Sstevel@tonic-gate prg->func_no, prg->offset, local_data); 5077c478bd9Sstevel@tonic-gate break; 5087c478bd9Sstevel@tonic-gate case 4: 5097c478bd9Sstevel@tonic-gate (*pci_putl_func)(prg->bus_no, prg->dev_no, 5107c478bd9Sstevel@tonic-gate prg->func_no, prg->offset, local_data); 5117c478bd9Sstevel@tonic-gate break; 5127c478bd9Sstevel@tonic-gate default: 5137c478bd9Sstevel@tonic-gate rval = ENOTSUP; 5147c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 5157c478bd9Sstevel@tonic-gate break; 5167c478bd9Sstevel@tonic-gate } 5177c478bd9Sstevel@tonic-gate } else { 5187c478bd9Sstevel@tonic-gate switch (size) { 5197c478bd9Sstevel@tonic-gate case 1: 5207c478bd9Sstevel@tonic-gate local_data = (*pci_getb_func)(prg->bus_no, prg->dev_no, 5217c478bd9Sstevel@tonic-gate prg->func_no, prg->offset); 5227c478bd9Sstevel@tonic-gate break; 5237c478bd9Sstevel@tonic-gate case 2: 5247c478bd9Sstevel@tonic-gate local_data = (*pci_getw_func)(prg->bus_no, prg->dev_no, 5257c478bd9Sstevel@tonic-gate prg->func_no, prg->offset); 5267c478bd9Sstevel@tonic-gate break; 5277c478bd9Sstevel@tonic-gate case 4: 5287c478bd9Sstevel@tonic-gate local_data = (*pci_getl_func)(prg->bus_no, prg->dev_no, 5297c478bd9Sstevel@tonic-gate prg->func_no, prg->offset); 5307c478bd9Sstevel@tonic-gate break; 5317c478bd9Sstevel@tonic-gate default: 5327c478bd9Sstevel@tonic-gate rval = ENOTSUP; 5337c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 5347c478bd9Sstevel@tonic-gate break; 5357c478bd9Sstevel@tonic-gate } 5367c478bd9Sstevel@tonic-gate 5377c478bd9Sstevel@tonic-gate if (rval == SUCCESS) { 5387c478bd9Sstevel@tonic-gate if (big_endian) { 5397c478bd9Sstevel@tonic-gate prg->data = 5407c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 5417c478bd9Sstevel@tonic-gate } else { 5427c478bd9Sstevel@tonic-gate prg->data = local_data; 5437c478bd9Sstevel@tonic-gate } 5447c478bd9Sstevel@tonic-gate } 5457c478bd9Sstevel@tonic-gate } 5467c478bd9Sstevel@tonic-gate prg->phys_addr = 0; /* Config space is not memory mapped on X86. */ 5477c478bd9Sstevel@tonic-gate return (rval); 5487c478bd9Sstevel@tonic-gate } 5497c478bd9Sstevel@tonic-gate 5507c478bd9Sstevel@tonic-gate 5517c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5527c478bd9Sstevel@tonic-gate static int 5537c478bd9Sstevel@tonic-gate pcitool_io_access(dev_info_t *dip, pcitool_reg_t *prg, boolean_t write_flag) 5547c478bd9Sstevel@tonic-gate { 5557c478bd9Sstevel@tonic-gate int port = (int)prg->phys_addr; 5567c478bd9Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 5577c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 5587c478bd9Sstevel@tonic-gate int rval = SUCCESS; 5597c478bd9Sstevel@tonic-gate on_trap_data_t otd; 5607c478bd9Sstevel@tonic-gate uint64_t local_data; 5617c478bd9Sstevel@tonic-gate 5627c478bd9Sstevel@tonic-gate 5637c478bd9Sstevel@tonic-gate /* 5647c478bd9Sstevel@tonic-gate * on_trap works like setjmp. 5657c478bd9Sstevel@tonic-gate * 5667c478bd9Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 5677c478bd9Sstevel@tonic-gate * 5687c478bd9Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 5697c478bd9Sstevel@tonic-gate */ 5707c478bd9Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 5717c478bd9Sstevel@tonic-gate no_trap(); 5727c478bd9Sstevel@tonic-gate if (pcitool_debug) 5737c478bd9Sstevel@tonic-gate prom_printf( 5747c478bd9Sstevel@tonic-gate "pcitool_mem_access: on_trap caught an error...\n"); 5757c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 5767c478bd9Sstevel@tonic-gate return (EFAULT); 5777c478bd9Sstevel@tonic-gate } 5787c478bd9Sstevel@tonic-gate 5797c478bd9Sstevel@tonic-gate if (write_flag) { 5807c478bd9Sstevel@tonic-gate 5817c478bd9Sstevel@tonic-gate if (big_endian) { 5827c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 5837c478bd9Sstevel@tonic-gate } else { 5847c478bd9Sstevel@tonic-gate local_data = prg->data; 5857c478bd9Sstevel@tonic-gate } 5867c478bd9Sstevel@tonic-gate 5877c478bd9Sstevel@tonic-gate if (pcitool_debug) 5887c478bd9Sstevel@tonic-gate prom_printf("Writing %ld byte(s) to port 0x%x\n", 5897c478bd9Sstevel@tonic-gate size, port); 5907c478bd9Sstevel@tonic-gate 5917c478bd9Sstevel@tonic-gate switch (size) { 5927c478bd9Sstevel@tonic-gate case 1: 5937c478bd9Sstevel@tonic-gate outb(port, (uint8_t)local_data); 5947c478bd9Sstevel@tonic-gate break; 5957c478bd9Sstevel@tonic-gate case 2: 5967c478bd9Sstevel@tonic-gate outw(port, (uint16_t)local_data); 5977c478bd9Sstevel@tonic-gate break; 5987c478bd9Sstevel@tonic-gate case 4: 5997c478bd9Sstevel@tonic-gate outl(port, (uint32_t)local_data); 6007c478bd9Sstevel@tonic-gate break; 6017c478bd9Sstevel@tonic-gate default: 6027c478bd9Sstevel@tonic-gate rval = ENOTSUP; 6037c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 6047c478bd9Sstevel@tonic-gate break; 6057c478bd9Sstevel@tonic-gate } 6067c478bd9Sstevel@tonic-gate } else { 6077c478bd9Sstevel@tonic-gate if (pcitool_debug) 6087c478bd9Sstevel@tonic-gate prom_printf("Reading %ld byte(s) from port 0x%x\n", 6097c478bd9Sstevel@tonic-gate size, port); 6107c478bd9Sstevel@tonic-gate 6117c478bd9Sstevel@tonic-gate switch (size) { 6127c478bd9Sstevel@tonic-gate case 1: 6137c478bd9Sstevel@tonic-gate local_data = inb(port); 6147c478bd9Sstevel@tonic-gate break; 6157c478bd9Sstevel@tonic-gate case 2: 6167c478bd9Sstevel@tonic-gate local_data = inw(port); 6177c478bd9Sstevel@tonic-gate break; 6187c478bd9Sstevel@tonic-gate case 4: 6197c478bd9Sstevel@tonic-gate local_data = inl(port); 6207c478bd9Sstevel@tonic-gate break; 6217c478bd9Sstevel@tonic-gate default: 6227c478bd9Sstevel@tonic-gate rval = ENOTSUP; 6237c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 6247c478bd9Sstevel@tonic-gate break; 6257c478bd9Sstevel@tonic-gate } 6267c478bd9Sstevel@tonic-gate 6277c478bd9Sstevel@tonic-gate if (rval == SUCCESS) { 6287c478bd9Sstevel@tonic-gate if (big_endian) { 6297c478bd9Sstevel@tonic-gate prg->data = 6307c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 6317c478bd9Sstevel@tonic-gate } else { 6327c478bd9Sstevel@tonic-gate prg->data = local_data; 6337c478bd9Sstevel@tonic-gate } 6347c478bd9Sstevel@tonic-gate } 6357c478bd9Sstevel@tonic-gate } 6367c478bd9Sstevel@tonic-gate 6377c478bd9Sstevel@tonic-gate no_trap(); 6387c478bd9Sstevel@tonic-gate return (rval); 6397c478bd9Sstevel@tonic-gate } 6407c478bd9Sstevel@tonic-gate 6417c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 6427c478bd9Sstevel@tonic-gate static int 6437c478bd9Sstevel@tonic-gate pcitool_mem_access(dev_info_t *dip, pcitool_reg_t *prg, uint64_t virt_addr, 6447c478bd9Sstevel@tonic-gate boolean_t write_flag) 6457c478bd9Sstevel@tonic-gate { 6467c478bd9Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 6477c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 6487c478bd9Sstevel@tonic-gate int rval = DDI_SUCCESS; 6497c478bd9Sstevel@tonic-gate on_trap_data_t otd; 6507c478bd9Sstevel@tonic-gate uint64_t local_data; 6517c478bd9Sstevel@tonic-gate 6527c478bd9Sstevel@tonic-gate /* 6537c478bd9Sstevel@tonic-gate * on_trap works like setjmp. 6547c478bd9Sstevel@tonic-gate * 6557c478bd9Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 6567c478bd9Sstevel@tonic-gate * 6577c478bd9Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 6587c478bd9Sstevel@tonic-gate */ 6597c478bd9Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 6607c478bd9Sstevel@tonic-gate no_trap(); 6617c478bd9Sstevel@tonic-gate if (pcitool_debug) 6627c478bd9Sstevel@tonic-gate prom_printf( 6637c478bd9Sstevel@tonic-gate "pcitool_mem_access: on_trap caught an error...\n"); 6647c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 6657c478bd9Sstevel@tonic-gate return (EFAULT); 6667c478bd9Sstevel@tonic-gate } 6677c478bd9Sstevel@tonic-gate 6687c478bd9Sstevel@tonic-gate if (write_flag) { 6697c478bd9Sstevel@tonic-gate 6707c478bd9Sstevel@tonic-gate if (big_endian) { 6717c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 6727c478bd9Sstevel@tonic-gate } else { 6737c478bd9Sstevel@tonic-gate local_data = prg->data; 6747c478bd9Sstevel@tonic-gate } 6757c478bd9Sstevel@tonic-gate 6767c478bd9Sstevel@tonic-gate switch (size) { 6777c478bd9Sstevel@tonic-gate case 1: 6787c478bd9Sstevel@tonic-gate *((uint8_t *)(uintptr_t)virt_addr) = local_data; 6797c478bd9Sstevel@tonic-gate break; 6807c478bd9Sstevel@tonic-gate case 2: 6817c478bd9Sstevel@tonic-gate *((uint16_t *)(uintptr_t)virt_addr) = local_data; 6827c478bd9Sstevel@tonic-gate break; 6837c478bd9Sstevel@tonic-gate case 4: 6847c478bd9Sstevel@tonic-gate *((uint32_t *)(uintptr_t)virt_addr) = local_data; 6857c478bd9Sstevel@tonic-gate break; 6867c478bd9Sstevel@tonic-gate case 8: 6877c478bd9Sstevel@tonic-gate *((uint64_t *)(uintptr_t)virt_addr) = local_data; 6887c478bd9Sstevel@tonic-gate break; 6897c478bd9Sstevel@tonic-gate default: 6907c478bd9Sstevel@tonic-gate rval = ENOTSUP; 6917c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 6927c478bd9Sstevel@tonic-gate break; 6937c478bd9Sstevel@tonic-gate } 6947c478bd9Sstevel@tonic-gate } else { 6957c478bd9Sstevel@tonic-gate switch (size) { 6967c478bd9Sstevel@tonic-gate case 1: 6977c478bd9Sstevel@tonic-gate local_data = *((uint8_t *)(uintptr_t)virt_addr); 6987c478bd9Sstevel@tonic-gate break; 6997c478bd9Sstevel@tonic-gate case 2: 7007c478bd9Sstevel@tonic-gate local_data = *((uint16_t *)(uintptr_t)virt_addr); 7017c478bd9Sstevel@tonic-gate break; 7027c478bd9Sstevel@tonic-gate case 4: 7037c478bd9Sstevel@tonic-gate local_data = *((uint32_t *)(uintptr_t)virt_addr); 7047c478bd9Sstevel@tonic-gate break; 7057c478bd9Sstevel@tonic-gate case 8: 7067c478bd9Sstevel@tonic-gate local_data = *((uint64_t *)(uintptr_t)virt_addr); 7077c478bd9Sstevel@tonic-gate break; 7087c478bd9Sstevel@tonic-gate default: 7097c478bd9Sstevel@tonic-gate rval = ENOTSUP; 7107c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 7117c478bd9Sstevel@tonic-gate break; 7127c478bd9Sstevel@tonic-gate } 7137c478bd9Sstevel@tonic-gate 7147c478bd9Sstevel@tonic-gate if (rval == SUCCESS) { 7157c478bd9Sstevel@tonic-gate if (big_endian) { 7167c478bd9Sstevel@tonic-gate prg->data = 7177c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 7187c478bd9Sstevel@tonic-gate } else { 7197c478bd9Sstevel@tonic-gate prg->data = local_data; 7207c478bd9Sstevel@tonic-gate } 7217c478bd9Sstevel@tonic-gate } 7227c478bd9Sstevel@tonic-gate } 7237c478bd9Sstevel@tonic-gate 7247c478bd9Sstevel@tonic-gate no_trap(); 7257c478bd9Sstevel@tonic-gate return (rval); 7267c478bd9Sstevel@tonic-gate } 7277c478bd9Sstevel@tonic-gate 7287c478bd9Sstevel@tonic-gate /* 7297c478bd9Sstevel@tonic-gate * Map up to 2 pages which contain the address we want to access. 7307c478bd9Sstevel@tonic-gate * 7317c478bd9Sstevel@tonic-gate * Mapping should span no more than 8 bytes. With X86 it is possible for an 7327c478bd9Sstevel@tonic-gate * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary. 7337c478bd9Sstevel@tonic-gate * We'll never have to map more than two pages. 7347c478bd9Sstevel@tonic-gate */ 7357c478bd9Sstevel@tonic-gate 7367c478bd9Sstevel@tonic-gate static uint64_t 7377c478bd9Sstevel@tonic-gate pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages) 7387c478bd9Sstevel@tonic-gate { 7397c478bd9Sstevel@tonic-gate 7407c478bd9Sstevel@tonic-gate uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET; 7417c478bd9Sstevel@tonic-gate uint64_t offset = phys_addr & MMU_PAGEOFFSET; 7427c478bd9Sstevel@tonic-gate void *virt_base; 7437c478bd9Sstevel@tonic-gate uint64_t returned_addr; 7447c478bd9Sstevel@tonic-gate 7457c478bd9Sstevel@tonic-gate if (pcitool_debug) 7467c478bd9Sstevel@tonic-gate prom_printf("pcitool_map: Called with PA:0x%p\n", 7477c478bd9Sstevel@tonic-gate (uint8_t *)(uintptr_t)phys_addr); 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate *num_pages = 1; 7507c478bd9Sstevel@tonic-gate 7517c478bd9Sstevel@tonic-gate /* Desired mapping would span more than two pages. */ 7527c478bd9Sstevel@tonic-gate if ((offset + size) > (MMU_PAGESIZE * 2)) { 7537c478bd9Sstevel@tonic-gate if (pcitool_debug) 7547c478bd9Sstevel@tonic-gate prom_printf("boundary violation: " 755d4476ccbSschwartz "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n", 756d4476ccbSschwartz offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE); 7577c478bd9Sstevel@tonic-gate return (NULL); 7587c478bd9Sstevel@tonic-gate 7597c478bd9Sstevel@tonic-gate } else if ((offset + size) > MMU_PAGESIZE) { 7607c478bd9Sstevel@tonic-gate (*num_pages)++; 7617c478bd9Sstevel@tonic-gate } 7627c478bd9Sstevel@tonic-gate 7637c478bd9Sstevel@tonic-gate /* Get page(s) of virtual space. */ 7647c478bd9Sstevel@tonic-gate virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP); 7657c478bd9Sstevel@tonic-gate if (virt_base == NULL) { 7667c478bd9Sstevel@tonic-gate if (pcitool_debug) 7677c478bd9Sstevel@tonic-gate prom_printf("Couldn't get virtual base address.\n"); 7687c478bd9Sstevel@tonic-gate return (NULL); 7697c478bd9Sstevel@tonic-gate } 7707c478bd9Sstevel@tonic-gate 7717c478bd9Sstevel@tonic-gate if (pcitool_debug) 7727c478bd9Sstevel@tonic-gate prom_printf("Got base virtual address:0x%p\n", virt_base); 7737c478bd9Sstevel@tonic-gate 7747c478bd9Sstevel@tonic-gate /* Now map the allocated virtual space to the physical address. */ 7757c478bd9Sstevel@tonic-gate hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), 7767c478bd9Sstevel@tonic-gate mmu_btop(page_base), PROT_READ | PROT_WRITE | HAT_STRICTORDER, 7777c478bd9Sstevel@tonic-gate HAT_LOAD_LOCK); 7787c478bd9Sstevel@tonic-gate 7797c478bd9Sstevel@tonic-gate returned_addr = ((uintptr_t)(virt_base)) + offset; 7807c478bd9Sstevel@tonic-gate 7817c478bd9Sstevel@tonic-gate if (pcitool_debug) 7827c478bd9Sstevel@tonic-gate prom_printf("pcitool_map: returning VA:0x%p\n", 7837c478bd9Sstevel@tonic-gate (void *)(uintptr_t)returned_addr); 7847c478bd9Sstevel@tonic-gate 7857c478bd9Sstevel@tonic-gate return (returned_addr); 7867c478bd9Sstevel@tonic-gate } 7877c478bd9Sstevel@tonic-gate 7887c478bd9Sstevel@tonic-gate /* Unmap the mapped page(s). */ 7897c478bd9Sstevel@tonic-gate static void 7907c478bd9Sstevel@tonic-gate pcitool_unmap(uint64_t virt_addr, size_t num_pages) 7917c478bd9Sstevel@tonic-gate { 7927c478bd9Sstevel@tonic-gate void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET); 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages), 7957c478bd9Sstevel@tonic-gate HAT_UNLOAD_UNLOCK); 7967c478bd9Sstevel@tonic-gate vmem_free(heap_arena, base_virt_addr, ptob(num_pages)); 7977c478bd9Sstevel@tonic-gate } 7987c478bd9Sstevel@tonic-gate 7997c478bd9Sstevel@tonic-gate 8007c478bd9Sstevel@tonic-gate /* Perform register accesses on PCI leaf devices. */ 8017c478bd9Sstevel@tonic-gate int 802d4476ccbSschwartz pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 8037c478bd9Sstevel@tonic-gate { 8047c478bd9Sstevel@tonic-gate boolean_t write_flag = B_FALSE; 8057c478bd9Sstevel@tonic-gate int rval = 0; 8067c478bd9Sstevel@tonic-gate pcitool_reg_t prg; 8077c478bd9Sstevel@tonic-gate uint8_t size; 8087c478bd9Sstevel@tonic-gate 8097c478bd9Sstevel@tonic-gate uint64_t base_addr; 8107c478bd9Sstevel@tonic-gate uint64_t virt_addr; 8117c478bd9Sstevel@tonic-gate size_t num_virt_pages; 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate switch (cmd) { 8147c478bd9Sstevel@tonic-gate case (PCITOOL_DEVICE_SET_REG): 8157c478bd9Sstevel@tonic-gate write_flag = B_TRUE; 8167c478bd9Sstevel@tonic-gate 8177c478bd9Sstevel@tonic-gate /*FALLTHRU*/ 8187c478bd9Sstevel@tonic-gate case (PCITOOL_DEVICE_GET_REG): 8197c478bd9Sstevel@tonic-gate if (pcitool_debug) 8207c478bd9Sstevel@tonic-gate prom_printf("pci_dev_reg_ops set/get reg\n"); 8217c478bd9Sstevel@tonic-gate if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) != 8227c478bd9Sstevel@tonic-gate DDI_SUCCESS) { 8237c478bd9Sstevel@tonic-gate if (pcitool_debug) 8247c478bd9Sstevel@tonic-gate prom_printf("Error reading arguments\n"); 8257c478bd9Sstevel@tonic-gate return (EFAULT); 8267c478bd9Sstevel@tonic-gate } 8277c478bd9Sstevel@tonic-gate 8287c478bd9Sstevel@tonic-gate if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) { 8297c478bd9Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 8307c478bd9Sstevel@tonic-gate rval = EINVAL; 8317c478bd9Sstevel@tonic-gate goto done_reg; 8327c478bd9Sstevel@tonic-gate } 8337c478bd9Sstevel@tonic-gate 8347c478bd9Sstevel@tonic-gate if (pcitool_debug) 8357c478bd9Sstevel@tonic-gate prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n", 8367c478bd9Sstevel@tonic-gate prg.bus_no, prg.dev_no, prg.func_no); 8377c478bd9Sstevel@tonic-gate /* Validate address arguments of bus / dev / func */ 8387c478bd9Sstevel@tonic-gate if (((prg.bus_no & 8397c478bd9Sstevel@tonic-gate (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != 8407c478bd9Sstevel@tonic-gate prg.bus_no) || 8417c478bd9Sstevel@tonic-gate ((prg.dev_no & 8427c478bd9Sstevel@tonic-gate (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != 8437c478bd9Sstevel@tonic-gate prg.dev_no) || 8447c478bd9Sstevel@tonic-gate ((prg.func_no & 8457c478bd9Sstevel@tonic-gate (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != 8467c478bd9Sstevel@tonic-gate prg.func_no)) { 8477c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 8487c478bd9Sstevel@tonic-gate rval = EINVAL; 8497c478bd9Sstevel@tonic-gate goto done_reg; 8507c478bd9Sstevel@tonic-gate } 8517c478bd9Sstevel@tonic-gate 8527c478bd9Sstevel@tonic-gate size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr); 8537c478bd9Sstevel@tonic-gate 8547c478bd9Sstevel@tonic-gate /* Proper config space desired. */ 8557c478bd9Sstevel@tonic-gate if (prg.barnum == 0) { 8567c478bd9Sstevel@tonic-gate 8577c478bd9Sstevel@tonic-gate if (pcitool_debug) 8587c478bd9Sstevel@tonic-gate prom_printf( 8597c478bd9Sstevel@tonic-gate "config access: offset:0x%" PRIx64 ", " 8607c478bd9Sstevel@tonic-gate "phys_addr:0x%" PRIx64 "\n", 8617c478bd9Sstevel@tonic-gate prg.offset, prg.phys_addr); 862d4476ccbSschwartz 863d4476ccbSschwartz if (prg.offset >= max_cfg_size) { 864d4476ccbSschwartz prg.status = PCITOOL_OUT_OF_RANGE; 865d4476ccbSschwartz rval = EINVAL; 866d4476ccbSschwartz goto done_reg; 867d4476ccbSschwartz } 868d4476ccbSschwartz 869*649d4cceSanish /* 870*649d4cceSanish * Access device. prg is modified. 871*649d4cceSanish * First, check for AMD northbridges for I/O access 872*649d4cceSanish * (This fix will move in future to pcitool user-land) 873*649d4cceSanish * Next, check for PCIe devices and do 874*649d4cceSanish * memory-mapped access 875*649d4cceSanish * Lastly, check for PCI devices and do I/O access 876*649d4cceSanish */ 877*649d4cceSanish if (prg.bus_no == 0 && prg.dev_no == 0x18) { 878*649d4cceSanish if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) 879*649d4cceSanish rval = pcitool_cfg_access(dip, &prg, 880*649d4cceSanish write_flag); 881*649d4cceSanish } else if (max_cfg_size == PCIE_CONF_HDR_SIZE) 882d4476ccbSschwartz rval = pcitool_pciex_cfg_access(dip, &prg, 883d4476ccbSschwartz write_flag); 884d4476ccbSschwartz else 885d4476ccbSschwartz rval = pcitool_cfg_access(dip, &prg, 886d4476ccbSschwartz write_flag); 8877c478bd9Sstevel@tonic-gate 8887c478bd9Sstevel@tonic-gate if (pcitool_debug) 8897c478bd9Sstevel@tonic-gate prom_printf( 8907c478bd9Sstevel@tonic-gate "config access: data:0x%" PRIx64 "\n", 8917c478bd9Sstevel@tonic-gate prg.data); 8927c478bd9Sstevel@tonic-gate 8937c478bd9Sstevel@tonic-gate /* IO/ MEM/ MEM64 space. */ 8947c478bd9Sstevel@tonic-gate } else { 8957c478bd9Sstevel@tonic-gate 8967c478bd9Sstevel@tonic-gate pcitool_reg_t prg2; 8977c478bd9Sstevel@tonic-gate bcopy(&prg, &prg2, sizeof (pcitool_reg_t)); 8987c478bd9Sstevel@tonic-gate 8997c478bd9Sstevel@tonic-gate /* 9007c478bd9Sstevel@tonic-gate * Translate BAR number into offset of the BAR in 9017c478bd9Sstevel@tonic-gate * the device's config space. 9027c478bd9Sstevel@tonic-gate */ 9037c478bd9Sstevel@tonic-gate prg2.offset = pci_bars[prg2.barnum]; 9047c478bd9Sstevel@tonic-gate prg2.acc_attr = 9057c478bd9Sstevel@tonic-gate PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL; 9067c478bd9Sstevel@tonic-gate 9077c478bd9Sstevel@tonic-gate if (pcitool_debug) 9087c478bd9Sstevel@tonic-gate prom_printf( 9097c478bd9Sstevel@tonic-gate "barnum:%d, bar_offset:0x%" PRIx64 "\n", 9107c478bd9Sstevel@tonic-gate prg2.barnum, prg2.offset); 9117c478bd9Sstevel@tonic-gate /* 9127c478bd9Sstevel@tonic-gate * Get Bus Address Register (BAR) from config space. 9137c478bd9Sstevel@tonic-gate * prg2.offset is the offset into config space of the 9147c478bd9Sstevel@tonic-gate * BAR desired. prg.status is modified on error. 9157c478bd9Sstevel@tonic-gate */ 9167c478bd9Sstevel@tonic-gate rval = pcitool_cfg_access(dip, &prg2, B_FALSE); 9177c478bd9Sstevel@tonic-gate if (rval != SUCCESS) { 9187c478bd9Sstevel@tonic-gate if (pcitool_debug) 9197c478bd9Sstevel@tonic-gate prom_printf("BAR access failed\n"); 9207c478bd9Sstevel@tonic-gate prg.status = prg2.status; 9217c478bd9Sstevel@tonic-gate goto done_reg; 9227c478bd9Sstevel@tonic-gate } 9237c478bd9Sstevel@tonic-gate /* 9247c478bd9Sstevel@tonic-gate * Reference proper PCI space based on the BAR. 9257c478bd9Sstevel@tonic-gate * If 64 bit MEM space, need to load other half of the 9267c478bd9Sstevel@tonic-gate * BAR first. 9277c478bd9Sstevel@tonic-gate */ 9287c478bd9Sstevel@tonic-gate 9297c478bd9Sstevel@tonic-gate if (pcitool_debug) 9307c478bd9Sstevel@tonic-gate prom_printf("bar returned is 0x%" PRIx64 "\n", 9317c478bd9Sstevel@tonic-gate prg2.data); 9327c478bd9Sstevel@tonic-gate if (!prg2.data) { 9337c478bd9Sstevel@tonic-gate if (pcitool_debug) 9347c478bd9Sstevel@tonic-gate prom_printf("BAR data == 0\n"); 9357c478bd9Sstevel@tonic-gate rval = EINVAL; 9367c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 9377c478bd9Sstevel@tonic-gate goto done_reg; 9387c478bd9Sstevel@tonic-gate } 9397c478bd9Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 9407c478bd9Sstevel@tonic-gate if (pcitool_debug) 9417c478bd9Sstevel@tonic-gate prom_printf("BAR data == -1\n"); 9427c478bd9Sstevel@tonic-gate rval = EINVAL; 9437c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 9447c478bd9Sstevel@tonic-gate goto done_reg; 9457c478bd9Sstevel@tonic-gate } 9467c478bd9Sstevel@tonic-gate 9477c478bd9Sstevel@tonic-gate /* 9487c478bd9Sstevel@tonic-gate * BAR has bits saying this space is IO space, unless 9497c478bd9Sstevel@tonic-gate * this is the ROM address register. 9507c478bd9Sstevel@tonic-gate */ 9517c478bd9Sstevel@tonic-gate if (((PCI_BASE_SPACE_M & prg2.data) == 9527c478bd9Sstevel@tonic-gate PCI_BASE_SPACE_IO) && 9537c478bd9Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 9547c478bd9Sstevel@tonic-gate if (pcitool_debug) 9557c478bd9Sstevel@tonic-gate prom_printf("IO space\n"); 9567c478bd9Sstevel@tonic-gate 9577c478bd9Sstevel@tonic-gate prg2.data &= PCI_BASE_IO_ADDR_M; 9587c478bd9Sstevel@tonic-gate prg.phys_addr = prg2.data + prg.offset; 9597c478bd9Sstevel@tonic-gate 9607c478bd9Sstevel@tonic-gate rval = pcitool_io_access(dip, &prg, write_flag); 9617c478bd9Sstevel@tonic-gate if ((rval != SUCCESS) && (pcitool_debug)) 9627c478bd9Sstevel@tonic-gate prom_printf("IO access failed\n"); 9637c478bd9Sstevel@tonic-gate 9647c478bd9Sstevel@tonic-gate goto done_reg; 9657c478bd9Sstevel@tonic-gate 9667c478bd9Sstevel@tonic-gate 9677c478bd9Sstevel@tonic-gate /* 9687c478bd9Sstevel@tonic-gate * BAR has bits saying this space is 64 bit memory 9697c478bd9Sstevel@tonic-gate * space, unless this is the ROM address register. 9707c478bd9Sstevel@tonic-gate * 9717c478bd9Sstevel@tonic-gate * The 64 bit address stored in two BAR cells is not 9727c478bd9Sstevel@tonic-gate * necessarily aligned on an 8-byte boundary. 9737c478bd9Sstevel@tonic-gate * Need to keep the first 4 bytes read, 9747c478bd9Sstevel@tonic-gate * and do a separate read of the high 4 bytes. 9757c478bd9Sstevel@tonic-gate */ 9767c478bd9Sstevel@tonic-gate 9777c478bd9Sstevel@tonic-gate } else if ((PCI_BASE_TYPE_ALL & prg2.data) && 9787c478bd9Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 9797c478bd9Sstevel@tonic-gate 9807c478bd9Sstevel@tonic-gate uint32_t low_bytes = 9817c478bd9Sstevel@tonic-gate (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL); 9827c478bd9Sstevel@tonic-gate 9837c478bd9Sstevel@tonic-gate /* 9847c478bd9Sstevel@tonic-gate * Don't try to read the next 4 bytes 9857c478bd9Sstevel@tonic-gate * past the end of BARs. 9867c478bd9Sstevel@tonic-gate */ 9877c478bd9Sstevel@tonic-gate if (prg2.offset >= PCI_CONF_BASE5) { 9887c478bd9Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 9897c478bd9Sstevel@tonic-gate rval = EIO; 9907c478bd9Sstevel@tonic-gate goto done_reg; 9917c478bd9Sstevel@tonic-gate } 9927c478bd9Sstevel@tonic-gate 9937c478bd9Sstevel@tonic-gate /* 9947c478bd9Sstevel@tonic-gate * Access device. 9957c478bd9Sstevel@tonic-gate * prg2.status is modified on error. 9967c478bd9Sstevel@tonic-gate */ 9977c478bd9Sstevel@tonic-gate prg2.offset += 4; 9987c478bd9Sstevel@tonic-gate rval = pcitool_cfg_access(dip, &prg2, B_FALSE); 9997c478bd9Sstevel@tonic-gate if (rval != SUCCESS) { 10007c478bd9Sstevel@tonic-gate prg.status = prg2.status; 10017c478bd9Sstevel@tonic-gate goto done_reg; 10027c478bd9Sstevel@tonic-gate } 10037c478bd9Sstevel@tonic-gate 10047c478bd9Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 10057c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 10067c478bd9Sstevel@tonic-gate prg.status = EFAULT; 10077c478bd9Sstevel@tonic-gate goto done_reg; 10087c478bd9Sstevel@tonic-gate } 10097c478bd9Sstevel@tonic-gate 10107c478bd9Sstevel@tonic-gate prg2.data = (prg2.data << 32) + low_bytes; 10117c478bd9Sstevel@tonic-gate if (pcitool_debug) 10127c478bd9Sstevel@tonic-gate prom_printf( 10137c478bd9Sstevel@tonic-gate "64 bit mem space. " 10147c478bd9Sstevel@tonic-gate "64-bit bar is 0x%" PRIx64 "\n", 10157c478bd9Sstevel@tonic-gate prg2.data); 10167c478bd9Sstevel@tonic-gate 10177c478bd9Sstevel@tonic-gate /* Mem32 space, including ROM */ 10187c478bd9Sstevel@tonic-gate } else { 10197c478bd9Sstevel@tonic-gate 10207c478bd9Sstevel@tonic-gate if (prg2.offset == PCI_CONF_ROM) { 10217c478bd9Sstevel@tonic-gate if (pcitool_debug) 10227c478bd9Sstevel@tonic-gate prom_printf( 10237c478bd9Sstevel@tonic-gate "Additional ROM " 10247c478bd9Sstevel@tonic-gate "checking\n"); 10257c478bd9Sstevel@tonic-gate /* Can't write to ROM */ 10267c478bd9Sstevel@tonic-gate if (write_flag) { 10277c478bd9Sstevel@tonic-gate prg.status = PCITOOL_ROM_WRITE; 10287c478bd9Sstevel@tonic-gate rval = EIO; 10297c478bd9Sstevel@tonic-gate goto done_reg; 10307c478bd9Sstevel@tonic-gate 10317c478bd9Sstevel@tonic-gate /* ROM disabled for reading */ 10327c478bd9Sstevel@tonic-gate } else if (!(prg2.data & 0x00000001)) { 10337c478bd9Sstevel@tonic-gate prg.status = 10347c478bd9Sstevel@tonic-gate PCITOOL_ROM_DISABLED; 10357c478bd9Sstevel@tonic-gate rval = EIO; 10367c478bd9Sstevel@tonic-gate goto done_reg; 10377c478bd9Sstevel@tonic-gate } 10387c478bd9Sstevel@tonic-gate } 10397c478bd9Sstevel@tonic-gate 10407c478bd9Sstevel@tonic-gate if (pcitool_debug) 10417c478bd9Sstevel@tonic-gate prom_printf("32 bit mem space\n"); 10427c478bd9Sstevel@tonic-gate } 10437c478bd9Sstevel@tonic-gate 10447c478bd9Sstevel@tonic-gate /* Common code for all IO/MEM range spaces. */ 10457c478bd9Sstevel@tonic-gate 10467c478bd9Sstevel@tonic-gate base_addr = prg2.data; 10477c478bd9Sstevel@tonic-gate if (pcitool_debug) 10487c478bd9Sstevel@tonic-gate prom_printf( 10497c478bd9Sstevel@tonic-gate "addr portion of bar is 0x%" PRIx64 ", " 10507c478bd9Sstevel@tonic-gate "base=0x%" PRIx64 ", " 10517c478bd9Sstevel@tonic-gate "offset:0x%" PRIx64 "\n", 10527c478bd9Sstevel@tonic-gate prg2.data, base_addr, prg.offset); 10537c478bd9Sstevel@tonic-gate /* 10547c478bd9Sstevel@tonic-gate * Use offset provided by caller to index into 10557c478bd9Sstevel@tonic-gate * desired space, then access. 10567c478bd9Sstevel@tonic-gate * Note that prg.status is modified on error. 10577c478bd9Sstevel@tonic-gate */ 10587c478bd9Sstevel@tonic-gate prg.phys_addr = base_addr + prg.offset; 10597c478bd9Sstevel@tonic-gate 10607c478bd9Sstevel@tonic-gate virt_addr = pcitool_map(prg.phys_addr, size, 10617c478bd9Sstevel@tonic-gate &num_virt_pages); 10627c478bd9Sstevel@tonic-gate if (virt_addr == NULL) { 10637c478bd9Sstevel@tonic-gate prg.status = PCITOOL_IO_ERROR; 10647c478bd9Sstevel@tonic-gate rval = EIO; 10657c478bd9Sstevel@tonic-gate goto done_reg; 10667c478bd9Sstevel@tonic-gate } 10677c478bd9Sstevel@tonic-gate 10687c478bd9Sstevel@tonic-gate rval = pcitool_mem_access(dip, &prg, virt_addr, 10697c478bd9Sstevel@tonic-gate write_flag); 10707c478bd9Sstevel@tonic-gate pcitool_unmap(virt_addr, num_virt_pages); 10717c478bd9Sstevel@tonic-gate } 10727c478bd9Sstevel@tonic-gate done_reg: 10737c478bd9Sstevel@tonic-gate if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) != 10747c478bd9Sstevel@tonic-gate DDI_SUCCESS) { 10757c478bd9Sstevel@tonic-gate if (pcitool_debug) 10767c478bd9Sstevel@tonic-gate prom_printf("Error returning arguments.\n"); 10777c478bd9Sstevel@tonic-gate rval = EFAULT; 10787c478bd9Sstevel@tonic-gate } 10797c478bd9Sstevel@tonic-gate break; 10807c478bd9Sstevel@tonic-gate default: 10817c478bd9Sstevel@tonic-gate rval = ENOTTY; 10827c478bd9Sstevel@tonic-gate break; 10837c478bd9Sstevel@tonic-gate } 10847c478bd9Sstevel@tonic-gate return (rval); 10857c478bd9Sstevel@tonic-gate } 1086