17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 50e6b5dadSanish * Common Development and Distribution License (the "License"). 60e6b5dadSanish * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 228d7fafffSZhi-Jun Robin Fu * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 247c478bd9Sstevel@tonic-gate 25*de710d24SJosef 'Jeff' Sipek #include <sys/sysmacros.h> 267c478bd9Sstevel@tonic-gate #include <sys/types.h> 277c478bd9Sstevel@tonic-gate #include <sys/mkdev.h> 287851eb82Sschwartz #include <sys/stat.h> 297c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 307c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 317c478bd9Sstevel@tonic-gate #include <sys/machparam.h> 327a364d25Sschwartz #include <sys/sunndi.h> 337c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 347a364d25Sschwartz #include <sys/psm.h> 3570025d76Sjohnny #include <sys/pcie.h> 367c478bd9Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 377c478bd9Sstevel@tonic-gate #include <sys/pci_tools.h> 38649d4cceSanish #include <io/pci/pci_tools_ext.h> 39ae115bc7Smrj #include <sys/apic.h> 407ff178cdSJimmy Vetayases #include <sys/apix.h> 417a364d25Sschwartz #include <io/pci/pci_var.h> 4226947304SEvan Yan #include <sys/pci_impl.h> 437c478bd9Sstevel@tonic-gate #include <sys/promif.h> 44649d4cceSanish #include <sys/x86_archext.h> 450e6b5dadSanish #include <sys/cpuvar.h> 46c0da6274SZhi-Jun Robin Fu #include <sys/pci_cfgacc.h> 477c478bd9Sstevel@tonic-gate 48843e1988Sjohnlev #ifdef __xpv 49843e1988Sjohnlev #include <sys/hypervisor.h> 50843e1988Sjohnlev #endif 51843e1988Sjohnlev 52d4476ccbSschwartz #define PCIEX_BDF_OFFSET_DELTA 4 53d4476ccbSschwartz #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA) 54d4476ccbSschwartz #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA) 55d4476ccbSschwartz #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA) 56d4476ccbSschwartz 577c478bd9Sstevel@tonic-gate #define SUCCESS 0 587c478bd9Sstevel@tonic-gate 59c0da6274SZhi-Jun Robin Fu extern uint64_t mcfg_mem_base; 607c478bd9Sstevel@tonic-gate int pcitool_debug = 0; 617c478bd9Sstevel@tonic-gate 627c478bd9Sstevel@tonic-gate /* 637c478bd9Sstevel@tonic-gate * Offsets of BARS in config space. First entry of 0 means config space. 647c478bd9Sstevel@tonic-gate * Entries here correlate to pcitool_bars_t enumerated type. 657c478bd9Sstevel@tonic-gate */ 667c478bd9Sstevel@tonic-gate static uint8_t pci_bars[] = { 677c478bd9Sstevel@tonic-gate 0x0, 687c478bd9Sstevel@tonic-gate PCI_CONF_BASE0, 697c478bd9Sstevel@tonic-gate PCI_CONF_BASE1, 707c478bd9Sstevel@tonic-gate PCI_CONF_BASE2, 717c478bd9Sstevel@tonic-gate PCI_CONF_BASE3, 727c478bd9Sstevel@tonic-gate PCI_CONF_BASE4, 737c478bd9Sstevel@tonic-gate PCI_CONF_BASE5, 747c478bd9Sstevel@tonic-gate PCI_CONF_ROM 757c478bd9Sstevel@tonic-gate }; 767c478bd9Sstevel@tonic-gate 77d4476ccbSschwartz /* Max offset allowed into config space for a particular device. */ 78d4476ccbSschwartz static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE; 79d4476ccbSschwartz 807c478bd9Sstevel@tonic-gate static uint64_t pcitool_swap_endian(uint64_t data, int size); 81c0da6274SZhi-Jun Robin Fu static int pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 82c0da6274SZhi-Jun Robin Fu boolean_t io_access); 83c0da6274SZhi-Jun Robin Fu static int pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag); 84c0da6274SZhi-Jun Robin Fu static int pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, 85d4476ccbSschwartz boolean_t write_flag); 867c478bd9Sstevel@tonic-gate static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages); 877c478bd9Sstevel@tonic-gate static void pcitool_unmap(uint64_t virt_addr, size_t num_pages); 887c478bd9Sstevel@tonic-gate 892917a9c9Sschwartz /* Extern declarations */ 907a364d25Sschwartz extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 917a364d25Sschwartz psm_intr_op_t, int *); 927a364d25Sschwartz 937851eb82Sschwartz int 94d4476ccbSschwartz pcitool_init(dev_info_t *dip, boolean_t is_pciex) 957851eb82Sschwartz { 967851eb82Sschwartz int instance = ddi_get_instance(dip); 977851eb82Sschwartz 987851eb82Sschwartz /* Create pcitool nodes for register access and interrupt routing. */ 997851eb82Sschwartz 1007851eb82Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR, 10126947304SEvan Yan PCI_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM), 1027851eb82Sschwartz DDI_NT_REGACC, 0) != DDI_SUCCESS) { 1037851eb82Sschwartz return (DDI_FAILURE); 1047851eb82Sschwartz } 1057851eb82Sschwartz 1067851eb82Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR, 10726947304SEvan Yan PCI_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM), 1087851eb82Sschwartz DDI_NT_INTRCTL, 0) != DDI_SUCCESS) { 1097851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 1107851eb82Sschwartz return (DDI_FAILURE); 1117851eb82Sschwartz } 1127851eb82Sschwartz 113d4476ccbSschwartz if (is_pciex) 114d4476ccbSschwartz max_cfg_size = PCIE_CONF_HDR_SIZE; 115d4476ccbSschwartz 1167851eb82Sschwartz return (DDI_SUCCESS); 1177851eb82Sschwartz } 1187851eb82Sschwartz 1197851eb82Sschwartz void 1207851eb82Sschwartz pcitool_uninit(dev_info_t *dip) 1217851eb82Sschwartz { 1227851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_INTR); 1237851eb82Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 1247851eb82Sschwartz } 1257851eb82Sschwartz 1267a364d25Sschwartz /*ARGSUSED*/ 1277a364d25Sschwartz static int 1287a364d25Sschwartz pcitool_set_intr(dev_info_t *dip, void *arg, int mode) 1297a364d25Sschwartz { 1307a364d25Sschwartz ddi_intr_handle_impl_t info_hdl; 1317a364d25Sschwartz pcitool_intr_set_t iset; 1327a364d25Sschwartz uint32_t old_cpu; 1337a364d25Sschwartz int ret, result; 1342917a9c9Sschwartz size_t copyinout_size; 1357a364d25Sschwartz int rval = SUCCESS; 1367ff178cdSJimmy Vetayases apic_get_type_t type_info; 1377a364d25Sschwartz 1382917a9c9Sschwartz /* Version 1 of pcitool_intr_set_t doesn't have flags. */ 1392917a9c9Sschwartz copyinout_size = (size_t)&iset.flags - (size_t)&iset; 1402917a9c9Sschwartz 1412917a9c9Sschwartz if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 1427a364d25Sschwartz return (EFAULT); 1437a364d25Sschwartz 1442917a9c9Sschwartz switch (iset.user_version) { 1452917a9c9Sschwartz case PCITOOL_V1: 1462917a9c9Sschwartz break; 1472917a9c9Sschwartz 1482917a9c9Sschwartz case PCITOOL_V2: 1492917a9c9Sschwartz copyinout_size = sizeof (pcitool_intr_set_t); 1502917a9c9Sschwartz if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 1512917a9c9Sschwartz return (EFAULT); 1522917a9c9Sschwartz break; 1532917a9c9Sschwartz 1542917a9c9Sschwartz default: 1552917a9c9Sschwartz iset.status = PCITOOL_OUT_OF_RANGE; 1562917a9c9Sschwartz rval = ENOTSUP; 1572917a9c9Sschwartz goto done_set_intr; 1582917a9c9Sschwartz } 1592917a9c9Sschwartz 16009b1eac2SEvan Yan if (iset.flags & PCITOOL_INTR_FLAG_SET_MSI) { 16109b1eac2SEvan Yan rval = ENOTSUP; 16209b1eac2SEvan Yan iset.status = PCITOOL_IO_ERROR; 16309b1eac2SEvan Yan goto done_set_intr; 16409b1eac2SEvan Yan } 16509b1eac2SEvan Yan 1667ff178cdSJimmy Vetayases info_hdl.ih_private = &type_info; 1677ff178cdSJimmy Vetayases 1687ff178cdSJimmy Vetayases if ((*psm_intr_ops)(NULL, &info_hdl, 1697ff178cdSJimmy Vetayases PSM_INTR_OP_APIC_TYPE, NULL) != PSM_SUCCESS) { 1707ff178cdSJimmy Vetayases rval = ENOTSUP; 1717ff178cdSJimmy Vetayases iset.status = PCITOOL_IO_ERROR; 1727ff178cdSJimmy Vetayases goto done_set_intr; 1737ff178cdSJimmy Vetayases } 1747ff178cdSJimmy Vetayases 1757ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) { 1767ff178cdSJimmy Vetayases if (iset.old_cpu > type_info.avgi_num_cpu) { 1777ff178cdSJimmy Vetayases rval = EINVAL; 1787ff178cdSJimmy Vetayases iset.status = PCITOOL_INVALID_CPUID; 1797ff178cdSJimmy Vetayases goto done_set_intr; 1807ff178cdSJimmy Vetayases } 1817ff178cdSJimmy Vetayases old_cpu = iset.old_cpu; 1827ff178cdSJimmy Vetayases } else { 1837ff178cdSJimmy Vetayases if ((old_cpu = 1847ff178cdSJimmy Vetayases pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) { 1857ff178cdSJimmy Vetayases iset.status = PCITOOL_IO_ERROR; 1867ff178cdSJimmy Vetayases rval = EINVAL; 1877ff178cdSJimmy Vetayases goto done_set_intr; 1887ff178cdSJimmy Vetayases } 1897ff178cdSJimmy Vetayases } 1907ff178cdSJimmy Vetayases 1917ff178cdSJimmy Vetayases if (iset.ino > type_info.avgi_num_intr) { 1927a364d25Sschwartz rval = EINVAL; 1937a364d25Sschwartz iset.status = PCITOOL_INVALID_INO; 1947a364d25Sschwartz goto done_set_intr; 1957a364d25Sschwartz } 1967a364d25Sschwartz 1977a364d25Sschwartz iset.status = PCITOOL_SUCCESS; 1987a364d25Sschwartz 1997a364d25Sschwartz old_cpu &= ~PSMGI_CPU_USER_BOUND; 2007a364d25Sschwartz 2017a364d25Sschwartz /* 2027a364d25Sschwartz * For this locally-declared and used handle, ih_private will contain a 2037a364d25Sschwartz * CPU value, not an ihdl_plat_t as used for global interrupt handling. 2047a364d25Sschwartz */ 2057ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) { 2067ff178cdSJimmy Vetayases info_hdl.ih_vector = APIX_VIRTVECTOR(old_cpu, iset.ino); 2077ff178cdSJimmy Vetayases } else { 2087a364d25Sschwartz info_hdl.ih_vector = iset.ino; 2097ff178cdSJimmy Vetayases } 2107a364d25Sschwartz info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id; 21109b1eac2SEvan Yan info_hdl.ih_flags = PSMGI_INTRBY_VEC; 2122917a9c9Sschwartz if (pcitool_debug) 2132917a9c9Sschwartz prom_printf("user version:%d, flags:0x%x\n", 2142917a9c9Sschwartz iset.user_version, iset.flags); 2157a364d25Sschwartz 2162917a9c9Sschwartz result = ENOTSUP; 2172917a9c9Sschwartz if ((iset.user_version >= PCITOOL_V2) && 21809b1eac2SEvan Yan (iset.flags & PCITOOL_INTR_FLAG_SET_GROUP)) { 2192917a9c9Sschwartz ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_GRP_SET_CPU, 2202917a9c9Sschwartz &result); 2212917a9c9Sschwartz } else { 2222917a9c9Sschwartz ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU, 2232917a9c9Sschwartz &result); 2242917a9c9Sschwartz } 2252917a9c9Sschwartz 2267a364d25Sschwartz if (ret != PSM_SUCCESS) { 2277a364d25Sschwartz switch (result) { 2287a364d25Sschwartz case EIO: /* Error making the change */ 2297a364d25Sschwartz rval = EIO; 2307a364d25Sschwartz iset.status = PCITOOL_IO_ERROR; 2317a364d25Sschwartz break; 2327a364d25Sschwartz case ENXIO: /* Couldn't convert vector to irq */ 2337a364d25Sschwartz rval = EINVAL; 2347a364d25Sschwartz iset.status = PCITOOL_INVALID_INO; 2357a364d25Sschwartz break; 2367a364d25Sschwartz case EINVAL: /* CPU out of range */ 2377a364d25Sschwartz rval = EINVAL; 2387a364d25Sschwartz iset.status = PCITOOL_INVALID_CPUID; 2397a364d25Sschwartz break; 2402917a9c9Sschwartz case ENOTSUP: /* Requested PSM intr ops missing */ 2412917a9c9Sschwartz rval = ENOTSUP; 2422917a9c9Sschwartz iset.status = PCITOOL_IO_ERROR; 2432917a9c9Sschwartz break; 2447a364d25Sschwartz } 2457a364d25Sschwartz } 2467a364d25Sschwartz 2477a364d25Sschwartz /* Return original CPU. */ 2487a364d25Sschwartz iset.cpu_id = old_cpu; 2497a364d25Sschwartz 2507ff178cdSJimmy Vetayases /* Return new vector */ 2517ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) { 2527ff178cdSJimmy Vetayases iset.ino = APIX_VIRTVEC_VECTOR(info_hdl.ih_vector); 2537ff178cdSJimmy Vetayases } 2547ff178cdSJimmy Vetayases 2557a364d25Sschwartz done_set_intr: 2562917a9c9Sschwartz iset.drvr_version = PCITOOL_VERSION; 2572917a9c9Sschwartz if (ddi_copyout(&iset, arg, copyinout_size, mode) != DDI_SUCCESS) 2587a364d25Sschwartz rval = EFAULT; 2597a364d25Sschwartz return (rval); 2607a364d25Sschwartz } 2617a364d25Sschwartz 2627a364d25Sschwartz 2637a364d25Sschwartz /* It is assumed that dip != NULL */ 2647a364d25Sschwartz static void 2657a364d25Sschwartz pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs) 2667a364d25Sschwartz { 2677a364d25Sschwartz (void) strncpy(devs->driver_name, 268d5ace945SErwin T Tsaur ddi_driver_name(dip), MAXMODCONFNAME-2); 269d5ace945SErwin T Tsaur devs->driver_name[MAXMODCONFNAME-1] = '\0'; 2707a364d25Sschwartz (void) ddi_pathname(dip, devs->path); 2717a364d25Sschwartz devs->dev_inst = ddi_get_instance(dip); 2727a364d25Sschwartz } 2737a364d25Sschwartz 2747a364d25Sschwartz static int 2757a364d25Sschwartz pcitool_get_intr(dev_info_t *dip, void *arg, int mode) 2767a364d25Sschwartz { 2777a364d25Sschwartz /* Array part isn't used here, but oh well... */ 2787a364d25Sschwartz pcitool_intr_get_t partial_iget; 2797a364d25Sschwartz pcitool_intr_get_t *iget = &partial_iget; 2807a364d25Sschwartz size_t iget_kmem_alloc_size = 0; 2817a364d25Sschwartz uint8_t num_devs_ret; 2827a364d25Sschwartz int copyout_rval; 2837a364d25Sschwartz int rval = SUCCESS; 2847a364d25Sschwartz int circ; 2857a364d25Sschwartz int i; 2867a364d25Sschwartz 2877a364d25Sschwartz ddi_intr_handle_impl_t info_hdl; 2887a364d25Sschwartz apic_get_intr_t intr_info; 2897ff178cdSJimmy Vetayases apic_get_type_t type_info; 2907a364d25Sschwartz 2917a364d25Sschwartz /* Read in just the header part, no array section. */ 2927a364d25Sschwartz if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) != 2937a364d25Sschwartz DDI_SUCCESS) 2947a364d25Sschwartz return (EFAULT); 2957a364d25Sschwartz 29609b1eac2SEvan Yan if (partial_iget.flags & PCITOOL_INTR_FLAG_GET_MSI) { 29709b1eac2SEvan Yan partial_iget.status = PCITOOL_IO_ERROR; 29809b1eac2SEvan Yan partial_iget.num_devs_ret = 0; 29909b1eac2SEvan Yan rval = ENOTSUP; 30009b1eac2SEvan Yan goto done_get_intr; 30109b1eac2SEvan Yan } 30209b1eac2SEvan Yan 3037ff178cdSJimmy Vetayases info_hdl.ih_private = &type_info; 3047ff178cdSJimmy Vetayases 3057ff178cdSJimmy Vetayases if ((*psm_intr_ops)(NULL, &info_hdl, 3067ff178cdSJimmy Vetayases PSM_INTR_OP_APIC_TYPE, NULL) != PSM_SUCCESS) { 3077ff178cdSJimmy Vetayases iget->status = PCITOOL_IO_ERROR; 3087ff178cdSJimmy Vetayases iget->num_devs_ret = 0; 3097ff178cdSJimmy Vetayases rval = EINVAL; 3107ff178cdSJimmy Vetayases goto done_get_intr; 3117ff178cdSJimmy Vetayases } 3127ff178cdSJimmy Vetayases 3137ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) { 3147ff178cdSJimmy Vetayases if (partial_iget.cpu_id > type_info.avgi_num_cpu) { 3157ff178cdSJimmy Vetayases partial_iget.status = PCITOOL_INVALID_CPUID; 3167ff178cdSJimmy Vetayases partial_iget.num_devs_ret = 0; 3177ff178cdSJimmy Vetayases rval = EINVAL; 3187ff178cdSJimmy Vetayases goto done_get_intr; 3197ff178cdSJimmy Vetayases } 3207ff178cdSJimmy Vetayases } 3217ff178cdSJimmy Vetayases 3227a364d25Sschwartz /* Validate argument. */ 3237ff178cdSJimmy Vetayases if ((partial_iget.ino & APIX_VIRTVEC_VECMASK) > 3247ff178cdSJimmy Vetayases type_info.avgi_num_intr) { 3257a364d25Sschwartz partial_iget.status = PCITOOL_INVALID_INO; 3267a364d25Sschwartz partial_iget.num_devs_ret = 0; 3277a364d25Sschwartz rval = EINVAL; 3287a364d25Sschwartz goto done_get_intr; 3297a364d25Sschwartz } 3307a364d25Sschwartz 3317a364d25Sschwartz num_devs_ret = partial_iget.num_devs_ret; 3327a364d25Sschwartz intr_info.avgi_dip_list = NULL; 3337a364d25Sschwartz intr_info.avgi_req_flags = 3347a364d25Sschwartz PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC; 3357a364d25Sschwartz /* 3367a364d25Sschwartz * For this locally-declared and used handle, ih_private will contain a 3377a364d25Sschwartz * pointer to apic_get_intr_t, not an ihdl_plat_t as used for 3387a364d25Sschwartz * global interrupt handling. 3397a364d25Sschwartz */ 3407a364d25Sschwartz info_hdl.ih_private = &intr_info; 3417ff178cdSJimmy Vetayases 3427ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, APIC_APIX_NAME) == 0) { 3437ff178cdSJimmy Vetayases info_hdl.ih_vector = 3447ff178cdSJimmy Vetayases APIX_VIRTVECTOR(partial_iget.cpu_id, partial_iget.ino); 3457ff178cdSJimmy Vetayases } else { 3467a364d25Sschwartz info_hdl.ih_vector = partial_iget.ino; 3477ff178cdSJimmy Vetayases } 3487a364d25Sschwartz 3497a364d25Sschwartz /* Caller wants device information returned. */ 3507a364d25Sschwartz if (num_devs_ret > 0) { 3517a364d25Sschwartz 3527a364d25Sschwartz intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS; 3537a364d25Sschwartz 3547a364d25Sschwartz /* 3557a364d25Sschwartz * Allocate room. 3567a364d25Sschwartz * If num_devs_ret == 0 iget remains pointing to partial_iget. 3577a364d25Sschwartz */ 3587a364d25Sschwartz iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret); 3597a364d25Sschwartz iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP); 3607a364d25Sschwartz 3617a364d25Sschwartz /* Read in whole structure to verify there's room. */ 3627a364d25Sschwartz if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) != 3637a364d25Sschwartz SUCCESS) { 3647a364d25Sschwartz 3657a364d25Sschwartz /* Be consistent and just return EFAULT here. */ 3667a364d25Sschwartz kmem_free(iget, iget_kmem_alloc_size); 3677a364d25Sschwartz 3687a364d25Sschwartz return (EFAULT); 3697a364d25Sschwartz } 3707a364d25Sschwartz } 3717a364d25Sschwartz 3727a364d25Sschwartz bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret)); 3737a364d25Sschwartz iget->ino = info_hdl.ih_vector; 3747a364d25Sschwartz 3757a364d25Sschwartz /* 3767a364d25Sschwartz * Lock device tree branch from the pci root nexus on down if info will 3777a364d25Sschwartz * be extracted from dips returned from the tree. 3787a364d25Sschwartz */ 3797a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 3807a364d25Sschwartz ndi_devi_enter(dip, &circ); 3817a364d25Sschwartz } 3827a364d25Sschwartz 3837a364d25Sschwartz /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */ 3847a364d25Sschwartz if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 3857a364d25Sschwartz PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) { 3867a364d25Sschwartz iget->status = PCITOOL_IO_ERROR; 3877a364d25Sschwartz iget->num_devs_ret = 0; 3887a364d25Sschwartz rval = EINVAL; 3897a364d25Sschwartz goto done_get_intr; 3907a364d25Sschwartz } 3917a364d25Sschwartz 3927a364d25Sschwartz /* 3937a364d25Sschwartz * Fill in the pcitool_intr_get_t to be returned, 3947a364d25Sschwartz * with the CPU, num_devs_ret and num_devs. 3957a364d25Sschwartz */ 3964e30c628SEvan Yan if (intr_info.avgi_cpu_id == IRQ_UNBOUND || 3974e30c628SEvan Yan intr_info.avgi_cpu_id == IRQ_UNINIT) 3984e30c628SEvan Yan iget->cpu_id = 0; 3994e30c628SEvan Yan else 4007a364d25Sschwartz iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND; 4017a364d25Sschwartz 4027a364d25Sschwartz /* Number of devices returned by apic. */ 4037a364d25Sschwartz iget->num_devs = intr_info.avgi_num_devs; 4047a364d25Sschwartz 4057a364d25Sschwartz /* Device info was returned. */ 4067a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 4077a364d25Sschwartz 4087a364d25Sschwartz /* 4097a364d25Sschwartz * num devs returned is num devs ret by apic, 4107a364d25Sschwartz * space permitting. 4117a364d25Sschwartz */ 4127a364d25Sschwartz iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs); 4137a364d25Sschwartz 4147a364d25Sschwartz /* 4157a364d25Sschwartz * Loop thru list of dips and extract driver, name and instance. 4167a364d25Sschwartz * Fill in the pcitool_intr_dev_t's with this info. 4177a364d25Sschwartz */ 4187a364d25Sschwartz for (i = 0; i < iget->num_devs_ret; i++) 4197a364d25Sschwartz pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i], 4207a364d25Sschwartz &iget->dev[i]); 4217a364d25Sschwartz 4227a364d25Sschwartz /* Free kmem_alloc'ed memory of the apic_get_intr_t */ 4237a364d25Sschwartz kmem_free(intr_info.avgi_dip_list, 4247a364d25Sschwartz intr_info.avgi_num_devs * sizeof (dev_info_t *)); 4257a364d25Sschwartz } 4267a364d25Sschwartz 4277a364d25Sschwartz done_get_intr: 4287a364d25Sschwartz 4297a364d25Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 4307a364d25Sschwartz ndi_devi_exit(dip, circ); 4317a364d25Sschwartz } 4327a364d25Sschwartz 4332917a9c9Sschwartz iget->drvr_version = PCITOOL_VERSION; 4347a364d25Sschwartz copyout_rval = ddi_copyout(iget, arg, 4357a364d25Sschwartz PCITOOL_IGET_SIZE(num_devs_ret), mode); 4367a364d25Sschwartz 4377a364d25Sschwartz if (iget_kmem_alloc_size > 0) 4387a364d25Sschwartz kmem_free(iget, iget_kmem_alloc_size); 4397a364d25Sschwartz 4407a364d25Sschwartz if (copyout_rval != DDI_SUCCESS) 4417a364d25Sschwartz rval = EFAULT; 4427a364d25Sschwartz 4437a364d25Sschwartz return (rval); 4447a364d25Sschwartz } 4457a364d25Sschwartz 4462917a9c9Sschwartz /*ARGSUSED*/ 4472917a9c9Sschwartz static int 4482917a9c9Sschwartz pcitool_intr_info(dev_info_t *dip, void *arg, int mode) 4492917a9c9Sschwartz { 4502917a9c9Sschwartz pcitool_intr_info_t intr_info; 4512917a9c9Sschwartz ddi_intr_handle_impl_t info_hdl; 4522917a9c9Sschwartz int rval = SUCCESS; 4537ff178cdSJimmy Vetayases apic_get_type_t type_info; 4542917a9c9Sschwartz 4552917a9c9Sschwartz /* If we need user_version, and to ret same user version as passed in */ 4562917a9c9Sschwartz if (ddi_copyin(arg, &intr_info, sizeof (pcitool_intr_info_t), mode) != 4572917a9c9Sschwartz DDI_SUCCESS) { 4582917a9c9Sschwartz if (pcitool_debug) 4592917a9c9Sschwartz prom_printf("Error reading arguments\n"); 4602917a9c9Sschwartz return (EFAULT); 4612917a9c9Sschwartz } 4622917a9c9Sschwartz 46309b1eac2SEvan Yan if (intr_info.flags & PCITOOL_INTR_FLAG_GET_MSI) 46409b1eac2SEvan Yan return (ENOTSUP); 46509b1eac2SEvan Yan 4667ff178cdSJimmy Vetayases info_hdl.ih_private = &type_info; 4677ff178cdSJimmy Vetayases 4682917a9c9Sschwartz /* For UPPC systems, psm_intr_ops has no entry for APIC_TYPE. */ 4692917a9c9Sschwartz if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 4702917a9c9Sschwartz PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) { 4712917a9c9Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UPPC; 4722917a9c9Sschwartz intr_info.ctlr_version = 0; 4737ff178cdSJimmy Vetayases intr_info.num_intr = APIC_MAX_VECTOR; 4742917a9c9Sschwartz } else { 4752917a9c9Sschwartz intr_info.ctlr_version = (uint32_t)info_hdl.ih_ver; 4767ff178cdSJimmy Vetayases intr_info.num_cpu = type_info.avgi_num_cpu; 4777ff178cdSJimmy Vetayases if (strcmp(type_info.avgi_type, 4787ff178cdSJimmy Vetayases APIC_PCPLUSMP_NAME) == 0) { 4792917a9c9Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_PCPLUSMP; 4807ff178cdSJimmy Vetayases intr_info.num_intr = type_info.avgi_num_intr; 4817ff178cdSJimmy Vetayases } else if (strcmp(type_info.avgi_type, 4827ff178cdSJimmy Vetayases APIC_APIX_NAME) == 0) { 4837ff178cdSJimmy Vetayases intr_info.ctlr_type = PCITOOL_CTLR_TYPE_APIX; 4847ff178cdSJimmy Vetayases intr_info.num_intr = type_info.avgi_num_intr; 4857ff178cdSJimmy Vetayases } else { 4862917a9c9Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UNKNOWN; 4877ff178cdSJimmy Vetayases intr_info.num_intr = APIC_MAX_VECTOR; 4887ff178cdSJimmy Vetayases } 4892917a9c9Sschwartz } 4902917a9c9Sschwartz 4912917a9c9Sschwartz intr_info.drvr_version = PCITOOL_VERSION; 4922917a9c9Sschwartz if (ddi_copyout(&intr_info, arg, sizeof (pcitool_intr_info_t), mode) != 4932917a9c9Sschwartz DDI_SUCCESS) { 4942917a9c9Sschwartz if (pcitool_debug) 4952917a9c9Sschwartz prom_printf("Error returning arguments.\n"); 4962917a9c9Sschwartz rval = EFAULT; 4972917a9c9Sschwartz } 4982917a9c9Sschwartz 4992917a9c9Sschwartz return (rval); 5002917a9c9Sschwartz } 5012917a9c9Sschwartz 5022917a9c9Sschwartz 5037a364d25Sschwartz 5047a364d25Sschwartz /* 5057a364d25Sschwartz * Main function for handling interrupt CPU binding requests and queries. 5067a364d25Sschwartz * Need to implement later 5077a364d25Sschwartz */ 5087a364d25Sschwartz int 5097a364d25Sschwartz pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 5107a364d25Sschwartz { 5117a364d25Sschwartz int rval; 5127a364d25Sschwartz 5137a364d25Sschwartz switch (cmd) { 5147a364d25Sschwartz 5157a364d25Sschwartz /* Associate a new CPU with a given vector */ 5167a364d25Sschwartz case PCITOOL_DEVICE_SET_INTR: 5177a364d25Sschwartz rval = pcitool_set_intr(dip, arg, mode); 5187a364d25Sschwartz break; 5197a364d25Sschwartz 5207a364d25Sschwartz case PCITOOL_DEVICE_GET_INTR: 5217a364d25Sschwartz rval = pcitool_get_intr(dip, arg, mode); 5227a364d25Sschwartz break; 5237a364d25Sschwartz 5242917a9c9Sschwartz case PCITOOL_SYSTEM_INTR_INFO: 5252917a9c9Sschwartz rval = pcitool_intr_info(dip, arg, mode); 5267a364d25Sschwartz break; 5277a364d25Sschwartz 5287a364d25Sschwartz default: 5297a364d25Sschwartz rval = ENOTSUP; 5307a364d25Sschwartz } 5317a364d25Sschwartz 5327a364d25Sschwartz return (rval); 5337a364d25Sschwartz } 5347a364d25Sschwartz 5357c478bd9Sstevel@tonic-gate /* 5367c478bd9Sstevel@tonic-gate * Perform register accesses on the nexus device itself. 5377c478bd9Sstevel@tonic-gate * No explicit PCI nexus device for X86, so not applicable. 5387c478bd9Sstevel@tonic-gate */ 5397a364d25Sschwartz 5407c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 5417c478bd9Sstevel@tonic-gate int 542d4476ccbSschwartz pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 5437c478bd9Sstevel@tonic-gate { 5447c478bd9Sstevel@tonic-gate return (ENOTSUP); 5457c478bd9Sstevel@tonic-gate } 5467c478bd9Sstevel@tonic-gate 5477c478bd9Sstevel@tonic-gate /* Swap endianness. */ 5487c478bd9Sstevel@tonic-gate static uint64_t 5497c478bd9Sstevel@tonic-gate pcitool_swap_endian(uint64_t data, int size) 5507c478bd9Sstevel@tonic-gate { 5517c478bd9Sstevel@tonic-gate typedef union { 5527c478bd9Sstevel@tonic-gate uint64_t data64; 5537c478bd9Sstevel@tonic-gate uint8_t data8[8]; 5547c478bd9Sstevel@tonic-gate } data_split_t; 5557c478bd9Sstevel@tonic-gate 5567c478bd9Sstevel@tonic-gate data_split_t orig_data; 5577c478bd9Sstevel@tonic-gate data_split_t returned_data; 5587c478bd9Sstevel@tonic-gate int i; 5597c478bd9Sstevel@tonic-gate 5607c478bd9Sstevel@tonic-gate orig_data.data64 = data; 5617c478bd9Sstevel@tonic-gate returned_data.data64 = 0; 5627c478bd9Sstevel@tonic-gate 5637c478bd9Sstevel@tonic-gate for (i = 0; i < size; i++) { 5647c478bd9Sstevel@tonic-gate returned_data.data8[i] = orig_data.data8[size - 1 - i]; 5657c478bd9Sstevel@tonic-gate } 5667c478bd9Sstevel@tonic-gate 5677c478bd9Sstevel@tonic-gate return (returned_data.data64); 5687c478bd9Sstevel@tonic-gate } 5697c478bd9Sstevel@tonic-gate 570d4476ccbSschwartz /* 571c0da6274SZhi-Jun Robin Fu * A note about ontrap handling: 572d4476ccbSschwartz * 573c0da6274SZhi-Jun Robin Fu * X86 systems on which this module was tested return FFs instead of bus errors 574c0da6274SZhi-Jun Robin Fu * when accessing devices with invalid addresses. Ontrap handling, which 575c0da6274SZhi-Jun Robin Fu * gracefully handles kernel bus errors, is installed anyway for I/O and mem 576c0da6274SZhi-Jun Robin Fu * space accessing (not for pci config space), in case future X86 platforms 577c0da6274SZhi-Jun Robin Fu * require it. 578d4476ccbSschwartz */ 579d4476ccbSschwartz 5807c478bd9Sstevel@tonic-gate /* Access device. prg is modified. */ 5817c478bd9Sstevel@tonic-gate static int 582c0da6274SZhi-Jun Robin Fu pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 583c0da6274SZhi-Jun Robin Fu boolean_t io_access) 5847c478bd9Sstevel@tonic-gate { 5857c478bd9Sstevel@tonic-gate int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 5867c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 5877c478bd9Sstevel@tonic-gate int rval = SUCCESS; 5887c478bd9Sstevel@tonic-gate uint64_t local_data; 589c0da6274SZhi-Jun Robin Fu pci_cfgacc_req_t req; 590c0da6274SZhi-Jun Robin Fu uint32_t max_offset; 591c0da6274SZhi-Jun Robin Fu 592*de710d24SJosef 'Jeff' Sipek if ((size <= 0) || (size > 8) || !ISP2(size)) { 593c0da6274SZhi-Jun Robin Fu prg->status = PCITOOL_INVALID_SIZE; 594c0da6274SZhi-Jun Robin Fu return (ENOTSUP); 595c0da6274SZhi-Jun Robin Fu } 5967c478bd9Sstevel@tonic-gate 5977c478bd9Sstevel@tonic-gate /* 5985c59319bSDan Mick * NOTE: there is no way to verify whether or not the address is 5995c59319bSDan Mick * valid other than that it is within the maximum offset. The 600c0da6274SZhi-Jun Robin Fu * put functions return void and the get functions return -1 on error. 6017c478bd9Sstevel@tonic-gate */ 6025c59319bSDan Mick 603c0da6274SZhi-Jun Robin Fu if (io_access) 604c0da6274SZhi-Jun Robin Fu max_offset = 0xFF; 605c0da6274SZhi-Jun Robin Fu else 606c0da6274SZhi-Jun Robin Fu max_offset = 0xFFF; 607c0da6274SZhi-Jun Robin Fu if (prg->offset + size - 1 > max_offset) { 6085c59319bSDan Mick prg->status = PCITOOL_INVALID_ADDRESS; 6095c59319bSDan Mick return (ENOTSUP); 6105c59319bSDan Mick } 6115c59319bSDan Mick 6127c478bd9Sstevel@tonic-gate prg->status = PCITOOL_SUCCESS; 6137c478bd9Sstevel@tonic-gate 614c0da6274SZhi-Jun Robin Fu req.rcdip = NULL; 615c0da6274SZhi-Jun Robin Fu req.bdf = PCI_GETBDF(prg->bus_no, prg->dev_no, prg->func_no); 616c0da6274SZhi-Jun Robin Fu req.offset = prg->offset; 617c0da6274SZhi-Jun Robin Fu req.size = size; 618c0da6274SZhi-Jun Robin Fu req.write = write_flag; 619c0da6274SZhi-Jun Robin Fu req.ioacc = io_access; 6207c478bd9Sstevel@tonic-gate if (write_flag) { 6217c478bd9Sstevel@tonic-gate if (big_endian) { 6227c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 6237c478bd9Sstevel@tonic-gate } else { 6247c478bd9Sstevel@tonic-gate local_data = prg->data; 6257c478bd9Sstevel@tonic-gate } 626c0da6274SZhi-Jun Robin Fu VAL64(&req) = local_data; 627c0da6274SZhi-Jun Robin Fu pci_cfgacc_acc(&req); 6287c478bd9Sstevel@tonic-gate } else { 629c0da6274SZhi-Jun Robin Fu pci_cfgacc_acc(&req); 6308d7fafffSZhi-Jun Robin Fu switch (size) { 6318d7fafffSZhi-Jun Robin Fu case 1: 6328d7fafffSZhi-Jun Robin Fu local_data = VAL8(&req); 6338d7fafffSZhi-Jun Robin Fu break; 6348d7fafffSZhi-Jun Robin Fu case 2: 6358d7fafffSZhi-Jun Robin Fu local_data = VAL16(&req); 6368d7fafffSZhi-Jun Robin Fu break; 6378d7fafffSZhi-Jun Robin Fu case 4: 6388d7fafffSZhi-Jun Robin Fu local_data = VAL32(&req); 6398d7fafffSZhi-Jun Robin Fu break; 6408d7fafffSZhi-Jun Robin Fu case 8: 641c0da6274SZhi-Jun Robin Fu local_data = VAL64(&req); 6428d7fafffSZhi-Jun Robin Fu break; 6438d7fafffSZhi-Jun Robin Fu } 6447c478bd9Sstevel@tonic-gate if (big_endian) { 6457c478bd9Sstevel@tonic-gate prg->data = 6467c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 6477c478bd9Sstevel@tonic-gate } else { 6487c478bd9Sstevel@tonic-gate prg->data = local_data; 6497c478bd9Sstevel@tonic-gate } 6507c478bd9Sstevel@tonic-gate } 651c0da6274SZhi-Jun Robin Fu /* 652c0da6274SZhi-Jun Robin Fu * Check if legacy IO config access is used, in which case 653c0da6274SZhi-Jun Robin Fu * only first 256 bytes are valid. 654c0da6274SZhi-Jun Robin Fu */ 655c0da6274SZhi-Jun Robin Fu if (req.ioacc && (prg->offset + size - 1 > 0xFF)) { 656c0da6274SZhi-Jun Robin Fu prg->status = PCITOOL_INVALID_ADDRESS; 657c0da6274SZhi-Jun Robin Fu return (ENOTSUP); 6587c478bd9Sstevel@tonic-gate } 659c0da6274SZhi-Jun Robin Fu 660c0da6274SZhi-Jun Robin Fu /* Set phys_addr only if MMIO is used */ 661c0da6274SZhi-Jun Robin Fu prg->phys_addr = 0; 662c0da6274SZhi-Jun Robin Fu if (!req.ioacc && mcfg_mem_base != 0) { 663c0da6274SZhi-Jun Robin Fu prg->phys_addr = mcfg_mem_base + prg->offset + 664c0da6274SZhi-Jun Robin Fu ((prg->bus_no << PCIEX_REG_BUS_SHIFT) | 665c0da6274SZhi-Jun Robin Fu (prg->dev_no << PCIEX_REG_DEV_SHIFT) | 666c0da6274SZhi-Jun Robin Fu (prg->func_no << PCIEX_REG_FUNC_SHIFT)); 667c0da6274SZhi-Jun Robin Fu } 668c0da6274SZhi-Jun Robin Fu 6697c478bd9Sstevel@tonic-gate return (rval); 6707c478bd9Sstevel@tonic-gate } 6717c478bd9Sstevel@tonic-gate 6727c478bd9Sstevel@tonic-gate static int 673c0da6274SZhi-Jun Robin Fu pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag) 6747c478bd9Sstevel@tonic-gate { 6757c478bd9Sstevel@tonic-gate int port = (int)prg->phys_addr; 6767c478bd9Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 6777c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 6787c478bd9Sstevel@tonic-gate int rval = SUCCESS; 6797c478bd9Sstevel@tonic-gate on_trap_data_t otd; 6807c478bd9Sstevel@tonic-gate uint64_t local_data; 6817c478bd9Sstevel@tonic-gate 6827c478bd9Sstevel@tonic-gate 6837c478bd9Sstevel@tonic-gate /* 6847c478bd9Sstevel@tonic-gate * on_trap works like setjmp. 6857c478bd9Sstevel@tonic-gate * 6867c478bd9Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 6877c478bd9Sstevel@tonic-gate * 6887c478bd9Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 6897c478bd9Sstevel@tonic-gate */ 6907c478bd9Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 6917c478bd9Sstevel@tonic-gate no_trap(); 6927c478bd9Sstevel@tonic-gate if (pcitool_debug) 6937c478bd9Sstevel@tonic-gate prom_printf( 6942917a9c9Sschwartz "pcitool_io_access: on_trap caught an error...\n"); 6957c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 6967c478bd9Sstevel@tonic-gate return (EFAULT); 6977c478bd9Sstevel@tonic-gate } 6987c478bd9Sstevel@tonic-gate 6997c478bd9Sstevel@tonic-gate if (write_flag) { 7007c478bd9Sstevel@tonic-gate 7017c478bd9Sstevel@tonic-gate if (big_endian) { 7027c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 7037c478bd9Sstevel@tonic-gate } else { 7047c478bd9Sstevel@tonic-gate local_data = prg->data; 7057c478bd9Sstevel@tonic-gate } 7067c478bd9Sstevel@tonic-gate 7077c478bd9Sstevel@tonic-gate if (pcitool_debug) 7087c478bd9Sstevel@tonic-gate prom_printf("Writing %ld byte(s) to port 0x%x\n", 7097c478bd9Sstevel@tonic-gate size, port); 7107c478bd9Sstevel@tonic-gate 7117c478bd9Sstevel@tonic-gate switch (size) { 7127c478bd9Sstevel@tonic-gate case 1: 7137c478bd9Sstevel@tonic-gate outb(port, (uint8_t)local_data); 7147c478bd9Sstevel@tonic-gate break; 7157c478bd9Sstevel@tonic-gate case 2: 7167c478bd9Sstevel@tonic-gate outw(port, (uint16_t)local_data); 7177c478bd9Sstevel@tonic-gate break; 7187c478bd9Sstevel@tonic-gate case 4: 7197c478bd9Sstevel@tonic-gate outl(port, (uint32_t)local_data); 7207c478bd9Sstevel@tonic-gate break; 7217c478bd9Sstevel@tonic-gate default: 7227c478bd9Sstevel@tonic-gate rval = ENOTSUP; 7237c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 7247c478bd9Sstevel@tonic-gate break; 7257c478bd9Sstevel@tonic-gate } 7267c478bd9Sstevel@tonic-gate } else { 7277c478bd9Sstevel@tonic-gate if (pcitool_debug) 7287c478bd9Sstevel@tonic-gate prom_printf("Reading %ld byte(s) from port 0x%x\n", 7297c478bd9Sstevel@tonic-gate size, port); 7307c478bd9Sstevel@tonic-gate 7317c478bd9Sstevel@tonic-gate switch (size) { 7327c478bd9Sstevel@tonic-gate case 1: 7337c478bd9Sstevel@tonic-gate local_data = inb(port); 7347c478bd9Sstevel@tonic-gate break; 7357c478bd9Sstevel@tonic-gate case 2: 7367c478bd9Sstevel@tonic-gate local_data = inw(port); 7377c478bd9Sstevel@tonic-gate break; 7387c478bd9Sstevel@tonic-gate case 4: 7397c478bd9Sstevel@tonic-gate local_data = inl(port); 7407c478bd9Sstevel@tonic-gate break; 7417c478bd9Sstevel@tonic-gate default: 7427c478bd9Sstevel@tonic-gate rval = ENOTSUP; 7437c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 7447c478bd9Sstevel@tonic-gate break; 7457c478bd9Sstevel@tonic-gate } 7467c478bd9Sstevel@tonic-gate 7477c478bd9Sstevel@tonic-gate if (rval == SUCCESS) { 7487c478bd9Sstevel@tonic-gate if (big_endian) { 7497c478bd9Sstevel@tonic-gate prg->data = 7507c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 7517c478bd9Sstevel@tonic-gate } else { 7527c478bd9Sstevel@tonic-gate prg->data = local_data; 7537c478bd9Sstevel@tonic-gate } 7547c478bd9Sstevel@tonic-gate } 7557c478bd9Sstevel@tonic-gate } 7567c478bd9Sstevel@tonic-gate 7577c478bd9Sstevel@tonic-gate no_trap(); 7587c478bd9Sstevel@tonic-gate return (rval); 7597c478bd9Sstevel@tonic-gate } 7607c478bd9Sstevel@tonic-gate 7617c478bd9Sstevel@tonic-gate static int 762c0da6274SZhi-Jun Robin Fu pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, boolean_t write_flag) 7637c478bd9Sstevel@tonic-gate { 7647c478bd9Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 7657c478bd9Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 7667c478bd9Sstevel@tonic-gate int rval = DDI_SUCCESS; 7677c478bd9Sstevel@tonic-gate on_trap_data_t otd; 7687c478bd9Sstevel@tonic-gate uint64_t local_data; 7697c478bd9Sstevel@tonic-gate 7707c478bd9Sstevel@tonic-gate /* 7717c478bd9Sstevel@tonic-gate * on_trap works like setjmp. 7727c478bd9Sstevel@tonic-gate * 7737c478bd9Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 7747c478bd9Sstevel@tonic-gate * 7757c478bd9Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 7767c478bd9Sstevel@tonic-gate */ 7777c478bd9Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 7787c478bd9Sstevel@tonic-gate no_trap(); 7797c478bd9Sstevel@tonic-gate if (pcitool_debug) 7807c478bd9Sstevel@tonic-gate prom_printf( 7817c478bd9Sstevel@tonic-gate "pcitool_mem_access: on_trap caught an error...\n"); 7827c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 7837c478bd9Sstevel@tonic-gate return (EFAULT); 7847c478bd9Sstevel@tonic-gate } 7857c478bd9Sstevel@tonic-gate 7867c478bd9Sstevel@tonic-gate if (write_flag) { 7877c478bd9Sstevel@tonic-gate 7887c478bd9Sstevel@tonic-gate if (big_endian) { 7897c478bd9Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 7907c478bd9Sstevel@tonic-gate } else { 7917c478bd9Sstevel@tonic-gate local_data = prg->data; 7927c478bd9Sstevel@tonic-gate } 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate switch (size) { 7957c478bd9Sstevel@tonic-gate case 1: 7967c478bd9Sstevel@tonic-gate *((uint8_t *)(uintptr_t)virt_addr) = local_data; 7977c478bd9Sstevel@tonic-gate break; 7987c478bd9Sstevel@tonic-gate case 2: 7997c478bd9Sstevel@tonic-gate *((uint16_t *)(uintptr_t)virt_addr) = local_data; 8007c478bd9Sstevel@tonic-gate break; 8017c478bd9Sstevel@tonic-gate case 4: 8027c478bd9Sstevel@tonic-gate *((uint32_t *)(uintptr_t)virt_addr) = local_data; 8037c478bd9Sstevel@tonic-gate break; 8047c478bd9Sstevel@tonic-gate case 8: 8057c478bd9Sstevel@tonic-gate *((uint64_t *)(uintptr_t)virt_addr) = local_data; 8067c478bd9Sstevel@tonic-gate break; 8077c478bd9Sstevel@tonic-gate default: 8087c478bd9Sstevel@tonic-gate rval = ENOTSUP; 8097c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 8107c478bd9Sstevel@tonic-gate break; 8117c478bd9Sstevel@tonic-gate } 8127c478bd9Sstevel@tonic-gate } else { 8137c478bd9Sstevel@tonic-gate switch (size) { 8147c478bd9Sstevel@tonic-gate case 1: 8157c478bd9Sstevel@tonic-gate local_data = *((uint8_t *)(uintptr_t)virt_addr); 8167c478bd9Sstevel@tonic-gate break; 8177c478bd9Sstevel@tonic-gate case 2: 8187c478bd9Sstevel@tonic-gate local_data = *((uint16_t *)(uintptr_t)virt_addr); 8197c478bd9Sstevel@tonic-gate break; 8207c478bd9Sstevel@tonic-gate case 4: 8217c478bd9Sstevel@tonic-gate local_data = *((uint32_t *)(uintptr_t)virt_addr); 8227c478bd9Sstevel@tonic-gate break; 8237c478bd9Sstevel@tonic-gate case 8: 8247c478bd9Sstevel@tonic-gate local_data = *((uint64_t *)(uintptr_t)virt_addr); 8257c478bd9Sstevel@tonic-gate break; 8267c478bd9Sstevel@tonic-gate default: 8277c478bd9Sstevel@tonic-gate rval = ENOTSUP; 8287c478bd9Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 8297c478bd9Sstevel@tonic-gate break; 8307c478bd9Sstevel@tonic-gate } 8317c478bd9Sstevel@tonic-gate 8327c478bd9Sstevel@tonic-gate if (rval == SUCCESS) { 8337c478bd9Sstevel@tonic-gate if (big_endian) { 8347c478bd9Sstevel@tonic-gate prg->data = 8357c478bd9Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 8367c478bd9Sstevel@tonic-gate } else { 8377c478bd9Sstevel@tonic-gate prg->data = local_data; 8387c478bd9Sstevel@tonic-gate } 8397c478bd9Sstevel@tonic-gate } 8407c478bd9Sstevel@tonic-gate } 8417c478bd9Sstevel@tonic-gate 8427c478bd9Sstevel@tonic-gate no_trap(); 8437c478bd9Sstevel@tonic-gate return (rval); 8447c478bd9Sstevel@tonic-gate } 8457c478bd9Sstevel@tonic-gate 8467c478bd9Sstevel@tonic-gate /* 8477c478bd9Sstevel@tonic-gate * Map up to 2 pages which contain the address we want to access. 8487c478bd9Sstevel@tonic-gate * 8497c478bd9Sstevel@tonic-gate * Mapping should span no more than 8 bytes. With X86 it is possible for an 8507c478bd9Sstevel@tonic-gate * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary. 8517c478bd9Sstevel@tonic-gate * We'll never have to map more than two pages. 8527c478bd9Sstevel@tonic-gate */ 8537c478bd9Sstevel@tonic-gate 8547c478bd9Sstevel@tonic-gate static uint64_t 8557c478bd9Sstevel@tonic-gate pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages) 8567c478bd9Sstevel@tonic-gate { 8577c478bd9Sstevel@tonic-gate 8587c478bd9Sstevel@tonic-gate uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET; 8597c478bd9Sstevel@tonic-gate uint64_t offset = phys_addr & MMU_PAGEOFFSET; 8607c478bd9Sstevel@tonic-gate void *virt_base; 8617c478bd9Sstevel@tonic-gate uint64_t returned_addr; 862ae115bc7Smrj pfn_t pfn; 8637c478bd9Sstevel@tonic-gate 8647c478bd9Sstevel@tonic-gate if (pcitool_debug) 8657c478bd9Sstevel@tonic-gate prom_printf("pcitool_map: Called with PA:0x%p\n", 8668793b36bSNick Todd (void *)(uintptr_t)phys_addr); 8677c478bd9Sstevel@tonic-gate 8687c478bd9Sstevel@tonic-gate *num_pages = 1; 8697c478bd9Sstevel@tonic-gate 8707c478bd9Sstevel@tonic-gate /* Desired mapping would span more than two pages. */ 8717c478bd9Sstevel@tonic-gate if ((offset + size) > (MMU_PAGESIZE * 2)) { 8727c478bd9Sstevel@tonic-gate if (pcitool_debug) 8737c478bd9Sstevel@tonic-gate prom_printf("boundary violation: " 874d4476ccbSschwartz "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n", 875d4476ccbSschwartz offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE); 8767c478bd9Sstevel@tonic-gate return (NULL); 8777c478bd9Sstevel@tonic-gate 8787c478bd9Sstevel@tonic-gate } else if ((offset + size) > MMU_PAGESIZE) { 8797c478bd9Sstevel@tonic-gate (*num_pages)++; 8807c478bd9Sstevel@tonic-gate } 8817c478bd9Sstevel@tonic-gate 8827c478bd9Sstevel@tonic-gate /* Get page(s) of virtual space. */ 8837c478bd9Sstevel@tonic-gate virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP); 8847c478bd9Sstevel@tonic-gate if (virt_base == NULL) { 8857c478bd9Sstevel@tonic-gate if (pcitool_debug) 8867c478bd9Sstevel@tonic-gate prom_printf("Couldn't get virtual base address.\n"); 8877c478bd9Sstevel@tonic-gate return (NULL); 8887c478bd9Sstevel@tonic-gate } 8897c478bd9Sstevel@tonic-gate 8907c478bd9Sstevel@tonic-gate if (pcitool_debug) 8917c478bd9Sstevel@tonic-gate prom_printf("Got base virtual address:0x%p\n", virt_base); 8927c478bd9Sstevel@tonic-gate 893843e1988Sjohnlev #ifdef __xpv 894843e1988Sjohnlev /* 895843e1988Sjohnlev * We should only get here if we are dom0. 896843e1988Sjohnlev * We're using a real device so we need to translate the MA to a PFN. 897843e1988Sjohnlev */ 898843e1988Sjohnlev ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 899843e1988Sjohnlev pfn = xen_assign_pfn(mmu_btop(page_base)); 900843e1988Sjohnlev #else 901ae115bc7Smrj pfn = btop(page_base); 902843e1988Sjohnlev #endif 903ae115bc7Smrj 9047c478bd9Sstevel@tonic-gate /* Now map the allocated virtual space to the physical address. */ 905ae115bc7Smrj hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), pfn, 906ae115bc7Smrj PROT_READ | PROT_WRITE | HAT_STRICTORDER, 9077c478bd9Sstevel@tonic-gate HAT_LOAD_LOCK); 9087c478bd9Sstevel@tonic-gate 9097c478bd9Sstevel@tonic-gate returned_addr = ((uintptr_t)(virt_base)) + offset; 9107c478bd9Sstevel@tonic-gate 9117c478bd9Sstevel@tonic-gate if (pcitool_debug) 9127c478bd9Sstevel@tonic-gate prom_printf("pcitool_map: returning VA:0x%p\n", 9137c478bd9Sstevel@tonic-gate (void *)(uintptr_t)returned_addr); 9147c478bd9Sstevel@tonic-gate 9157c478bd9Sstevel@tonic-gate return (returned_addr); 9167c478bd9Sstevel@tonic-gate } 9177c478bd9Sstevel@tonic-gate 9187c478bd9Sstevel@tonic-gate /* Unmap the mapped page(s). */ 9197c478bd9Sstevel@tonic-gate static void 9207c478bd9Sstevel@tonic-gate pcitool_unmap(uint64_t virt_addr, size_t num_pages) 9217c478bd9Sstevel@tonic-gate { 9227c478bd9Sstevel@tonic-gate void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET); 9237c478bd9Sstevel@tonic-gate 9247c478bd9Sstevel@tonic-gate hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages), 9257c478bd9Sstevel@tonic-gate HAT_UNLOAD_UNLOCK); 9267c478bd9Sstevel@tonic-gate vmem_free(heap_arena, base_virt_addr, ptob(num_pages)); 9277c478bd9Sstevel@tonic-gate } 9287c478bd9Sstevel@tonic-gate 9297c478bd9Sstevel@tonic-gate 9307c478bd9Sstevel@tonic-gate /* Perform register accesses on PCI leaf devices. */ 931c0da6274SZhi-Jun Robin Fu /*ARGSUSED*/ 9327c478bd9Sstevel@tonic-gate int 933d4476ccbSschwartz pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 9347c478bd9Sstevel@tonic-gate { 9357c478bd9Sstevel@tonic-gate boolean_t write_flag = B_FALSE; 936c0da6274SZhi-Jun Robin Fu boolean_t io_access = B_TRUE; 9377c478bd9Sstevel@tonic-gate int rval = 0; 9387c478bd9Sstevel@tonic-gate pcitool_reg_t prg; 9397c478bd9Sstevel@tonic-gate uint8_t size; 9407c478bd9Sstevel@tonic-gate 9417c478bd9Sstevel@tonic-gate uint64_t base_addr; 9427c478bd9Sstevel@tonic-gate uint64_t virt_addr; 9437c478bd9Sstevel@tonic-gate size_t num_virt_pages; 9447c478bd9Sstevel@tonic-gate 9457c478bd9Sstevel@tonic-gate switch (cmd) { 9467c478bd9Sstevel@tonic-gate case (PCITOOL_DEVICE_SET_REG): 9477c478bd9Sstevel@tonic-gate write_flag = B_TRUE; 9487c478bd9Sstevel@tonic-gate 9497c478bd9Sstevel@tonic-gate /*FALLTHRU*/ 9507c478bd9Sstevel@tonic-gate case (PCITOOL_DEVICE_GET_REG): 9517c478bd9Sstevel@tonic-gate if (pcitool_debug) 9527c478bd9Sstevel@tonic-gate prom_printf("pci_dev_reg_ops set/get reg\n"); 9537c478bd9Sstevel@tonic-gate if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) != 9547c478bd9Sstevel@tonic-gate DDI_SUCCESS) { 9557c478bd9Sstevel@tonic-gate if (pcitool_debug) 9567c478bd9Sstevel@tonic-gate prom_printf("Error reading arguments\n"); 9577c478bd9Sstevel@tonic-gate return (EFAULT); 9587c478bd9Sstevel@tonic-gate } 9597c478bd9Sstevel@tonic-gate 9607c478bd9Sstevel@tonic-gate if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) { 9617c478bd9Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 9627c478bd9Sstevel@tonic-gate rval = EINVAL; 9637c478bd9Sstevel@tonic-gate goto done_reg; 9647c478bd9Sstevel@tonic-gate } 9657c478bd9Sstevel@tonic-gate 9667c478bd9Sstevel@tonic-gate if (pcitool_debug) 9677c478bd9Sstevel@tonic-gate prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n", 9687c478bd9Sstevel@tonic-gate prg.bus_no, prg.dev_no, prg.func_no); 9697c478bd9Sstevel@tonic-gate /* Validate address arguments of bus / dev / func */ 9707c478bd9Sstevel@tonic-gate if (((prg.bus_no & 9717c478bd9Sstevel@tonic-gate (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != 9727c478bd9Sstevel@tonic-gate prg.bus_no) || 9737c478bd9Sstevel@tonic-gate ((prg.dev_no & 9747c478bd9Sstevel@tonic-gate (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != 9757c478bd9Sstevel@tonic-gate prg.dev_no) || 9767c478bd9Sstevel@tonic-gate ((prg.func_no & 9777c478bd9Sstevel@tonic-gate (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != 9787c478bd9Sstevel@tonic-gate prg.func_no)) { 9797c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 9807c478bd9Sstevel@tonic-gate rval = EINVAL; 9817c478bd9Sstevel@tonic-gate goto done_reg; 9827c478bd9Sstevel@tonic-gate } 9837c478bd9Sstevel@tonic-gate 9847c478bd9Sstevel@tonic-gate size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr); 9857c478bd9Sstevel@tonic-gate 9867c478bd9Sstevel@tonic-gate /* Proper config space desired. */ 9877c478bd9Sstevel@tonic-gate if (prg.barnum == 0) { 9887c478bd9Sstevel@tonic-gate 9897c478bd9Sstevel@tonic-gate if (pcitool_debug) 9907c478bd9Sstevel@tonic-gate prom_printf( 9917c478bd9Sstevel@tonic-gate "config access: offset:0x%" PRIx64 ", " 9927c478bd9Sstevel@tonic-gate "phys_addr:0x%" PRIx64 "\n", 9937c478bd9Sstevel@tonic-gate prg.offset, prg.phys_addr); 994d4476ccbSschwartz 995d4476ccbSschwartz if (prg.offset >= max_cfg_size) { 996d4476ccbSschwartz prg.status = PCITOOL_OUT_OF_RANGE; 997d4476ccbSschwartz rval = EINVAL; 998d4476ccbSschwartz goto done_reg; 999d4476ccbSschwartz } 1000c0da6274SZhi-Jun Robin Fu if (max_cfg_size == PCIE_CONF_HDR_SIZE) 1001c0da6274SZhi-Jun Robin Fu io_access = B_FALSE; 1002d4476ccbSschwartz 1003c0da6274SZhi-Jun Robin Fu rval = pcitool_cfg_access(&prg, write_flag, io_access); 10047c478bd9Sstevel@tonic-gate if (pcitool_debug) 10057c478bd9Sstevel@tonic-gate prom_printf( 10067c478bd9Sstevel@tonic-gate "config access: data:0x%" PRIx64 "\n", 10077c478bd9Sstevel@tonic-gate prg.data); 10087c478bd9Sstevel@tonic-gate 10097c478bd9Sstevel@tonic-gate /* IO/ MEM/ MEM64 space. */ 10107c478bd9Sstevel@tonic-gate } else { 10117c478bd9Sstevel@tonic-gate 10127c478bd9Sstevel@tonic-gate pcitool_reg_t prg2; 10137c478bd9Sstevel@tonic-gate bcopy(&prg, &prg2, sizeof (pcitool_reg_t)); 10147c478bd9Sstevel@tonic-gate 10157c478bd9Sstevel@tonic-gate /* 10167c478bd9Sstevel@tonic-gate * Translate BAR number into offset of the BAR in 10177c478bd9Sstevel@tonic-gate * the device's config space. 10187c478bd9Sstevel@tonic-gate */ 10197c478bd9Sstevel@tonic-gate prg2.offset = pci_bars[prg2.barnum]; 10207c478bd9Sstevel@tonic-gate prg2.acc_attr = 10217c478bd9Sstevel@tonic-gate PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL; 10227c478bd9Sstevel@tonic-gate 10237c478bd9Sstevel@tonic-gate if (pcitool_debug) 10247c478bd9Sstevel@tonic-gate prom_printf( 10257c478bd9Sstevel@tonic-gate "barnum:%d, bar_offset:0x%" PRIx64 "\n", 10267c478bd9Sstevel@tonic-gate prg2.barnum, prg2.offset); 10277c478bd9Sstevel@tonic-gate /* 10287c478bd9Sstevel@tonic-gate * Get Bus Address Register (BAR) from config space. 10297c478bd9Sstevel@tonic-gate * prg2.offset is the offset into config space of the 10307c478bd9Sstevel@tonic-gate * BAR desired. prg.status is modified on error. 10317c478bd9Sstevel@tonic-gate */ 1032c0da6274SZhi-Jun Robin Fu rval = pcitool_cfg_access(&prg2, B_FALSE, B_TRUE); 10337c478bd9Sstevel@tonic-gate if (rval != SUCCESS) { 10347c478bd9Sstevel@tonic-gate if (pcitool_debug) 10357c478bd9Sstevel@tonic-gate prom_printf("BAR access failed\n"); 10367c478bd9Sstevel@tonic-gate prg.status = prg2.status; 10377c478bd9Sstevel@tonic-gate goto done_reg; 10387c478bd9Sstevel@tonic-gate } 10397c478bd9Sstevel@tonic-gate /* 10407c478bd9Sstevel@tonic-gate * Reference proper PCI space based on the BAR. 10417c478bd9Sstevel@tonic-gate * If 64 bit MEM space, need to load other half of the 10427c478bd9Sstevel@tonic-gate * BAR first. 10437c478bd9Sstevel@tonic-gate */ 10447c478bd9Sstevel@tonic-gate 10457c478bd9Sstevel@tonic-gate if (pcitool_debug) 10467c478bd9Sstevel@tonic-gate prom_printf("bar returned is 0x%" PRIx64 "\n", 10477c478bd9Sstevel@tonic-gate prg2.data); 10487c478bd9Sstevel@tonic-gate if (!prg2.data) { 10497c478bd9Sstevel@tonic-gate if (pcitool_debug) 10507c478bd9Sstevel@tonic-gate prom_printf("BAR data == 0\n"); 10517c478bd9Sstevel@tonic-gate rval = EINVAL; 10527c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 10537c478bd9Sstevel@tonic-gate goto done_reg; 10547c478bd9Sstevel@tonic-gate } 10557c478bd9Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 10567c478bd9Sstevel@tonic-gate if (pcitool_debug) 10577c478bd9Sstevel@tonic-gate prom_printf("BAR data == -1\n"); 10587c478bd9Sstevel@tonic-gate rval = EINVAL; 10597c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 10607c478bd9Sstevel@tonic-gate goto done_reg; 10617c478bd9Sstevel@tonic-gate } 10627c478bd9Sstevel@tonic-gate 10637c478bd9Sstevel@tonic-gate /* 10647c478bd9Sstevel@tonic-gate * BAR has bits saying this space is IO space, unless 10657c478bd9Sstevel@tonic-gate * this is the ROM address register. 10667c478bd9Sstevel@tonic-gate */ 10677c478bd9Sstevel@tonic-gate if (((PCI_BASE_SPACE_M & prg2.data) == 10687c478bd9Sstevel@tonic-gate PCI_BASE_SPACE_IO) && 10697c478bd9Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 10707c478bd9Sstevel@tonic-gate if (pcitool_debug) 10717c478bd9Sstevel@tonic-gate prom_printf("IO space\n"); 10727c478bd9Sstevel@tonic-gate 10737c478bd9Sstevel@tonic-gate prg2.data &= PCI_BASE_IO_ADDR_M; 10747c478bd9Sstevel@tonic-gate prg.phys_addr = prg2.data + prg.offset; 10757c478bd9Sstevel@tonic-gate 1076c0da6274SZhi-Jun Robin Fu rval = pcitool_io_access(&prg, write_flag); 10777c478bd9Sstevel@tonic-gate if ((rval != SUCCESS) && (pcitool_debug)) 10787c478bd9Sstevel@tonic-gate prom_printf("IO access failed\n"); 10797c478bd9Sstevel@tonic-gate 10807c478bd9Sstevel@tonic-gate goto done_reg; 10817c478bd9Sstevel@tonic-gate 10827c478bd9Sstevel@tonic-gate 10837c478bd9Sstevel@tonic-gate /* 10847c478bd9Sstevel@tonic-gate * BAR has bits saying this space is 64 bit memory 10857c478bd9Sstevel@tonic-gate * space, unless this is the ROM address register. 10867c478bd9Sstevel@tonic-gate * 10877c478bd9Sstevel@tonic-gate * The 64 bit address stored in two BAR cells is not 10887c478bd9Sstevel@tonic-gate * necessarily aligned on an 8-byte boundary. 10897c478bd9Sstevel@tonic-gate * Need to keep the first 4 bytes read, 10907c478bd9Sstevel@tonic-gate * and do a separate read of the high 4 bytes. 10917c478bd9Sstevel@tonic-gate */ 10927c478bd9Sstevel@tonic-gate 10937c478bd9Sstevel@tonic-gate } else if ((PCI_BASE_TYPE_ALL & prg2.data) && 10947c478bd9Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 10957c478bd9Sstevel@tonic-gate 10967c478bd9Sstevel@tonic-gate uint32_t low_bytes = 10977c478bd9Sstevel@tonic-gate (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL); 10987c478bd9Sstevel@tonic-gate 10997c478bd9Sstevel@tonic-gate /* 11007c478bd9Sstevel@tonic-gate * Don't try to read the next 4 bytes 11017c478bd9Sstevel@tonic-gate * past the end of BARs. 11027c478bd9Sstevel@tonic-gate */ 11037c478bd9Sstevel@tonic-gate if (prg2.offset >= PCI_CONF_BASE5) { 11047c478bd9Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 11057c478bd9Sstevel@tonic-gate rval = EIO; 11067c478bd9Sstevel@tonic-gate goto done_reg; 11077c478bd9Sstevel@tonic-gate } 11087c478bd9Sstevel@tonic-gate 11097c478bd9Sstevel@tonic-gate /* 11107c478bd9Sstevel@tonic-gate * Access device. 11117c478bd9Sstevel@tonic-gate * prg2.status is modified on error. 11127c478bd9Sstevel@tonic-gate */ 11137c478bd9Sstevel@tonic-gate prg2.offset += 4; 1114c0da6274SZhi-Jun Robin Fu rval = pcitool_cfg_access(&prg2, 1115c0da6274SZhi-Jun Robin Fu B_FALSE, B_TRUE); 11167c478bd9Sstevel@tonic-gate if (rval != SUCCESS) { 11177c478bd9Sstevel@tonic-gate prg.status = prg2.status; 11187c478bd9Sstevel@tonic-gate goto done_reg; 11197c478bd9Sstevel@tonic-gate } 11207c478bd9Sstevel@tonic-gate 11217c478bd9Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 11227c478bd9Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 11237c478bd9Sstevel@tonic-gate prg.status = EFAULT; 11247c478bd9Sstevel@tonic-gate goto done_reg; 11257c478bd9Sstevel@tonic-gate } 11267c478bd9Sstevel@tonic-gate 11277c478bd9Sstevel@tonic-gate prg2.data = (prg2.data << 32) + low_bytes; 11287c478bd9Sstevel@tonic-gate if (pcitool_debug) 11297c478bd9Sstevel@tonic-gate prom_printf( 11307c478bd9Sstevel@tonic-gate "64 bit mem space. " 11317c478bd9Sstevel@tonic-gate "64-bit bar is 0x%" PRIx64 "\n", 11327c478bd9Sstevel@tonic-gate prg2.data); 11337c478bd9Sstevel@tonic-gate 11347c478bd9Sstevel@tonic-gate /* Mem32 space, including ROM */ 11357c478bd9Sstevel@tonic-gate } else { 11367c478bd9Sstevel@tonic-gate 11377c478bd9Sstevel@tonic-gate if (prg2.offset == PCI_CONF_ROM) { 11387c478bd9Sstevel@tonic-gate if (pcitool_debug) 11397c478bd9Sstevel@tonic-gate prom_printf( 11407c478bd9Sstevel@tonic-gate "Additional ROM " 11417c478bd9Sstevel@tonic-gate "checking\n"); 11427c478bd9Sstevel@tonic-gate /* Can't write to ROM */ 11437c478bd9Sstevel@tonic-gate if (write_flag) { 11447c478bd9Sstevel@tonic-gate prg.status = PCITOOL_ROM_WRITE; 11457c478bd9Sstevel@tonic-gate rval = EIO; 11467c478bd9Sstevel@tonic-gate goto done_reg; 11477c478bd9Sstevel@tonic-gate 11487c478bd9Sstevel@tonic-gate /* ROM disabled for reading */ 11497c478bd9Sstevel@tonic-gate } else if (!(prg2.data & 0x00000001)) { 11507c478bd9Sstevel@tonic-gate prg.status = 11517c478bd9Sstevel@tonic-gate PCITOOL_ROM_DISABLED; 11527c478bd9Sstevel@tonic-gate rval = EIO; 11537c478bd9Sstevel@tonic-gate goto done_reg; 11547c478bd9Sstevel@tonic-gate } 11557c478bd9Sstevel@tonic-gate } 11567c478bd9Sstevel@tonic-gate 11577c478bd9Sstevel@tonic-gate if (pcitool_debug) 11587c478bd9Sstevel@tonic-gate prom_printf("32 bit mem space\n"); 11597c478bd9Sstevel@tonic-gate } 11607c478bd9Sstevel@tonic-gate 11617c478bd9Sstevel@tonic-gate /* Common code for all IO/MEM range spaces. */ 11627c478bd9Sstevel@tonic-gate 11637c478bd9Sstevel@tonic-gate base_addr = prg2.data; 11647c478bd9Sstevel@tonic-gate if (pcitool_debug) 11657c478bd9Sstevel@tonic-gate prom_printf( 11667c478bd9Sstevel@tonic-gate "addr portion of bar is 0x%" PRIx64 ", " 11677c478bd9Sstevel@tonic-gate "base=0x%" PRIx64 ", " 11687c478bd9Sstevel@tonic-gate "offset:0x%" PRIx64 "\n", 11697c478bd9Sstevel@tonic-gate prg2.data, base_addr, prg.offset); 11707c478bd9Sstevel@tonic-gate /* 11717c478bd9Sstevel@tonic-gate * Use offset provided by caller to index into 11727c478bd9Sstevel@tonic-gate * desired space, then access. 11737c478bd9Sstevel@tonic-gate * Note that prg.status is modified on error. 11747c478bd9Sstevel@tonic-gate */ 11757c478bd9Sstevel@tonic-gate prg.phys_addr = base_addr + prg.offset; 11767c478bd9Sstevel@tonic-gate 11777c478bd9Sstevel@tonic-gate virt_addr = pcitool_map(prg.phys_addr, size, 11787c478bd9Sstevel@tonic-gate &num_virt_pages); 11797c478bd9Sstevel@tonic-gate if (virt_addr == NULL) { 11807c478bd9Sstevel@tonic-gate prg.status = PCITOOL_IO_ERROR; 11817c478bd9Sstevel@tonic-gate rval = EIO; 11827c478bd9Sstevel@tonic-gate goto done_reg; 11837c478bd9Sstevel@tonic-gate } 11847c478bd9Sstevel@tonic-gate 1185c0da6274SZhi-Jun Robin Fu rval = pcitool_mem_access(&prg, virt_addr, write_flag); 11867c478bd9Sstevel@tonic-gate pcitool_unmap(virt_addr, num_virt_pages); 11877c478bd9Sstevel@tonic-gate } 11887c478bd9Sstevel@tonic-gate done_reg: 11892917a9c9Sschwartz prg.drvr_version = PCITOOL_VERSION; 11907c478bd9Sstevel@tonic-gate if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) != 11917c478bd9Sstevel@tonic-gate DDI_SUCCESS) { 11927c478bd9Sstevel@tonic-gate if (pcitool_debug) 11937c478bd9Sstevel@tonic-gate prom_printf("Error returning arguments.\n"); 11947c478bd9Sstevel@tonic-gate rval = EFAULT; 11957c478bd9Sstevel@tonic-gate } 11967c478bd9Sstevel@tonic-gate break; 11977c478bd9Sstevel@tonic-gate default: 11987c478bd9Sstevel@tonic-gate rval = ENOTTY; 11997c478bd9Sstevel@tonic-gate break; 12007c478bd9Sstevel@tonic-gate } 12017c478bd9Sstevel@tonic-gate return (rval); 12027c478bd9Sstevel@tonic-gate } 1203