1ae115bc7Smrj /*
2ae115bc7Smrj * CDDL HEADER START
3ae115bc7Smrj *
4ae115bc7Smrj * The contents of this file are subject to the terms of the
5ae115bc7Smrj * Common Development and Distribution License (the "License").
6ae115bc7Smrj * You may not use this file except in compliance with the License.
7ae115bc7Smrj *
8ae115bc7Smrj * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9ae115bc7Smrj * or http://www.opensolaris.org/os/licensing.
10ae115bc7Smrj * See the License for the specific language governing permissions
11ae115bc7Smrj * and limitations under the License.
12ae115bc7Smrj *
13ae115bc7Smrj * When distributing Covered Code, include this CDDL HEADER in each
14ae115bc7Smrj * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15ae115bc7Smrj * If applicable, add the following below this CDDL HEADER, with the
16ae115bc7Smrj * fields enclosed by brackets "[]" replaced with your own identifying
17ae115bc7Smrj * information: Portions Copyright [yyyy] [name of copyright owner]
18ae115bc7Smrj *
19ae115bc7Smrj * CDDL HEADER END
20ae115bc7Smrj */
21ae115bc7Smrj
22ae115bc7Smrj /*
230db3240dSStephen Hanson * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24*60bb5373SAndy Fiddaman * Copyright 2023 Oxide Computer Company
25ae115bc7Smrj */
26ae115bc7Smrj
27ae115bc7Smrj /*
28ae115bc7Smrj * Library file that has code for PCIe booting
29ae115bc7Smrj */
30ae115bc7Smrj
31ae115bc7Smrj #include <sys/conf.h>
32ae115bc7Smrj #include <sys/pci.h>
33ae115bc7Smrj #include <sys/sunndi.h>
34ae115bc7Smrj #include <sys/pcie.h>
35c0da6274SZhi-Jun Robin Fu #include <sys/pcie_impl.h>
36ae115bc7Smrj #include <sys/pci_cfgspace.h>
37ae115bc7Smrj #include <io/pciex/pcie_nvidia.h>
38ae115bc7Smrj
39ae115bc7Smrj /*
40ae115bc7Smrj * PCI Configuration (Nvidia chipsets, PCIe) related library functions
41ae115bc7Smrj */
42ae115bc7Smrj
43ae115bc7Smrj /* Globals */
44ae115bc7Smrj extern int pci_boot_debug;
45ae115bc7Smrj
46c0da6274SZhi-Jun Robin Fu extern uint64_t mcfg_mem_base;
47c0da6274SZhi-Jun Robin Fu
48ae115bc7Smrj boolean_t
check_if_device_is_pciex(dev_info_t * cdip,uchar_t bus,uchar_t dev,uchar_t func,boolean_t * slot_valid,ushort_t * slot_number,ushort_t * is_pci_bridge)49ae115bc7Smrj check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev,
500db3240dSStephen Hanson uchar_t func, boolean_t *slot_valid, ushort_t *slot_number,
510db3240dSStephen Hanson ushort_t *is_pci_bridge)
52ae115bc7Smrj {
53ae115bc7Smrj boolean_t found_pciex = B_FALSE;
54ae115bc7Smrj ushort_t cap;
55ae115bc7Smrj ushort_t capsp;
56ae115bc7Smrj ushort_t cap_count = PCI_CAP_MAX_PTR;
57ae115bc7Smrj ushort_t status;
58ae115bc7Smrj uint32_t slot_cap;
59ae115bc7Smrj
600db3240dSStephen Hanson *slot_valid = B_FALSE;
61ae115bc7Smrj
62ae115bc7Smrj status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT);
63ae115bc7Smrj if (!(status & PCI_STAT_CAP))
64ae115bc7Smrj return (B_FALSE);
65ae115bc7Smrj
66ae115bc7Smrj capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR);
67ae115bc7Smrj while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) {
68ae115bc7Smrj capsp &= PCI_CAP_PTR_MASK;
69ae115bc7Smrj cap = (*pci_getb_func)(bus, dev, func, capsp);
70ae115bc7Smrj
71ae115bc7Smrj if (cap == PCI_CAP_ID_PCI_E) {
72ae115bc7Smrj #ifdef DEBUG
73ae115bc7Smrj if (pci_boot_debug)
74ae115bc7Smrj cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) "
75ae115bc7Smrj "capability found\n", bus, dev, func);
76ae115bc7Smrj #endif /* DEBUG */
77ae115bc7Smrj
78ae115bc7Smrj status = (*pci_getw_func)(bus, dev, func, capsp + 2);
79ae115bc7Smrj /*
80ae115bc7Smrj * See section 7.8.2 of PCI-Express Base Spec v1.0a
81ae115bc7Smrj * for Device/Port Type.
82ae115bc7Smrj * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the
83ae115bc7Smrj * device is a PCIe2PCI bridge
84ae115bc7Smrj */
85ae115bc7Smrj *is_pci_bridge =
8649fbdd30SErwin T Tsaur ((status & PCIE_PCIECAP_DEV_TYPE_MASK) ==
87ae115bc7Smrj PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0;
88ae115bc7Smrj
89ae115bc7Smrj /*
90ae115bc7Smrj * Check for "Slot Implemented" bit
91ae115bc7Smrj * PCIE_PCIECAP_SLOT_IMPL implies that.
92ae115bc7Smrj */
93ae115bc7Smrj if (status & PCIE_PCIECAP_SLOT_IMPL) {
94ae115bc7Smrj /* offset 14h is Slot Cap Register */
95ae115bc7Smrj slot_cap = (*pci_getl_func)(bus, dev, func,
96ae115bc7Smrj capsp + PCIE_SLOTCAP);
970db3240dSStephen Hanson *slot_valid = B_TRUE;
98ae115bc7Smrj *slot_number =
99ae115bc7Smrj PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap);
100ae115bc7Smrj }
101ae115bc7Smrj
102ae115bc7Smrj found_pciex = B_TRUE;
103ae115bc7Smrj }
104ae115bc7Smrj
105ae115bc7Smrj capsp = (*pci_getb_func)(bus, dev, func,
106ae115bc7Smrj capsp + PCI_CAP_NEXT_PTR);
107ae115bc7Smrj }
108ae115bc7Smrj
109ae115bc7Smrj return (found_pciex);
110ae115bc7Smrj }
111ae115bc7Smrj
112ae115bc7Smrj
113ae115bc7Smrj /*
114ae115bc7Smrj * scan all buses, devices, functions to look for any
115ae115bc7Smrj * PCI-Express device in the system.
116ae115bc7Smrj * If found, return B_TRUE else B_FALSE
117ae115bc7Smrj */
118c0da6274SZhi-Jun Robin Fu boolean_t
look_for_any_pciex_device(uchar_t bus)119ae115bc7Smrj look_for_any_pciex_device(uchar_t bus)
120ae115bc7Smrj {
121ae115bc7Smrj uchar_t dev, func;
122ae115bc7Smrj uchar_t nfunc, header;
123ae115bc7Smrj ushort_t venid, slot_num, is_pci_bridge = 0;
1240db3240dSStephen Hanson boolean_t slot_valid;
125ae115bc7Smrj
126ae115bc7Smrj for (dev = 0; dev < 32; dev++) {
127ae115bc7Smrj nfunc = 1;
128ae115bc7Smrj for (func = 0; func < nfunc; func++) {
129ae115bc7Smrj #ifdef DEBUG
130ae115bc7Smrj if (pci_boot_debug)
131ae115bc7Smrj cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x",
132ae115bc7Smrj dev, func);
133ae115bc7Smrj #endif /* DEBUG */
134ae115bc7Smrj
135ae115bc7Smrj venid = (*pci_getw_func)(bus, dev, func,
136ae115bc7Smrj PCI_CONF_VENID);
137ae115bc7Smrj /* no function at this address */
138ae115bc7Smrj if ((venid == 0xffff) || (venid == 0))
139ae115bc7Smrj continue;
140ae115bc7Smrj
141ae115bc7Smrj header = (*pci_getb_func)(bus, dev, func,
142ae115bc7Smrj PCI_CONF_HEADER);
143ae115bc7Smrj if (header == 0xff)
144ae115bc7Smrj continue; /* illegal value */
145ae115bc7Smrj
146ae115bc7Smrj /*
147ae115bc7Smrj * according to some mail from Microsoft posted to
148ae115bc7Smrj * the pci-drivers alias, their only requirement for
149ae115bc7Smrj * a multifunction device is for the 1st function to
150ae115bc7Smrj * have to PCI_HEADER_MULTI bit set.
151ae115bc7Smrj */
152ae115bc7Smrj if ((func == 0) && (header & PCI_HEADER_MULTI))
153ae115bc7Smrj nfunc = 8;
154ae115bc7Smrj
155ae115bc7Smrj if (check_if_device_is_pciex(NULL, bus, dev, func,
1560db3240dSStephen Hanson &slot_valid, &slot_num, &is_pci_bridge) == B_TRUE)
157ae115bc7Smrj return (B_TRUE);
158ae115bc7Smrj } /* end of func */
159ae115bc7Smrj } /* end of dev */
160ae115bc7Smrj
161ae115bc7Smrj return (B_FALSE);
162ae115bc7Smrj }
163ae115bc7Smrj
164ae115bc7Smrj boolean_t
create_pcie_root_bus(uchar_t bus,dev_info_t * dip)165ae115bc7Smrj create_pcie_root_bus(uchar_t bus, dev_info_t *dip)
166ae115bc7Smrj {
167ae115bc7Smrj /*
168ae115bc7Smrj * Currently this is being hard-coded.
169ae115bc7Smrj * We need to figure out if the root bus does indeed
170ae115bc7Smrj * have PCI-Ex in the path by looking for MCFG in
171ae115bc7Smrj * the ACPI tables
172ae115bc7Smrj */
173ae115bc7Smrj if (look_for_any_pciex_device(bus) == B_FALSE)
174ae115bc7Smrj return (B_FALSE);
175ae115bc7Smrj
176ae115bc7Smrj #ifdef DEBUG
177ae115bc7Smrj if (pci_boot_debug)
178ae115bc7Smrj cmn_err(CE_CONT, "Found PCI-Ex in the system\n");
179ae115bc7Smrj #endif /* DEBUG */
180ae115bc7Smrj (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
181ae115bc7Smrj "device_type", "pciex");
182ae115bc7Smrj (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
183ae115bc7Smrj "compatible", "pciex_root_complex");
184ae115bc7Smrj
185c0da6274SZhi-Jun Robin Fu pcie_rc_init_bus(dip);
186c0da6274SZhi-Jun Robin Fu
187ae115bc7Smrj return (B_TRUE);
188ae115bc7Smrj }
189ae115bc7Smrj
190ae115bc7Smrj
191ae115bc7Smrj /*
192ae115bc7Smrj * add_nvidia_isa_bridge_props():
193ae115bc7Smrj * To enable native hotplug; we need to map in two I/O BARs
194ae115bc7Smrj * from ISA bridge's config space
195ae115bc7Smrj *
196ae115bc7Smrj * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets.
197ae115bc7Smrj */
198ae115bc7Smrj void
add_nvidia_isa_bridge_props(dev_info_t * dip,uchar_t bus,uchar_t dev,uchar_t func)199ae115bc7Smrj add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev,
200ae115bc7Smrj uchar_t func)
201ae115bc7Smrj {
202ae115bc7Smrj uint_t devloc, base;
203ae115bc7Smrj pci_regspec_t regs[2] = {{0}};
204ae115bc7Smrj pci_regspec_t assigned[2] = {{0}};
205ae115bc7Smrj
206*60bb5373SAndy Fiddaman devloc = PCI_REG_MAKE_BDFR(bus, dev, func, 0);
207ae115bc7Smrj regs[0].pci_phys_hi = devloc;
208ae115bc7Smrj
209ae115bc7Smrj /* System Control BAR i/o space */
210ae115bc7Smrj base = (*pci_getl_func)(bus, dev, func,
211ae115bc7Smrj NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
212ae115bc7Smrj regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE;
213ae115bc7Smrj assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B |
214ae115bc7Smrj PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF);
215ae115bc7Smrj assigned[0].pci_phys_low = regs[0].pci_phys_low =
216ae115bc7Smrj base & PCI_BASE_IO_ADDR_M;
217ae115bc7Smrj
218ae115bc7Smrj /* Analog BAR i/o space */
219ae115bc7Smrj base = (*pci_getl_func)(bus, dev, func,
220ae115bc7Smrj NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
221ae115bc7Smrj regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE;
222ae115bc7Smrj assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B |
223ae115bc7Smrj PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF);
224ae115bc7Smrj assigned[1].pci_phys_low = regs[1].pci_phys_low =
225ae115bc7Smrj base & PCI_BASE_IO_ADDR_M;
226ae115bc7Smrj
227ae115bc7Smrj (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg",
228ae115bc7Smrj (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int));
229ae115bc7Smrj (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip,
230ae115bc7Smrj "assigned-addresses",
231ae115bc7Smrj (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int));
232ae115bc7Smrj }
233