1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_SC_H 28 #define _SYS_PCI_SC_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * streaming cache (sc) block soft state structure: 38 * 39 * Each pci node contains has its own private sc block structure. 40 */ 41 typedef struct sc sc_t; 42 struct sc { 43 44 pci_t *sc_pci_p; /* link back to pci soft state */ 45 46 /* 47 * control registers (psycho and schizo): 48 */ 49 volatile uint64_t *sc_ctrl_reg; 50 volatile uint64_t *sc_invl_reg; 51 volatile uint64_t *sc_sync_reg; 52 uint64_t sc_sync_reg_pa; 53 54 /* 55 * control registers (schizo only): 56 */ 57 volatile uint64_t *sc_ctx_invl_reg; 58 volatile uint64_t *sc_ctx_match_reg; 59 60 /* 61 * diagnostic access registers: 62 */ 63 volatile uint64_t *sc_data_diag_acc; 64 volatile uint64_t *sc_tag_diag_acc; 65 volatile uint64_t *sc_ltag_diag_acc; 66 67 /* 68 * Sync flag and its associated buffer. 69 */ 70 caddr_t sc_sync_flag_base; 71 volatile uint64_t *sc_sync_flag_vaddr; 72 uint64_t sc_sync_flag_pa; 73 74 kmutex_t sc_sync_mutex; /* mutex for flush/sync register */ 75 }; 76 77 #define PCI_SBUF_ENTRIES 16 /* number of i/o cache lines */ 78 #define PCI_SBUF_LINE_SIZE 64 /* size of i/o cache line */ 79 80 #define PCI_CACHE_LINE_SIZE (PCI_SBUF_LINE_SIZE / 4) 81 82 extern void sc_create(pci_t *pci_p); 83 extern void sc_destroy(pci_t *pci_p); 84 extern void sc_configure(sc_t *sc_p); 85 86 /* 87 * The most significant bit (63) of each context match register. 88 */ 89 #define SC_CMR_DIRTY_BIT 1 90 #define SC_ENTRIES 16 91 #define SC_ENT_SHIFT (64 - SC_ENTRIES) 92 93 #ifdef __cplusplus 94 } 95 #endif 96 97 #endif /* _SYS_PCI_SC_H */ 98