1 /* 2 * linux/arch/alpha/kernel/core_mcpcia.c 3 * 4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com). 5 * 6 * Code common to all MCbus-PCI Adaptor core logic chipsets 7 */ 8 9 #define __EXTERN_INLINE inline 10 #include <asm/io.h> 11 #include <asm/core_mcpcia.h> 12 #undef __EXTERN_INLINE 13 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/sched.h> 17 #include <linux/init.h> 18 #include <linux/delay.h> 19 20 #include <asm/ptrace.h> 21 22 #include "proto.h" 23 #include "pci_impl.h" 24 25 /* 26 * NOTE: Herein lie back-to-back mb instructions. They are magic. 27 * One plausible explanation is that the i/o controller does not properly 28 * handle the system transaction. Another involves timing. Ho hum. 29 */ 30 31 /* 32 * BIOS32-style PCI interface: 33 */ 34 35 #define DEBUG_CFG 0 36 37 #if DEBUG_CFG 38 # define DBG_CFG(args) printk args 39 #else 40 # define DBG_CFG(args) 41 #endif 42 43 #define MCPCIA_MAX_HOSES 4 44 45 /* 46 * Given a bus, device, and function number, compute resulting 47 * configuration space address and setup the MCPCIA_HAXR2 register 48 * accordingly. It is therefore not safe to have concurrent 49 * invocations to configuration space access routines, but there 50 * really shouldn't be any need for this. 51 * 52 * Type 0: 53 * 54 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 55 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 56 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 57 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| 58 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 59 * 60 * 31:11 Device select bit. 61 * 10:8 Function number 62 * 7:2 Register number 63 * 64 * Type 1: 65 * 66 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 67 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 68 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 69 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| 70 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 71 * 72 * 31:24 reserved 73 * 23:16 bus number (8 bits = 128 possible buses) 74 * 15:11 Device number (5 bits) 75 * 10:8 function number 76 * 7:2 register number 77 * 78 * Notes: 79 * The function number selects which function of a multi-function device 80 * (e.g., SCSI and Ethernet). 81 * 82 * The register selects a DWORD (32 bit) register offset. Hence it 83 * doesn't get shifted by 2 bits as we want to "drop" the bottom two 84 * bits. 85 */ 86 87 static unsigned int 88 conf_read(unsigned long addr, unsigned char type1, 89 struct pci_controller *hose) 90 { 91 unsigned long flags; 92 unsigned long mid = MCPCIA_HOSE2MID(hose->index); 93 unsigned int stat0, value, temp, cpu; 94 95 cpu = smp_processor_id(); 96 97 local_irq_save(flags); 98 99 DBG_CFG(("conf_read(addr=0x%lx, type1=%d, hose=%d)\n", 100 addr, type1, mid)); 101 102 /* Reset status register to avoid losing errors. */ 103 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); 104 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; 105 mb(); 106 temp = *(vuip)MCPCIA_CAP_ERR(mid); 107 DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0)); 108 109 mb(); 110 draina(); 111 mcheck_expected(cpu) = 1; 112 mcheck_taken(cpu) = 0; 113 mcheck_extra(cpu) = mid; 114 mb(); 115 116 /* Access configuration space. */ 117 value = *((vuip)addr); 118 mb(); 119 mb(); /* magic */ 120 121 if (mcheck_taken(cpu)) { 122 mcheck_taken(cpu) = 0; 123 value = 0xffffffffU; 124 mb(); 125 } 126 mcheck_expected(cpu) = 0; 127 mb(); 128 129 DBG_CFG(("conf_read(): finished\n")); 130 131 local_irq_restore(flags); 132 return value; 133 } 134 135 static void 136 conf_write(unsigned long addr, unsigned int value, unsigned char type1, 137 struct pci_controller *hose) 138 { 139 unsigned long flags; 140 unsigned long mid = MCPCIA_HOSE2MID(hose->index); 141 unsigned int stat0, temp, cpu; 142 143 cpu = smp_processor_id(); 144 145 local_irq_save(flags); /* avoid getting hit by machine check */ 146 147 /* Reset status register to avoid losing errors. */ 148 stat0 = *(vuip)MCPCIA_CAP_ERR(mid); 149 *(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb(); 150 temp = *(vuip)MCPCIA_CAP_ERR(mid); 151 DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0)); 152 153 draina(); 154 mcheck_expected(cpu) = 1; 155 mcheck_extra(cpu) = mid; 156 mb(); 157 158 /* Access configuration space. */ 159 *((vuip)addr) = value; 160 mb(); 161 mb(); /* magic */ 162 temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */ 163 mcheck_expected(cpu) = 0; 164 mb(); 165 166 DBG_CFG(("conf_write(): finished\n")); 167 local_irq_restore(flags); 168 } 169 170 static int 171 mk_conf_addr(struct pci_bus *pbus, unsigned int devfn, int where, 172 struct pci_controller *hose, unsigned long *pci_addr, 173 unsigned char *type1) 174 { 175 u8 bus = pbus->number; 176 unsigned long addr; 177 178 DBG_CFG(("mk_conf_addr(bus=%d,devfn=0x%x,hose=%d,where=0x%x," 179 " pci_addr=0x%p, type1=0x%p)\n", 180 bus, devfn, hose->index, where, pci_addr, type1)); 181 182 /* Type 1 configuration cycle for *ALL* busses. */ 183 *type1 = 1; 184 185 if (!pbus->parent) /* No parent means peer PCI bus. */ 186 bus = 0; 187 addr = (bus << 16) | (devfn << 8) | (where); 188 addr <<= 5; /* swizzle for SPARSE */ 189 addr |= hose->config_space_base; 190 191 *pci_addr = addr; 192 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr)); 193 return 0; 194 } 195 196 static int 197 mcpcia_read_config(struct pci_bus *bus, unsigned int devfn, int where, 198 int size, u32 *value) 199 { 200 struct pci_controller *hose = bus->sysdata; 201 unsigned long addr, w; 202 unsigned char type1; 203 204 if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1)) 205 return PCIBIOS_DEVICE_NOT_FOUND; 206 207 addr |= (size - 1) * 8; 208 w = conf_read(addr, type1, hose); 209 switch (size) { 210 case 1: 211 *value = __kernel_extbl(w, where & 3); 212 break; 213 case 2: 214 *value = __kernel_extwl(w, where & 3); 215 break; 216 case 4: 217 *value = w; 218 break; 219 } 220 return PCIBIOS_SUCCESSFUL; 221 } 222 223 static int 224 mcpcia_write_config(struct pci_bus *bus, unsigned int devfn, int where, 225 int size, u32 value) 226 { 227 struct pci_controller *hose = bus->sysdata; 228 unsigned long addr; 229 unsigned char type1; 230 231 if (mk_conf_addr(bus, devfn, where, hose, &addr, &type1)) 232 return PCIBIOS_DEVICE_NOT_FOUND; 233 234 addr |= (size - 1) * 8; 235 value = __kernel_insql(value, where & 3); 236 conf_write(addr, value, type1, hose); 237 return PCIBIOS_SUCCESSFUL; 238 } 239 240 struct pci_ops mcpcia_pci_ops = 241 { 242 .read = mcpcia_read_config, 243 .write = mcpcia_write_config, 244 }; 245 246 void 247 mcpcia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 248 { 249 wmb(); 250 *(vuip)MCPCIA_SG_TBIA(MCPCIA_HOSE2MID(hose->index)) = 0; 251 mb(); 252 } 253 254 static int __init 255 mcpcia_probe_hose(int h) 256 { 257 int cpu = smp_processor_id(); 258 int mid = MCPCIA_HOSE2MID(h); 259 unsigned int pci_rev; 260 261 /* Gotta be REAL careful. If hose is absent, we get an mcheck. */ 262 263 mb(); 264 mb(); 265 draina(); 266 wrmces(7); 267 268 mcheck_expected(cpu) = 2; /* indicates probing */ 269 mcheck_taken(cpu) = 0; 270 mcheck_extra(cpu) = mid; 271 mb(); 272 273 /* Access the bus revision word. */ 274 pci_rev = *(vuip)MCPCIA_REV(mid); 275 276 mb(); 277 mb(); /* magic */ 278 if (mcheck_taken(cpu)) { 279 mcheck_taken(cpu) = 0; 280 pci_rev = 0xffffffff; 281 mb(); 282 } 283 mcheck_expected(cpu) = 0; 284 mb(); 285 286 return (pci_rev >> 16) == PCI_CLASS_BRIDGE_HOST; 287 } 288 289 static void __init 290 mcpcia_new_hose(int h) 291 { 292 struct pci_controller *hose; 293 struct resource *io, *mem, *hae_mem; 294 int mid = MCPCIA_HOSE2MID(h); 295 296 hose = alloc_pci_controller(); 297 if (h == 0) 298 pci_isa_hose = hose; 299 io = alloc_resource(); 300 mem = alloc_resource(); 301 hae_mem = alloc_resource(); 302 303 hose->io_space = io; 304 hose->mem_space = hae_mem; 305 hose->sparse_mem_base = MCPCIA_SPARSE(mid) - IDENT_ADDR; 306 hose->dense_mem_base = MCPCIA_DENSE(mid) - IDENT_ADDR; 307 hose->sparse_io_base = MCPCIA_IO(mid) - IDENT_ADDR; 308 hose->dense_io_base = 0; 309 hose->config_space_base = MCPCIA_CONF(mid); 310 hose->index = h; 311 312 io->start = MCPCIA_IO(mid) - MCPCIA_IO_BIAS; 313 io->end = io->start + 0xffff; 314 io->name = pci_io_names[h]; 315 io->flags = IORESOURCE_IO; 316 317 mem->start = MCPCIA_DENSE(mid) - MCPCIA_MEM_BIAS; 318 mem->end = mem->start + 0xffffffff; 319 mem->name = pci_mem_names[h]; 320 mem->flags = IORESOURCE_MEM; 321 322 hae_mem->start = mem->start; 323 hae_mem->end = mem->start + MCPCIA_MEM_MASK; 324 hae_mem->name = pci_hae0_name; 325 hae_mem->flags = IORESOURCE_MEM; 326 327 if (request_resource(&ioport_resource, io) < 0) 328 printk(KERN_ERR "Failed to request IO on hose %d\n", h); 329 if (request_resource(&iomem_resource, mem) < 0) 330 printk(KERN_ERR "Failed to request MEM on hose %d\n", h); 331 if (request_resource(mem, hae_mem) < 0) 332 printk(KERN_ERR "Failed to request HAE_MEM on hose %d\n", h); 333 } 334 335 static void 336 mcpcia_pci_clr_err(int mid) 337 { 338 *(vuip)MCPCIA_CAP_ERR(mid); 339 *(vuip)MCPCIA_CAP_ERR(mid) = 0xffffffff; /* Clear them all. */ 340 mb(); 341 *(vuip)MCPCIA_CAP_ERR(mid); /* Re-read for force write. */ 342 } 343 344 static void __init 345 mcpcia_startup_hose(struct pci_controller *hose) 346 { 347 int mid = MCPCIA_HOSE2MID(hose->index); 348 unsigned int tmp; 349 350 mcpcia_pci_clr_err(mid); 351 352 /* 353 * Set up error reporting. 354 */ 355 tmp = *(vuip)MCPCIA_CAP_ERR(mid); 356 tmp |= 0x0006; /* master/target abort */ 357 *(vuip)MCPCIA_CAP_ERR(mid) = tmp; 358 mb(); 359 tmp = *(vuip)MCPCIA_CAP_ERR(mid); 360 361 /* 362 * Set up the PCI->physical memory translation windows. 363 * 364 * Window 0 is scatter-gather 8MB at 8MB (for isa) 365 * Window 1 is scatter-gather (up to) 1GB at 1GB (for pci) 366 * Window 2 is direct access 2GB at 2GB 367 */ 368 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0); 369 hose->sg_pci = iommu_arena_new(hose, 0x40000000, 370 size_for_memory(0x40000000), 0); 371 372 __direct_map_base = 0x80000000; 373 __direct_map_size = 0x80000000; 374 375 *(vuip)MCPCIA_W0_BASE(mid) = hose->sg_isa->dma_base | 3; 376 *(vuip)MCPCIA_W0_MASK(mid) = (hose->sg_isa->size - 1) & 0xfff00000; 377 *(vuip)MCPCIA_T0_BASE(mid) = virt_to_phys(hose->sg_isa->ptes) >> 8; 378 379 *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3; 380 *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000; 381 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8; 382 383 *(vuip)MCPCIA_W2_BASE(mid) = __direct_map_base | 1; 384 *(vuip)MCPCIA_W2_MASK(mid) = (__direct_map_size - 1) & 0xfff00000; 385 *(vuip)MCPCIA_T2_BASE(mid) = 0; 386 387 *(vuip)MCPCIA_W3_BASE(mid) = 0x0; 388 389 mcpcia_pci_tbi(hose, 0, -1); 390 391 *(vuip)MCPCIA_HBASE(mid) = 0x0; 392 mb(); 393 394 *(vuip)MCPCIA_HAE_MEM(mid) = 0U; 395 mb(); 396 *(vuip)MCPCIA_HAE_MEM(mid); /* read it back. */ 397 *(vuip)MCPCIA_HAE_IO(mid) = 0; 398 mb(); 399 *(vuip)MCPCIA_HAE_IO(mid); /* read it back. */ 400 } 401 402 void __init 403 mcpcia_init_arch(void) 404 { 405 /* With multiple PCI busses, we play with I/O as physical addrs. */ 406 ioport_resource.end = ~0UL; 407 408 /* Allocate hose 0. That's the one that all the ISA junk hangs 409 off of, from which we'll be registering stuff here in a bit. 410 Other hose detection is done in mcpcia_init_hoses, which is 411 called from init_IRQ. */ 412 413 mcpcia_new_hose(0); 414 } 415 416 /* This is called from init_IRQ, since we cannot take interrupts 417 before then. Which means we cannot do this in init_arch. */ 418 419 void __init 420 mcpcia_init_hoses(void) 421 { 422 struct pci_controller *hose; 423 int hose_count; 424 int h; 425 426 /* First, find how many hoses we have. */ 427 hose_count = 0; 428 for (h = 0; h < MCPCIA_MAX_HOSES; ++h) { 429 if (mcpcia_probe_hose(h)) { 430 if (h != 0) 431 mcpcia_new_hose(h); 432 hose_count++; 433 } 434 } 435 436 printk("mcpcia_init_hoses: found %d hoses\n", hose_count); 437 438 /* Now do init for each hose. */ 439 for (hose = hose_head; hose; hose = hose->next) 440 mcpcia_startup_hose(hose); 441 } 442 443 static void 444 mcpcia_print_uncorrectable(struct el_MCPCIA_uncorrected_frame_mcheck *logout) 445 { 446 struct el_common_EV5_uncorrectable_mcheck *frame; 447 int i; 448 449 frame = &logout->procdata; 450 451 /* Print PAL fields */ 452 for (i = 0; i < 24; i += 2) { 453 printk(" paltmp[%d-%d] = %16lx %16lx\n", 454 i, i+1, frame->paltemp[i], frame->paltemp[i+1]); 455 } 456 for (i = 0; i < 8; i += 2) { 457 printk(" shadow[%d-%d] = %16lx %16lx\n", 458 i, i+1, frame->shadow[i], 459 frame->shadow[i+1]); 460 } 461 printk(" Addr of excepting instruction = %16lx\n", 462 frame->exc_addr); 463 printk(" Summary of arithmetic traps = %16lx\n", 464 frame->exc_sum); 465 printk(" Exception mask = %16lx\n", 466 frame->exc_mask); 467 printk(" Base address for PALcode = %16lx\n", 468 frame->pal_base); 469 printk(" Interrupt Status Reg = %16lx\n", 470 frame->isr); 471 printk(" CURRENT SETUP OF EV5 IBOX = %16lx\n", 472 frame->icsr); 473 printk(" I-CACHE Reg %s parity error = %16lx\n", 474 (frame->ic_perr_stat & 0x800L) ? 475 "Data" : "Tag", 476 frame->ic_perr_stat); 477 printk(" D-CACHE error Reg = %16lx\n", 478 frame->dc_perr_stat); 479 if (frame->dc_perr_stat & 0x2) { 480 switch (frame->dc_perr_stat & 0x03c) { 481 case 8: 482 printk(" Data error in bank 1\n"); 483 break; 484 case 4: 485 printk(" Data error in bank 0\n"); 486 break; 487 case 20: 488 printk(" Tag error in bank 1\n"); 489 break; 490 case 10: 491 printk(" Tag error in bank 0\n"); 492 break; 493 } 494 } 495 printk(" Effective VA = %16lx\n", 496 frame->va); 497 printk(" Reason for D-stream = %16lx\n", 498 frame->mm_stat); 499 printk(" EV5 SCache address = %16lx\n", 500 frame->sc_addr); 501 printk(" EV5 SCache TAG/Data parity = %16lx\n", 502 frame->sc_stat); 503 printk(" EV5 BC_TAG_ADDR = %16lx\n", 504 frame->bc_tag_addr); 505 printk(" EV5 EI_ADDR: Phys addr of Xfer = %16lx\n", 506 frame->ei_addr); 507 printk(" Fill Syndrome = %16lx\n", 508 frame->fill_syndrome); 509 printk(" EI_STAT reg = %16lx\n", 510 frame->ei_stat); 511 printk(" LD_LOCK = %16lx\n", 512 frame->ld_lock); 513 } 514 515 static void 516 mcpcia_print_system_area(unsigned long la_ptr) 517 { 518 struct el_common *frame; 519 struct pci_controller *hose; 520 521 struct IOD_subpacket { 522 unsigned long base; 523 unsigned int whoami; 524 unsigned int rsvd1; 525 unsigned int pci_rev; 526 unsigned int cap_ctrl; 527 unsigned int hae_mem; 528 unsigned int hae_io; 529 unsigned int int_ctl; 530 unsigned int int_reg; 531 unsigned int int_mask0; 532 unsigned int int_mask1; 533 unsigned int mc_err0; 534 unsigned int mc_err1; 535 unsigned int cap_err; 536 unsigned int rsvd2; 537 unsigned int pci_err1; 538 unsigned int mdpa_stat; 539 unsigned int mdpa_syn; 540 unsigned int mdpb_stat; 541 unsigned int mdpb_syn; 542 unsigned int rsvd3; 543 unsigned int rsvd4; 544 unsigned int rsvd5; 545 } *iodpp; 546 547 frame = (struct el_common *)la_ptr; 548 iodpp = (struct IOD_subpacket *) (la_ptr + frame->sys_offset); 549 550 for (hose = hose_head; hose; hose = hose->next, iodpp++) { 551 552 printk("IOD %d Register Subpacket - Bridge Base Address %16lx\n", 553 hose->index, iodpp->base); 554 printk(" WHOAMI = %8x\n", iodpp->whoami); 555 printk(" PCI_REV = %8x\n", iodpp->pci_rev); 556 printk(" CAP_CTRL = %8x\n", iodpp->cap_ctrl); 557 printk(" HAE_MEM = %8x\n", iodpp->hae_mem); 558 printk(" HAE_IO = %8x\n", iodpp->hae_io); 559 printk(" INT_CTL = %8x\n", iodpp->int_ctl); 560 printk(" INT_REG = %8x\n", iodpp->int_reg); 561 printk(" INT_MASK0 = %8x\n", iodpp->int_mask0); 562 printk(" INT_MASK1 = %8x\n", iodpp->int_mask1); 563 printk(" MC_ERR0 = %8x\n", iodpp->mc_err0); 564 printk(" MC_ERR1 = %8x\n", iodpp->mc_err1); 565 printk(" CAP_ERR = %8x\n", iodpp->cap_err); 566 printk(" PCI_ERR1 = %8x\n", iodpp->pci_err1); 567 printk(" MDPA_STAT = %8x\n", iodpp->mdpa_stat); 568 printk(" MDPA_SYN = %8x\n", iodpp->mdpa_syn); 569 printk(" MDPB_STAT = %8x\n", iodpp->mdpb_stat); 570 printk(" MDPB_SYN = %8x\n", iodpp->mdpb_syn); 571 } 572 } 573 574 void 575 mcpcia_machine_check(unsigned long vector, unsigned long la_ptr, 576 struct pt_regs * regs) 577 { 578 struct el_common *mchk_header; 579 struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout; 580 unsigned int cpu = smp_processor_id(); 581 int expected; 582 583 mchk_header = (struct el_common *)la_ptr; 584 mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr; 585 expected = mcheck_expected(cpu); 586 587 mb(); 588 mb(); /* magic */ 589 draina(); 590 591 switch (expected) { 592 case 0: 593 { 594 /* FIXME: how do we figure out which hose the 595 error was on? */ 596 struct pci_controller *hose; 597 for (hose = hose_head; hose; hose = hose->next) 598 mcpcia_pci_clr_err(MCPCIA_HOSE2MID(hose->index)); 599 break; 600 } 601 case 1: 602 mcpcia_pci_clr_err(mcheck_extra(cpu)); 603 break; 604 default: 605 /* Otherwise, we're being called from mcpcia_probe_hose 606 and there's no hose clear an error from. */ 607 break; 608 } 609 610 wrmces(0x7); 611 mb(); 612 613 process_mcheck_info(vector, la_ptr, regs, "MCPCIA", expected != 0); 614 if (!expected && vector != 0x620 && vector != 0x630) { 615 mcpcia_print_uncorrectable(mchk_logout); 616 mcpcia_print_system_area(la_ptr); 617 } 618 } 619