1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/include/asm/pgtable-3level.h 4 * 5 * Copyright (C) 2011 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 #ifndef _ASM_PGTABLE_3LEVEL_H 9 #define _ASM_PGTABLE_3LEVEL_H 10 11 /* 12 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of 13 * 8 bytes each, occupying a 4K page. The first level table covers a range of 14 * 512GB, each entry representing 1GB. Since we are limited to 4GB input 15 * address range, only 4 entries in the PGD are used. 16 * 17 * There are enough spare bits in a page table entry for the kernel specific 18 * state. 19 */ 20 #define PTRS_PER_PTE 512 21 #define PTRS_PER_PMD 512 22 #define PTRS_PER_PGD 4 23 24 #define PTE_HWTABLE_PTRS (0) 25 #define PTE_HWTABLE_OFF (0) 26 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64)) 27 28 #define MAX_POSSIBLE_PHYSMEM_BITS 40 29 30 /* 31 * PGDIR_SHIFT determines the size a top-level page table entry can map. 32 */ 33 #define PGDIR_SHIFT 30 34 35 /* 36 * PMD_SHIFT determines the size a middle-level page table entry can map. 37 */ 38 #define PMD_SHIFT 21 39 40 #define PMD_SIZE (1UL << PMD_SHIFT) 41 #define PMD_MASK (~((1 << PMD_SHIFT) - 1)) 42 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 43 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1)) 44 45 /* 46 * section address mask and size definitions. 47 */ 48 #define SECTION_SHIFT 21 49 #define SECTION_SIZE (1UL << SECTION_SHIFT) 50 #define SECTION_MASK (~((1 << SECTION_SHIFT) - 1)) 51 52 #define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE) 53 54 /* 55 * Hugetlb definitions. 56 */ 57 #define HPAGE_SHIFT PMD_SHIFT 58 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) 59 #define HPAGE_MASK (~(HPAGE_SIZE - 1)) 60 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) 61 62 /* 63 * "Linux" PTE definitions for LPAE. 64 * 65 * These bits overlap with the hardware bits but the naming is preserved for 66 * consistency with the classic page table format. 67 */ 68 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ 69 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */ 70 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ 71 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ 72 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */ 73 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ 74 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) 75 #define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) 76 #define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */ 77 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */ 78 79 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0) 80 #define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55) 81 #define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57) 82 #define L_PMD_SECT_RDONLY (_AT(pteval_t, 1) << 58) 83 84 /* 85 * To be used in assembly code with the upper page attributes. 86 */ 87 #define L_PTE_XN_HIGH (1 << (54 - 32)) 88 #define L_PTE_DIRTY_HIGH (1 << (55 - 32)) 89 90 /* 91 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). 92 */ 93 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */ 94 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 95 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */ 96 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 97 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */ 98 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */ 99 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */ 100 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */ 101 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */ 102 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2) 103 104 /* 105 * Software PGD flags. 106 */ 107 #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */ 108 109 #ifndef __ASSEMBLY__ 110 111 #define pud_none(pud) (!pud_val(pud)) 112 #define pud_bad(pud) (!(pud_val(pud) & 2)) 113 #define pud_present(pud) (pud_val(pud)) 114 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 115 PMD_TYPE_TABLE) 116 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ 117 PMD_TYPE_SECT) 118 #define pmd_large(pmd) pmd_sect(pmd) 119 #define pmd_leaf(pmd) pmd_sect(pmd) 120 121 #define pud_clear(pudp) \ 122 do { \ 123 *pudp = __pud(0); \ 124 clean_pmd_entry(pudp); \ 125 } while (0) 126 127 #define set_pud(pudp, pud) \ 128 do { \ 129 *pudp = pud; \ 130 flush_pmd_entry(pudp); \ 131 } while (0) 132 133 static inline pmd_t *pud_page_vaddr(pud_t pud) 134 { 135 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK); 136 } 137 138 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2)) 139 140 #define copy_pmd(pmdpd,pmdps) \ 141 do { \ 142 *pmdpd = *pmdps; \ 143 flush_pmd_entry(pmdpd); \ 144 } while (0) 145 146 #define pmd_clear(pmdp) \ 147 do { \ 148 *pmdp = __pmd(0); \ 149 clean_pmd_entry(pmdp); \ 150 } while (0) 151 152 /* 153 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes 154 * that are written to a page table but not for ptes created with mk_pte. 155 * 156 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to 157 * hugetlb_cow, where it is compared with an entry in a page table. 158 * This comparison test fails erroneously leading ultimately to a memory leak. 159 * 160 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is 161 * present before running the comparison. 162 */ 163 #define __HAVE_ARCH_PTE_SAME 164 #define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \ 165 : pte_val(pte_a)) \ 166 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \ 167 : pte_val(pte_b))) 168 169 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext))) 170 171 #define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT)) 172 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) 173 174 #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \ 175 : !!(pmd_val(pmd) & (val))) 176 #define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val))) 177 178 #define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID)) 179 #define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF)) 180 #define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL)) 181 static inline pte_t pte_mkspecial(pte_t pte) 182 { 183 pte_val(pte) |= L_PTE_SPECIAL; 184 return pte; 185 } 186 187 #define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY)) 188 #define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY)) 189 190 #define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd)) 191 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) 192 193 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 194 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd)) 195 #endif 196 197 #define PMD_BIT_FUNC(fn,op) \ 198 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; } 199 200 PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY); 201 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF); 202 PMD_BIT_FUNC(mkwrite, &= ~L_PMD_SECT_RDONLY); 203 PMD_BIT_FUNC(mkdirty, |= L_PMD_SECT_DIRTY); 204 PMD_BIT_FUNC(mkclean, &= ~L_PMD_SECT_DIRTY); 205 PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF); 206 207 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) 208 209 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) 210 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) 211 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 212 213 /* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */ 214 #define pmdp_establish generic_pmdp_establish 215 216 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */ 217 static inline pmd_t pmd_mkinvalid(pmd_t pmd) 218 { 219 return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID); 220 } 221 222 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) 223 { 224 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY | 225 L_PMD_SECT_VALID | L_PMD_SECT_NONE; 226 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask); 227 return pmd; 228 } 229 230 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, 231 pmd_t *pmdp, pmd_t pmd) 232 { 233 BUG_ON(addr >= TASK_SIZE); 234 235 /* create a faulting entry if PROT_NONE protected */ 236 if (pmd_val(pmd) & L_PMD_SECT_NONE) 237 pmd_val(pmd) &= ~L_PMD_SECT_VALID; 238 239 if (pmd_write(pmd) && pmd_dirty(pmd)) 240 pmd_val(pmd) &= ~PMD_SECT_AP2; 241 else 242 pmd_val(pmd) |= PMD_SECT_AP2; 243 244 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG); 245 flush_pmd_entry(pmdp); 246 } 247 248 #endif /* __ASSEMBLY__ */ 249 250 #endif /* _ASM_PGTABLE_3LEVEL_H */ 251