1 /* 2 * Copyright (C) 2017 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_DAIFFLAGS_H 17 #define __ASM_DAIFFLAGS_H 18 19 #include <linux/irqflags.h> 20 21 #include <asm/arch_gicv3.h> 22 #include <asm/cpufeature.h> 23 24 #define DAIF_PROCCTX 0 25 #define DAIF_PROCCTX_NOIRQ PSR_I_BIT 26 #define DAIF_ERRCTX (PSR_I_BIT | PSR_A_BIT) 27 28 /* mask/save/unmask/restore all exceptions, including interrupts. */ 29 static inline void local_daif_mask(void) 30 { 31 asm volatile( 32 "msr daifset, #0xf // local_daif_mask\n" 33 : 34 : 35 : "memory"); 36 37 /* Don't really care for a dsb here, we don't intend to enable IRQs */ 38 if (system_uses_irq_prio_masking()) 39 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 40 41 trace_hardirqs_off(); 42 } 43 44 static inline unsigned long local_daif_save(void) 45 { 46 unsigned long flags; 47 48 flags = read_sysreg(daif); 49 50 if (system_uses_irq_prio_masking()) { 51 /* If IRQs are masked with PMR, reflect it in the flags */ 52 if (read_sysreg_s(SYS_ICC_PMR_EL1) != GIC_PRIO_IRQON) 53 flags |= PSR_I_BIT; 54 } 55 56 local_daif_mask(); 57 58 return flags; 59 } 60 61 static inline void local_daif_restore(unsigned long flags) 62 { 63 bool irq_disabled = flags & PSR_I_BIT; 64 65 if (!irq_disabled) { 66 trace_hardirqs_on(); 67 68 if (system_uses_irq_prio_masking()) { 69 gic_write_pmr(GIC_PRIO_IRQON); 70 dsb(sy); 71 } 72 } else if (system_uses_irq_prio_masking()) { 73 u64 pmr; 74 75 if (!(flags & PSR_A_BIT)) { 76 /* 77 * If interrupts are disabled but we can take 78 * asynchronous errors, we can take NMIs 79 */ 80 flags &= ~PSR_I_BIT; 81 pmr = GIC_PRIO_IRQOFF; 82 } else { 83 pmr = GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET; 84 } 85 86 /* 87 * There has been concern that the write to daif 88 * might be reordered before this write to PMR. 89 * From the ARM ARM DDI 0487D.a, section D1.7.1 90 * "Accessing PSTATE fields": 91 * Writes to the PSTATE fields have side-effects on 92 * various aspects of the PE operation. All of these 93 * side-effects are guaranteed: 94 * - Not to be visible to earlier instructions in 95 * the execution stream. 96 * - To be visible to later instructions in the 97 * execution stream 98 * 99 * Also, writes to PMR are self-synchronizing, so no 100 * interrupts with a lower priority than PMR is signaled 101 * to the PE after the write. 102 * 103 * So we don't need additional synchronization here. 104 */ 105 gic_write_pmr(pmr); 106 } 107 108 write_sysreg(flags, daif); 109 110 if (irq_disabled) 111 trace_hardirqs_off(); 112 } 113 114 #endif 115