1*fe005201SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*fe005201SGregory CLEMENT/* 3*fe005201SGregory CLEMENT * Copyright (c) 2018 Microsemi Corporation 4*fe005201SGregory CLEMENT */ 5*fe005201SGregory CLEMENT 6*fe005201SGregory CLEMENT/ { 7*fe005201SGregory CLEMENT #address-cells = <1>; 8*fe005201SGregory CLEMENT #size-cells = <1>; 9*fe005201SGregory CLEMENT compatible = "mscc,serval"; 10*fe005201SGregory CLEMENT 11*fe005201SGregory CLEMENT cpus { 12*fe005201SGregory CLEMENT #address-cells = <1>; 13*fe005201SGregory CLEMENT #size-cells = <0>; 14*fe005201SGregory CLEMENT 15*fe005201SGregory CLEMENT cpu@0 { 16*fe005201SGregory CLEMENT compatible = "mips,mips24KEc"; 17*fe005201SGregory CLEMENT device_type = "cpu"; 18*fe005201SGregory CLEMENT clocks = <&cpu_clk>; 19*fe005201SGregory CLEMENT reg = <0>; 20*fe005201SGregory CLEMENT }; 21*fe005201SGregory CLEMENT }; 22*fe005201SGregory CLEMENT 23*fe005201SGregory CLEMENT aliases { 24*fe005201SGregory CLEMENT serial0 = &uart0; 25*fe005201SGregory CLEMENT gpio0 = &gpio; 26*fe005201SGregory CLEMENT }; 27*fe005201SGregory CLEMENT 28*fe005201SGregory CLEMENT cpuintc: interrupt-controller { 29*fe005201SGregory CLEMENT #address-cells = <0>; 30*fe005201SGregory CLEMENT #interrupt-cells = <1>; 31*fe005201SGregory CLEMENT interrupt-controller; 32*fe005201SGregory CLEMENT compatible = "mti,cpu-interrupt-controller"; 33*fe005201SGregory CLEMENT }; 34*fe005201SGregory CLEMENT 35*fe005201SGregory CLEMENT cpu_clk: cpu-clock { 36*fe005201SGregory CLEMENT compatible = "fixed-clock"; 37*fe005201SGregory CLEMENT #clock-cells = <0>; 38*fe005201SGregory CLEMENT clock-frequency = <416666666>; 39*fe005201SGregory CLEMENT }; 40*fe005201SGregory CLEMENT 41*fe005201SGregory CLEMENT ahb_clk: ahb-clk { 42*fe005201SGregory CLEMENT compatible = "fixed-factor-clock"; 43*fe005201SGregory CLEMENT #clock-cells = <0>; 44*fe005201SGregory CLEMENT clocks = <&cpu_clk>; 45*fe005201SGregory CLEMENT clock-div = <2>; 46*fe005201SGregory CLEMENT clock-mult = <1>; 47*fe005201SGregory CLEMENT }; 48*fe005201SGregory CLEMENT 49*fe005201SGregory CLEMENT ahb: ahb { 50*fe005201SGregory CLEMENT compatible = "simple-bus"; 51*fe005201SGregory CLEMENT #address-cells = <1>; 52*fe005201SGregory CLEMENT #size-cells = <1>; 53*fe005201SGregory CLEMENT ranges; 54*fe005201SGregory CLEMENT 55*fe005201SGregory CLEMENT interrupt-parent = <&intc>; 56*fe005201SGregory CLEMENT 57*fe005201SGregory CLEMENT cpu_ctrl: syscon@70000000 { 58*fe005201SGregory CLEMENT compatible = "mscc,ocelot-cpu-syscon", "syscon"; 59*fe005201SGregory CLEMENT reg = <0x70000000 0x2c>; 60*fe005201SGregory CLEMENT }; 61*fe005201SGregory CLEMENT 62*fe005201SGregory CLEMENT intc: interrupt-controller@70000070 { 63*fe005201SGregory CLEMENT compatible = "mscc,serval-icpu-intr"; 64*fe005201SGregory CLEMENT reg = <0x70000070 0x70>; 65*fe005201SGregory CLEMENT #interrupt-cells = <1>; 66*fe005201SGregory CLEMENT interrupt-controller; 67*fe005201SGregory CLEMENT interrupt-parent = <&cpuintc>; 68*fe005201SGregory CLEMENT interrupts = <2>; 69*fe005201SGregory CLEMENT }; 70*fe005201SGregory CLEMENT 71*fe005201SGregory CLEMENT uart0: serial@70100000 { 72*fe005201SGregory CLEMENT pinctrl-0 = <&uart_pins>; 73*fe005201SGregory CLEMENT pinctrl-names = "default"; 74*fe005201SGregory CLEMENT compatible = "ns16550a"; 75*fe005201SGregory CLEMENT reg = <0x70100000 0x20>; 76*fe005201SGregory CLEMENT interrupts = <6>; 77*fe005201SGregory CLEMENT clocks = <&ahb_clk>; 78*fe005201SGregory CLEMENT reg-io-width = <4>; 79*fe005201SGregory CLEMENT reg-shift = <2>; 80*fe005201SGregory CLEMENT 81*fe005201SGregory CLEMENT status = "disabled"; 82*fe005201SGregory CLEMENT }; 83*fe005201SGregory CLEMENT 84*fe005201SGregory CLEMENT uart2: serial@70100800 { 85*fe005201SGregory CLEMENT pinctrl-0 = <&uart2_pins>; 86*fe005201SGregory CLEMENT pinctrl-names = "default"; 87*fe005201SGregory CLEMENT compatible = "ns16550a"; 88*fe005201SGregory CLEMENT reg = <0x70100800 0x20>; 89*fe005201SGregory CLEMENT interrupts = <7>; 90*fe005201SGregory CLEMENT clocks = <&ahb_clk>; 91*fe005201SGregory CLEMENT reg-io-width = <4>; 92*fe005201SGregory CLEMENT reg-shift = <2>; 93*fe005201SGregory CLEMENT 94*fe005201SGregory CLEMENT status = "disabled"; 95*fe005201SGregory CLEMENT }; 96*fe005201SGregory CLEMENT 97*fe005201SGregory CLEMENT gpio: pinctrl@71070034 { 98*fe005201SGregory CLEMENT compatible = "mscc,serval-pinctrl"; 99*fe005201SGregory CLEMENT reg = <0x71070034 0x28>; 100*fe005201SGregory CLEMENT gpio-controller; 101*fe005201SGregory CLEMENT #gpio-cells = <2>; 102*fe005201SGregory CLEMENT gpio-ranges = <&gpio 0 0 22>; 103*fe005201SGregory CLEMENT 104*fe005201SGregory CLEMENT sgpio_pins: sgpio-pins { 105*fe005201SGregory CLEMENT pins = "GPIO_0", "GPIO_2", "GPIO_3", "GPIO_1"; 106*fe005201SGregory CLEMENT function = "sg0"; 107*fe005201SGregory CLEMENT }; 108*fe005201SGregory CLEMENT 109*fe005201SGregory CLEMENT i2c_pins: i2c-pins { 110*fe005201SGregory CLEMENT pins = "GPIO_6", "GPIO_7"; 111*fe005201SGregory CLEMENT function = "twi"; 112*fe005201SGregory CLEMENT }; 113*fe005201SGregory CLEMENT 114*fe005201SGregory CLEMENT uart_pins: uart-pins { 115*fe005201SGregory CLEMENT pins = "GPIO_26", "GPIO_27"; 116*fe005201SGregory CLEMENT function = "uart"; 117*fe005201SGregory CLEMENT }; 118*fe005201SGregory CLEMENT 119*fe005201SGregory CLEMENT uart2_pins: uart2-pins { 120*fe005201SGregory CLEMENT pins = "GPIO_13", "GPIO_14"; 121*fe005201SGregory CLEMENT function = "uart2"; 122*fe005201SGregory CLEMENT }; 123*fe005201SGregory CLEMENT 124*fe005201SGregory CLEMENT cs1_pins: cs1-pins { 125*fe005201SGregory CLEMENT pins = "GPIO_8"; 126*fe005201SGregory CLEMENT function = "si"; 127*fe005201SGregory CLEMENT }; 128*fe005201SGregory CLEMENT 129*fe005201SGregory CLEMENT irqext0_pins: irqext0-pins { 130*fe005201SGregory CLEMENT pins = "GPIO_28"; 131*fe005201SGregory CLEMENT function = "irq0"; 132*fe005201SGregory CLEMENT }; 133*fe005201SGregory CLEMENT 134*fe005201SGregory CLEMENT irqext1_pins: irqext1-pins { 135*fe005201SGregory CLEMENT pins = "GPIO_29"; 136*fe005201SGregory CLEMENT function = "irq1"; 137*fe005201SGregory CLEMENT }; 138*fe005201SGregory CLEMENT }; 139*fe005201SGregory CLEMENT 140*fe005201SGregory CLEMENT i2c0: i2c@70100400 { 141*fe005201SGregory CLEMENT compatible = "mscc,ocelot-i2c", "snps,designware-i2c"; 142*fe005201SGregory CLEMENT status = "disabled"; 143*fe005201SGregory CLEMENT pinctrl-0 = <&i2c_pins>; 144*fe005201SGregory CLEMENT pinctrl-names = "default"; 145*fe005201SGregory CLEMENT reg = <0x70100400 0x100>, <0x70000190 0x8>; 146*fe005201SGregory CLEMENT #address-cells = <1>; 147*fe005201SGregory CLEMENT #size-cells = <0>; 148*fe005201SGregory CLEMENT interrupts = <8>; 149*fe005201SGregory CLEMENT clock-frequency = <100000>; 150*fe005201SGregory CLEMENT clocks = <&ahb_clk>; 151*fe005201SGregory CLEMENT }; 152*fe005201SGregory CLEMENT }; 153*fe005201SGregory CLEMENT}; 154