1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright IBM Corp. 2004, 2011
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
6 * Thomas Spatzier <tspat@de.ibm.com>,
7 *
8 * This file contains interrupt related functions.
9 */
10
11 #include <linux/kernel_stat.h>
12 #include <linux/interrupt.h>
13 #include <linux/seq_file.h>
14 #include <linux/proc_fs.h>
15 #include <linux/profile.h>
16 #include <linux/export.h>
17 #include <linux/kernel.h>
18 #include <linux/ftrace.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/init.h>
22 #include <linux/cpu.h>
23 #include <linux/irq.h>
24 #include <linux/entry-common.h>
25 #include <asm/irq_regs.h>
26 #include <asm/cputime.h>
27 #include <asm/lowcore.h>
28 #include <asm/irq.h>
29 #include <asm/hw_irq.h>
30 #include <asm/stacktrace.h>
31 #include <asm/softirq_stack.h>
32 #include <asm/vtime.h>
33 #include "entry.h"
34
35 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
36 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
37
38 struct irq_class {
39 int irq;
40 char *name;
41 char *desc;
42 };
43
44 /*
45 * The list of "main" irq classes on s390. This is the list of interrupts
46 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
47 * Historically only external and I/O interrupts have been part of /proc/stat.
48 * We can't add the split external and I/O sub classes since the first field
49 * in the "intr" line in /proc/stat is supposed to be the sum of all other
50 * fields.
51 * Since the external and I/O interrupt fields are already sums we would end
52 * up with having a sum which accounts each interrupt twice.
53 */
54 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
55 {.irq = EXT_INTERRUPT, .name = "EXT"},
56 {.irq = IO_INTERRUPT, .name = "I/O"},
57 {.irq = THIN_INTERRUPT, .name = "AIO"},
58 };
59
60 /*
61 * The list of split external and I/O interrupts that appear only in
62 * /proc/interrupts.
63 * In addition this list contains non external / I/O events like NMIs.
64 */
65 static const struct irq_class irqclass_sub_desc[] = {
66 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
67 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
68 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
69 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
70 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
71 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
72 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
73 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
74 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
75 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
76 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
77 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
78 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
79 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"},
80 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
81 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
82 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
83 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
84 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
85 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
86 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
87 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
88 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
89 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
90 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
91 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
92 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
93 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
94 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
95 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
96 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
97 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
98 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
99 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
100 };
101
do_IRQ(struct pt_regs * regs,int irq)102 static void do_IRQ(struct pt_regs *regs, int irq)
103 {
104 if (tod_after_eq(get_lowcore()->int_clock,
105 get_lowcore()->clock_comparator))
106 /* Serve timer interrupts first. */
107 clock_comparator_work();
108 generic_handle_irq(irq);
109 }
110
on_async_stack(void)111 static int on_async_stack(void)
112 {
113 unsigned long frame = current_frame_address();
114
115 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0;
116 }
117
do_irq_async(struct pt_regs * regs,int irq)118 static void do_irq_async(struct pt_regs *regs, int irq)
119 {
120 if (on_async_stack()) {
121 do_IRQ(regs, irq);
122 } else {
123 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ,
124 struct pt_regs *, regs, int, irq);
125 }
126 }
127
irq_pending(struct pt_regs * regs)128 static int irq_pending(struct pt_regs *regs)
129 {
130 int cc;
131
132 asm volatile("tpi 0\n"
133 "ipm %0" : "=d" (cc) : : "cc");
134 return cc >> 28;
135 }
136
do_io_irq(struct pt_regs * regs)137 void noinstr do_io_irq(struct pt_regs *regs)
138 {
139 irqentry_state_t state = irqentry_enter(regs);
140 struct pt_regs *old_regs = set_irq_regs(regs);
141 bool from_idle;
142
143 irq_enter_rcu();
144
145 if (user_mode(regs)) {
146 update_timer_sys();
147 if (static_branch_likely(&cpu_has_bear))
148 current->thread.last_break = regs->last_break;
149 }
150
151 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
152 if (from_idle)
153 account_idle_time_irq();
154
155 set_cpu_flag(CIF_NOHZ_DELAY);
156 do {
157 regs->tpi_info = get_lowcore()->tpi_info;
158 if (get_lowcore()->tpi_info.adapter_IO)
159 do_irq_async(regs, THIN_INTERRUPT);
160 else
161 do_irq_async(regs, IO_INTERRUPT);
162 } while (MACHINE_IS_LPAR && irq_pending(regs));
163
164 irq_exit_rcu();
165
166 set_irq_regs(old_regs);
167 irqentry_exit(regs, state);
168
169 if (from_idle)
170 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
171 }
172
do_ext_irq(struct pt_regs * regs)173 void noinstr do_ext_irq(struct pt_regs *regs)
174 {
175 irqentry_state_t state = irqentry_enter(regs);
176 struct pt_regs *old_regs = set_irq_regs(regs);
177 bool from_idle;
178
179 irq_enter_rcu();
180
181 if (user_mode(regs)) {
182 update_timer_sys();
183 if (static_branch_likely(&cpu_has_bear))
184 current->thread.last_break = regs->last_break;
185 }
186
187 regs->int_code = get_lowcore()->ext_int_code_addr;
188 regs->int_parm = get_lowcore()->ext_params;
189 regs->int_parm_long = get_lowcore()->ext_params2;
190
191 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
192 if (from_idle)
193 account_idle_time_irq();
194
195 do_irq_async(regs, EXT_INTERRUPT);
196
197 irq_exit_rcu();
198 set_irq_regs(old_regs);
199 irqentry_exit(regs, state);
200
201 if (from_idle)
202 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
203 }
204
show_msi_interrupt(struct seq_file * p,int irq)205 static void show_msi_interrupt(struct seq_file *p, int irq)
206 {
207 struct irq_desc *desc;
208 unsigned long flags;
209 int cpu;
210
211 rcu_read_lock();
212 desc = irq_to_desc(irq);
213 if (!desc)
214 goto out;
215
216 raw_spin_lock_irqsave(&desc->lock, flags);
217 seq_printf(p, "%3d: ", irq);
218 for_each_online_cpu(cpu)
219 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu));
220
221 if (desc->irq_data.chip)
222 seq_printf(p, " %8s", desc->irq_data.chip->name);
223
224 if (desc->action)
225 seq_printf(p, " %s", desc->action->name);
226
227 seq_putc(p, '\n');
228 raw_spin_unlock_irqrestore(&desc->lock, flags);
229 out:
230 rcu_read_unlock();
231 }
232
233 /*
234 * show_interrupts is needed by /proc/interrupts.
235 */
show_interrupts(struct seq_file * p,void * v)236 int show_interrupts(struct seq_file *p, void *v)
237 {
238 int index = *(loff_t *) v;
239 int cpu, irq;
240
241 cpus_read_lock();
242 if (index == 0) {
243 seq_puts(p, " ");
244 for_each_online_cpu(cpu)
245 seq_printf(p, "CPU%-8d", cpu);
246 seq_putc(p, '\n');
247 }
248 if (index < NR_IRQS_BASE) {
249 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
250 irq = irqclass_main_desc[index].irq;
251 for_each_online_cpu(cpu)
252 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
253 seq_putc(p, '\n');
254 goto out;
255 }
256 if (index < nr_irqs) {
257 show_msi_interrupt(p, index);
258 goto out;
259 }
260 for (index = 0; index < NR_ARCH_IRQS; index++) {
261 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
262 irq = irqclass_sub_desc[index].irq;
263 for_each_online_cpu(cpu)
264 seq_printf(p, "%10u ",
265 per_cpu(irq_stat, cpu).irqs[irq]);
266 if (irqclass_sub_desc[index].desc)
267 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
268 seq_putc(p, '\n');
269 }
270 out:
271 cpus_read_unlock();
272 return 0;
273 }
274
arch_dynirq_lower_bound(unsigned int from)275 unsigned int arch_dynirq_lower_bound(unsigned int from)
276 {
277 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
278 }
279
280 /*
281 * ext_int_hash[index] is the list head for all external interrupts that hash
282 * to this index.
283 */
284 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
285
286 struct ext_int_info {
287 ext_int_handler_t handler;
288 struct hlist_node entry;
289 struct rcu_head rcu;
290 u16 code;
291 };
292
293 /* ext_int_hash_lock protects the handler lists for external interrupts */
294 static DEFINE_SPINLOCK(ext_int_hash_lock);
295
ext_hash(u16 code)296 static inline int ext_hash(u16 code)
297 {
298 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
299
300 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
301 }
302
register_external_irq(u16 code,ext_int_handler_t handler)303 int register_external_irq(u16 code, ext_int_handler_t handler)
304 {
305 struct ext_int_info *p;
306 unsigned long flags;
307 int index;
308
309 p = kmalloc(sizeof(*p), GFP_ATOMIC);
310 if (!p)
311 return -ENOMEM;
312 p->code = code;
313 p->handler = handler;
314 index = ext_hash(code);
315
316 spin_lock_irqsave(&ext_int_hash_lock, flags);
317 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
318 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
319 return 0;
320 }
321 EXPORT_SYMBOL(register_external_irq);
322
unregister_external_irq(u16 code,ext_int_handler_t handler)323 int unregister_external_irq(u16 code, ext_int_handler_t handler)
324 {
325 struct ext_int_info *p;
326 unsigned long flags;
327 int index = ext_hash(code);
328
329 spin_lock_irqsave(&ext_int_hash_lock, flags);
330 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
331 if (p->code == code && p->handler == handler) {
332 hlist_del_rcu(&p->entry);
333 kfree_rcu(p, rcu);
334 }
335 }
336 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
337 return 0;
338 }
339 EXPORT_SYMBOL(unregister_external_irq);
340
do_ext_interrupt(int irq,void * dummy)341 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
342 {
343 struct pt_regs *regs = get_irq_regs();
344 struct ext_code ext_code;
345 struct ext_int_info *p;
346 int index;
347
348 ext_code.int_code = regs->int_code;
349 if (ext_code.code != EXT_IRQ_CLK_COMP)
350 set_cpu_flag(CIF_NOHZ_DELAY);
351
352 index = ext_hash(ext_code.code);
353 rcu_read_lock();
354 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
355 if (unlikely(p->code != ext_code.code))
356 continue;
357 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
358 }
359 rcu_read_unlock();
360 return IRQ_HANDLED;
361 }
362
init_ext_interrupts(void)363 static void __init init_ext_interrupts(void)
364 {
365 int idx;
366
367 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
368 INIT_HLIST_HEAD(&ext_int_hash[idx]);
369
370 irq_set_chip_and_handler(EXT_INTERRUPT,
371 &dummy_irq_chip, handle_percpu_irq);
372 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
373 panic("Failed to register EXT interrupt\n");
374 }
375
init_IRQ(void)376 void __init init_IRQ(void)
377 {
378 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
379 init_cio_interrupts();
380 init_airq_interrupts();
381 init_ext_interrupts();
382 }
383
384 static DEFINE_SPINLOCK(irq_subclass_lock);
385 static unsigned char irq_subclass_refcount[64];
386
irq_subclass_register(enum irq_subclass subclass)387 void irq_subclass_register(enum irq_subclass subclass)
388 {
389 spin_lock(&irq_subclass_lock);
390 if (!irq_subclass_refcount[subclass])
391 system_ctl_set_bit(0, subclass);
392 irq_subclass_refcount[subclass]++;
393 spin_unlock(&irq_subclass_lock);
394 }
395 EXPORT_SYMBOL(irq_subclass_register);
396
irq_subclass_unregister(enum irq_subclass subclass)397 void irq_subclass_unregister(enum irq_subclass subclass)
398 {
399 spin_lock(&irq_subclass_lock);
400 irq_subclass_refcount[subclass]--;
401 if (!irq_subclass_refcount[subclass])
402 system_ctl_clear_bit(0, subclass);
403 spin_unlock(&irq_subclass_lock);
404 }
405 EXPORT_SYMBOL(irq_subclass_unregister);
406