1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/desc.h> 64 #include <asm/nmi.h> 65 #include <asm/irq.h> 66 #include <asm/realmode.h> 67 #include <asm/cpu.h> 68 #include <asm/numa.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/api.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 #include <asm/stackprotector.h> 86 #include <asm/sev.h> 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 /* representing HT, core, and die siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* Logical package management. We might want to allocate that dynamically */ 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 static unsigned int logical_packages __read_mostly; 108 static unsigned int logical_die __read_mostly; 109 110 /* Maximum number of SMT threads on any online core */ 111 int __read_mostly __max_smt_threads = 1; 112 113 /* Flag to indicate if a complete sched domain rebuild is required */ 114 bool x86_topology_update; 115 116 int arch_update_cpu_topology(void) 117 { 118 int retval = x86_topology_update; 119 120 x86_topology_update = false; 121 return retval; 122 } 123 124 125 static unsigned int smpboot_warm_reset_vector_count; 126 127 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 128 { 129 unsigned long flags; 130 131 spin_lock_irqsave(&rtc_lock, flags); 132 if (!smpboot_warm_reset_vector_count++) { 133 CMOS_WRITE(0xa, 0xf); 134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 136 } 137 spin_unlock_irqrestore(&rtc_lock, flags); 138 } 139 140 static inline void smpboot_restore_warm_reset_vector(void) 141 { 142 unsigned long flags; 143 144 /* 145 * Paranoid: Set warm reset code and vector here back 146 * to default values. 147 */ 148 spin_lock_irqsave(&rtc_lock, flags); 149 if (!--smpboot_warm_reset_vector_count) { 150 CMOS_WRITE(0, 0xf); 151 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 152 } 153 spin_unlock_irqrestore(&rtc_lock, flags); 154 155 } 156 157 /* 158 * Report back to the Boot Processor during boot time or to the caller processor 159 * during CPU online. 160 */ 161 static void smp_callin(void) 162 { 163 int cpuid; 164 165 /* 166 * If waken up by an INIT in an 82489DX configuration 167 * cpu_callout_mask guarantees we don't get here before 168 * an INIT_deassert IPI reaches our local APIC, so it is 169 * now safe to touch our local APIC. 170 */ 171 cpuid = smp_processor_id(); 172 173 /* 174 * the boot CPU has finished the init stage and is spinning 175 * on callin_map until we finish. We are free to set up this 176 * CPU, first the APIC. (this is probably redundant on most 177 * boards) 178 */ 179 apic_ap_setup(); 180 181 /* Save our processor parameters. */ 182 smp_store_cpu_info(cpuid); 183 184 /* 185 * The topology information must be up to date before 186 * notify_cpu_starting(). 187 */ 188 set_cpu_sibling_map(raw_smp_processor_id()); 189 190 ap_init_aperfmperf(); 191 192 pr_debug("Stack at about %p\n", &cpuid); 193 194 wmb(); 195 196 notify_cpu_starting(cpuid); 197 198 /* 199 * Allow the master to continue. 200 */ 201 cpumask_set_cpu(cpuid, cpu_callin_mask); 202 } 203 204 static void ap_calibrate_delay(void) 205 { 206 /* 207 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 208 * smp_store_cpu_info() stored a value that is close but not as 209 * accurate as the value just calculated. 210 * 211 * As this is invoked after the TSC synchronization check, 212 * calibrate_delay_is_known() will skip the calibration routine 213 * when TSC is synchronized across sockets. 214 */ 215 calibrate_delay(); 216 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 217 } 218 219 static int cpu0_logical_apicid; 220 static int enable_start_cpu0; 221 222 /* 223 * Activate a secondary processor. 224 */ 225 static void notrace start_secondary(void *unused) 226 { 227 /* 228 * Don't put *anything* except direct CPU state initialization 229 * before cpu_init(), SMP booting is too fragile that we want to 230 * limit the things done here to the most necessary things. 231 */ 232 cr4_init(); 233 234 #ifdef CONFIG_X86_32 235 /* switch away from the initial page table */ 236 load_cr3(swapper_pg_dir); 237 __flush_tlb_all(); 238 #endif 239 cpu_init_secondary(); 240 rcu_cpu_starting(raw_smp_processor_id()); 241 x86_cpuinit.early_percpu_clock_init(); 242 smp_callin(); 243 244 enable_start_cpu0 = 0; 245 246 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 247 barrier(); 248 /* Check TSC synchronization with the control CPU: */ 249 check_tsc_sync_target(); 250 251 /* 252 * Calibrate the delay loop after the TSC synchronization check. 253 * This allows to skip the calibration when TSC is synchronized 254 * across sockets. 255 */ 256 ap_calibrate_delay(); 257 258 speculative_store_bypass_ht_init(); 259 260 /* 261 * Lock vector_lock, set CPU online and bring the vector 262 * allocator online. Online must be set with vector_lock held 263 * to prevent a concurrent irq setup/teardown from seeing a 264 * half valid vector space. 265 */ 266 lock_vector_lock(); 267 set_cpu_online(smp_processor_id(), true); 268 lapic_online(); 269 unlock_vector_lock(); 270 cpu_set_state_online(smp_processor_id()); 271 x86_platform.nmi_init(); 272 273 /* enable local interrupts */ 274 local_irq_enable(); 275 276 x86_cpuinit.setup_percpu_clockev(); 277 278 wmb(); 279 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 280 } 281 282 /** 283 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 284 * @cpu: CPU to check 285 */ 286 bool topology_is_primary_thread(unsigned int cpu) 287 { 288 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 289 } 290 291 /** 292 * topology_smt_supported - Check whether SMT is supported by the CPUs 293 */ 294 bool topology_smt_supported(void) 295 { 296 return smp_num_siblings > 1; 297 } 298 299 /** 300 * topology_phys_to_logical_pkg - Map a physical package id to a logical 301 * @phys_pkg: The physical package id to map 302 * 303 * Returns logical package id or -1 if not found 304 */ 305 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 306 { 307 int cpu; 308 309 for_each_possible_cpu(cpu) { 310 struct cpuinfo_x86 *c = &cpu_data(cpu); 311 312 if (c->initialized && c->phys_proc_id == phys_pkg) 313 return c->logical_proc_id; 314 } 315 return -1; 316 } 317 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 318 319 /** 320 * topology_phys_to_logical_die - Map a physical die id to logical 321 * @die_id: The physical die id to map 322 * @cur_cpu: The CPU for which the mapping is done 323 * 324 * Returns logical die id or -1 if not found 325 */ 326 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 327 { 328 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 329 330 for_each_possible_cpu(cpu) { 331 struct cpuinfo_x86 *c = &cpu_data(cpu); 332 333 if (c->initialized && c->cpu_die_id == die_id && 334 c->phys_proc_id == proc_id) 335 return c->logical_die_id; 336 } 337 return -1; 338 } 339 340 /** 341 * topology_update_package_map - Update the physical to logical package map 342 * @pkg: The physical package id as retrieved via CPUID 343 * @cpu: The cpu for which this is updated 344 */ 345 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 346 { 347 int new; 348 349 /* Already available somewhere? */ 350 new = topology_phys_to_logical_pkg(pkg); 351 if (new >= 0) 352 goto found; 353 354 new = logical_packages++; 355 if (new != pkg) { 356 pr_info("CPU %u Converting physical %u to logical package %u\n", 357 cpu, pkg, new); 358 } 359 found: 360 cpu_data(cpu).logical_proc_id = new; 361 return 0; 362 } 363 /** 364 * topology_update_die_map - Update the physical to logical die map 365 * @die: The die id as retrieved via CPUID 366 * @cpu: The cpu for which this is updated 367 */ 368 int topology_update_die_map(unsigned int die, unsigned int cpu) 369 { 370 int new; 371 372 /* Already available somewhere? */ 373 new = topology_phys_to_logical_die(die, cpu); 374 if (new >= 0) 375 goto found; 376 377 new = logical_die++; 378 if (new != die) { 379 pr_info("CPU %u Converting physical %u to logical die %u\n", 380 cpu, die, new); 381 } 382 found: 383 cpu_data(cpu).logical_die_id = new; 384 return 0; 385 } 386 387 void __init smp_store_boot_cpu_info(void) 388 { 389 int id = 0; /* CPU 0 */ 390 struct cpuinfo_x86 *c = &cpu_data(id); 391 392 *c = boot_cpu_data; 393 c->cpu_index = id; 394 topology_update_package_map(c->phys_proc_id, id); 395 topology_update_die_map(c->cpu_die_id, id); 396 c->initialized = true; 397 } 398 399 /* 400 * The bootstrap kernel entry code has set these up. Save them for 401 * a given CPU 402 */ 403 void smp_store_cpu_info(int id) 404 { 405 struct cpuinfo_x86 *c = &cpu_data(id); 406 407 /* Copy boot_cpu_data only on the first bringup */ 408 if (!c->initialized) 409 *c = boot_cpu_data; 410 c->cpu_index = id; 411 /* 412 * During boot time, CPU0 has this setup already. Save the info when 413 * bringing up AP or offlined CPU0. 414 */ 415 identify_secondary_cpu(c); 416 c->initialized = true; 417 } 418 419 static bool 420 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 421 { 422 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 423 424 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 425 } 426 427 static bool 428 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 429 { 430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 431 432 return !WARN_ONCE(!topology_same_node(c, o), 433 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 434 "[node: %d != %d]. Ignoring dependency.\n", 435 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 436 } 437 438 #define link_mask(mfunc, c1, c2) \ 439 do { \ 440 cpumask_set_cpu((c1), mfunc(c2)); \ 441 cpumask_set_cpu((c2), mfunc(c1)); \ 442 } while (0) 443 444 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 445 { 446 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 447 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 448 449 if (c->phys_proc_id == o->phys_proc_id && 450 c->cpu_die_id == o->cpu_die_id && 451 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 452 if (c->cpu_core_id == o->cpu_core_id) 453 return topology_sane(c, o, "smt"); 454 455 if ((c->cu_id != 0xff) && 456 (o->cu_id != 0xff) && 457 (c->cu_id == o->cu_id)) 458 return topology_sane(c, o, "smt"); 459 } 460 461 } else if (c->phys_proc_id == o->phys_proc_id && 462 c->cpu_die_id == o->cpu_die_id && 463 c->cpu_core_id == o->cpu_core_id) { 464 return topology_sane(c, o, "smt"); 465 } 466 467 return false; 468 } 469 470 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 471 { 472 if (c->phys_proc_id == o->phys_proc_id && 473 c->cpu_die_id == o->cpu_die_id) 474 return true; 475 return false; 476 } 477 478 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 479 { 480 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 481 482 /* If the arch didn't set up l2c_id, fall back to SMT */ 483 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 484 return match_smt(c, o); 485 486 /* Do not match if L2 cache id does not match: */ 487 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 488 return false; 489 490 return topology_sane(c, o, "l2c"); 491 } 492 493 /* 494 * Unlike the other levels, we do not enforce keeping a 495 * multicore group inside a NUMA node. If this happens, we will 496 * discard the MC level of the topology later. 497 */ 498 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 499 { 500 if (c->phys_proc_id == o->phys_proc_id) 501 return true; 502 return false; 503 } 504 505 /* 506 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 507 * 508 * Any Intel CPU that has multiple nodes per package and does not 509 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 510 * 511 * When in SNC mode, these CPUs enumerate an LLC that is shared 512 * by multiple NUMA nodes. The LLC is shared for off-package data 513 * access but private to the NUMA node (half of the package) for 514 * on-package access. CPUID (the source of the information about 515 * the LLC) can only enumerate the cache as shared or unshared, 516 * but not this particular configuration. 517 */ 518 519 static const struct x86_cpu_id intel_cod_cpu[] = { 520 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 521 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 522 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 523 {} 524 }; 525 526 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 527 { 528 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 529 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 530 bool intel_snc = id && id->driver_data; 531 532 /* Do not match if we do not have a valid APICID for cpu: */ 533 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 534 return false; 535 536 /* Do not match if LLC id does not match: */ 537 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 538 return false; 539 540 /* 541 * Allow the SNC topology without warning. Return of false 542 * means 'c' does not share the LLC of 'o'. This will be 543 * reflected to userspace. 544 */ 545 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 546 return false; 547 548 return topology_sane(c, o, "llc"); 549 } 550 551 552 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 553 static inline int x86_sched_itmt_flags(void) 554 { 555 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 556 } 557 558 #ifdef CONFIG_SCHED_MC 559 static int x86_core_flags(void) 560 { 561 return cpu_core_flags() | x86_sched_itmt_flags(); 562 } 563 #endif 564 #ifdef CONFIG_SCHED_SMT 565 static int x86_smt_flags(void) 566 { 567 return cpu_smt_flags() | x86_sched_itmt_flags(); 568 } 569 #endif 570 #ifdef CONFIG_SCHED_CLUSTER 571 static int x86_cluster_flags(void) 572 { 573 return cpu_cluster_flags() | x86_sched_itmt_flags(); 574 } 575 #endif 576 #endif 577 578 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 579 #ifdef CONFIG_SCHED_SMT 580 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 581 #endif 582 #ifdef CONFIG_SCHED_CLUSTER 583 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 584 #endif 585 #ifdef CONFIG_SCHED_MC 586 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 587 #endif 588 { NULL, }, 589 }; 590 591 static struct sched_domain_topology_level x86_hybrid_topology[] = { 592 #ifdef CONFIG_SCHED_SMT 593 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 594 #endif 595 #ifdef CONFIG_SCHED_MC 596 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 597 #endif 598 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 599 { NULL, }, 600 }; 601 602 static struct sched_domain_topology_level x86_topology[] = { 603 #ifdef CONFIG_SCHED_SMT 604 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 605 #endif 606 #ifdef CONFIG_SCHED_CLUSTER 607 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 608 #endif 609 #ifdef CONFIG_SCHED_MC 610 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 611 #endif 612 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 613 { NULL, }, 614 }; 615 616 /* 617 * Set if a package/die has multiple NUMA nodes inside. 618 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 619 * Sub-NUMA Clustering have this. 620 */ 621 static bool x86_has_numa_in_package; 622 623 void set_cpu_sibling_map(int cpu) 624 { 625 bool has_smt = smp_num_siblings > 1; 626 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 627 struct cpuinfo_x86 *c = &cpu_data(cpu); 628 struct cpuinfo_x86 *o; 629 int i, threads; 630 631 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 632 633 if (!has_mp) { 634 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 635 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 636 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 637 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 638 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 639 c->booted_cores = 1; 640 return; 641 } 642 643 for_each_cpu(i, cpu_sibling_setup_mask) { 644 o = &cpu_data(i); 645 646 if (match_pkg(c, o) && !topology_same_node(c, o)) 647 x86_has_numa_in_package = true; 648 649 if ((i == cpu) || (has_smt && match_smt(c, o))) 650 link_mask(topology_sibling_cpumask, cpu, i); 651 652 if ((i == cpu) || (has_mp && match_llc(c, o))) 653 link_mask(cpu_llc_shared_mask, cpu, i); 654 655 if ((i == cpu) || (has_mp && match_l2c(c, o))) 656 link_mask(cpu_l2c_shared_mask, cpu, i); 657 658 if ((i == cpu) || (has_mp && match_die(c, o))) 659 link_mask(topology_die_cpumask, cpu, i); 660 } 661 662 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 663 if (threads > __max_smt_threads) 664 __max_smt_threads = threads; 665 666 for_each_cpu(i, topology_sibling_cpumask(cpu)) 667 cpu_data(i).smt_active = threads > 1; 668 669 /* 670 * This needs a separate iteration over the cpus because we rely on all 671 * topology_sibling_cpumask links to be set-up. 672 */ 673 for_each_cpu(i, cpu_sibling_setup_mask) { 674 o = &cpu_data(i); 675 676 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 677 link_mask(topology_core_cpumask, cpu, i); 678 679 /* 680 * Does this new cpu bringup a new core? 681 */ 682 if (threads == 1) { 683 /* 684 * for each core in package, increment 685 * the booted_cores for this new cpu 686 */ 687 if (cpumask_first( 688 topology_sibling_cpumask(i)) == i) 689 c->booted_cores++; 690 /* 691 * increment the core count for all 692 * the other cpus in this package 693 */ 694 if (i != cpu) 695 cpu_data(i).booted_cores++; 696 } else if (i != cpu && !c->booted_cores) 697 c->booted_cores = cpu_data(i).booted_cores; 698 } 699 } 700 } 701 702 /* maps the cpu to the sched domain representing multi-core */ 703 const struct cpumask *cpu_coregroup_mask(int cpu) 704 { 705 return cpu_llc_shared_mask(cpu); 706 } 707 708 const struct cpumask *cpu_clustergroup_mask(int cpu) 709 { 710 return cpu_l2c_shared_mask(cpu); 711 } 712 713 static void impress_friends(void) 714 { 715 int cpu; 716 unsigned long bogosum = 0; 717 /* 718 * Allow the user to impress friends. 719 */ 720 pr_debug("Before bogomips\n"); 721 for_each_possible_cpu(cpu) 722 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 723 bogosum += cpu_data(cpu).loops_per_jiffy; 724 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 725 num_online_cpus(), 726 bogosum/(500000/HZ), 727 (bogosum/(5000/HZ))%100); 728 729 pr_debug("Before bogocount - setting activated=1\n"); 730 } 731 732 void __inquire_remote_apic(int apicid) 733 { 734 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 735 const char * const names[] = { "ID", "VERSION", "SPIV" }; 736 int timeout; 737 u32 status; 738 739 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 740 741 for (i = 0; i < ARRAY_SIZE(regs); i++) { 742 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 743 744 /* 745 * Wait for idle. 746 */ 747 status = safe_apic_wait_icr_idle(); 748 if (status) 749 pr_cont("a previous APIC delivery may have failed\n"); 750 751 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 752 753 timeout = 0; 754 do { 755 udelay(100); 756 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 757 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 758 759 switch (status) { 760 case APIC_ICR_RR_VALID: 761 status = apic_read(APIC_RRR); 762 pr_cont("%08x\n", status); 763 break; 764 default: 765 pr_cont("failed\n"); 766 } 767 } 768 } 769 770 /* 771 * The Multiprocessor Specification 1.4 (1997) example code suggests 772 * that there should be a 10ms delay between the BSP asserting INIT 773 * and de-asserting INIT, when starting a remote processor. 774 * But that slows boot and resume on modern processors, which include 775 * many cores and don't require that delay. 776 * 777 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 778 * Modern processor families are quirked to remove the delay entirely. 779 */ 780 #define UDELAY_10MS_DEFAULT 10000 781 782 static unsigned int init_udelay = UINT_MAX; 783 784 static int __init cpu_init_udelay(char *str) 785 { 786 get_option(&str, &init_udelay); 787 788 return 0; 789 } 790 early_param("cpu_init_udelay", cpu_init_udelay); 791 792 static void __init smp_quirk_init_udelay(void) 793 { 794 /* if cmdline changed it from default, leave it alone */ 795 if (init_udelay != UINT_MAX) 796 return; 797 798 /* if modern processor, use no delay */ 799 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 800 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 801 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 802 init_udelay = 0; 803 return; 804 } 805 /* else, use legacy delay */ 806 init_udelay = UDELAY_10MS_DEFAULT; 807 } 808 809 /* 810 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 811 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 812 * won't ... remember to clear down the APIC, etc later. 813 */ 814 int 815 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 816 { 817 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 818 unsigned long send_status, accept_status = 0; 819 int maxlvt; 820 821 /* Target chip */ 822 /* Boot on the stack */ 823 /* Kick the second */ 824 apic_icr_write(APIC_DM_NMI | dm, apicid); 825 826 pr_debug("Waiting for send to finish...\n"); 827 send_status = safe_apic_wait_icr_idle(); 828 829 /* 830 * Give the other CPU some time to accept the IPI. 831 */ 832 udelay(200); 833 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 834 maxlvt = lapic_get_maxlvt(); 835 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 836 apic_write(APIC_ESR, 0); 837 accept_status = (apic_read(APIC_ESR) & 0xEF); 838 } 839 pr_debug("NMI sent\n"); 840 841 if (send_status) 842 pr_err("APIC never delivered???\n"); 843 if (accept_status) 844 pr_err("APIC delivery error (%lx)\n", accept_status); 845 846 return (send_status | accept_status); 847 } 848 849 static int 850 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 851 { 852 unsigned long send_status = 0, accept_status = 0; 853 int maxlvt, num_starts, j; 854 855 maxlvt = lapic_get_maxlvt(); 856 857 /* 858 * Be paranoid about clearing APIC errors. 859 */ 860 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 861 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 862 apic_write(APIC_ESR, 0); 863 apic_read(APIC_ESR); 864 } 865 866 pr_debug("Asserting INIT\n"); 867 868 /* 869 * Turn INIT on target chip 870 */ 871 /* 872 * Send IPI 873 */ 874 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 875 phys_apicid); 876 877 pr_debug("Waiting for send to finish...\n"); 878 send_status = safe_apic_wait_icr_idle(); 879 880 udelay(init_udelay); 881 882 pr_debug("Deasserting INIT\n"); 883 884 /* Target chip */ 885 /* Send IPI */ 886 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 887 888 pr_debug("Waiting for send to finish...\n"); 889 send_status = safe_apic_wait_icr_idle(); 890 891 mb(); 892 893 /* 894 * Should we send STARTUP IPIs ? 895 * 896 * Determine this based on the APIC version. 897 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 898 */ 899 if (APIC_INTEGRATED(boot_cpu_apic_version)) 900 num_starts = 2; 901 else 902 num_starts = 0; 903 904 /* 905 * Run STARTUP IPI loop. 906 */ 907 pr_debug("#startup loops: %d\n", num_starts); 908 909 for (j = 1; j <= num_starts; j++) { 910 pr_debug("Sending STARTUP #%d\n", j); 911 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 912 apic_write(APIC_ESR, 0); 913 apic_read(APIC_ESR); 914 pr_debug("After apic_write\n"); 915 916 /* 917 * STARTUP IPI 918 */ 919 920 /* Target chip */ 921 /* Boot on the stack */ 922 /* Kick the second */ 923 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 924 phys_apicid); 925 926 /* 927 * Give the other CPU some time to accept the IPI. 928 */ 929 if (init_udelay == 0) 930 udelay(10); 931 else 932 udelay(300); 933 934 pr_debug("Startup point 1\n"); 935 936 pr_debug("Waiting for send to finish...\n"); 937 send_status = safe_apic_wait_icr_idle(); 938 939 /* 940 * Give the other CPU some time to accept the IPI. 941 */ 942 if (init_udelay == 0) 943 udelay(10); 944 else 945 udelay(200); 946 947 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 948 apic_write(APIC_ESR, 0); 949 accept_status = (apic_read(APIC_ESR) & 0xEF); 950 if (send_status || accept_status) 951 break; 952 } 953 pr_debug("After Startup\n"); 954 955 if (send_status) 956 pr_err("APIC never delivered???\n"); 957 if (accept_status) 958 pr_err("APIC delivery error (%lx)\n", accept_status); 959 960 return (send_status | accept_status); 961 } 962 963 /* reduce the number of lines printed when booting a large cpu count system */ 964 static void announce_cpu(int cpu, int apicid) 965 { 966 static int current_node = NUMA_NO_NODE; 967 int node = early_cpu_to_node(cpu); 968 static int width, node_width; 969 970 if (!width) 971 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 972 973 if (!node_width) 974 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 975 976 if (cpu == 1) 977 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 978 979 if (system_state < SYSTEM_RUNNING) { 980 if (node != current_node) { 981 if (current_node > (-1)) 982 pr_cont("\n"); 983 current_node = node; 984 985 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 986 node_width - num_digits(node), " ", node); 987 } 988 989 /* Add padding for the BSP */ 990 if (cpu == 1) 991 pr_cont("%*s", width + 1, " "); 992 993 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 994 995 } else 996 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 997 node, cpu, apicid); 998 } 999 1000 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 1001 { 1002 int cpu; 1003 1004 cpu = smp_processor_id(); 1005 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 1006 return NMI_HANDLED; 1007 1008 return NMI_DONE; 1009 } 1010 1011 /* 1012 * Wake up AP by INIT, INIT, STARTUP sequence. 1013 * 1014 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 1015 * boot-strap code which is not a desired behavior for waking up BSP. To 1016 * void the boot-strap code, wake up CPU0 by NMI instead. 1017 * 1018 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 1019 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 1020 * We'll change this code in the future to wake up hard offlined CPU0 if 1021 * real platform and request are available. 1022 */ 1023 static int 1024 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 1025 int *cpu0_nmi_registered) 1026 { 1027 int id; 1028 int boot_error; 1029 1030 preempt_disable(); 1031 1032 /* 1033 * Wake up AP by INIT, INIT, STARTUP sequence. 1034 */ 1035 if (cpu) { 1036 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 1037 goto out; 1038 } 1039 1040 /* 1041 * Wake up BSP by nmi. 1042 * 1043 * Register a NMI handler to help wake up CPU0. 1044 */ 1045 boot_error = register_nmi_handler(NMI_LOCAL, 1046 wakeup_cpu0_nmi, 0, "wake_cpu0"); 1047 1048 if (!boot_error) { 1049 enable_start_cpu0 = 1; 1050 *cpu0_nmi_registered = 1; 1051 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 1052 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 1053 } 1054 1055 out: 1056 preempt_enable(); 1057 1058 return boot_error; 1059 } 1060 1061 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1062 { 1063 int ret; 1064 1065 /* Just in case we booted with a single CPU. */ 1066 alternatives_enable_smp(); 1067 1068 per_cpu(pcpu_hot.current_task, cpu) = idle; 1069 cpu_init_stack_canary(cpu, idle); 1070 1071 /* Initialize the interrupt stack(s) */ 1072 ret = irq_init_percpu_irqstack(cpu); 1073 if (ret) 1074 return ret; 1075 1076 #ifdef CONFIG_X86_32 1077 /* Stack for startup_32 can be just as for start_secondary onwards */ 1078 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1079 #endif 1080 return 0; 1081 } 1082 1083 /* 1084 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1085 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1086 * Returns zero if CPU booted OK, else error code from 1087 * ->wakeup_secondary_cpu. 1088 */ 1089 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1090 int *cpu0_nmi_registered) 1091 { 1092 /* start_ip had better be page-aligned! */ 1093 unsigned long start_ip = real_mode_header->trampoline_start; 1094 1095 unsigned long boot_error = 0; 1096 unsigned long timeout; 1097 1098 #ifdef CONFIG_X86_64 1099 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1100 if (apic->wakeup_secondary_cpu_64) 1101 start_ip = real_mode_header->trampoline_start64; 1102 #endif 1103 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1104 initial_code = (unsigned long)start_secondary; 1105 1106 if (IS_ENABLED(CONFIG_X86_32)) { 1107 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1108 initial_stack = idle->thread.sp; 1109 } else { 1110 smpboot_control = cpu; 1111 } 1112 1113 /* Enable the espfix hack for this CPU */ 1114 init_espfix_ap(cpu); 1115 1116 /* So we see what's up */ 1117 announce_cpu(cpu, apicid); 1118 1119 /* 1120 * This grunge runs the startup process for 1121 * the targeted processor. 1122 */ 1123 1124 if (x86_platform.legacy.warm_reset) { 1125 1126 pr_debug("Setting warm reset code and vector.\n"); 1127 1128 smpboot_setup_warm_reset_vector(start_ip); 1129 /* 1130 * Be paranoid about clearing APIC errors. 1131 */ 1132 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1133 apic_write(APIC_ESR, 0); 1134 apic_read(APIC_ESR); 1135 } 1136 } 1137 1138 /* 1139 * AP might wait on cpu_callout_mask in cpu_init() with 1140 * cpu_initialized_mask set if previous attempt to online 1141 * it timed-out. Clear cpu_initialized_mask so that after 1142 * INIT/SIPI it could start with a clean state. 1143 */ 1144 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1145 smp_mb(); 1146 1147 /* 1148 * Wake up a CPU in difference cases: 1149 * - Use a method from the APIC driver if one defined, with wakeup 1150 * straight to 64-bit mode preferred over wakeup to RM. 1151 * Otherwise, 1152 * - Use an INIT boot APIC message for APs or NMI for BSP. 1153 */ 1154 if (apic->wakeup_secondary_cpu_64) 1155 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1156 else if (apic->wakeup_secondary_cpu) 1157 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1158 else 1159 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1160 cpu0_nmi_registered); 1161 1162 if (!boot_error) { 1163 /* 1164 * Wait 10s total for first sign of life from AP 1165 */ 1166 boot_error = -1; 1167 timeout = jiffies + 10*HZ; 1168 while (time_before(jiffies, timeout)) { 1169 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1170 /* 1171 * Tell AP to proceed with initialization 1172 */ 1173 cpumask_set_cpu(cpu, cpu_callout_mask); 1174 boot_error = 0; 1175 break; 1176 } 1177 schedule(); 1178 } 1179 } 1180 1181 if (!boot_error) { 1182 /* 1183 * Wait till AP completes initial initialization 1184 */ 1185 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1186 /* 1187 * Allow other tasks to run while we wait for the 1188 * AP to come online. This also gives a chance 1189 * for the MTRR work(triggered by the AP coming online) 1190 * to be completed in the stop machine context. 1191 */ 1192 schedule(); 1193 } 1194 } 1195 1196 if (x86_platform.legacy.warm_reset) { 1197 /* 1198 * Cleanup possible dangling ends... 1199 */ 1200 smpboot_restore_warm_reset_vector(); 1201 } 1202 1203 return boot_error; 1204 } 1205 1206 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1207 { 1208 int apicid = apic->cpu_present_to_apicid(cpu); 1209 int cpu0_nmi_registered = 0; 1210 unsigned long flags; 1211 int err, ret = 0; 1212 1213 lockdep_assert_irqs_enabled(); 1214 1215 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1216 1217 if (apicid == BAD_APICID || 1218 !physid_isset(apicid, phys_cpu_present_map) || 1219 !apic->apic_id_valid(apicid)) { 1220 pr_err("%s: bad cpu %d\n", __func__, cpu); 1221 return -EINVAL; 1222 } 1223 1224 /* 1225 * Already booted CPU? 1226 */ 1227 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1228 pr_debug("do_boot_cpu %d Already started\n", cpu); 1229 return -ENOSYS; 1230 } 1231 1232 /* 1233 * Save current MTRR state in case it was changed since early boot 1234 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1235 */ 1236 mtrr_save_state(); 1237 1238 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1239 err = cpu_check_up_prepare(cpu); 1240 if (err && err != -EBUSY) 1241 return err; 1242 1243 /* the FPU context is blank, nobody can own it */ 1244 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1245 1246 err = common_cpu_up(cpu, tidle); 1247 if (err) 1248 return err; 1249 1250 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1251 if (err) { 1252 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1253 ret = -EIO; 1254 goto unreg_nmi; 1255 } 1256 1257 /* 1258 * Check TSC synchronization with the AP (keep irqs disabled 1259 * while doing so): 1260 */ 1261 local_irq_save(flags); 1262 check_tsc_sync_source(cpu); 1263 local_irq_restore(flags); 1264 1265 while (!cpu_online(cpu)) { 1266 cpu_relax(); 1267 touch_nmi_watchdog(); 1268 } 1269 1270 unreg_nmi: 1271 /* 1272 * Clean up the nmi handler. Do this after the callin and callout sync 1273 * to avoid impact of possible long unregister time. 1274 */ 1275 if (cpu0_nmi_registered) 1276 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1277 1278 return ret; 1279 } 1280 1281 /** 1282 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1283 */ 1284 void __init arch_disable_smp_support(void) 1285 { 1286 disable_ioapic_support(); 1287 } 1288 1289 /* 1290 * Fall back to non SMP mode after errors. 1291 * 1292 * RED-PEN audit/test this more. I bet there is more state messed up here. 1293 */ 1294 static __init void disable_smp(void) 1295 { 1296 pr_info("SMP disabled\n"); 1297 1298 disable_ioapic_support(); 1299 1300 init_cpu_present(cpumask_of(0)); 1301 init_cpu_possible(cpumask_of(0)); 1302 1303 if (smp_found_config) 1304 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1305 else 1306 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1307 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1308 cpumask_set_cpu(0, topology_core_cpumask(0)); 1309 cpumask_set_cpu(0, topology_die_cpumask(0)); 1310 } 1311 1312 /* 1313 * Various sanity checks. 1314 */ 1315 static void __init smp_sanity_check(void) 1316 { 1317 preempt_disable(); 1318 1319 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1320 if (def_to_bigsmp && nr_cpu_ids > 8) { 1321 unsigned int cpu; 1322 unsigned nr; 1323 1324 pr_warn("More than 8 CPUs detected - skipping them\n" 1325 "Use CONFIG_X86_BIGSMP\n"); 1326 1327 nr = 0; 1328 for_each_present_cpu(cpu) { 1329 if (nr >= 8) 1330 set_cpu_present(cpu, false); 1331 nr++; 1332 } 1333 1334 nr = 0; 1335 for_each_possible_cpu(cpu) { 1336 if (nr >= 8) 1337 set_cpu_possible(cpu, false); 1338 nr++; 1339 } 1340 1341 set_nr_cpu_ids(8); 1342 } 1343 #endif 1344 1345 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1346 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1347 hard_smp_processor_id()); 1348 1349 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1350 } 1351 1352 /* 1353 * Should not be necessary because the MP table should list the boot 1354 * CPU too, but we do it for the sake of robustness anyway. 1355 */ 1356 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1357 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1358 boot_cpu_physical_apicid); 1359 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1360 } 1361 preempt_enable(); 1362 } 1363 1364 static void __init smp_cpu_index_default(void) 1365 { 1366 int i; 1367 struct cpuinfo_x86 *c; 1368 1369 for_each_possible_cpu(i) { 1370 c = &cpu_data(i); 1371 /* mark all to hotplug */ 1372 c->cpu_index = nr_cpu_ids; 1373 } 1374 } 1375 1376 static void __init smp_get_logical_apicid(void) 1377 { 1378 if (x2apic_mode) 1379 cpu0_logical_apicid = apic_read(APIC_LDR); 1380 else 1381 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1382 } 1383 1384 void __init smp_prepare_cpus_common(void) 1385 { 1386 unsigned int i; 1387 1388 smp_cpu_index_default(); 1389 1390 /* 1391 * Setup boot CPU information 1392 */ 1393 smp_store_boot_cpu_info(); /* Final full version of the data */ 1394 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1395 mb(); 1396 1397 for_each_possible_cpu(i) { 1398 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1399 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1400 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1401 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1402 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1403 } 1404 1405 /* 1406 * Set 'default' x86 topology, this matches default_topology() in that 1407 * it has NUMA nodes as a topology level. See also 1408 * native_smp_cpus_done(). 1409 * 1410 * Must be done before set_cpus_sibling_map() is ran. 1411 */ 1412 set_sched_topology(x86_topology); 1413 1414 set_cpu_sibling_map(0); 1415 } 1416 1417 /* 1418 * Prepare for SMP bootup. 1419 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1420 * for common interface support. 1421 */ 1422 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1423 { 1424 smp_prepare_cpus_common(); 1425 1426 smp_sanity_check(); 1427 1428 switch (apic_intr_mode) { 1429 case APIC_PIC: 1430 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1431 disable_smp(); 1432 return; 1433 case APIC_SYMMETRIC_IO_NO_ROUTING: 1434 disable_smp(); 1435 /* Setup local timer */ 1436 x86_init.timers.setup_percpu_clockev(); 1437 return; 1438 case APIC_VIRTUAL_WIRE: 1439 case APIC_SYMMETRIC_IO: 1440 break; 1441 } 1442 1443 /* Setup local timer */ 1444 x86_init.timers.setup_percpu_clockev(); 1445 1446 smp_get_logical_apicid(); 1447 1448 pr_info("CPU0: "); 1449 print_cpu_info(&cpu_data(0)); 1450 1451 uv_system_init(); 1452 1453 smp_quirk_init_udelay(); 1454 1455 speculative_store_bypass_ht_init(); 1456 1457 snp_set_wakeup_secondary_cpu(); 1458 } 1459 1460 void arch_thaw_secondary_cpus_begin(void) 1461 { 1462 set_cache_aps_delayed_init(true); 1463 } 1464 1465 void arch_thaw_secondary_cpus_end(void) 1466 { 1467 cache_aps_init(); 1468 } 1469 1470 /* 1471 * Early setup to make printk work. 1472 */ 1473 void __init native_smp_prepare_boot_cpu(void) 1474 { 1475 int me = smp_processor_id(); 1476 1477 /* SMP handles this from setup_per_cpu_areas() */ 1478 if (!IS_ENABLED(CONFIG_SMP)) 1479 switch_gdt_and_percpu_base(me); 1480 1481 /* already set me in cpu_online_mask in boot_cpu_init() */ 1482 cpumask_set_cpu(me, cpu_callout_mask); 1483 cpu_set_state_online(me); 1484 native_pv_lock_init(); 1485 } 1486 1487 void __init calculate_max_logical_packages(void) 1488 { 1489 int ncpus; 1490 1491 /* 1492 * Today neither Intel nor AMD support heterogeneous systems so 1493 * extrapolate the boot cpu's data to all packages. 1494 */ 1495 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1496 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1497 pr_info("Max logical packages: %u\n", __max_logical_packages); 1498 } 1499 1500 void __init native_smp_cpus_done(unsigned int max_cpus) 1501 { 1502 pr_debug("Boot done\n"); 1503 1504 calculate_max_logical_packages(); 1505 1506 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1507 if (x86_has_numa_in_package) 1508 set_sched_topology(x86_numa_in_package_topology); 1509 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1510 set_sched_topology(x86_hybrid_topology); 1511 1512 nmi_selftest(); 1513 impress_friends(); 1514 cache_aps_init(); 1515 } 1516 1517 static int __initdata setup_possible_cpus = -1; 1518 static int __init _setup_possible_cpus(char *str) 1519 { 1520 get_option(&str, &setup_possible_cpus); 1521 return 0; 1522 } 1523 early_param("possible_cpus", _setup_possible_cpus); 1524 1525 1526 /* 1527 * cpu_possible_mask should be static, it cannot change as cpu's 1528 * are onlined, or offlined. The reason is per-cpu data-structures 1529 * are allocated by some modules at init time, and don't expect to 1530 * do this dynamically on cpu arrival/departure. 1531 * cpu_present_mask on the other hand can change dynamically. 1532 * In case when cpu_hotplug is not compiled, then we resort to current 1533 * behaviour, which is cpu_possible == cpu_present. 1534 * - Ashok Raj 1535 * 1536 * Three ways to find out the number of additional hotplug CPUs: 1537 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1538 * - The user can overwrite it with possible_cpus=NUM 1539 * - Otherwise don't reserve additional CPUs. 1540 * We do this because additional CPUs waste a lot of memory. 1541 * -AK 1542 */ 1543 __init void prefill_possible_map(void) 1544 { 1545 int i, possible; 1546 1547 /* No boot processor was found in mptable or ACPI MADT */ 1548 if (!num_processors) { 1549 if (boot_cpu_has(X86_FEATURE_APIC)) { 1550 int apicid = boot_cpu_physical_apicid; 1551 int cpu = hard_smp_processor_id(); 1552 1553 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1554 1555 /* Make sure boot cpu is enumerated */ 1556 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1557 apic->apic_id_valid(apicid)) 1558 generic_processor_info(apicid, boot_cpu_apic_version); 1559 } 1560 1561 if (!num_processors) 1562 num_processors = 1; 1563 } 1564 1565 i = setup_max_cpus ?: 1; 1566 if (setup_possible_cpus == -1) { 1567 possible = num_processors; 1568 #ifdef CONFIG_HOTPLUG_CPU 1569 if (setup_max_cpus) 1570 possible += disabled_cpus; 1571 #else 1572 if (possible > i) 1573 possible = i; 1574 #endif 1575 } else 1576 possible = setup_possible_cpus; 1577 1578 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1579 1580 /* nr_cpu_ids could be reduced via nr_cpus= */ 1581 if (possible > nr_cpu_ids) { 1582 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1583 possible, nr_cpu_ids); 1584 possible = nr_cpu_ids; 1585 } 1586 1587 #ifdef CONFIG_HOTPLUG_CPU 1588 if (!setup_max_cpus) 1589 #endif 1590 if (possible > i) { 1591 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1592 possible, setup_max_cpus); 1593 possible = i; 1594 } 1595 1596 set_nr_cpu_ids(possible); 1597 1598 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1599 possible, max_t(int, possible - num_processors, 0)); 1600 1601 reset_cpu_possible_mask(); 1602 1603 for (i = 0; i < possible; i++) 1604 set_cpu_possible(i, true); 1605 } 1606 1607 #ifdef CONFIG_HOTPLUG_CPU 1608 1609 /* Recompute SMT state for all CPUs on offline */ 1610 static void recompute_smt_state(void) 1611 { 1612 int max_threads, cpu; 1613 1614 max_threads = 0; 1615 for_each_online_cpu (cpu) { 1616 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1617 1618 if (threads > max_threads) 1619 max_threads = threads; 1620 } 1621 __max_smt_threads = max_threads; 1622 } 1623 1624 static void remove_siblinginfo(int cpu) 1625 { 1626 int sibling; 1627 struct cpuinfo_x86 *c = &cpu_data(cpu); 1628 1629 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1630 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1631 /*/ 1632 * last thread sibling in this cpu core going down 1633 */ 1634 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1635 cpu_data(sibling).booted_cores--; 1636 } 1637 1638 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1639 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1640 1641 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1642 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1643 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1644 cpu_data(sibling).smt_active = false; 1645 } 1646 1647 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1648 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1649 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1650 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1651 cpumask_clear(cpu_llc_shared_mask(cpu)); 1652 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1653 cpumask_clear(topology_sibling_cpumask(cpu)); 1654 cpumask_clear(topology_core_cpumask(cpu)); 1655 cpumask_clear(topology_die_cpumask(cpu)); 1656 c->cpu_core_id = 0; 1657 c->booted_cores = 0; 1658 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1659 recompute_smt_state(); 1660 } 1661 1662 static void remove_cpu_from_maps(int cpu) 1663 { 1664 set_cpu_online(cpu, false); 1665 cpumask_clear_cpu(cpu, cpu_callout_mask); 1666 cpumask_clear_cpu(cpu, cpu_callin_mask); 1667 /* was set by cpu_init() */ 1668 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1669 numa_remove_cpu(cpu); 1670 } 1671 1672 void cpu_disable_common(void) 1673 { 1674 int cpu = smp_processor_id(); 1675 1676 remove_siblinginfo(cpu); 1677 1678 /* It's now safe to remove this processor from the online map */ 1679 lock_vector_lock(); 1680 remove_cpu_from_maps(cpu); 1681 unlock_vector_lock(); 1682 fixup_irqs(); 1683 lapic_offline(); 1684 } 1685 1686 int native_cpu_disable(void) 1687 { 1688 int ret; 1689 1690 ret = lapic_can_unplug_cpu(); 1691 if (ret) 1692 return ret; 1693 1694 cpu_disable_common(); 1695 1696 /* 1697 * Disable the local APIC. Otherwise IPI broadcasts will reach 1698 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1699 * messages. 1700 * 1701 * Disabling the APIC must happen after cpu_disable_common() 1702 * which invokes fixup_irqs(). 1703 * 1704 * Disabling the APIC preserves already set bits in IRR, but 1705 * an interrupt arriving after disabling the local APIC does not 1706 * set the corresponding IRR bit. 1707 * 1708 * fixup_irqs() scans IRR for set bits so it can raise a not 1709 * yet handled interrupt on the new destination CPU via an IPI 1710 * but obviously it can't do so for IRR bits which are not set. 1711 * IOW, interrupts arriving after disabling the local APIC will 1712 * be lost. 1713 */ 1714 apic_soft_disable(); 1715 1716 return 0; 1717 } 1718 1719 int common_cpu_die(unsigned int cpu) 1720 { 1721 int ret = 0; 1722 1723 /* We don't do anything here: idle task is faking death itself. */ 1724 1725 /* They ack this in play_dead() by setting CPU_DEAD */ 1726 if (cpu_wait_death(cpu, 5)) { 1727 if (system_state == SYSTEM_RUNNING) 1728 pr_info("CPU %u is now offline\n", cpu); 1729 } else { 1730 pr_err("CPU %u didn't die...\n", cpu); 1731 ret = -1; 1732 } 1733 1734 return ret; 1735 } 1736 1737 void native_cpu_die(unsigned int cpu) 1738 { 1739 common_cpu_die(cpu); 1740 } 1741 1742 void play_dead_common(void) 1743 { 1744 idle_task_exit(); 1745 1746 /* Ack it */ 1747 (void)cpu_report_death(); 1748 1749 /* 1750 * With physical CPU hotplug, we should halt the cpu 1751 */ 1752 local_irq_disable(); 1753 } 1754 1755 /** 1756 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1757 * 1758 * If NMI wants to wake up CPU0, start CPU0. 1759 */ 1760 void cond_wakeup_cpu0(void) 1761 { 1762 if (smp_processor_id() == 0 && enable_start_cpu0) 1763 start_cpu0(); 1764 } 1765 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1766 1767 /* 1768 * We need to flush the caches before going to sleep, lest we have 1769 * dirty data in our caches when we come back up. 1770 */ 1771 static inline void mwait_play_dead(void) 1772 { 1773 unsigned int eax, ebx, ecx, edx; 1774 unsigned int highest_cstate = 0; 1775 unsigned int highest_subcstate = 0; 1776 void *mwait_ptr; 1777 int i; 1778 1779 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1780 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1781 return; 1782 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1783 return; 1784 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1785 return; 1786 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1787 return; 1788 1789 eax = CPUID_MWAIT_LEAF; 1790 ecx = 0; 1791 native_cpuid(&eax, &ebx, &ecx, &edx); 1792 1793 /* 1794 * eax will be 0 if EDX enumeration is not valid. 1795 * Initialized below to cstate, sub_cstate value when EDX is valid. 1796 */ 1797 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1798 eax = 0; 1799 } else { 1800 edx >>= MWAIT_SUBSTATE_SIZE; 1801 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1802 if (edx & MWAIT_SUBSTATE_MASK) { 1803 highest_cstate = i; 1804 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1805 } 1806 } 1807 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1808 (highest_subcstate - 1); 1809 } 1810 1811 /* 1812 * This should be a memory location in a cache line which is 1813 * unlikely to be touched by other processors. The actual 1814 * content is immaterial as it is not actually modified in any way. 1815 */ 1816 mwait_ptr = ¤t_thread_info()->flags; 1817 1818 wbinvd(); 1819 1820 while (1) { 1821 /* 1822 * The CLFLUSH is a workaround for erratum AAI65 for 1823 * the Xeon 7400 series. It's not clear it is actually 1824 * needed, but it should be harmless in either case. 1825 * The WBINVD is insufficient due to the spurious-wakeup 1826 * case where we return around the loop. 1827 */ 1828 mb(); 1829 clflush(mwait_ptr); 1830 mb(); 1831 __monitor(mwait_ptr, 0, 0); 1832 mb(); 1833 __mwait(eax, 0); 1834 1835 cond_wakeup_cpu0(); 1836 } 1837 } 1838 1839 void __noreturn hlt_play_dead(void) 1840 { 1841 if (__this_cpu_read(cpu_info.x86) >= 4) 1842 wbinvd(); 1843 1844 while (1) { 1845 native_halt(); 1846 1847 cond_wakeup_cpu0(); 1848 } 1849 } 1850 1851 void native_play_dead(void) 1852 { 1853 play_dead_common(); 1854 tboot_shutdown(TB_SHUTDOWN_WFS); 1855 1856 mwait_play_dead(); 1857 if (cpuidle_play_dead()) 1858 hlt_play_dead(); 1859 } 1860 1861 #else /* ... !CONFIG_HOTPLUG_CPU */ 1862 int native_cpu_disable(void) 1863 { 1864 return -ENOSYS; 1865 } 1866 1867 void native_cpu_die(unsigned int cpu) 1868 { 1869 /* We said "no" in __cpu_disable */ 1870 BUG(); 1871 } 1872 1873 void native_play_dead(void) 1874 { 1875 BUG(); 1876 } 1877 1878 #endif 1879