1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/fpu/internal.h> 72 #include <asm/setup.h> 73 #include <asm/uv/uv.h> 74 #include <linux/mc146818rtc.h> 75 #include <asm/i8259.h> 76 #include <asm/realmode.h> 77 #include <asm/misc.h> 78 79 /* Number of siblings per CPU package */ 80 int smp_num_siblings = 1; 81 EXPORT_SYMBOL(smp_num_siblings); 82 83 /* Last level cache ID of each logical CPU */ 84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 101 { 102 unsigned long flags; 103 104 spin_lock_irqsave(&rtc_lock, flags); 105 CMOS_WRITE(0xa, 0xf); 106 spin_unlock_irqrestore(&rtc_lock, flags); 107 local_flush_tlb(); 108 pr_debug("1.\n"); 109 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 110 start_eip >> 4; 111 pr_debug("2.\n"); 112 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 113 start_eip & 0xf; 114 pr_debug("3.\n"); 115 } 116 117 static inline void smpboot_restore_warm_reset_vector(void) 118 { 119 unsigned long flags; 120 121 /* 122 * Install writable page 0 entry to set BIOS data area. 123 */ 124 local_flush_tlb(); 125 126 /* 127 * Paranoid: Set warm reset code and vector here back 128 * to default values. 129 */ 130 spin_lock_irqsave(&rtc_lock, flags); 131 CMOS_WRITE(0, 0xf); 132 spin_unlock_irqrestore(&rtc_lock, flags); 133 134 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 135 } 136 137 /* 138 * Report back to the Boot Processor during boot time or to the caller processor 139 * during CPU online. 140 */ 141 static void smp_callin(void) 142 { 143 int cpuid, phys_id; 144 145 /* 146 * If waken up by an INIT in an 82489DX configuration 147 * cpu_callout_mask guarantees we don't get here before 148 * an INIT_deassert IPI reaches our local APIC, so it is 149 * now safe to touch our local APIC. 150 */ 151 cpuid = smp_processor_id(); 152 153 /* 154 * (This works even if the APIC is not enabled.) 155 */ 156 phys_id = read_apic_id(); 157 158 /* 159 * the boot CPU has finished the init stage and is spinning 160 * on callin_map until we finish. We are free to set up this 161 * CPU, first the APIC. (this is probably redundant on most 162 * boards) 163 */ 164 apic_ap_setup(); 165 166 /* 167 * Save our processor parameters. Note: this information 168 * is needed for clock calibration. 169 */ 170 smp_store_cpu_info(cpuid); 171 172 /* 173 * Get our bogomips. 174 * Update loops_per_jiffy in cpu_data. Previous call to 175 * smp_store_cpu_info() stored a value that is close but not as 176 * accurate as the value just calculated. 177 */ 178 calibrate_delay(); 179 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 180 pr_debug("Stack at about %p\n", &cpuid); 181 182 /* 183 * This must be done before setting cpu_online_mask 184 * or calling notify_cpu_starting. 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 wmb(); 188 189 notify_cpu_starting(cpuid); 190 191 /* 192 * Allow the master to continue. 193 */ 194 cpumask_set_cpu(cpuid, cpu_callin_mask); 195 } 196 197 static int cpu0_logical_apicid; 198 static int enable_start_cpu0; 199 /* 200 * Activate a secondary processor. 201 */ 202 static void notrace start_secondary(void *unused) 203 { 204 /* 205 * Don't put *anything* before cpu_init(), SMP booting is too 206 * fragile that we want to limit the things done here to the 207 * most necessary things. 208 */ 209 cpu_init(); 210 x86_cpuinit.early_percpu_clock_init(); 211 preempt_disable(); 212 smp_callin(); 213 214 enable_start_cpu0 = 0; 215 216 #ifdef CONFIG_X86_32 217 /* switch away from the initial page table */ 218 load_cr3(swapper_pg_dir); 219 __flush_tlb_all(); 220 #endif 221 222 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 223 barrier(); 224 /* 225 * Check TSC synchronization with the BP: 226 */ 227 check_tsc_sync_target(); 228 229 /* 230 * Lock vector_lock and initialize the vectors on this cpu 231 * before setting the cpu online. We must set it online with 232 * vector_lock held to prevent a concurrent setup/teardown 233 * from seeing a half valid vector space. 234 */ 235 lock_vector_lock(); 236 setup_vector_irq(smp_processor_id()); 237 set_cpu_online(smp_processor_id(), true); 238 unlock_vector_lock(); 239 cpu_set_state_online(smp_processor_id()); 240 x86_platform.nmi_init(); 241 242 /* enable local interrupts */ 243 local_irq_enable(); 244 245 /* to prevent fake stack check failure in clock setup */ 246 boot_init_stack_canary(); 247 248 x86_cpuinit.setup_percpu_clockev(); 249 250 wmb(); 251 cpu_startup_entry(CPUHP_ONLINE); 252 } 253 254 void __init smp_store_boot_cpu_info(void) 255 { 256 int id = 0; /* CPU 0 */ 257 struct cpuinfo_x86 *c = &cpu_data(id); 258 259 *c = boot_cpu_data; 260 c->cpu_index = id; 261 } 262 263 /* 264 * The bootstrap kernel entry code has set these up. Save them for 265 * a given CPU 266 */ 267 void smp_store_cpu_info(int id) 268 { 269 struct cpuinfo_x86 *c = &cpu_data(id); 270 271 *c = boot_cpu_data; 272 c->cpu_index = id; 273 /* 274 * During boot time, CPU0 has this setup already. Save the info when 275 * bringing up AP or offlined CPU0. 276 */ 277 identify_secondary_cpu(c); 278 } 279 280 static bool 281 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 282 { 283 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 284 285 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 286 } 287 288 static bool 289 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 290 { 291 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 292 293 return !WARN_ONCE(!topology_same_node(c, o), 294 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 295 "[node: %d != %d]. Ignoring dependency.\n", 296 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 297 } 298 299 #define link_mask(mfunc, c1, c2) \ 300 do { \ 301 cpumask_set_cpu((c1), mfunc(c2)); \ 302 cpumask_set_cpu((c2), mfunc(c1)); \ 303 } while (0) 304 305 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 306 { 307 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 308 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 309 310 if (c->phys_proc_id == o->phys_proc_id && 311 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 312 c->compute_unit_id == o->compute_unit_id) 313 return topology_sane(c, o, "smt"); 314 315 } else if (c->phys_proc_id == o->phys_proc_id && 316 c->cpu_core_id == o->cpu_core_id) { 317 return topology_sane(c, o, "smt"); 318 } 319 320 return false; 321 } 322 323 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 324 { 325 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 326 327 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 328 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 329 return topology_sane(c, o, "llc"); 330 331 return false; 332 } 333 334 /* 335 * Unlike the other levels, we do not enforce keeping a 336 * multicore group inside a NUMA node. If this happens, we will 337 * discard the MC level of the topology later. 338 */ 339 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 340 { 341 if (c->phys_proc_id == o->phys_proc_id) 342 return true; 343 return false; 344 } 345 346 static struct sched_domain_topology_level numa_inside_package_topology[] = { 347 #ifdef CONFIG_SCHED_SMT 348 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 349 #endif 350 #ifdef CONFIG_SCHED_MC 351 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 352 #endif 353 { NULL, }, 354 }; 355 /* 356 * set_sched_topology() sets the topology internal to a CPU. The 357 * NUMA topologies are layered on top of it to build the full 358 * system topology. 359 * 360 * If NUMA nodes are observed to occur within a CPU package, this 361 * function should be called. It forces the sched domain code to 362 * only use the SMT level for the CPU portion of the topology. 363 * This essentially falls back to relying on NUMA information 364 * from the SRAT table to describe the entire system topology 365 * (except for hyperthreads). 366 */ 367 static void primarily_use_numa_for_topology(void) 368 { 369 set_sched_topology(numa_inside_package_topology); 370 } 371 372 void set_cpu_sibling_map(int cpu) 373 { 374 bool has_smt = smp_num_siblings > 1; 375 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 376 struct cpuinfo_x86 *c = &cpu_data(cpu); 377 struct cpuinfo_x86 *o; 378 int i; 379 380 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 381 382 if (!has_mp) { 383 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 384 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 385 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 386 c->booted_cores = 1; 387 return; 388 } 389 390 for_each_cpu(i, cpu_sibling_setup_mask) { 391 o = &cpu_data(i); 392 393 if ((i == cpu) || (has_smt && match_smt(c, o))) 394 link_mask(topology_sibling_cpumask, cpu, i); 395 396 if ((i == cpu) || (has_mp && match_llc(c, o))) 397 link_mask(cpu_llc_shared_mask, cpu, i); 398 399 } 400 401 /* 402 * This needs a separate iteration over the cpus because we rely on all 403 * topology_sibling_cpumask links to be set-up. 404 */ 405 for_each_cpu(i, cpu_sibling_setup_mask) { 406 o = &cpu_data(i); 407 408 if ((i == cpu) || (has_mp && match_die(c, o))) { 409 link_mask(topology_core_cpumask, cpu, i); 410 411 /* 412 * Does this new cpu bringup a new core? 413 */ 414 if (cpumask_weight( 415 topology_sibling_cpumask(cpu)) == 1) { 416 /* 417 * for each core in package, increment 418 * the booted_cores for this new cpu 419 */ 420 if (cpumask_first( 421 topology_sibling_cpumask(i)) == i) 422 c->booted_cores++; 423 /* 424 * increment the core count for all 425 * the other cpus in this package 426 */ 427 if (i != cpu) 428 cpu_data(i).booted_cores++; 429 } else if (i != cpu && !c->booted_cores) 430 c->booted_cores = cpu_data(i).booted_cores; 431 } 432 if (match_die(c, o) && !topology_same_node(c, o)) 433 primarily_use_numa_for_topology(); 434 } 435 } 436 437 /* maps the cpu to the sched domain representing multi-core */ 438 const struct cpumask *cpu_coregroup_mask(int cpu) 439 { 440 return cpu_llc_shared_mask(cpu); 441 } 442 443 static void impress_friends(void) 444 { 445 int cpu; 446 unsigned long bogosum = 0; 447 /* 448 * Allow the user to impress friends. 449 */ 450 pr_debug("Before bogomips\n"); 451 for_each_possible_cpu(cpu) 452 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 453 bogosum += cpu_data(cpu).loops_per_jiffy; 454 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 455 num_online_cpus(), 456 bogosum/(500000/HZ), 457 (bogosum/(5000/HZ))%100); 458 459 pr_debug("Before bogocount - setting activated=1\n"); 460 } 461 462 void __inquire_remote_apic(int apicid) 463 { 464 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 465 const char * const names[] = { "ID", "VERSION", "SPIV" }; 466 int timeout; 467 u32 status; 468 469 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 470 471 for (i = 0; i < ARRAY_SIZE(regs); i++) { 472 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 473 474 /* 475 * Wait for idle. 476 */ 477 status = safe_apic_wait_icr_idle(); 478 if (status) 479 pr_cont("a previous APIC delivery may have failed\n"); 480 481 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 482 483 timeout = 0; 484 do { 485 udelay(100); 486 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 487 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 488 489 switch (status) { 490 case APIC_ICR_RR_VALID: 491 status = apic_read(APIC_RRR); 492 pr_cont("%08x\n", status); 493 break; 494 default: 495 pr_cont("failed\n"); 496 } 497 } 498 } 499 500 /* 501 * The Multiprocessor Specification 1.4 (1997) example code suggests 502 * that there should be a 10ms delay between the BSP asserting INIT 503 * and de-asserting INIT, when starting a remote processor. 504 * But that slows boot and resume on modern processors, which include 505 * many cores and don't require that delay. 506 * 507 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 508 * Modern processor families are quirked to remove the delay entirely. 509 */ 510 #define UDELAY_10MS_DEFAULT 10000 511 512 static unsigned int init_udelay = UINT_MAX; 513 514 static int __init cpu_init_udelay(char *str) 515 { 516 get_option(&str, &init_udelay); 517 518 return 0; 519 } 520 early_param("cpu_init_udelay", cpu_init_udelay); 521 522 static void __init smp_quirk_init_udelay(void) 523 { 524 /* if cmdline changed it from default, leave it alone */ 525 if (init_udelay != UINT_MAX) 526 return; 527 528 /* if modern processor, use no delay */ 529 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 530 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 531 init_udelay = 0; 532 return; 533 } 534 /* else, use legacy delay */ 535 init_udelay = UDELAY_10MS_DEFAULT; 536 } 537 538 /* 539 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 540 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 541 * won't ... remember to clear down the APIC, etc later. 542 */ 543 int 544 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 545 { 546 unsigned long send_status, accept_status = 0; 547 int maxlvt; 548 549 /* Target chip */ 550 /* Boot on the stack */ 551 /* Kick the second */ 552 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 553 554 pr_debug("Waiting for send to finish...\n"); 555 send_status = safe_apic_wait_icr_idle(); 556 557 /* 558 * Give the other CPU some time to accept the IPI. 559 */ 560 udelay(200); 561 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 562 maxlvt = lapic_get_maxlvt(); 563 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 564 apic_write(APIC_ESR, 0); 565 accept_status = (apic_read(APIC_ESR) & 0xEF); 566 } 567 pr_debug("NMI sent\n"); 568 569 if (send_status) 570 pr_err("APIC never delivered???\n"); 571 if (accept_status) 572 pr_err("APIC delivery error (%lx)\n", accept_status); 573 574 return (send_status | accept_status); 575 } 576 577 static int 578 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 579 { 580 unsigned long send_status = 0, accept_status = 0; 581 int maxlvt, num_starts, j; 582 583 maxlvt = lapic_get_maxlvt(); 584 585 /* 586 * Be paranoid about clearing APIC errors. 587 */ 588 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 589 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 590 apic_write(APIC_ESR, 0); 591 apic_read(APIC_ESR); 592 } 593 594 pr_debug("Asserting INIT\n"); 595 596 /* 597 * Turn INIT on target chip 598 */ 599 /* 600 * Send IPI 601 */ 602 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 603 phys_apicid); 604 605 pr_debug("Waiting for send to finish...\n"); 606 send_status = safe_apic_wait_icr_idle(); 607 608 udelay(init_udelay); 609 610 pr_debug("Deasserting INIT\n"); 611 612 /* Target chip */ 613 /* Send IPI */ 614 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 615 616 pr_debug("Waiting for send to finish...\n"); 617 send_status = safe_apic_wait_icr_idle(); 618 619 mb(); 620 621 /* 622 * Should we send STARTUP IPIs ? 623 * 624 * Determine this based on the APIC version. 625 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 626 */ 627 if (APIC_INTEGRATED(apic_version[phys_apicid])) 628 num_starts = 2; 629 else 630 num_starts = 0; 631 632 /* 633 * Run STARTUP IPI loop. 634 */ 635 pr_debug("#startup loops: %d\n", num_starts); 636 637 for (j = 1; j <= num_starts; j++) { 638 pr_debug("Sending STARTUP #%d\n", j); 639 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 640 apic_write(APIC_ESR, 0); 641 apic_read(APIC_ESR); 642 pr_debug("After apic_write\n"); 643 644 /* 645 * STARTUP IPI 646 */ 647 648 /* Target chip */ 649 /* Boot on the stack */ 650 /* Kick the second */ 651 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 652 phys_apicid); 653 654 /* 655 * Give the other CPU some time to accept the IPI. 656 */ 657 if (init_udelay == 0) 658 udelay(10); 659 else 660 udelay(300); 661 662 pr_debug("Startup point 1\n"); 663 664 pr_debug("Waiting for send to finish...\n"); 665 send_status = safe_apic_wait_icr_idle(); 666 667 /* 668 * Give the other CPU some time to accept the IPI. 669 */ 670 if (init_udelay == 0) 671 udelay(10); 672 else 673 udelay(200); 674 675 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 676 apic_write(APIC_ESR, 0); 677 accept_status = (apic_read(APIC_ESR) & 0xEF); 678 if (send_status || accept_status) 679 break; 680 } 681 pr_debug("After Startup\n"); 682 683 if (send_status) 684 pr_err("APIC never delivered???\n"); 685 if (accept_status) 686 pr_err("APIC delivery error (%lx)\n", accept_status); 687 688 return (send_status | accept_status); 689 } 690 691 void smp_announce(void) 692 { 693 int num_nodes = num_online_nodes(); 694 695 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 696 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 697 } 698 699 /* reduce the number of lines printed when booting a large cpu count system */ 700 static void announce_cpu(int cpu, int apicid) 701 { 702 static int current_node = -1; 703 int node = early_cpu_to_node(cpu); 704 static int width, node_width; 705 706 if (!width) 707 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 708 709 if (!node_width) 710 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 711 712 if (cpu == 1) 713 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 714 715 if (system_state == SYSTEM_BOOTING) { 716 if (node != current_node) { 717 if (current_node > (-1)) 718 pr_cont("\n"); 719 current_node = node; 720 721 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 722 node_width - num_digits(node), " ", node); 723 } 724 725 /* Add padding for the BSP */ 726 if (cpu == 1) 727 pr_cont("%*s", width + 1, " "); 728 729 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 730 731 } else 732 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 733 node, cpu, apicid); 734 } 735 736 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 737 { 738 int cpu; 739 740 cpu = smp_processor_id(); 741 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 742 return NMI_HANDLED; 743 744 return NMI_DONE; 745 } 746 747 /* 748 * Wake up AP by INIT, INIT, STARTUP sequence. 749 * 750 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 751 * boot-strap code which is not a desired behavior for waking up BSP. To 752 * void the boot-strap code, wake up CPU0 by NMI instead. 753 * 754 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 755 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 756 * We'll change this code in the future to wake up hard offlined CPU0 if 757 * real platform and request are available. 758 */ 759 static int 760 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 761 int *cpu0_nmi_registered) 762 { 763 int id; 764 int boot_error; 765 766 preempt_disable(); 767 768 /* 769 * Wake up AP by INIT, INIT, STARTUP sequence. 770 */ 771 if (cpu) { 772 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 773 goto out; 774 } 775 776 /* 777 * Wake up BSP by nmi. 778 * 779 * Register a NMI handler to help wake up CPU0. 780 */ 781 boot_error = register_nmi_handler(NMI_LOCAL, 782 wakeup_cpu0_nmi, 0, "wake_cpu0"); 783 784 if (!boot_error) { 785 enable_start_cpu0 = 1; 786 *cpu0_nmi_registered = 1; 787 if (apic->dest_logical == APIC_DEST_LOGICAL) 788 id = cpu0_logical_apicid; 789 else 790 id = apicid; 791 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 792 } 793 794 out: 795 preempt_enable(); 796 797 return boot_error; 798 } 799 800 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 801 { 802 /* Just in case we booted with a single CPU. */ 803 alternatives_enable_smp(); 804 805 per_cpu(current_task, cpu) = idle; 806 807 #ifdef CONFIG_X86_32 808 /* Stack for startup_32 can be just as for start_secondary onwards */ 809 irq_ctx_init(cpu); 810 per_cpu(cpu_current_top_of_stack, cpu) = 811 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 812 #else 813 clear_tsk_thread_flag(idle, TIF_FORK); 814 initial_gs = per_cpu_offset(cpu); 815 #endif 816 } 817 818 /* 819 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 820 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 821 * Returns zero if CPU booted OK, else error code from 822 * ->wakeup_secondary_cpu. 823 */ 824 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 825 { 826 volatile u32 *trampoline_status = 827 (volatile u32 *) __va(real_mode_header->trampoline_status); 828 /* start_ip had better be page-aligned! */ 829 unsigned long start_ip = real_mode_header->trampoline_start; 830 831 unsigned long boot_error = 0; 832 int cpu0_nmi_registered = 0; 833 unsigned long timeout; 834 835 idle->thread.sp = (unsigned long) (((struct pt_regs *) 836 (THREAD_SIZE + task_stack_page(idle))) - 1); 837 838 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 839 initial_code = (unsigned long)start_secondary; 840 stack_start = idle->thread.sp; 841 842 /* 843 * Enable the espfix hack for this CPU 844 */ 845 #ifdef CONFIG_X86_ESPFIX64 846 init_espfix_ap(cpu); 847 #endif 848 849 /* So we see what's up */ 850 announce_cpu(cpu, apicid); 851 852 /* 853 * This grunge runs the startup process for 854 * the targeted processor. 855 */ 856 857 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 858 859 pr_debug("Setting warm reset code and vector.\n"); 860 861 smpboot_setup_warm_reset_vector(start_ip); 862 /* 863 * Be paranoid about clearing APIC errors. 864 */ 865 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 866 apic_write(APIC_ESR, 0); 867 apic_read(APIC_ESR); 868 } 869 } 870 871 /* 872 * AP might wait on cpu_callout_mask in cpu_init() with 873 * cpu_initialized_mask set if previous attempt to online 874 * it timed-out. Clear cpu_initialized_mask so that after 875 * INIT/SIPI it could start with a clean state. 876 */ 877 cpumask_clear_cpu(cpu, cpu_initialized_mask); 878 smp_mb(); 879 880 /* 881 * Wake up a CPU in difference cases: 882 * - Use the method in the APIC driver if it's defined 883 * Otherwise, 884 * - Use an INIT boot APIC message for APs or NMI for BSP. 885 */ 886 if (apic->wakeup_secondary_cpu) 887 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 888 else 889 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 890 &cpu0_nmi_registered); 891 892 if (!boot_error) { 893 /* 894 * Wait 10s total for first sign of life from AP 895 */ 896 boot_error = -1; 897 timeout = jiffies + 10*HZ; 898 while (time_before(jiffies, timeout)) { 899 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 900 /* 901 * Tell AP to proceed with initialization 902 */ 903 cpumask_set_cpu(cpu, cpu_callout_mask); 904 boot_error = 0; 905 break; 906 } 907 schedule(); 908 } 909 } 910 911 if (!boot_error) { 912 /* 913 * Wait till AP completes initial initialization 914 */ 915 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 916 /* 917 * Allow other tasks to run while we wait for the 918 * AP to come online. This also gives a chance 919 * for the MTRR work(triggered by the AP coming online) 920 * to be completed in the stop machine context. 921 */ 922 schedule(); 923 } 924 } 925 926 /* mark "stuck" area as not stuck */ 927 *trampoline_status = 0; 928 929 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 930 /* 931 * Cleanup possible dangling ends... 932 */ 933 smpboot_restore_warm_reset_vector(); 934 } 935 /* 936 * Clean up the nmi handler. Do this after the callin and callout sync 937 * to avoid impact of possible long unregister time. 938 */ 939 if (cpu0_nmi_registered) 940 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 941 942 return boot_error; 943 } 944 945 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 946 { 947 int apicid = apic->cpu_present_to_apicid(cpu); 948 unsigned long flags; 949 int err; 950 951 WARN_ON(irqs_disabled()); 952 953 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 954 955 if (apicid == BAD_APICID || 956 !physid_isset(apicid, phys_cpu_present_map) || 957 !apic->apic_id_valid(apicid)) { 958 pr_err("%s: bad cpu %d\n", __func__, cpu); 959 return -EINVAL; 960 } 961 962 /* 963 * Already booted CPU? 964 */ 965 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 966 pr_debug("do_boot_cpu %d Already started\n", cpu); 967 return -ENOSYS; 968 } 969 970 /* 971 * Save current MTRR state in case it was changed since early boot 972 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 973 */ 974 mtrr_save_state(); 975 976 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 977 err = cpu_check_up_prepare(cpu); 978 if (err && err != -EBUSY) 979 return err; 980 981 /* the FPU context is blank, nobody can own it */ 982 __cpu_disable_lazy_restore(cpu); 983 984 common_cpu_up(cpu, tidle); 985 986 /* 987 * We have to walk the irq descriptors to setup the vector 988 * space for the cpu which comes online. Prevent irq 989 * alloc/free across the bringup. 990 */ 991 irq_lock_sparse(); 992 993 err = do_boot_cpu(apicid, cpu, tidle); 994 995 if (err) { 996 irq_unlock_sparse(); 997 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 998 return -EIO; 999 } 1000 1001 /* 1002 * Check TSC synchronization with the AP (keep irqs disabled 1003 * while doing so): 1004 */ 1005 local_irq_save(flags); 1006 check_tsc_sync_source(cpu); 1007 local_irq_restore(flags); 1008 1009 while (!cpu_online(cpu)) { 1010 cpu_relax(); 1011 touch_nmi_watchdog(); 1012 } 1013 1014 irq_unlock_sparse(); 1015 1016 return 0; 1017 } 1018 1019 /** 1020 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1021 */ 1022 void arch_disable_smp_support(void) 1023 { 1024 disable_ioapic_support(); 1025 } 1026 1027 /* 1028 * Fall back to non SMP mode after errors. 1029 * 1030 * RED-PEN audit/test this more. I bet there is more state messed up here. 1031 */ 1032 static __init void disable_smp(void) 1033 { 1034 pr_info("SMP disabled\n"); 1035 1036 disable_ioapic_support(); 1037 1038 init_cpu_present(cpumask_of(0)); 1039 init_cpu_possible(cpumask_of(0)); 1040 1041 if (smp_found_config) 1042 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1043 else 1044 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1045 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1046 cpumask_set_cpu(0, topology_core_cpumask(0)); 1047 } 1048 1049 enum { 1050 SMP_OK, 1051 SMP_NO_CONFIG, 1052 SMP_NO_APIC, 1053 SMP_FORCE_UP, 1054 }; 1055 1056 /* 1057 * Various sanity checks. 1058 */ 1059 static int __init smp_sanity_check(unsigned max_cpus) 1060 { 1061 preempt_disable(); 1062 1063 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1064 if (def_to_bigsmp && nr_cpu_ids > 8) { 1065 unsigned int cpu; 1066 unsigned nr; 1067 1068 pr_warn("More than 8 CPUs detected - skipping them\n" 1069 "Use CONFIG_X86_BIGSMP\n"); 1070 1071 nr = 0; 1072 for_each_present_cpu(cpu) { 1073 if (nr >= 8) 1074 set_cpu_present(cpu, false); 1075 nr++; 1076 } 1077 1078 nr = 0; 1079 for_each_possible_cpu(cpu) { 1080 if (nr >= 8) 1081 set_cpu_possible(cpu, false); 1082 nr++; 1083 } 1084 1085 nr_cpu_ids = 8; 1086 } 1087 #endif 1088 1089 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1090 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1091 hard_smp_processor_id()); 1092 1093 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1094 } 1095 1096 /* 1097 * If we couldn't find an SMP configuration at boot time, 1098 * get out of here now! 1099 */ 1100 if (!smp_found_config && !acpi_lapic) { 1101 preempt_enable(); 1102 pr_notice("SMP motherboard not detected\n"); 1103 return SMP_NO_CONFIG; 1104 } 1105 1106 /* 1107 * Should not be necessary because the MP table should list the boot 1108 * CPU too, but we do it for the sake of robustness anyway. 1109 */ 1110 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1111 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1112 boot_cpu_physical_apicid); 1113 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1114 } 1115 preempt_enable(); 1116 1117 /* 1118 * If we couldn't find a local APIC, then get out of here now! 1119 */ 1120 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1121 !cpu_has_apic) { 1122 if (!disable_apic) { 1123 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1124 boot_cpu_physical_apicid); 1125 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1126 } 1127 return SMP_NO_APIC; 1128 } 1129 1130 /* 1131 * If SMP should be disabled, then really disable it! 1132 */ 1133 if (!max_cpus) { 1134 pr_info("SMP mode deactivated\n"); 1135 return SMP_FORCE_UP; 1136 } 1137 1138 return SMP_OK; 1139 } 1140 1141 static void __init smp_cpu_index_default(void) 1142 { 1143 int i; 1144 struct cpuinfo_x86 *c; 1145 1146 for_each_possible_cpu(i) { 1147 c = &cpu_data(i); 1148 /* mark all to hotplug */ 1149 c->cpu_index = nr_cpu_ids; 1150 } 1151 } 1152 1153 /* 1154 * Prepare for SMP bootup. The MP table or ACPI has been read 1155 * earlier. Just do some sanity checking here and enable APIC mode. 1156 */ 1157 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1158 { 1159 unsigned int i; 1160 1161 smp_cpu_index_default(); 1162 1163 /* 1164 * Setup boot CPU information 1165 */ 1166 smp_store_boot_cpu_info(); /* Final full version of the data */ 1167 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1168 mb(); 1169 1170 current_thread_info()->cpu = 0; /* needed? */ 1171 for_each_possible_cpu(i) { 1172 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1173 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1174 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1175 } 1176 set_cpu_sibling_map(0); 1177 1178 switch (smp_sanity_check(max_cpus)) { 1179 case SMP_NO_CONFIG: 1180 disable_smp(); 1181 if (APIC_init_uniprocessor()) 1182 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1183 return; 1184 case SMP_NO_APIC: 1185 disable_smp(); 1186 return; 1187 case SMP_FORCE_UP: 1188 disable_smp(); 1189 apic_bsp_setup(false); 1190 return; 1191 case SMP_OK: 1192 break; 1193 } 1194 1195 default_setup_apic_routing(); 1196 1197 if (read_apic_id() != boot_cpu_physical_apicid) { 1198 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1199 read_apic_id(), boot_cpu_physical_apicid); 1200 /* Or can we switch back to PIC here? */ 1201 } 1202 1203 cpu0_logical_apicid = apic_bsp_setup(false); 1204 1205 pr_info("CPU%d: ", 0); 1206 print_cpu_info(&cpu_data(0)); 1207 1208 if (is_uv_system()) 1209 uv_system_init(); 1210 1211 set_mtrr_aps_delayed_init(); 1212 1213 smp_quirk_init_udelay(); 1214 } 1215 1216 void arch_enable_nonboot_cpus_begin(void) 1217 { 1218 set_mtrr_aps_delayed_init(); 1219 } 1220 1221 void arch_enable_nonboot_cpus_end(void) 1222 { 1223 mtrr_aps_init(); 1224 } 1225 1226 /* 1227 * Early setup to make printk work. 1228 */ 1229 void __init native_smp_prepare_boot_cpu(void) 1230 { 1231 int me = smp_processor_id(); 1232 switch_to_new_gdt(me); 1233 /* already set me in cpu_online_mask in boot_cpu_init() */ 1234 cpumask_set_cpu(me, cpu_callout_mask); 1235 cpu_set_state_online(me); 1236 } 1237 1238 void __init native_smp_cpus_done(unsigned int max_cpus) 1239 { 1240 pr_debug("Boot done\n"); 1241 1242 nmi_selftest(); 1243 impress_friends(); 1244 setup_ioapic_dest(); 1245 mtrr_aps_init(); 1246 } 1247 1248 static int __initdata setup_possible_cpus = -1; 1249 static int __init _setup_possible_cpus(char *str) 1250 { 1251 get_option(&str, &setup_possible_cpus); 1252 return 0; 1253 } 1254 early_param("possible_cpus", _setup_possible_cpus); 1255 1256 1257 /* 1258 * cpu_possible_mask should be static, it cannot change as cpu's 1259 * are onlined, or offlined. The reason is per-cpu data-structures 1260 * are allocated by some modules at init time, and dont expect to 1261 * do this dynamically on cpu arrival/departure. 1262 * cpu_present_mask on the other hand can change dynamically. 1263 * In case when cpu_hotplug is not compiled, then we resort to current 1264 * behaviour, which is cpu_possible == cpu_present. 1265 * - Ashok Raj 1266 * 1267 * Three ways to find out the number of additional hotplug CPUs: 1268 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1269 * - The user can overwrite it with possible_cpus=NUM 1270 * - Otherwise don't reserve additional CPUs. 1271 * We do this because additional CPUs waste a lot of memory. 1272 * -AK 1273 */ 1274 __init void prefill_possible_map(void) 1275 { 1276 int i, possible; 1277 1278 /* no processor from mptable or madt */ 1279 if (!num_processors) 1280 num_processors = 1; 1281 1282 i = setup_max_cpus ?: 1; 1283 if (setup_possible_cpus == -1) { 1284 possible = num_processors; 1285 #ifdef CONFIG_HOTPLUG_CPU 1286 if (setup_max_cpus) 1287 possible += disabled_cpus; 1288 #else 1289 if (possible > i) 1290 possible = i; 1291 #endif 1292 } else 1293 possible = setup_possible_cpus; 1294 1295 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1296 1297 /* nr_cpu_ids could be reduced via nr_cpus= */ 1298 if (possible > nr_cpu_ids) { 1299 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1300 possible, nr_cpu_ids); 1301 possible = nr_cpu_ids; 1302 } 1303 1304 #ifdef CONFIG_HOTPLUG_CPU 1305 if (!setup_max_cpus) 1306 #endif 1307 if (possible > i) { 1308 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1309 possible, setup_max_cpus); 1310 possible = i; 1311 } 1312 1313 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1314 possible, max_t(int, possible - num_processors, 0)); 1315 1316 for (i = 0; i < possible; i++) 1317 set_cpu_possible(i, true); 1318 for (; i < NR_CPUS; i++) 1319 set_cpu_possible(i, false); 1320 1321 nr_cpu_ids = possible; 1322 } 1323 1324 #ifdef CONFIG_HOTPLUG_CPU 1325 1326 static void remove_siblinginfo(int cpu) 1327 { 1328 int sibling; 1329 struct cpuinfo_x86 *c = &cpu_data(cpu); 1330 1331 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1332 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1333 /*/ 1334 * last thread sibling in this cpu core going down 1335 */ 1336 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1337 cpu_data(sibling).booted_cores--; 1338 } 1339 1340 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1341 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1342 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1343 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1344 cpumask_clear(cpu_llc_shared_mask(cpu)); 1345 cpumask_clear(topology_sibling_cpumask(cpu)); 1346 cpumask_clear(topology_core_cpumask(cpu)); 1347 c->phys_proc_id = 0; 1348 c->cpu_core_id = 0; 1349 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1350 } 1351 1352 static void remove_cpu_from_maps(int cpu) 1353 { 1354 set_cpu_online(cpu, false); 1355 cpumask_clear_cpu(cpu, cpu_callout_mask); 1356 cpumask_clear_cpu(cpu, cpu_callin_mask); 1357 /* was set by cpu_init() */ 1358 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1359 numa_remove_cpu(cpu); 1360 } 1361 1362 void cpu_disable_common(void) 1363 { 1364 int cpu = smp_processor_id(); 1365 1366 remove_siblinginfo(cpu); 1367 1368 /* It's now safe to remove this processor from the online map */ 1369 lock_vector_lock(); 1370 remove_cpu_from_maps(cpu); 1371 unlock_vector_lock(); 1372 fixup_irqs(); 1373 } 1374 1375 int native_cpu_disable(void) 1376 { 1377 int ret; 1378 1379 ret = check_irq_vectors_for_cpu_disable(); 1380 if (ret) 1381 return ret; 1382 1383 clear_local_APIC(); 1384 cpu_disable_common(); 1385 1386 return 0; 1387 } 1388 1389 int common_cpu_die(unsigned int cpu) 1390 { 1391 int ret = 0; 1392 1393 /* We don't do anything here: idle task is faking death itself. */ 1394 1395 /* They ack this in play_dead() by setting CPU_DEAD */ 1396 if (cpu_wait_death(cpu, 5)) { 1397 if (system_state == SYSTEM_RUNNING) 1398 pr_info("CPU %u is now offline\n", cpu); 1399 } else { 1400 pr_err("CPU %u didn't die...\n", cpu); 1401 ret = -1; 1402 } 1403 1404 return ret; 1405 } 1406 1407 void native_cpu_die(unsigned int cpu) 1408 { 1409 common_cpu_die(cpu); 1410 } 1411 1412 void play_dead_common(void) 1413 { 1414 idle_task_exit(); 1415 reset_lazy_tlbstate(); 1416 amd_e400_remove_cpu(raw_smp_processor_id()); 1417 1418 /* Ack it */ 1419 (void)cpu_report_death(); 1420 1421 /* 1422 * With physical CPU hotplug, we should halt the cpu 1423 */ 1424 local_irq_disable(); 1425 } 1426 1427 static bool wakeup_cpu0(void) 1428 { 1429 if (smp_processor_id() == 0 && enable_start_cpu0) 1430 return true; 1431 1432 return false; 1433 } 1434 1435 /* 1436 * We need to flush the caches before going to sleep, lest we have 1437 * dirty data in our caches when we come back up. 1438 */ 1439 static inline void mwait_play_dead(void) 1440 { 1441 unsigned int eax, ebx, ecx, edx; 1442 unsigned int highest_cstate = 0; 1443 unsigned int highest_subcstate = 0; 1444 void *mwait_ptr; 1445 int i; 1446 1447 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1448 return; 1449 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1450 return; 1451 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1452 return; 1453 1454 eax = CPUID_MWAIT_LEAF; 1455 ecx = 0; 1456 native_cpuid(&eax, &ebx, &ecx, &edx); 1457 1458 /* 1459 * eax will be 0 if EDX enumeration is not valid. 1460 * Initialized below to cstate, sub_cstate value when EDX is valid. 1461 */ 1462 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1463 eax = 0; 1464 } else { 1465 edx >>= MWAIT_SUBSTATE_SIZE; 1466 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1467 if (edx & MWAIT_SUBSTATE_MASK) { 1468 highest_cstate = i; 1469 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1470 } 1471 } 1472 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1473 (highest_subcstate - 1); 1474 } 1475 1476 /* 1477 * This should be a memory location in a cache line which is 1478 * unlikely to be touched by other processors. The actual 1479 * content is immaterial as it is not actually modified in any way. 1480 */ 1481 mwait_ptr = ¤t_thread_info()->flags; 1482 1483 wbinvd(); 1484 1485 while (1) { 1486 /* 1487 * The CLFLUSH is a workaround for erratum AAI65 for 1488 * the Xeon 7400 series. It's not clear it is actually 1489 * needed, but it should be harmless in either case. 1490 * The WBINVD is insufficient due to the spurious-wakeup 1491 * case where we return around the loop. 1492 */ 1493 mb(); 1494 clflush(mwait_ptr); 1495 mb(); 1496 __monitor(mwait_ptr, 0, 0); 1497 mb(); 1498 __mwait(eax, 0); 1499 /* 1500 * If NMI wants to wake up CPU0, start CPU0. 1501 */ 1502 if (wakeup_cpu0()) 1503 start_cpu0(); 1504 } 1505 } 1506 1507 static inline void hlt_play_dead(void) 1508 { 1509 if (__this_cpu_read(cpu_info.x86) >= 4) 1510 wbinvd(); 1511 1512 while (1) { 1513 native_halt(); 1514 /* 1515 * If NMI wants to wake up CPU0, start CPU0. 1516 */ 1517 if (wakeup_cpu0()) 1518 start_cpu0(); 1519 } 1520 } 1521 1522 void native_play_dead(void) 1523 { 1524 play_dead_common(); 1525 tboot_shutdown(TB_SHUTDOWN_WFS); 1526 1527 mwait_play_dead(); /* Only returns on failure */ 1528 if (cpuidle_play_dead()) 1529 hlt_play_dead(); 1530 } 1531 1532 #else /* ... !CONFIG_HOTPLUG_CPU */ 1533 int native_cpu_disable(void) 1534 { 1535 return -ENOSYS; 1536 } 1537 1538 void native_cpu_die(unsigned int cpu) 1539 { 1540 /* We said "no" in __cpu_disable */ 1541 BUG(); 1542 } 1543 1544 void native_play_dead(void) 1545 { 1546 BUG(); 1547 } 1548 1549 #endif 1550