1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/desc.h> 64 #include <asm/nmi.h> 65 #include <asm/irq.h> 66 #include <asm/realmode.h> 67 #include <asm/cpu.h> 68 #include <asm/numa.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/api.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 #include <asm/stackprotector.h> 86 #include <asm/sev.h> 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 /* representing HT, core, and die siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* Logical package management. We might want to allocate that dynamically */ 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 static unsigned int logical_packages __read_mostly; 108 static unsigned int logical_die __read_mostly; 109 110 /* Maximum number of SMT threads on any online core */ 111 int __read_mostly __max_smt_threads = 1; 112 113 /* Flag to indicate if a complete sched domain rebuild is required */ 114 bool x86_topology_update; 115 116 int arch_update_cpu_topology(void) 117 { 118 int retval = x86_topology_update; 119 120 x86_topology_update = false; 121 return retval; 122 } 123 124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 125 { 126 unsigned long flags; 127 128 spin_lock_irqsave(&rtc_lock, flags); 129 CMOS_WRITE(0xa, 0xf); 130 spin_unlock_irqrestore(&rtc_lock, flags); 131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 132 start_eip >> 4; 133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 134 start_eip & 0xf; 135 } 136 137 static inline void smpboot_restore_warm_reset_vector(void) 138 { 139 unsigned long flags; 140 141 /* 142 * Paranoid: Set warm reset code and vector here back 143 * to default values. 144 */ 145 spin_lock_irqsave(&rtc_lock, flags); 146 CMOS_WRITE(0, 0xf); 147 spin_unlock_irqrestore(&rtc_lock, flags); 148 149 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 150 } 151 152 /* 153 * Report back to the Boot Processor during boot time or to the caller processor 154 * during CPU online. 155 */ 156 static void smp_callin(void) 157 { 158 int cpuid; 159 160 /* 161 * If waken up by an INIT in an 82489DX configuration 162 * cpu_callout_mask guarantees we don't get here before 163 * an INIT_deassert IPI reaches our local APIC, so it is 164 * now safe to touch our local APIC. 165 */ 166 cpuid = smp_processor_id(); 167 168 /* 169 * the boot CPU has finished the init stage and is spinning 170 * on callin_map until we finish. We are free to set up this 171 * CPU, first the APIC. (this is probably redundant on most 172 * boards) 173 */ 174 apic_ap_setup(); 175 176 /* 177 * Save our processor parameters. Note: this information 178 * is needed for clock calibration. 179 */ 180 smp_store_cpu_info(cpuid); 181 182 /* 183 * The topology information must be up to date before 184 * calibrate_delay() and notify_cpu_starting(). 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 188 ap_init_aperfmperf(); 189 190 /* 191 * Get our bogomips. 192 * Update loops_per_jiffy in cpu_data. Previous call to 193 * smp_store_cpu_info() stored a value that is close but not as 194 * accurate as the value just calculated. 195 */ 196 calibrate_delay(); 197 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 198 pr_debug("Stack at about %p\n", &cpuid); 199 200 wmb(); 201 202 notify_cpu_starting(cpuid); 203 204 /* 205 * Allow the master to continue. 206 */ 207 cpumask_set_cpu(cpuid, cpu_callin_mask); 208 } 209 210 static int cpu0_logical_apicid; 211 static int enable_start_cpu0; 212 /* 213 * Activate a secondary processor. 214 */ 215 static void notrace start_secondary(void *unused) 216 { 217 /* 218 * Don't put *anything* except direct CPU state initialization 219 * before cpu_init(), SMP booting is too fragile that we want to 220 * limit the things done here to the most necessary things. 221 */ 222 cr4_init(); 223 224 #ifdef CONFIG_X86_32 225 /* switch away from the initial page table */ 226 load_cr3(swapper_pg_dir); 227 __flush_tlb_all(); 228 #endif 229 cpu_init_secondary(); 230 rcu_cpu_starting(raw_smp_processor_id()); 231 x86_cpuinit.early_percpu_clock_init(); 232 smp_callin(); 233 234 enable_start_cpu0 = 0; 235 236 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 237 barrier(); 238 /* 239 * Check TSC synchronization with the boot CPU: 240 */ 241 check_tsc_sync_target(); 242 243 speculative_store_bypass_ht_init(); 244 245 /* 246 * Lock vector_lock, set CPU online and bring the vector 247 * allocator online. Online must be set with vector_lock held 248 * to prevent a concurrent irq setup/teardown from seeing a 249 * half valid vector space. 250 */ 251 lock_vector_lock(); 252 set_cpu_online(smp_processor_id(), true); 253 lapic_online(); 254 unlock_vector_lock(); 255 cpu_set_state_online(smp_processor_id()); 256 x86_platform.nmi_init(); 257 258 /* enable local interrupts */ 259 local_irq_enable(); 260 261 x86_cpuinit.setup_percpu_clockev(); 262 263 wmb(); 264 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 265 } 266 267 /** 268 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 269 * @cpu: CPU to check 270 */ 271 bool topology_is_primary_thread(unsigned int cpu) 272 { 273 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 274 } 275 276 /** 277 * topology_smt_supported - Check whether SMT is supported by the CPUs 278 */ 279 bool topology_smt_supported(void) 280 { 281 return smp_num_siblings > 1; 282 } 283 284 /** 285 * topology_phys_to_logical_pkg - Map a physical package id to a logical 286 * 287 * Returns logical package id or -1 if not found 288 */ 289 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 290 { 291 int cpu; 292 293 for_each_possible_cpu(cpu) { 294 struct cpuinfo_x86 *c = &cpu_data(cpu); 295 296 if (c->initialized && c->phys_proc_id == phys_pkg) 297 return c->logical_proc_id; 298 } 299 return -1; 300 } 301 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 302 /** 303 * topology_phys_to_logical_die - Map a physical die id to logical 304 * 305 * Returns logical die id or -1 if not found 306 */ 307 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 308 { 309 int cpu; 310 int proc_id = cpu_data(cur_cpu).phys_proc_id; 311 312 for_each_possible_cpu(cpu) { 313 struct cpuinfo_x86 *c = &cpu_data(cpu); 314 315 if (c->initialized && c->cpu_die_id == die_id && 316 c->phys_proc_id == proc_id) 317 return c->logical_die_id; 318 } 319 return -1; 320 } 321 EXPORT_SYMBOL(topology_phys_to_logical_die); 322 323 /** 324 * topology_update_package_map - Update the physical to logical package map 325 * @pkg: The physical package id as retrieved via CPUID 326 * @cpu: The cpu for which this is updated 327 */ 328 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 329 { 330 int new; 331 332 /* Already available somewhere? */ 333 new = topology_phys_to_logical_pkg(pkg); 334 if (new >= 0) 335 goto found; 336 337 new = logical_packages++; 338 if (new != pkg) { 339 pr_info("CPU %u Converting physical %u to logical package %u\n", 340 cpu, pkg, new); 341 } 342 found: 343 cpu_data(cpu).logical_proc_id = new; 344 return 0; 345 } 346 /** 347 * topology_update_die_map - Update the physical to logical die map 348 * @die: The die id as retrieved via CPUID 349 * @cpu: The cpu for which this is updated 350 */ 351 int topology_update_die_map(unsigned int die, unsigned int cpu) 352 { 353 int new; 354 355 /* Already available somewhere? */ 356 new = topology_phys_to_logical_die(die, cpu); 357 if (new >= 0) 358 goto found; 359 360 new = logical_die++; 361 if (new != die) { 362 pr_info("CPU %u Converting physical %u to logical die %u\n", 363 cpu, die, new); 364 } 365 found: 366 cpu_data(cpu).logical_die_id = new; 367 return 0; 368 } 369 370 void __init smp_store_boot_cpu_info(void) 371 { 372 int id = 0; /* CPU 0 */ 373 struct cpuinfo_x86 *c = &cpu_data(id); 374 375 *c = boot_cpu_data; 376 c->cpu_index = id; 377 topology_update_package_map(c->phys_proc_id, id); 378 topology_update_die_map(c->cpu_die_id, id); 379 c->initialized = true; 380 } 381 382 /* 383 * The bootstrap kernel entry code has set these up. Save them for 384 * a given CPU 385 */ 386 void smp_store_cpu_info(int id) 387 { 388 struct cpuinfo_x86 *c = &cpu_data(id); 389 390 /* Copy boot_cpu_data only on the first bringup */ 391 if (!c->initialized) 392 *c = boot_cpu_data; 393 c->cpu_index = id; 394 /* 395 * During boot time, CPU0 has this setup already. Save the info when 396 * bringing up AP or offlined CPU0. 397 */ 398 identify_secondary_cpu(c); 399 c->initialized = true; 400 } 401 402 static bool 403 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 404 { 405 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 406 407 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 408 } 409 410 static bool 411 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 412 { 413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 414 415 return !WARN_ONCE(!topology_same_node(c, o), 416 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 417 "[node: %d != %d]. Ignoring dependency.\n", 418 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 419 } 420 421 #define link_mask(mfunc, c1, c2) \ 422 do { \ 423 cpumask_set_cpu((c1), mfunc(c2)); \ 424 cpumask_set_cpu((c2), mfunc(c1)); \ 425 } while (0) 426 427 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 428 { 429 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 431 432 if (c->phys_proc_id == o->phys_proc_id && 433 c->cpu_die_id == o->cpu_die_id && 434 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 435 if (c->cpu_core_id == o->cpu_core_id) 436 return topology_sane(c, o, "smt"); 437 438 if ((c->cu_id != 0xff) && 439 (o->cu_id != 0xff) && 440 (c->cu_id == o->cu_id)) 441 return topology_sane(c, o, "smt"); 442 } 443 444 } else if (c->phys_proc_id == o->phys_proc_id && 445 c->cpu_die_id == o->cpu_die_id && 446 c->cpu_core_id == o->cpu_core_id) { 447 return topology_sane(c, o, "smt"); 448 } 449 450 return false; 451 } 452 453 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 454 { 455 if (c->phys_proc_id == o->phys_proc_id && 456 c->cpu_die_id == o->cpu_die_id) 457 return true; 458 return false; 459 } 460 461 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 462 { 463 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 464 465 /* If the arch didn't set up l2c_id, fall back to SMT */ 466 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 467 return match_smt(c, o); 468 469 /* Do not match if L2 cache id does not match: */ 470 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 471 return false; 472 473 return topology_sane(c, o, "l2c"); 474 } 475 476 /* 477 * Unlike the other levels, we do not enforce keeping a 478 * multicore group inside a NUMA node. If this happens, we will 479 * discard the MC level of the topology later. 480 */ 481 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 482 { 483 if (c->phys_proc_id == o->phys_proc_id) 484 return true; 485 return false; 486 } 487 488 /* 489 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 490 * 491 * Any Intel CPU that has multiple nodes per package and does not 492 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 493 * 494 * When in SNC mode, these CPUs enumerate an LLC that is shared 495 * by multiple NUMA nodes. The LLC is shared for off-package data 496 * access but private to the NUMA node (half of the package) for 497 * on-package access. CPUID (the source of the information about 498 * the LLC) can only enumerate the cache as shared or unshared, 499 * but not this particular configuration. 500 */ 501 502 static const struct x86_cpu_id intel_cod_cpu[] = { 503 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 504 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 505 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 506 {} 507 }; 508 509 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 510 { 511 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 512 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 513 bool intel_snc = id && id->driver_data; 514 515 /* Do not match if we do not have a valid APICID for cpu: */ 516 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 517 return false; 518 519 /* Do not match if LLC id does not match: */ 520 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 521 return false; 522 523 /* 524 * Allow the SNC topology without warning. Return of false 525 * means 'c' does not share the LLC of 'o'. This will be 526 * reflected to userspace. 527 */ 528 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 529 return false; 530 531 return topology_sane(c, o, "llc"); 532 } 533 534 535 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 536 static inline int x86_sched_itmt_flags(void) 537 { 538 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 539 } 540 541 #ifdef CONFIG_SCHED_MC 542 static int x86_core_flags(void) 543 { 544 return cpu_core_flags() | x86_sched_itmt_flags(); 545 } 546 #endif 547 #ifdef CONFIG_SCHED_SMT 548 static int x86_smt_flags(void) 549 { 550 return cpu_smt_flags() | x86_sched_itmt_flags(); 551 } 552 #endif 553 #ifdef CONFIG_SCHED_CLUSTER 554 static int x86_cluster_flags(void) 555 { 556 return cpu_cluster_flags() | x86_sched_itmt_flags(); 557 } 558 #endif 559 #endif 560 561 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 562 #ifdef CONFIG_SCHED_SMT 563 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 564 #endif 565 #ifdef CONFIG_SCHED_CLUSTER 566 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 567 #endif 568 #ifdef CONFIG_SCHED_MC 569 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 570 #endif 571 { NULL, }, 572 }; 573 574 static struct sched_domain_topology_level x86_hybrid_topology[] = { 575 #ifdef CONFIG_SCHED_SMT 576 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 577 #endif 578 #ifdef CONFIG_SCHED_MC 579 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 580 #endif 581 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 582 { NULL, }, 583 }; 584 585 static struct sched_domain_topology_level x86_topology[] = { 586 #ifdef CONFIG_SCHED_SMT 587 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 588 #endif 589 #ifdef CONFIG_SCHED_CLUSTER 590 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 591 #endif 592 #ifdef CONFIG_SCHED_MC 593 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 594 #endif 595 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 596 { NULL, }, 597 }; 598 599 /* 600 * Set if a package/die has multiple NUMA nodes inside. 601 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 602 * Sub-NUMA Clustering have this. 603 */ 604 static bool x86_has_numa_in_package; 605 606 void set_cpu_sibling_map(int cpu) 607 { 608 bool has_smt = smp_num_siblings > 1; 609 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 610 struct cpuinfo_x86 *c = &cpu_data(cpu); 611 struct cpuinfo_x86 *o; 612 int i, threads; 613 614 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 615 616 if (!has_mp) { 617 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 618 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 619 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 620 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 621 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 622 c->booted_cores = 1; 623 return; 624 } 625 626 for_each_cpu(i, cpu_sibling_setup_mask) { 627 o = &cpu_data(i); 628 629 if (match_pkg(c, o) && !topology_same_node(c, o)) 630 x86_has_numa_in_package = true; 631 632 if ((i == cpu) || (has_smt && match_smt(c, o))) 633 link_mask(topology_sibling_cpumask, cpu, i); 634 635 if ((i == cpu) || (has_mp && match_llc(c, o))) 636 link_mask(cpu_llc_shared_mask, cpu, i); 637 638 if ((i == cpu) || (has_mp && match_l2c(c, o))) 639 link_mask(cpu_l2c_shared_mask, cpu, i); 640 641 if ((i == cpu) || (has_mp && match_die(c, o))) 642 link_mask(topology_die_cpumask, cpu, i); 643 } 644 645 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 646 if (threads > __max_smt_threads) 647 __max_smt_threads = threads; 648 649 for_each_cpu(i, topology_sibling_cpumask(cpu)) 650 cpu_data(i).smt_active = threads > 1; 651 652 /* 653 * This needs a separate iteration over the cpus because we rely on all 654 * topology_sibling_cpumask links to be set-up. 655 */ 656 for_each_cpu(i, cpu_sibling_setup_mask) { 657 o = &cpu_data(i); 658 659 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 660 link_mask(topology_core_cpumask, cpu, i); 661 662 /* 663 * Does this new cpu bringup a new core? 664 */ 665 if (threads == 1) { 666 /* 667 * for each core in package, increment 668 * the booted_cores for this new cpu 669 */ 670 if (cpumask_first( 671 topology_sibling_cpumask(i)) == i) 672 c->booted_cores++; 673 /* 674 * increment the core count for all 675 * the other cpus in this package 676 */ 677 if (i != cpu) 678 cpu_data(i).booted_cores++; 679 } else if (i != cpu && !c->booted_cores) 680 c->booted_cores = cpu_data(i).booted_cores; 681 } 682 } 683 } 684 685 /* maps the cpu to the sched domain representing multi-core */ 686 const struct cpumask *cpu_coregroup_mask(int cpu) 687 { 688 return cpu_llc_shared_mask(cpu); 689 } 690 691 const struct cpumask *cpu_clustergroup_mask(int cpu) 692 { 693 return cpu_l2c_shared_mask(cpu); 694 } 695 696 static void impress_friends(void) 697 { 698 int cpu; 699 unsigned long bogosum = 0; 700 /* 701 * Allow the user to impress friends. 702 */ 703 pr_debug("Before bogomips\n"); 704 for_each_possible_cpu(cpu) 705 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 706 bogosum += cpu_data(cpu).loops_per_jiffy; 707 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 708 num_online_cpus(), 709 bogosum/(500000/HZ), 710 (bogosum/(5000/HZ))%100); 711 712 pr_debug("Before bogocount - setting activated=1\n"); 713 } 714 715 void __inquire_remote_apic(int apicid) 716 { 717 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 718 const char * const names[] = { "ID", "VERSION", "SPIV" }; 719 int timeout; 720 u32 status; 721 722 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 723 724 for (i = 0; i < ARRAY_SIZE(regs); i++) { 725 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 726 727 /* 728 * Wait for idle. 729 */ 730 status = safe_apic_wait_icr_idle(); 731 if (status) 732 pr_cont("a previous APIC delivery may have failed\n"); 733 734 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 735 736 timeout = 0; 737 do { 738 udelay(100); 739 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 740 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 741 742 switch (status) { 743 case APIC_ICR_RR_VALID: 744 status = apic_read(APIC_RRR); 745 pr_cont("%08x\n", status); 746 break; 747 default: 748 pr_cont("failed\n"); 749 } 750 } 751 } 752 753 /* 754 * The Multiprocessor Specification 1.4 (1997) example code suggests 755 * that there should be a 10ms delay between the BSP asserting INIT 756 * and de-asserting INIT, when starting a remote processor. 757 * But that slows boot and resume on modern processors, which include 758 * many cores and don't require that delay. 759 * 760 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 761 * Modern processor families are quirked to remove the delay entirely. 762 */ 763 #define UDELAY_10MS_DEFAULT 10000 764 765 static unsigned int init_udelay = UINT_MAX; 766 767 static int __init cpu_init_udelay(char *str) 768 { 769 get_option(&str, &init_udelay); 770 771 return 0; 772 } 773 early_param("cpu_init_udelay", cpu_init_udelay); 774 775 static void __init smp_quirk_init_udelay(void) 776 { 777 /* if cmdline changed it from default, leave it alone */ 778 if (init_udelay != UINT_MAX) 779 return; 780 781 /* if modern processor, use no delay */ 782 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 783 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 784 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 785 init_udelay = 0; 786 return; 787 } 788 /* else, use legacy delay */ 789 init_udelay = UDELAY_10MS_DEFAULT; 790 } 791 792 /* 793 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 794 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 795 * won't ... remember to clear down the APIC, etc later. 796 */ 797 int 798 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 799 { 800 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 801 unsigned long send_status, accept_status = 0; 802 int maxlvt; 803 804 /* Target chip */ 805 /* Boot on the stack */ 806 /* Kick the second */ 807 apic_icr_write(APIC_DM_NMI | dm, apicid); 808 809 pr_debug("Waiting for send to finish...\n"); 810 send_status = safe_apic_wait_icr_idle(); 811 812 /* 813 * Give the other CPU some time to accept the IPI. 814 */ 815 udelay(200); 816 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 817 maxlvt = lapic_get_maxlvt(); 818 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 819 apic_write(APIC_ESR, 0); 820 accept_status = (apic_read(APIC_ESR) & 0xEF); 821 } 822 pr_debug("NMI sent\n"); 823 824 if (send_status) 825 pr_err("APIC never delivered???\n"); 826 if (accept_status) 827 pr_err("APIC delivery error (%lx)\n", accept_status); 828 829 return (send_status | accept_status); 830 } 831 832 static int 833 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 834 { 835 unsigned long send_status = 0, accept_status = 0; 836 int maxlvt, num_starts, j; 837 838 maxlvt = lapic_get_maxlvt(); 839 840 /* 841 * Be paranoid about clearing APIC errors. 842 */ 843 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 844 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 845 apic_write(APIC_ESR, 0); 846 apic_read(APIC_ESR); 847 } 848 849 pr_debug("Asserting INIT\n"); 850 851 /* 852 * Turn INIT on target chip 853 */ 854 /* 855 * Send IPI 856 */ 857 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 858 phys_apicid); 859 860 pr_debug("Waiting for send to finish...\n"); 861 send_status = safe_apic_wait_icr_idle(); 862 863 udelay(init_udelay); 864 865 pr_debug("Deasserting INIT\n"); 866 867 /* Target chip */ 868 /* Send IPI */ 869 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 870 871 pr_debug("Waiting for send to finish...\n"); 872 send_status = safe_apic_wait_icr_idle(); 873 874 mb(); 875 876 /* 877 * Should we send STARTUP IPIs ? 878 * 879 * Determine this based on the APIC version. 880 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 881 */ 882 if (APIC_INTEGRATED(boot_cpu_apic_version)) 883 num_starts = 2; 884 else 885 num_starts = 0; 886 887 /* 888 * Run STARTUP IPI loop. 889 */ 890 pr_debug("#startup loops: %d\n", num_starts); 891 892 for (j = 1; j <= num_starts; j++) { 893 pr_debug("Sending STARTUP #%d\n", j); 894 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 895 apic_write(APIC_ESR, 0); 896 apic_read(APIC_ESR); 897 pr_debug("After apic_write\n"); 898 899 /* 900 * STARTUP IPI 901 */ 902 903 /* Target chip */ 904 /* Boot on the stack */ 905 /* Kick the second */ 906 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 907 phys_apicid); 908 909 /* 910 * Give the other CPU some time to accept the IPI. 911 */ 912 if (init_udelay == 0) 913 udelay(10); 914 else 915 udelay(300); 916 917 pr_debug("Startup point 1\n"); 918 919 pr_debug("Waiting for send to finish...\n"); 920 send_status = safe_apic_wait_icr_idle(); 921 922 /* 923 * Give the other CPU some time to accept the IPI. 924 */ 925 if (init_udelay == 0) 926 udelay(10); 927 else 928 udelay(200); 929 930 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 931 apic_write(APIC_ESR, 0); 932 accept_status = (apic_read(APIC_ESR) & 0xEF); 933 if (send_status || accept_status) 934 break; 935 } 936 pr_debug("After Startup\n"); 937 938 if (send_status) 939 pr_err("APIC never delivered???\n"); 940 if (accept_status) 941 pr_err("APIC delivery error (%lx)\n", accept_status); 942 943 return (send_status | accept_status); 944 } 945 946 /* reduce the number of lines printed when booting a large cpu count system */ 947 static void announce_cpu(int cpu, int apicid) 948 { 949 static int current_node = NUMA_NO_NODE; 950 int node = early_cpu_to_node(cpu); 951 static int width, node_width; 952 953 if (!width) 954 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 955 956 if (!node_width) 957 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 958 959 if (cpu == 1) 960 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 961 962 if (system_state < SYSTEM_RUNNING) { 963 if (node != current_node) { 964 if (current_node > (-1)) 965 pr_cont("\n"); 966 current_node = node; 967 968 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 969 node_width - num_digits(node), " ", node); 970 } 971 972 /* Add padding for the BSP */ 973 if (cpu == 1) 974 pr_cont("%*s", width + 1, " "); 975 976 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 977 978 } else 979 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 980 node, cpu, apicid); 981 } 982 983 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 984 { 985 int cpu; 986 987 cpu = smp_processor_id(); 988 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 989 return NMI_HANDLED; 990 991 return NMI_DONE; 992 } 993 994 /* 995 * Wake up AP by INIT, INIT, STARTUP sequence. 996 * 997 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 998 * boot-strap code which is not a desired behavior for waking up BSP. To 999 * void the boot-strap code, wake up CPU0 by NMI instead. 1000 * 1001 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 1002 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 1003 * We'll change this code in the future to wake up hard offlined CPU0 if 1004 * real platform and request are available. 1005 */ 1006 static int 1007 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 1008 int *cpu0_nmi_registered) 1009 { 1010 int id; 1011 int boot_error; 1012 1013 preempt_disable(); 1014 1015 /* 1016 * Wake up AP by INIT, INIT, STARTUP sequence. 1017 */ 1018 if (cpu) { 1019 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 1020 goto out; 1021 } 1022 1023 /* 1024 * Wake up BSP by nmi. 1025 * 1026 * Register a NMI handler to help wake up CPU0. 1027 */ 1028 boot_error = register_nmi_handler(NMI_LOCAL, 1029 wakeup_cpu0_nmi, 0, "wake_cpu0"); 1030 1031 if (!boot_error) { 1032 enable_start_cpu0 = 1; 1033 *cpu0_nmi_registered = 1; 1034 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 1035 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 1036 } 1037 1038 out: 1039 preempt_enable(); 1040 1041 return boot_error; 1042 } 1043 1044 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1045 { 1046 int ret; 1047 1048 /* Just in case we booted with a single CPU. */ 1049 alternatives_enable_smp(); 1050 1051 per_cpu(pcpu_hot.current_task, cpu) = idle; 1052 cpu_init_stack_canary(cpu, idle); 1053 1054 /* Initialize the interrupt stack(s) */ 1055 ret = irq_init_percpu_irqstack(cpu); 1056 if (ret) 1057 return ret; 1058 1059 #ifdef CONFIG_X86_32 1060 /* Stack for startup_32 can be just as for start_secondary onwards */ 1061 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1062 #else 1063 initial_gs = per_cpu_offset(cpu); 1064 #endif 1065 return 0; 1066 } 1067 1068 /* 1069 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1070 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1071 * Returns zero if CPU booted OK, else error code from 1072 * ->wakeup_secondary_cpu. 1073 */ 1074 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1075 int *cpu0_nmi_registered) 1076 { 1077 /* start_ip had better be page-aligned! */ 1078 unsigned long start_ip = real_mode_header->trampoline_start; 1079 1080 unsigned long boot_error = 0; 1081 unsigned long timeout; 1082 1083 #ifdef CONFIG_X86_64 1084 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1085 if (apic->wakeup_secondary_cpu_64) 1086 start_ip = real_mode_header->trampoline_start64; 1087 #endif 1088 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1089 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1090 initial_code = (unsigned long)start_secondary; 1091 1092 if (IS_ENABLED(CONFIG_X86_32)) { 1093 initial_stack = idle->thread.sp; 1094 } else { 1095 smpboot_control = cpu; 1096 } 1097 1098 /* Enable the espfix hack for this CPU */ 1099 init_espfix_ap(cpu); 1100 1101 /* So we see what's up */ 1102 announce_cpu(cpu, apicid); 1103 1104 /* 1105 * This grunge runs the startup process for 1106 * the targeted processor. 1107 */ 1108 1109 if (x86_platform.legacy.warm_reset) { 1110 1111 pr_debug("Setting warm reset code and vector.\n"); 1112 1113 smpboot_setup_warm_reset_vector(start_ip); 1114 /* 1115 * Be paranoid about clearing APIC errors. 1116 */ 1117 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1118 apic_write(APIC_ESR, 0); 1119 apic_read(APIC_ESR); 1120 } 1121 } 1122 1123 /* 1124 * AP might wait on cpu_callout_mask in cpu_init() with 1125 * cpu_initialized_mask set if previous attempt to online 1126 * it timed-out. Clear cpu_initialized_mask so that after 1127 * INIT/SIPI it could start with a clean state. 1128 */ 1129 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1130 smp_mb(); 1131 1132 /* 1133 * Wake up a CPU in difference cases: 1134 * - Use a method from the APIC driver if one defined, with wakeup 1135 * straight to 64-bit mode preferred over wakeup to RM. 1136 * Otherwise, 1137 * - Use an INIT boot APIC message for APs or NMI for BSP. 1138 */ 1139 if (apic->wakeup_secondary_cpu_64) 1140 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1141 else if (apic->wakeup_secondary_cpu) 1142 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1143 else 1144 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1145 cpu0_nmi_registered); 1146 1147 if (!boot_error) { 1148 /* 1149 * Wait 10s total for first sign of life from AP 1150 */ 1151 boot_error = -1; 1152 timeout = jiffies + 10*HZ; 1153 while (time_before(jiffies, timeout)) { 1154 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1155 /* 1156 * Tell AP to proceed with initialization 1157 */ 1158 cpumask_set_cpu(cpu, cpu_callout_mask); 1159 boot_error = 0; 1160 break; 1161 } 1162 schedule(); 1163 } 1164 } 1165 1166 if (!boot_error) { 1167 /* 1168 * Wait till AP completes initial initialization 1169 */ 1170 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1171 /* 1172 * Allow other tasks to run while we wait for the 1173 * AP to come online. This also gives a chance 1174 * for the MTRR work(triggered by the AP coming online) 1175 * to be completed in the stop machine context. 1176 */ 1177 schedule(); 1178 } 1179 } 1180 1181 if (x86_platform.legacy.warm_reset) { 1182 /* 1183 * Cleanup possible dangling ends... 1184 */ 1185 smpboot_restore_warm_reset_vector(); 1186 } 1187 1188 return boot_error; 1189 } 1190 1191 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1192 { 1193 int apicid = apic->cpu_present_to_apicid(cpu); 1194 int cpu0_nmi_registered = 0; 1195 unsigned long flags; 1196 int err, ret = 0; 1197 1198 lockdep_assert_irqs_enabled(); 1199 1200 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1201 1202 if (apicid == BAD_APICID || 1203 !physid_isset(apicid, phys_cpu_present_map) || 1204 !apic->apic_id_valid(apicid)) { 1205 pr_err("%s: bad cpu %d\n", __func__, cpu); 1206 return -EINVAL; 1207 } 1208 1209 /* 1210 * Already booted CPU? 1211 */ 1212 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1213 pr_debug("do_boot_cpu %d Already started\n", cpu); 1214 return -ENOSYS; 1215 } 1216 1217 /* 1218 * Save current MTRR state in case it was changed since early boot 1219 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1220 */ 1221 mtrr_save_state(); 1222 1223 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1224 err = cpu_check_up_prepare(cpu); 1225 if (err && err != -EBUSY) 1226 return err; 1227 1228 /* the FPU context is blank, nobody can own it */ 1229 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1230 1231 err = common_cpu_up(cpu, tidle); 1232 if (err) 1233 return err; 1234 1235 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1236 if (err) { 1237 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1238 ret = -EIO; 1239 goto unreg_nmi; 1240 } 1241 1242 /* 1243 * Check TSC synchronization with the AP (keep irqs disabled 1244 * while doing so): 1245 */ 1246 local_irq_save(flags); 1247 check_tsc_sync_source(cpu); 1248 local_irq_restore(flags); 1249 1250 while (!cpu_online(cpu)) { 1251 cpu_relax(); 1252 touch_nmi_watchdog(); 1253 } 1254 1255 unreg_nmi: 1256 /* 1257 * Clean up the nmi handler. Do this after the callin and callout sync 1258 * to avoid impact of possible long unregister time. 1259 */ 1260 if (cpu0_nmi_registered) 1261 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1262 1263 return ret; 1264 } 1265 1266 /** 1267 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1268 */ 1269 void arch_disable_smp_support(void) 1270 { 1271 disable_ioapic_support(); 1272 } 1273 1274 /* 1275 * Fall back to non SMP mode after errors. 1276 * 1277 * RED-PEN audit/test this more. I bet there is more state messed up here. 1278 */ 1279 static __init void disable_smp(void) 1280 { 1281 pr_info("SMP disabled\n"); 1282 1283 disable_ioapic_support(); 1284 1285 init_cpu_present(cpumask_of(0)); 1286 init_cpu_possible(cpumask_of(0)); 1287 1288 if (smp_found_config) 1289 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1290 else 1291 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1292 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1293 cpumask_set_cpu(0, topology_core_cpumask(0)); 1294 cpumask_set_cpu(0, topology_die_cpumask(0)); 1295 } 1296 1297 /* 1298 * Various sanity checks. 1299 */ 1300 static void __init smp_sanity_check(void) 1301 { 1302 preempt_disable(); 1303 1304 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1305 if (def_to_bigsmp && nr_cpu_ids > 8) { 1306 unsigned int cpu; 1307 unsigned nr; 1308 1309 pr_warn("More than 8 CPUs detected - skipping them\n" 1310 "Use CONFIG_X86_BIGSMP\n"); 1311 1312 nr = 0; 1313 for_each_present_cpu(cpu) { 1314 if (nr >= 8) 1315 set_cpu_present(cpu, false); 1316 nr++; 1317 } 1318 1319 nr = 0; 1320 for_each_possible_cpu(cpu) { 1321 if (nr >= 8) 1322 set_cpu_possible(cpu, false); 1323 nr++; 1324 } 1325 1326 set_nr_cpu_ids(8); 1327 } 1328 #endif 1329 1330 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1331 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1332 hard_smp_processor_id()); 1333 1334 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1335 } 1336 1337 /* 1338 * Should not be necessary because the MP table should list the boot 1339 * CPU too, but we do it for the sake of robustness anyway. 1340 */ 1341 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1342 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1343 boot_cpu_physical_apicid); 1344 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1345 } 1346 preempt_enable(); 1347 } 1348 1349 static void __init smp_cpu_index_default(void) 1350 { 1351 int i; 1352 struct cpuinfo_x86 *c; 1353 1354 for_each_possible_cpu(i) { 1355 c = &cpu_data(i); 1356 /* mark all to hotplug */ 1357 c->cpu_index = nr_cpu_ids; 1358 } 1359 } 1360 1361 static void __init smp_get_logical_apicid(void) 1362 { 1363 if (x2apic_mode) 1364 cpu0_logical_apicid = apic_read(APIC_LDR); 1365 else 1366 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1367 } 1368 1369 void __init smp_prepare_cpus_common(void) 1370 { 1371 unsigned int i; 1372 1373 smp_cpu_index_default(); 1374 1375 /* 1376 * Setup boot CPU information 1377 */ 1378 smp_store_boot_cpu_info(); /* Final full version of the data */ 1379 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1380 mb(); 1381 1382 for_each_possible_cpu(i) { 1383 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1384 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1385 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1386 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1387 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1388 } 1389 1390 /* 1391 * Set 'default' x86 topology, this matches default_topology() in that 1392 * it has NUMA nodes as a topology level. See also 1393 * native_smp_cpus_done(). 1394 * 1395 * Must be done before set_cpus_sibling_map() is ran. 1396 */ 1397 set_sched_topology(x86_topology); 1398 1399 set_cpu_sibling_map(0); 1400 } 1401 1402 /* 1403 * Prepare for SMP bootup. 1404 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1405 * for common interface support. 1406 */ 1407 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1408 { 1409 smp_prepare_cpus_common(); 1410 1411 smp_sanity_check(); 1412 1413 switch (apic_intr_mode) { 1414 case APIC_PIC: 1415 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1416 disable_smp(); 1417 return; 1418 case APIC_SYMMETRIC_IO_NO_ROUTING: 1419 disable_smp(); 1420 /* Setup local timer */ 1421 x86_init.timers.setup_percpu_clockev(); 1422 return; 1423 case APIC_VIRTUAL_WIRE: 1424 case APIC_SYMMETRIC_IO: 1425 break; 1426 } 1427 1428 /* Setup local timer */ 1429 x86_init.timers.setup_percpu_clockev(); 1430 1431 smp_get_logical_apicid(); 1432 1433 pr_info("CPU0: "); 1434 print_cpu_info(&cpu_data(0)); 1435 1436 uv_system_init(); 1437 1438 smp_quirk_init_udelay(); 1439 1440 speculative_store_bypass_ht_init(); 1441 1442 snp_set_wakeup_secondary_cpu(); 1443 } 1444 1445 void arch_thaw_secondary_cpus_begin(void) 1446 { 1447 set_cache_aps_delayed_init(true); 1448 } 1449 1450 void arch_thaw_secondary_cpus_end(void) 1451 { 1452 cache_aps_init(); 1453 } 1454 1455 /* 1456 * Early setup to make printk work. 1457 */ 1458 void __init native_smp_prepare_boot_cpu(void) 1459 { 1460 int me = smp_processor_id(); 1461 1462 /* SMP handles this from setup_per_cpu_areas() */ 1463 if (!IS_ENABLED(CONFIG_SMP)) 1464 switch_gdt_and_percpu_base(me); 1465 1466 /* already set me in cpu_online_mask in boot_cpu_init() */ 1467 cpumask_set_cpu(me, cpu_callout_mask); 1468 cpu_set_state_online(me); 1469 native_pv_lock_init(); 1470 } 1471 1472 void __init calculate_max_logical_packages(void) 1473 { 1474 int ncpus; 1475 1476 /* 1477 * Today neither Intel nor AMD support heterogeneous systems so 1478 * extrapolate the boot cpu's data to all packages. 1479 */ 1480 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1481 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1482 pr_info("Max logical packages: %u\n", __max_logical_packages); 1483 } 1484 1485 void __init native_smp_cpus_done(unsigned int max_cpus) 1486 { 1487 pr_debug("Boot done\n"); 1488 1489 calculate_max_logical_packages(); 1490 1491 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1492 if (x86_has_numa_in_package) 1493 set_sched_topology(x86_numa_in_package_topology); 1494 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1495 set_sched_topology(x86_hybrid_topology); 1496 1497 nmi_selftest(); 1498 impress_friends(); 1499 cache_aps_init(); 1500 } 1501 1502 static int __initdata setup_possible_cpus = -1; 1503 static int __init _setup_possible_cpus(char *str) 1504 { 1505 get_option(&str, &setup_possible_cpus); 1506 return 0; 1507 } 1508 early_param("possible_cpus", _setup_possible_cpus); 1509 1510 1511 /* 1512 * cpu_possible_mask should be static, it cannot change as cpu's 1513 * are onlined, or offlined. The reason is per-cpu data-structures 1514 * are allocated by some modules at init time, and don't expect to 1515 * do this dynamically on cpu arrival/departure. 1516 * cpu_present_mask on the other hand can change dynamically. 1517 * In case when cpu_hotplug is not compiled, then we resort to current 1518 * behaviour, which is cpu_possible == cpu_present. 1519 * - Ashok Raj 1520 * 1521 * Three ways to find out the number of additional hotplug CPUs: 1522 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1523 * - The user can overwrite it with possible_cpus=NUM 1524 * - Otherwise don't reserve additional CPUs. 1525 * We do this because additional CPUs waste a lot of memory. 1526 * -AK 1527 */ 1528 __init void prefill_possible_map(void) 1529 { 1530 int i, possible; 1531 1532 /* No boot processor was found in mptable or ACPI MADT */ 1533 if (!num_processors) { 1534 if (boot_cpu_has(X86_FEATURE_APIC)) { 1535 int apicid = boot_cpu_physical_apicid; 1536 int cpu = hard_smp_processor_id(); 1537 1538 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1539 1540 /* Make sure boot cpu is enumerated */ 1541 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1542 apic->apic_id_valid(apicid)) 1543 generic_processor_info(apicid, boot_cpu_apic_version); 1544 } 1545 1546 if (!num_processors) 1547 num_processors = 1; 1548 } 1549 1550 i = setup_max_cpus ?: 1; 1551 if (setup_possible_cpus == -1) { 1552 possible = num_processors; 1553 #ifdef CONFIG_HOTPLUG_CPU 1554 if (setup_max_cpus) 1555 possible += disabled_cpus; 1556 #else 1557 if (possible > i) 1558 possible = i; 1559 #endif 1560 } else 1561 possible = setup_possible_cpus; 1562 1563 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1564 1565 /* nr_cpu_ids could be reduced via nr_cpus= */ 1566 if (possible > nr_cpu_ids) { 1567 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1568 possible, nr_cpu_ids); 1569 possible = nr_cpu_ids; 1570 } 1571 1572 #ifdef CONFIG_HOTPLUG_CPU 1573 if (!setup_max_cpus) 1574 #endif 1575 if (possible > i) { 1576 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1577 possible, setup_max_cpus); 1578 possible = i; 1579 } 1580 1581 set_nr_cpu_ids(possible); 1582 1583 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1584 possible, max_t(int, possible - num_processors, 0)); 1585 1586 reset_cpu_possible_mask(); 1587 1588 for (i = 0; i < possible; i++) 1589 set_cpu_possible(i, true); 1590 } 1591 1592 #ifdef CONFIG_HOTPLUG_CPU 1593 1594 /* Recompute SMT state for all CPUs on offline */ 1595 static void recompute_smt_state(void) 1596 { 1597 int max_threads, cpu; 1598 1599 max_threads = 0; 1600 for_each_online_cpu (cpu) { 1601 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1602 1603 if (threads > max_threads) 1604 max_threads = threads; 1605 } 1606 __max_smt_threads = max_threads; 1607 } 1608 1609 static void remove_siblinginfo(int cpu) 1610 { 1611 int sibling; 1612 struct cpuinfo_x86 *c = &cpu_data(cpu); 1613 1614 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1615 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1616 /*/ 1617 * last thread sibling in this cpu core going down 1618 */ 1619 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1620 cpu_data(sibling).booted_cores--; 1621 } 1622 1623 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1624 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1625 1626 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1627 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1628 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1629 cpu_data(sibling).smt_active = false; 1630 } 1631 1632 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1633 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1634 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1635 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1636 cpumask_clear(cpu_llc_shared_mask(cpu)); 1637 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1638 cpumask_clear(topology_sibling_cpumask(cpu)); 1639 cpumask_clear(topology_core_cpumask(cpu)); 1640 cpumask_clear(topology_die_cpumask(cpu)); 1641 c->cpu_core_id = 0; 1642 c->booted_cores = 0; 1643 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1644 recompute_smt_state(); 1645 } 1646 1647 static void remove_cpu_from_maps(int cpu) 1648 { 1649 set_cpu_online(cpu, false); 1650 cpumask_clear_cpu(cpu, cpu_callout_mask); 1651 cpumask_clear_cpu(cpu, cpu_callin_mask); 1652 /* was set by cpu_init() */ 1653 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1654 numa_remove_cpu(cpu); 1655 } 1656 1657 void cpu_disable_common(void) 1658 { 1659 int cpu = smp_processor_id(); 1660 1661 remove_siblinginfo(cpu); 1662 1663 /* It's now safe to remove this processor from the online map */ 1664 lock_vector_lock(); 1665 remove_cpu_from_maps(cpu); 1666 unlock_vector_lock(); 1667 fixup_irqs(); 1668 lapic_offline(); 1669 } 1670 1671 int native_cpu_disable(void) 1672 { 1673 int ret; 1674 1675 ret = lapic_can_unplug_cpu(); 1676 if (ret) 1677 return ret; 1678 1679 cpu_disable_common(); 1680 1681 /* 1682 * Disable the local APIC. Otherwise IPI broadcasts will reach 1683 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1684 * messages. 1685 * 1686 * Disabling the APIC must happen after cpu_disable_common() 1687 * which invokes fixup_irqs(). 1688 * 1689 * Disabling the APIC preserves already set bits in IRR, but 1690 * an interrupt arriving after disabling the local APIC does not 1691 * set the corresponding IRR bit. 1692 * 1693 * fixup_irqs() scans IRR for set bits so it can raise a not 1694 * yet handled interrupt on the new destination CPU via an IPI 1695 * but obviously it can't do so for IRR bits which are not set. 1696 * IOW, interrupts arriving after disabling the local APIC will 1697 * be lost. 1698 */ 1699 apic_soft_disable(); 1700 1701 return 0; 1702 } 1703 1704 int common_cpu_die(unsigned int cpu) 1705 { 1706 int ret = 0; 1707 1708 /* We don't do anything here: idle task is faking death itself. */ 1709 1710 /* They ack this in play_dead() by setting CPU_DEAD */ 1711 if (cpu_wait_death(cpu, 5)) { 1712 if (system_state == SYSTEM_RUNNING) 1713 pr_info("CPU %u is now offline\n", cpu); 1714 } else { 1715 pr_err("CPU %u didn't die...\n", cpu); 1716 ret = -1; 1717 } 1718 1719 return ret; 1720 } 1721 1722 void native_cpu_die(unsigned int cpu) 1723 { 1724 common_cpu_die(cpu); 1725 } 1726 1727 void play_dead_common(void) 1728 { 1729 idle_task_exit(); 1730 1731 /* Ack it */ 1732 (void)cpu_report_death(); 1733 1734 /* 1735 * With physical CPU hotplug, we should halt the cpu 1736 */ 1737 local_irq_disable(); 1738 } 1739 1740 /** 1741 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1742 * 1743 * If NMI wants to wake up CPU0, start CPU0. 1744 */ 1745 void cond_wakeup_cpu0(void) 1746 { 1747 if (smp_processor_id() == 0 && enable_start_cpu0) 1748 start_cpu0(); 1749 } 1750 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1751 1752 /* 1753 * We need to flush the caches before going to sleep, lest we have 1754 * dirty data in our caches when we come back up. 1755 */ 1756 static inline void mwait_play_dead(void) 1757 { 1758 unsigned int eax, ebx, ecx, edx; 1759 unsigned int highest_cstate = 0; 1760 unsigned int highest_subcstate = 0; 1761 void *mwait_ptr; 1762 int i; 1763 1764 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1765 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1766 return; 1767 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1768 return; 1769 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1770 return; 1771 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1772 return; 1773 1774 eax = CPUID_MWAIT_LEAF; 1775 ecx = 0; 1776 native_cpuid(&eax, &ebx, &ecx, &edx); 1777 1778 /* 1779 * eax will be 0 if EDX enumeration is not valid. 1780 * Initialized below to cstate, sub_cstate value when EDX is valid. 1781 */ 1782 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1783 eax = 0; 1784 } else { 1785 edx >>= MWAIT_SUBSTATE_SIZE; 1786 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1787 if (edx & MWAIT_SUBSTATE_MASK) { 1788 highest_cstate = i; 1789 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1790 } 1791 } 1792 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1793 (highest_subcstate - 1); 1794 } 1795 1796 /* 1797 * This should be a memory location in a cache line which is 1798 * unlikely to be touched by other processors. The actual 1799 * content is immaterial as it is not actually modified in any way. 1800 */ 1801 mwait_ptr = ¤t_thread_info()->flags; 1802 1803 wbinvd(); 1804 1805 while (1) { 1806 /* 1807 * The CLFLUSH is a workaround for erratum AAI65 for 1808 * the Xeon 7400 series. It's not clear it is actually 1809 * needed, but it should be harmless in either case. 1810 * The WBINVD is insufficient due to the spurious-wakeup 1811 * case where we return around the loop. 1812 */ 1813 mb(); 1814 clflush(mwait_ptr); 1815 mb(); 1816 __monitor(mwait_ptr, 0, 0); 1817 mb(); 1818 __mwait(eax, 0); 1819 1820 cond_wakeup_cpu0(); 1821 } 1822 } 1823 1824 void hlt_play_dead(void) 1825 { 1826 if (__this_cpu_read(cpu_info.x86) >= 4) 1827 wbinvd(); 1828 1829 while (1) { 1830 native_halt(); 1831 1832 cond_wakeup_cpu0(); 1833 } 1834 } 1835 1836 void native_play_dead(void) 1837 { 1838 play_dead_common(); 1839 tboot_shutdown(TB_SHUTDOWN_WFS); 1840 1841 mwait_play_dead(); 1842 if (cpuidle_play_dead()) 1843 hlt_play_dead(); 1844 } 1845 1846 #else /* ... !CONFIG_HOTPLUG_CPU */ 1847 int native_cpu_disable(void) 1848 { 1849 return -ENOSYS; 1850 } 1851 1852 void native_cpu_die(unsigned int cpu) 1853 { 1854 /* We said "no" in __cpu_disable */ 1855 BUG(); 1856 } 1857 1858 void native_play_dead(void) 1859 { 1860 BUG(); 1861 } 1862 1863 #endif 1864