1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/fpu/internal.h> 72 #include <asm/setup.h> 73 #include <asm/uv/uv.h> 74 #include <linux/mc146818rtc.h> 75 #include <asm/i8259.h> 76 #include <asm/realmode.h> 77 #include <asm/misc.h> 78 79 /* Number of siblings per CPU package */ 80 int smp_num_siblings = 1; 81 EXPORT_SYMBOL(smp_num_siblings); 82 83 /* Last level cache ID of each logical CPU */ 84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 /* Logical package management. We might want to allocate that dynamically */ 101 static int *physical_to_logical_pkg __read_mostly; 102 static unsigned long *physical_package_map __read_mostly;; 103 static unsigned long *logical_package_map __read_mostly; 104 static unsigned int max_physical_pkg_id __read_mostly; 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 108 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 109 { 110 unsigned long flags; 111 112 spin_lock_irqsave(&rtc_lock, flags); 113 CMOS_WRITE(0xa, 0xf); 114 spin_unlock_irqrestore(&rtc_lock, flags); 115 local_flush_tlb(); 116 pr_debug("1.\n"); 117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 118 start_eip >> 4; 119 pr_debug("2.\n"); 120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 121 start_eip & 0xf; 122 pr_debug("3.\n"); 123 } 124 125 static inline void smpboot_restore_warm_reset_vector(void) 126 { 127 unsigned long flags; 128 129 /* 130 * Install writable page 0 entry to set BIOS data area. 131 */ 132 local_flush_tlb(); 133 134 /* 135 * Paranoid: Set warm reset code and vector here back 136 * to default values. 137 */ 138 spin_lock_irqsave(&rtc_lock, flags); 139 CMOS_WRITE(0, 0xf); 140 spin_unlock_irqrestore(&rtc_lock, flags); 141 142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 143 } 144 145 /* 146 * Report back to the Boot Processor during boot time or to the caller processor 147 * during CPU online. 148 */ 149 static void smp_callin(void) 150 { 151 int cpuid, phys_id; 152 153 /* 154 * If waken up by an INIT in an 82489DX configuration 155 * cpu_callout_mask guarantees we don't get here before 156 * an INIT_deassert IPI reaches our local APIC, so it is 157 * now safe to touch our local APIC. 158 */ 159 cpuid = smp_processor_id(); 160 161 /* 162 * (This works even if the APIC is not enabled.) 163 */ 164 phys_id = read_apic_id(); 165 166 /* 167 * the boot CPU has finished the init stage and is spinning 168 * on callin_map until we finish. We are free to set up this 169 * CPU, first the APIC. (this is probably redundant on most 170 * boards) 171 */ 172 apic_ap_setup(); 173 174 /* 175 * Save our processor parameters. Note: this information 176 * is needed for clock calibration. 177 */ 178 smp_store_cpu_info(cpuid); 179 180 /* 181 * Get our bogomips. 182 * Update loops_per_jiffy in cpu_data. Previous call to 183 * smp_store_cpu_info() stored a value that is close but not as 184 * accurate as the value just calculated. 185 */ 186 calibrate_delay(); 187 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 188 pr_debug("Stack at about %p\n", &cpuid); 189 190 /* 191 * This must be done before setting cpu_online_mask 192 * or calling notify_cpu_starting. 193 */ 194 set_cpu_sibling_map(raw_smp_processor_id()); 195 wmb(); 196 197 notify_cpu_starting(cpuid); 198 199 /* 200 * Allow the master to continue. 201 */ 202 cpumask_set_cpu(cpuid, cpu_callin_mask); 203 } 204 205 static int cpu0_logical_apicid; 206 static int enable_start_cpu0; 207 /* 208 * Activate a secondary processor. 209 */ 210 static void notrace start_secondary(void *unused) 211 { 212 /* 213 * Don't put *anything* before cpu_init(), SMP booting is too 214 * fragile that we want to limit the things done here to the 215 * most necessary things. 216 */ 217 cpu_init(); 218 x86_cpuinit.early_percpu_clock_init(); 219 preempt_disable(); 220 smp_callin(); 221 222 enable_start_cpu0 = 0; 223 224 #ifdef CONFIG_X86_32 225 /* switch away from the initial page table */ 226 load_cr3(swapper_pg_dir); 227 __flush_tlb_all(); 228 #endif 229 230 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 231 barrier(); 232 /* 233 * Check TSC synchronization with the BP: 234 */ 235 check_tsc_sync_target(); 236 237 /* 238 * Lock vector_lock and initialize the vectors on this cpu 239 * before setting the cpu online. We must set it online with 240 * vector_lock held to prevent a concurrent setup/teardown 241 * from seeing a half valid vector space. 242 */ 243 lock_vector_lock(); 244 setup_vector_irq(smp_processor_id()); 245 set_cpu_online(smp_processor_id(), true); 246 unlock_vector_lock(); 247 cpu_set_state_online(smp_processor_id()); 248 x86_platform.nmi_init(); 249 250 /* enable local interrupts */ 251 local_irq_enable(); 252 253 /* to prevent fake stack check failure in clock setup */ 254 boot_init_stack_canary(); 255 256 x86_cpuinit.setup_percpu_clockev(); 257 258 wmb(); 259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 260 } 261 262 int topology_update_package_map(unsigned int apicid, unsigned int cpu) 263 { 264 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; 265 266 /* Called from early boot ? */ 267 if (!physical_package_map) 268 return 0; 269 270 if (pkg >= max_physical_pkg_id) 271 return -EINVAL; 272 273 /* Set the logical package id */ 274 if (test_and_set_bit(pkg, physical_package_map)) 275 goto found; 276 277 new = find_first_zero_bit(logical_package_map, __max_logical_packages); 278 if (new >= __max_logical_packages) { 279 physical_to_logical_pkg[pkg] = -1; 280 pr_warn("APIC(%x) Package %u exceeds logical package map\n", 281 apicid, pkg); 282 return -ENOSPC; 283 } 284 set_bit(new, logical_package_map); 285 pr_info("APIC(%x) Converting physical %u to logical package %u\n", 286 apicid, pkg, new); 287 physical_to_logical_pkg[pkg] = new; 288 289 found: 290 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 291 return 0; 292 } 293 294 /** 295 * topology_phys_to_logical_pkg - Map a physical package id to a logical 296 * 297 * Returns logical package id or -1 if not found 298 */ 299 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 300 { 301 if (phys_pkg >= max_physical_pkg_id) 302 return -1; 303 return physical_to_logical_pkg[phys_pkg]; 304 } 305 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 306 307 static void __init smp_init_package_map(void) 308 { 309 unsigned int ncpus, cpu; 310 size_t size; 311 312 /* 313 * Today neither Intel nor AMD support heterogenous systems. That 314 * might change in the future.... 315 * 316 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 317 * computation, this won't actually work since some Intel BIOSes 318 * report inconsistent HT data when they disable HT. 319 * 320 * In particular, they reduce the APIC-IDs to only include the cores, 321 * but leave the CPUID topology to say there are (2) siblings. 322 * This means we don't know how many threads there will be until 323 * after the APIC enumeration. 324 * 325 * By not including this we'll sometimes over-estimate the number of 326 * logical packages by the amount of !present siblings, but this is 327 * still better than MAX_LOCAL_APIC. 328 * 329 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 330 * on the command line leading to a similar issue as the HT disable 331 * problem because the hyperthreads are usually enumerated after the 332 * primary cores. 333 */ 334 ncpus = boot_cpu_data.x86_max_cores; 335 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 336 337 /* 338 * Possibly larger than what we need as the number of apic ids per 339 * package can be smaller than the actual used apic ids. 340 */ 341 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 342 size = max_physical_pkg_id * sizeof(unsigned int); 343 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 344 memset(physical_to_logical_pkg, 0xff, size); 345 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 346 physical_package_map = kzalloc(size, GFP_KERNEL); 347 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long); 348 logical_package_map = kzalloc(size, GFP_KERNEL); 349 350 pr_info("Max logical packages: %u\n", __max_logical_packages); 351 352 for_each_present_cpu(cpu) { 353 unsigned int apicid = apic->cpu_present_to_apicid(cpu); 354 355 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) 356 continue; 357 if (!topology_update_package_map(apicid, cpu)) 358 continue; 359 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); 360 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; 361 set_cpu_possible(cpu, false); 362 set_cpu_present(cpu, false); 363 } 364 } 365 366 void __init smp_store_boot_cpu_info(void) 367 { 368 int id = 0; /* CPU 0 */ 369 struct cpuinfo_x86 *c = &cpu_data(id); 370 371 *c = boot_cpu_data; 372 c->cpu_index = id; 373 smp_init_package_map(); 374 } 375 376 /* 377 * The bootstrap kernel entry code has set these up. Save them for 378 * a given CPU 379 */ 380 void smp_store_cpu_info(int id) 381 { 382 struct cpuinfo_x86 *c = &cpu_data(id); 383 384 *c = boot_cpu_data; 385 c->cpu_index = id; 386 /* 387 * During boot time, CPU0 has this setup already. Save the info when 388 * bringing up AP or offlined CPU0. 389 */ 390 identify_secondary_cpu(c); 391 } 392 393 static bool 394 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 395 { 396 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 397 398 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 399 } 400 401 static bool 402 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 403 { 404 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 405 406 return !WARN_ONCE(!topology_same_node(c, o), 407 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 408 "[node: %d != %d]. Ignoring dependency.\n", 409 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 410 } 411 412 #define link_mask(mfunc, c1, c2) \ 413 do { \ 414 cpumask_set_cpu((c1), mfunc(c2)); \ 415 cpumask_set_cpu((c2), mfunc(c1)); \ 416 } while (0) 417 418 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 419 { 420 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 422 423 if (c->phys_proc_id == o->phys_proc_id && 424 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 425 c->compute_unit_id == o->compute_unit_id) 426 return topology_sane(c, o, "smt"); 427 428 } else if (c->phys_proc_id == o->phys_proc_id && 429 c->cpu_core_id == o->cpu_core_id) { 430 return topology_sane(c, o, "smt"); 431 } 432 433 return false; 434 } 435 436 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 437 { 438 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 439 440 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 441 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 442 return topology_sane(c, o, "llc"); 443 444 return false; 445 } 446 447 /* 448 * Unlike the other levels, we do not enforce keeping a 449 * multicore group inside a NUMA node. If this happens, we will 450 * discard the MC level of the topology later. 451 */ 452 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 453 { 454 if (c->phys_proc_id == o->phys_proc_id) 455 return true; 456 return false; 457 } 458 459 static struct sched_domain_topology_level numa_inside_package_topology[] = { 460 #ifdef CONFIG_SCHED_SMT 461 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 462 #endif 463 #ifdef CONFIG_SCHED_MC 464 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 465 #endif 466 { NULL, }, 467 }; 468 /* 469 * set_sched_topology() sets the topology internal to a CPU. The 470 * NUMA topologies are layered on top of it to build the full 471 * system topology. 472 * 473 * If NUMA nodes are observed to occur within a CPU package, this 474 * function should be called. It forces the sched domain code to 475 * only use the SMT level for the CPU portion of the topology. 476 * This essentially falls back to relying on NUMA information 477 * from the SRAT table to describe the entire system topology 478 * (except for hyperthreads). 479 */ 480 static void primarily_use_numa_for_topology(void) 481 { 482 set_sched_topology(numa_inside_package_topology); 483 } 484 485 void set_cpu_sibling_map(int cpu) 486 { 487 bool has_smt = smp_num_siblings > 1; 488 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 489 struct cpuinfo_x86 *c = &cpu_data(cpu); 490 struct cpuinfo_x86 *o; 491 int i; 492 493 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 494 495 if (!has_mp) { 496 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 497 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 498 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 499 c->booted_cores = 1; 500 return; 501 } 502 503 for_each_cpu(i, cpu_sibling_setup_mask) { 504 o = &cpu_data(i); 505 506 if ((i == cpu) || (has_smt && match_smt(c, o))) 507 link_mask(topology_sibling_cpumask, cpu, i); 508 509 if ((i == cpu) || (has_mp && match_llc(c, o))) 510 link_mask(cpu_llc_shared_mask, cpu, i); 511 512 } 513 514 /* 515 * This needs a separate iteration over the cpus because we rely on all 516 * topology_sibling_cpumask links to be set-up. 517 */ 518 for_each_cpu(i, cpu_sibling_setup_mask) { 519 o = &cpu_data(i); 520 521 if ((i == cpu) || (has_mp && match_die(c, o))) { 522 link_mask(topology_core_cpumask, cpu, i); 523 524 /* 525 * Does this new cpu bringup a new core? 526 */ 527 if (cpumask_weight( 528 topology_sibling_cpumask(cpu)) == 1) { 529 /* 530 * for each core in package, increment 531 * the booted_cores for this new cpu 532 */ 533 if (cpumask_first( 534 topology_sibling_cpumask(i)) == i) 535 c->booted_cores++; 536 /* 537 * increment the core count for all 538 * the other cpus in this package 539 */ 540 if (i != cpu) 541 cpu_data(i).booted_cores++; 542 } else if (i != cpu && !c->booted_cores) 543 c->booted_cores = cpu_data(i).booted_cores; 544 } 545 if (match_die(c, o) && !topology_same_node(c, o)) 546 primarily_use_numa_for_topology(); 547 } 548 } 549 550 /* maps the cpu to the sched domain representing multi-core */ 551 const struct cpumask *cpu_coregroup_mask(int cpu) 552 { 553 return cpu_llc_shared_mask(cpu); 554 } 555 556 static void impress_friends(void) 557 { 558 int cpu; 559 unsigned long bogosum = 0; 560 /* 561 * Allow the user to impress friends. 562 */ 563 pr_debug("Before bogomips\n"); 564 for_each_possible_cpu(cpu) 565 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 566 bogosum += cpu_data(cpu).loops_per_jiffy; 567 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 568 num_online_cpus(), 569 bogosum/(500000/HZ), 570 (bogosum/(5000/HZ))%100); 571 572 pr_debug("Before bogocount - setting activated=1\n"); 573 } 574 575 void __inquire_remote_apic(int apicid) 576 { 577 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 578 const char * const names[] = { "ID", "VERSION", "SPIV" }; 579 int timeout; 580 u32 status; 581 582 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 583 584 for (i = 0; i < ARRAY_SIZE(regs); i++) { 585 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 586 587 /* 588 * Wait for idle. 589 */ 590 status = safe_apic_wait_icr_idle(); 591 if (status) 592 pr_cont("a previous APIC delivery may have failed\n"); 593 594 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 595 596 timeout = 0; 597 do { 598 udelay(100); 599 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 600 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 601 602 switch (status) { 603 case APIC_ICR_RR_VALID: 604 status = apic_read(APIC_RRR); 605 pr_cont("%08x\n", status); 606 break; 607 default: 608 pr_cont("failed\n"); 609 } 610 } 611 } 612 613 /* 614 * The Multiprocessor Specification 1.4 (1997) example code suggests 615 * that there should be a 10ms delay between the BSP asserting INIT 616 * and de-asserting INIT, when starting a remote processor. 617 * But that slows boot and resume on modern processors, which include 618 * many cores and don't require that delay. 619 * 620 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 621 * Modern processor families are quirked to remove the delay entirely. 622 */ 623 #define UDELAY_10MS_DEFAULT 10000 624 625 static unsigned int init_udelay = UINT_MAX; 626 627 static int __init cpu_init_udelay(char *str) 628 { 629 get_option(&str, &init_udelay); 630 631 return 0; 632 } 633 early_param("cpu_init_udelay", cpu_init_udelay); 634 635 static void __init smp_quirk_init_udelay(void) 636 { 637 /* if cmdline changed it from default, leave it alone */ 638 if (init_udelay != UINT_MAX) 639 return; 640 641 /* if modern processor, use no delay */ 642 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 643 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 644 init_udelay = 0; 645 return; 646 } 647 /* else, use legacy delay */ 648 init_udelay = UDELAY_10MS_DEFAULT; 649 } 650 651 /* 652 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 653 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 654 * won't ... remember to clear down the APIC, etc later. 655 */ 656 int 657 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 658 { 659 unsigned long send_status, accept_status = 0; 660 int maxlvt; 661 662 /* Target chip */ 663 /* Boot on the stack */ 664 /* Kick the second */ 665 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 666 667 pr_debug("Waiting for send to finish...\n"); 668 send_status = safe_apic_wait_icr_idle(); 669 670 /* 671 * Give the other CPU some time to accept the IPI. 672 */ 673 udelay(200); 674 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 675 maxlvt = lapic_get_maxlvt(); 676 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 677 apic_write(APIC_ESR, 0); 678 accept_status = (apic_read(APIC_ESR) & 0xEF); 679 } 680 pr_debug("NMI sent\n"); 681 682 if (send_status) 683 pr_err("APIC never delivered???\n"); 684 if (accept_status) 685 pr_err("APIC delivery error (%lx)\n", accept_status); 686 687 return (send_status | accept_status); 688 } 689 690 static int 691 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 692 { 693 unsigned long send_status = 0, accept_status = 0; 694 int maxlvt, num_starts, j; 695 696 maxlvt = lapic_get_maxlvt(); 697 698 /* 699 * Be paranoid about clearing APIC errors. 700 */ 701 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 702 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 703 apic_write(APIC_ESR, 0); 704 apic_read(APIC_ESR); 705 } 706 707 pr_debug("Asserting INIT\n"); 708 709 /* 710 * Turn INIT on target chip 711 */ 712 /* 713 * Send IPI 714 */ 715 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 716 phys_apicid); 717 718 pr_debug("Waiting for send to finish...\n"); 719 send_status = safe_apic_wait_icr_idle(); 720 721 udelay(init_udelay); 722 723 pr_debug("Deasserting INIT\n"); 724 725 /* Target chip */ 726 /* Send IPI */ 727 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 728 729 pr_debug("Waiting for send to finish...\n"); 730 send_status = safe_apic_wait_icr_idle(); 731 732 mb(); 733 734 /* 735 * Should we send STARTUP IPIs ? 736 * 737 * Determine this based on the APIC version. 738 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 739 */ 740 if (APIC_INTEGRATED(apic_version[phys_apicid])) 741 num_starts = 2; 742 else 743 num_starts = 0; 744 745 /* 746 * Run STARTUP IPI loop. 747 */ 748 pr_debug("#startup loops: %d\n", num_starts); 749 750 for (j = 1; j <= num_starts; j++) { 751 pr_debug("Sending STARTUP #%d\n", j); 752 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 753 apic_write(APIC_ESR, 0); 754 apic_read(APIC_ESR); 755 pr_debug("After apic_write\n"); 756 757 /* 758 * STARTUP IPI 759 */ 760 761 /* Target chip */ 762 /* Boot on the stack */ 763 /* Kick the second */ 764 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 765 phys_apicid); 766 767 /* 768 * Give the other CPU some time to accept the IPI. 769 */ 770 if (init_udelay == 0) 771 udelay(10); 772 else 773 udelay(300); 774 775 pr_debug("Startup point 1\n"); 776 777 pr_debug("Waiting for send to finish...\n"); 778 send_status = safe_apic_wait_icr_idle(); 779 780 /* 781 * Give the other CPU some time to accept the IPI. 782 */ 783 if (init_udelay == 0) 784 udelay(10); 785 else 786 udelay(200); 787 788 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 789 apic_write(APIC_ESR, 0); 790 accept_status = (apic_read(APIC_ESR) & 0xEF); 791 if (send_status || accept_status) 792 break; 793 } 794 pr_debug("After Startup\n"); 795 796 if (send_status) 797 pr_err("APIC never delivered???\n"); 798 if (accept_status) 799 pr_err("APIC delivery error (%lx)\n", accept_status); 800 801 return (send_status | accept_status); 802 } 803 804 void smp_announce(void) 805 { 806 int num_nodes = num_online_nodes(); 807 808 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 809 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 810 } 811 812 /* reduce the number of lines printed when booting a large cpu count system */ 813 static void announce_cpu(int cpu, int apicid) 814 { 815 static int current_node = -1; 816 int node = early_cpu_to_node(cpu); 817 static int width, node_width; 818 819 if (!width) 820 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 821 822 if (!node_width) 823 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 824 825 if (cpu == 1) 826 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 827 828 if (system_state == SYSTEM_BOOTING) { 829 if (node != current_node) { 830 if (current_node > (-1)) 831 pr_cont("\n"); 832 current_node = node; 833 834 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 835 node_width - num_digits(node), " ", node); 836 } 837 838 /* Add padding for the BSP */ 839 if (cpu == 1) 840 pr_cont("%*s", width + 1, " "); 841 842 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 843 844 } else 845 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 846 node, cpu, apicid); 847 } 848 849 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 850 { 851 int cpu; 852 853 cpu = smp_processor_id(); 854 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 855 return NMI_HANDLED; 856 857 return NMI_DONE; 858 } 859 860 /* 861 * Wake up AP by INIT, INIT, STARTUP sequence. 862 * 863 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 864 * boot-strap code which is not a desired behavior for waking up BSP. To 865 * void the boot-strap code, wake up CPU0 by NMI instead. 866 * 867 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 868 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 869 * We'll change this code in the future to wake up hard offlined CPU0 if 870 * real platform and request are available. 871 */ 872 static int 873 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 874 int *cpu0_nmi_registered) 875 { 876 int id; 877 int boot_error; 878 879 preempt_disable(); 880 881 /* 882 * Wake up AP by INIT, INIT, STARTUP sequence. 883 */ 884 if (cpu) { 885 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 886 goto out; 887 } 888 889 /* 890 * Wake up BSP by nmi. 891 * 892 * Register a NMI handler to help wake up CPU0. 893 */ 894 boot_error = register_nmi_handler(NMI_LOCAL, 895 wakeup_cpu0_nmi, 0, "wake_cpu0"); 896 897 if (!boot_error) { 898 enable_start_cpu0 = 1; 899 *cpu0_nmi_registered = 1; 900 if (apic->dest_logical == APIC_DEST_LOGICAL) 901 id = cpu0_logical_apicid; 902 else 903 id = apicid; 904 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 905 } 906 907 out: 908 preempt_enable(); 909 910 return boot_error; 911 } 912 913 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 914 { 915 /* Just in case we booted with a single CPU. */ 916 alternatives_enable_smp(); 917 918 per_cpu(current_task, cpu) = idle; 919 920 #ifdef CONFIG_X86_32 921 /* Stack for startup_32 can be just as for start_secondary onwards */ 922 irq_ctx_init(cpu); 923 per_cpu(cpu_current_top_of_stack, cpu) = 924 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 925 #else 926 clear_tsk_thread_flag(idle, TIF_FORK); 927 initial_gs = per_cpu_offset(cpu); 928 #endif 929 } 930 931 /* 932 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 933 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 934 * Returns zero if CPU booted OK, else error code from 935 * ->wakeup_secondary_cpu. 936 */ 937 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 938 { 939 volatile u32 *trampoline_status = 940 (volatile u32 *) __va(real_mode_header->trampoline_status); 941 /* start_ip had better be page-aligned! */ 942 unsigned long start_ip = real_mode_header->trampoline_start; 943 944 unsigned long boot_error = 0; 945 int cpu0_nmi_registered = 0; 946 unsigned long timeout; 947 948 idle->thread.sp = (unsigned long) (((struct pt_regs *) 949 (THREAD_SIZE + task_stack_page(idle))) - 1); 950 951 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 952 initial_code = (unsigned long)start_secondary; 953 stack_start = idle->thread.sp; 954 955 /* 956 * Enable the espfix hack for this CPU 957 */ 958 #ifdef CONFIG_X86_ESPFIX64 959 init_espfix_ap(cpu); 960 #endif 961 962 /* So we see what's up */ 963 announce_cpu(cpu, apicid); 964 965 /* 966 * This grunge runs the startup process for 967 * the targeted processor. 968 */ 969 970 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 971 972 pr_debug("Setting warm reset code and vector.\n"); 973 974 smpboot_setup_warm_reset_vector(start_ip); 975 /* 976 * Be paranoid about clearing APIC errors. 977 */ 978 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 979 apic_write(APIC_ESR, 0); 980 apic_read(APIC_ESR); 981 } 982 } 983 984 /* 985 * AP might wait on cpu_callout_mask in cpu_init() with 986 * cpu_initialized_mask set if previous attempt to online 987 * it timed-out. Clear cpu_initialized_mask so that after 988 * INIT/SIPI it could start with a clean state. 989 */ 990 cpumask_clear_cpu(cpu, cpu_initialized_mask); 991 smp_mb(); 992 993 /* 994 * Wake up a CPU in difference cases: 995 * - Use the method in the APIC driver if it's defined 996 * Otherwise, 997 * - Use an INIT boot APIC message for APs or NMI for BSP. 998 */ 999 if (apic->wakeup_secondary_cpu) 1000 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1001 else 1002 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1003 &cpu0_nmi_registered); 1004 1005 if (!boot_error) { 1006 /* 1007 * Wait 10s total for first sign of life from AP 1008 */ 1009 boot_error = -1; 1010 timeout = jiffies + 10*HZ; 1011 while (time_before(jiffies, timeout)) { 1012 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1013 /* 1014 * Tell AP to proceed with initialization 1015 */ 1016 cpumask_set_cpu(cpu, cpu_callout_mask); 1017 boot_error = 0; 1018 break; 1019 } 1020 schedule(); 1021 } 1022 } 1023 1024 if (!boot_error) { 1025 /* 1026 * Wait till AP completes initial initialization 1027 */ 1028 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1029 /* 1030 * Allow other tasks to run while we wait for the 1031 * AP to come online. This also gives a chance 1032 * for the MTRR work(triggered by the AP coming online) 1033 * to be completed in the stop machine context. 1034 */ 1035 schedule(); 1036 } 1037 } 1038 1039 /* mark "stuck" area as not stuck */ 1040 *trampoline_status = 0; 1041 1042 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1043 /* 1044 * Cleanup possible dangling ends... 1045 */ 1046 smpboot_restore_warm_reset_vector(); 1047 } 1048 /* 1049 * Clean up the nmi handler. Do this after the callin and callout sync 1050 * to avoid impact of possible long unregister time. 1051 */ 1052 if (cpu0_nmi_registered) 1053 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1054 1055 return boot_error; 1056 } 1057 1058 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1059 { 1060 int apicid = apic->cpu_present_to_apicid(cpu); 1061 unsigned long flags; 1062 int err; 1063 1064 WARN_ON(irqs_disabled()); 1065 1066 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1067 1068 if (apicid == BAD_APICID || 1069 !physid_isset(apicid, phys_cpu_present_map) || 1070 !apic->apic_id_valid(apicid)) { 1071 pr_err("%s: bad cpu %d\n", __func__, cpu); 1072 return -EINVAL; 1073 } 1074 1075 /* 1076 * Already booted CPU? 1077 */ 1078 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1079 pr_debug("do_boot_cpu %d Already started\n", cpu); 1080 return -ENOSYS; 1081 } 1082 1083 /* 1084 * Save current MTRR state in case it was changed since early boot 1085 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1086 */ 1087 mtrr_save_state(); 1088 1089 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1090 err = cpu_check_up_prepare(cpu); 1091 if (err && err != -EBUSY) 1092 return err; 1093 1094 /* the FPU context is blank, nobody can own it */ 1095 __cpu_disable_lazy_restore(cpu); 1096 1097 common_cpu_up(cpu, tidle); 1098 1099 /* 1100 * We have to walk the irq descriptors to setup the vector 1101 * space for the cpu which comes online. Prevent irq 1102 * alloc/free across the bringup. 1103 */ 1104 irq_lock_sparse(); 1105 1106 err = do_boot_cpu(apicid, cpu, tidle); 1107 1108 if (err) { 1109 irq_unlock_sparse(); 1110 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1111 return -EIO; 1112 } 1113 1114 /* 1115 * Check TSC synchronization with the AP (keep irqs disabled 1116 * while doing so): 1117 */ 1118 local_irq_save(flags); 1119 check_tsc_sync_source(cpu); 1120 local_irq_restore(flags); 1121 1122 while (!cpu_online(cpu)) { 1123 cpu_relax(); 1124 touch_nmi_watchdog(); 1125 } 1126 1127 irq_unlock_sparse(); 1128 1129 return 0; 1130 } 1131 1132 /** 1133 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1134 */ 1135 void arch_disable_smp_support(void) 1136 { 1137 disable_ioapic_support(); 1138 } 1139 1140 /* 1141 * Fall back to non SMP mode after errors. 1142 * 1143 * RED-PEN audit/test this more. I bet there is more state messed up here. 1144 */ 1145 static __init void disable_smp(void) 1146 { 1147 pr_info("SMP disabled\n"); 1148 1149 disable_ioapic_support(); 1150 1151 init_cpu_present(cpumask_of(0)); 1152 init_cpu_possible(cpumask_of(0)); 1153 1154 if (smp_found_config) 1155 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1156 else 1157 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1158 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1159 cpumask_set_cpu(0, topology_core_cpumask(0)); 1160 } 1161 1162 enum { 1163 SMP_OK, 1164 SMP_NO_CONFIG, 1165 SMP_NO_APIC, 1166 SMP_FORCE_UP, 1167 }; 1168 1169 /* 1170 * Various sanity checks. 1171 */ 1172 static int __init smp_sanity_check(unsigned max_cpus) 1173 { 1174 preempt_disable(); 1175 1176 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1177 if (def_to_bigsmp && nr_cpu_ids > 8) { 1178 unsigned int cpu; 1179 unsigned nr; 1180 1181 pr_warn("More than 8 CPUs detected - skipping them\n" 1182 "Use CONFIG_X86_BIGSMP\n"); 1183 1184 nr = 0; 1185 for_each_present_cpu(cpu) { 1186 if (nr >= 8) 1187 set_cpu_present(cpu, false); 1188 nr++; 1189 } 1190 1191 nr = 0; 1192 for_each_possible_cpu(cpu) { 1193 if (nr >= 8) 1194 set_cpu_possible(cpu, false); 1195 nr++; 1196 } 1197 1198 nr_cpu_ids = 8; 1199 } 1200 #endif 1201 1202 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1203 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1204 hard_smp_processor_id()); 1205 1206 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1207 } 1208 1209 /* 1210 * If we couldn't find an SMP configuration at boot time, 1211 * get out of here now! 1212 */ 1213 if (!smp_found_config && !acpi_lapic) { 1214 preempt_enable(); 1215 pr_notice("SMP motherboard not detected\n"); 1216 return SMP_NO_CONFIG; 1217 } 1218 1219 /* 1220 * Should not be necessary because the MP table should list the boot 1221 * CPU too, but we do it for the sake of robustness anyway. 1222 */ 1223 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1224 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1225 boot_cpu_physical_apicid); 1226 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1227 } 1228 preempt_enable(); 1229 1230 /* 1231 * If we couldn't find a local APIC, then get out of here now! 1232 */ 1233 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1234 !cpu_has_apic) { 1235 if (!disable_apic) { 1236 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1237 boot_cpu_physical_apicid); 1238 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1239 } 1240 return SMP_NO_APIC; 1241 } 1242 1243 /* 1244 * If SMP should be disabled, then really disable it! 1245 */ 1246 if (!max_cpus) { 1247 pr_info("SMP mode deactivated\n"); 1248 return SMP_FORCE_UP; 1249 } 1250 1251 return SMP_OK; 1252 } 1253 1254 static void __init smp_cpu_index_default(void) 1255 { 1256 int i; 1257 struct cpuinfo_x86 *c; 1258 1259 for_each_possible_cpu(i) { 1260 c = &cpu_data(i); 1261 /* mark all to hotplug */ 1262 c->cpu_index = nr_cpu_ids; 1263 } 1264 } 1265 1266 /* 1267 * Prepare for SMP bootup. The MP table or ACPI has been read 1268 * earlier. Just do some sanity checking here and enable APIC mode. 1269 */ 1270 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1271 { 1272 unsigned int i; 1273 1274 smp_cpu_index_default(); 1275 1276 /* 1277 * Setup boot CPU information 1278 */ 1279 smp_store_boot_cpu_info(); /* Final full version of the data */ 1280 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1281 mb(); 1282 1283 current_thread_info()->cpu = 0; /* needed? */ 1284 for_each_possible_cpu(i) { 1285 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1286 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1287 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1288 } 1289 set_cpu_sibling_map(0); 1290 1291 switch (smp_sanity_check(max_cpus)) { 1292 case SMP_NO_CONFIG: 1293 disable_smp(); 1294 if (APIC_init_uniprocessor()) 1295 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1296 return; 1297 case SMP_NO_APIC: 1298 disable_smp(); 1299 return; 1300 case SMP_FORCE_UP: 1301 disable_smp(); 1302 apic_bsp_setup(false); 1303 return; 1304 case SMP_OK: 1305 break; 1306 } 1307 1308 default_setup_apic_routing(); 1309 1310 if (read_apic_id() != boot_cpu_physical_apicid) { 1311 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1312 read_apic_id(), boot_cpu_physical_apicid); 1313 /* Or can we switch back to PIC here? */ 1314 } 1315 1316 cpu0_logical_apicid = apic_bsp_setup(false); 1317 1318 pr_info("CPU%d: ", 0); 1319 print_cpu_info(&cpu_data(0)); 1320 1321 if (is_uv_system()) 1322 uv_system_init(); 1323 1324 set_mtrr_aps_delayed_init(); 1325 1326 smp_quirk_init_udelay(); 1327 } 1328 1329 void arch_enable_nonboot_cpus_begin(void) 1330 { 1331 set_mtrr_aps_delayed_init(); 1332 } 1333 1334 void arch_enable_nonboot_cpus_end(void) 1335 { 1336 mtrr_aps_init(); 1337 } 1338 1339 /* 1340 * Early setup to make printk work. 1341 */ 1342 void __init native_smp_prepare_boot_cpu(void) 1343 { 1344 int me = smp_processor_id(); 1345 switch_to_new_gdt(me); 1346 /* already set me in cpu_online_mask in boot_cpu_init() */ 1347 cpumask_set_cpu(me, cpu_callout_mask); 1348 cpu_set_state_online(me); 1349 } 1350 1351 void __init native_smp_cpus_done(unsigned int max_cpus) 1352 { 1353 pr_debug("Boot done\n"); 1354 1355 nmi_selftest(); 1356 impress_friends(); 1357 setup_ioapic_dest(); 1358 mtrr_aps_init(); 1359 } 1360 1361 static int __initdata setup_possible_cpus = -1; 1362 static int __init _setup_possible_cpus(char *str) 1363 { 1364 get_option(&str, &setup_possible_cpus); 1365 return 0; 1366 } 1367 early_param("possible_cpus", _setup_possible_cpus); 1368 1369 1370 /* 1371 * cpu_possible_mask should be static, it cannot change as cpu's 1372 * are onlined, or offlined. The reason is per-cpu data-structures 1373 * are allocated by some modules at init time, and dont expect to 1374 * do this dynamically on cpu arrival/departure. 1375 * cpu_present_mask on the other hand can change dynamically. 1376 * In case when cpu_hotplug is not compiled, then we resort to current 1377 * behaviour, which is cpu_possible == cpu_present. 1378 * - Ashok Raj 1379 * 1380 * Three ways to find out the number of additional hotplug CPUs: 1381 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1382 * - The user can overwrite it with possible_cpus=NUM 1383 * - Otherwise don't reserve additional CPUs. 1384 * We do this because additional CPUs waste a lot of memory. 1385 * -AK 1386 */ 1387 __init void prefill_possible_map(void) 1388 { 1389 int i, possible; 1390 1391 /* no processor from mptable or madt */ 1392 if (!num_processors) 1393 num_processors = 1; 1394 1395 i = setup_max_cpus ?: 1; 1396 if (setup_possible_cpus == -1) { 1397 possible = num_processors; 1398 #ifdef CONFIG_HOTPLUG_CPU 1399 if (setup_max_cpus) 1400 possible += disabled_cpus; 1401 #else 1402 if (possible > i) 1403 possible = i; 1404 #endif 1405 } else 1406 possible = setup_possible_cpus; 1407 1408 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1409 1410 /* nr_cpu_ids could be reduced via nr_cpus= */ 1411 if (possible > nr_cpu_ids) { 1412 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1413 possible, nr_cpu_ids); 1414 possible = nr_cpu_ids; 1415 } 1416 1417 #ifdef CONFIG_HOTPLUG_CPU 1418 if (!setup_max_cpus) 1419 #endif 1420 if (possible > i) { 1421 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1422 possible, setup_max_cpus); 1423 possible = i; 1424 } 1425 1426 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1427 possible, max_t(int, possible - num_processors, 0)); 1428 1429 for (i = 0; i < possible; i++) 1430 set_cpu_possible(i, true); 1431 for (; i < NR_CPUS; i++) 1432 set_cpu_possible(i, false); 1433 1434 nr_cpu_ids = possible; 1435 } 1436 1437 #ifdef CONFIG_HOTPLUG_CPU 1438 1439 static void remove_siblinginfo(int cpu) 1440 { 1441 int sibling; 1442 struct cpuinfo_x86 *c = &cpu_data(cpu); 1443 1444 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1445 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1446 /*/ 1447 * last thread sibling in this cpu core going down 1448 */ 1449 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1450 cpu_data(sibling).booted_cores--; 1451 } 1452 1453 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1454 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1455 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1456 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1457 cpumask_clear(cpu_llc_shared_mask(cpu)); 1458 cpumask_clear(topology_sibling_cpumask(cpu)); 1459 cpumask_clear(topology_core_cpumask(cpu)); 1460 c->phys_proc_id = 0; 1461 c->cpu_core_id = 0; 1462 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1463 } 1464 1465 static void remove_cpu_from_maps(int cpu) 1466 { 1467 set_cpu_online(cpu, false); 1468 cpumask_clear_cpu(cpu, cpu_callout_mask); 1469 cpumask_clear_cpu(cpu, cpu_callin_mask); 1470 /* was set by cpu_init() */ 1471 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1472 numa_remove_cpu(cpu); 1473 } 1474 1475 void cpu_disable_common(void) 1476 { 1477 int cpu = smp_processor_id(); 1478 1479 remove_siblinginfo(cpu); 1480 1481 /* It's now safe to remove this processor from the online map */ 1482 lock_vector_lock(); 1483 remove_cpu_from_maps(cpu); 1484 unlock_vector_lock(); 1485 fixup_irqs(); 1486 } 1487 1488 int native_cpu_disable(void) 1489 { 1490 int ret; 1491 1492 ret = check_irq_vectors_for_cpu_disable(); 1493 if (ret) 1494 return ret; 1495 1496 clear_local_APIC(); 1497 cpu_disable_common(); 1498 1499 return 0; 1500 } 1501 1502 int common_cpu_die(unsigned int cpu) 1503 { 1504 int ret = 0; 1505 1506 /* We don't do anything here: idle task is faking death itself. */ 1507 1508 /* They ack this in play_dead() by setting CPU_DEAD */ 1509 if (cpu_wait_death(cpu, 5)) { 1510 if (system_state == SYSTEM_RUNNING) 1511 pr_info("CPU %u is now offline\n", cpu); 1512 } else { 1513 pr_err("CPU %u didn't die...\n", cpu); 1514 ret = -1; 1515 } 1516 1517 return ret; 1518 } 1519 1520 void native_cpu_die(unsigned int cpu) 1521 { 1522 common_cpu_die(cpu); 1523 } 1524 1525 void play_dead_common(void) 1526 { 1527 idle_task_exit(); 1528 reset_lazy_tlbstate(); 1529 amd_e400_remove_cpu(raw_smp_processor_id()); 1530 1531 /* Ack it */ 1532 (void)cpu_report_death(); 1533 1534 /* 1535 * With physical CPU hotplug, we should halt the cpu 1536 */ 1537 local_irq_disable(); 1538 } 1539 1540 static bool wakeup_cpu0(void) 1541 { 1542 if (smp_processor_id() == 0 && enable_start_cpu0) 1543 return true; 1544 1545 return false; 1546 } 1547 1548 /* 1549 * We need to flush the caches before going to sleep, lest we have 1550 * dirty data in our caches when we come back up. 1551 */ 1552 static inline void mwait_play_dead(void) 1553 { 1554 unsigned int eax, ebx, ecx, edx; 1555 unsigned int highest_cstate = 0; 1556 unsigned int highest_subcstate = 0; 1557 void *mwait_ptr; 1558 int i; 1559 1560 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1561 return; 1562 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1563 return; 1564 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1565 return; 1566 1567 eax = CPUID_MWAIT_LEAF; 1568 ecx = 0; 1569 native_cpuid(&eax, &ebx, &ecx, &edx); 1570 1571 /* 1572 * eax will be 0 if EDX enumeration is not valid. 1573 * Initialized below to cstate, sub_cstate value when EDX is valid. 1574 */ 1575 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1576 eax = 0; 1577 } else { 1578 edx >>= MWAIT_SUBSTATE_SIZE; 1579 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1580 if (edx & MWAIT_SUBSTATE_MASK) { 1581 highest_cstate = i; 1582 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1583 } 1584 } 1585 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1586 (highest_subcstate - 1); 1587 } 1588 1589 /* 1590 * This should be a memory location in a cache line which is 1591 * unlikely to be touched by other processors. The actual 1592 * content is immaterial as it is not actually modified in any way. 1593 */ 1594 mwait_ptr = ¤t_thread_info()->flags; 1595 1596 wbinvd(); 1597 1598 while (1) { 1599 /* 1600 * The CLFLUSH is a workaround for erratum AAI65 for 1601 * the Xeon 7400 series. It's not clear it is actually 1602 * needed, but it should be harmless in either case. 1603 * The WBINVD is insufficient due to the spurious-wakeup 1604 * case where we return around the loop. 1605 */ 1606 mb(); 1607 clflush(mwait_ptr); 1608 mb(); 1609 __monitor(mwait_ptr, 0, 0); 1610 mb(); 1611 __mwait(eax, 0); 1612 /* 1613 * If NMI wants to wake up CPU0, start CPU0. 1614 */ 1615 if (wakeup_cpu0()) 1616 start_cpu0(); 1617 } 1618 } 1619 1620 static inline void hlt_play_dead(void) 1621 { 1622 if (__this_cpu_read(cpu_info.x86) >= 4) 1623 wbinvd(); 1624 1625 while (1) { 1626 native_halt(); 1627 /* 1628 * If NMI wants to wake up CPU0, start CPU0. 1629 */ 1630 if (wakeup_cpu0()) 1631 start_cpu0(); 1632 } 1633 } 1634 1635 void native_play_dead(void) 1636 { 1637 play_dead_common(); 1638 tboot_shutdown(TB_SHUTDOWN_WFS); 1639 1640 mwait_play_dead(); /* Only returns on failure */ 1641 if (cpuidle_play_dead()) 1642 hlt_play_dead(); 1643 } 1644 1645 #else /* ... !CONFIG_HOTPLUG_CPU */ 1646 int native_cpu_disable(void) 1647 { 1648 return -ENOSYS; 1649 } 1650 1651 void native_cpu_die(unsigned int cpu) 1652 { 1653 /* We said "no" in __cpu_disable */ 1654 BUG(); 1655 } 1656 1657 void native_play_dead(void) 1658 { 1659 BUG(); 1660 } 1661 1662 #endif 1663