1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/fpu/internal.h> 72 #include <asm/setup.h> 73 #include <asm/uv/uv.h> 74 #include <linux/mc146818rtc.h> 75 #include <asm/i8259.h> 76 #include <asm/realmode.h> 77 #include <asm/misc.h> 78 79 /* Number of siblings per CPU package */ 80 int smp_num_siblings = 1; 81 EXPORT_SYMBOL(smp_num_siblings); 82 83 /* Last level cache ID of each logical CPU */ 84 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 atomic_t init_deasserted; 101 102 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 103 { 104 unsigned long flags; 105 106 spin_lock_irqsave(&rtc_lock, flags); 107 CMOS_WRITE(0xa, 0xf); 108 spin_unlock_irqrestore(&rtc_lock, flags); 109 local_flush_tlb(); 110 pr_debug("1.\n"); 111 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 112 start_eip >> 4; 113 pr_debug("2.\n"); 114 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 115 start_eip & 0xf; 116 pr_debug("3.\n"); 117 } 118 119 static inline void smpboot_restore_warm_reset_vector(void) 120 { 121 unsigned long flags; 122 123 /* 124 * Install writable page 0 entry to set BIOS data area. 125 */ 126 local_flush_tlb(); 127 128 /* 129 * Paranoid: Set warm reset code and vector here back 130 * to default values. 131 */ 132 spin_lock_irqsave(&rtc_lock, flags); 133 CMOS_WRITE(0, 0xf); 134 spin_unlock_irqrestore(&rtc_lock, flags); 135 136 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 137 } 138 139 /* 140 * Report back to the Boot Processor during boot time or to the caller processor 141 * during CPU online. 142 */ 143 static void smp_callin(void) 144 { 145 int cpuid, phys_id; 146 147 /* 148 * If waken up by an INIT in an 82489DX configuration 149 * we may get here before an INIT-deassert IPI reaches 150 * our local APIC. We have to wait for the IPI or we'll 151 * lock up on an APIC access. 152 * 153 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 154 */ 155 cpuid = smp_processor_id(); 156 if (apic->wait_for_init_deassert && cpuid) 157 while (!atomic_read(&init_deasserted)) 158 cpu_relax(); 159 160 /* 161 * (This works even if the APIC is not enabled.) 162 */ 163 phys_id = read_apic_id(); 164 165 /* 166 * the boot CPU has finished the init stage and is spinning 167 * on callin_map until we finish. We are free to set up this 168 * CPU, first the APIC. (this is probably redundant on most 169 * boards) 170 */ 171 apic_ap_setup(); 172 173 /* 174 * Save our processor parameters. Note: this information 175 * is needed for clock calibration. 176 */ 177 smp_store_cpu_info(cpuid); 178 179 /* 180 * Get our bogomips. 181 * Update loops_per_jiffy in cpu_data. Previous call to 182 * smp_store_cpu_info() stored a value that is close but not as 183 * accurate as the value just calculated. 184 */ 185 calibrate_delay(); 186 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 187 pr_debug("Stack at about %p\n", &cpuid); 188 189 /* 190 * This must be done before setting cpu_online_mask 191 * or calling notify_cpu_starting. 192 */ 193 set_cpu_sibling_map(raw_smp_processor_id()); 194 wmb(); 195 196 notify_cpu_starting(cpuid); 197 198 /* 199 * Allow the master to continue. 200 */ 201 cpumask_set_cpu(cpuid, cpu_callin_mask); 202 } 203 204 static int cpu0_logical_apicid; 205 static int enable_start_cpu0; 206 /* 207 * Activate a secondary processor. 208 */ 209 static void notrace start_secondary(void *unused) 210 { 211 /* 212 * Don't put *anything* before cpu_init(), SMP booting is too 213 * fragile that we want to limit the things done here to the 214 * most necessary things. 215 */ 216 cpu_init(); 217 x86_cpuinit.early_percpu_clock_init(); 218 preempt_disable(); 219 smp_callin(); 220 221 enable_start_cpu0 = 0; 222 223 #ifdef CONFIG_X86_32 224 /* switch away from the initial page table */ 225 load_cr3(swapper_pg_dir); 226 __flush_tlb_all(); 227 #endif 228 229 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 230 barrier(); 231 /* 232 * Check TSC synchronization with the BP: 233 */ 234 check_tsc_sync_target(); 235 236 /* 237 * Lock vector_lock and initialize the vectors on this cpu 238 * before setting the cpu online. We must set it online with 239 * vector_lock held to prevent a concurrent setup/teardown 240 * from seeing a half valid vector space. 241 */ 242 lock_vector_lock(); 243 setup_vector_irq(smp_processor_id()); 244 set_cpu_online(smp_processor_id(), true); 245 unlock_vector_lock(); 246 cpu_set_state_online(smp_processor_id()); 247 x86_platform.nmi_init(); 248 249 /* enable local interrupts */ 250 local_irq_enable(); 251 252 /* to prevent fake stack check failure in clock setup */ 253 boot_init_stack_canary(); 254 255 x86_cpuinit.setup_percpu_clockev(); 256 257 wmb(); 258 cpu_startup_entry(CPUHP_ONLINE); 259 } 260 261 void __init smp_store_boot_cpu_info(void) 262 { 263 int id = 0; /* CPU 0 */ 264 struct cpuinfo_x86 *c = &cpu_data(id); 265 266 *c = boot_cpu_data; 267 c->cpu_index = id; 268 } 269 270 /* 271 * The bootstrap kernel entry code has set these up. Save them for 272 * a given CPU 273 */ 274 void smp_store_cpu_info(int id) 275 { 276 struct cpuinfo_x86 *c = &cpu_data(id); 277 278 *c = boot_cpu_data; 279 c->cpu_index = id; 280 /* 281 * During boot time, CPU0 has this setup already. Save the info when 282 * bringing up AP or offlined CPU0. 283 */ 284 identify_secondary_cpu(c); 285 } 286 287 static bool 288 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 289 { 290 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 291 292 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 293 } 294 295 static bool 296 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 297 { 298 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 299 300 return !WARN_ONCE(!topology_same_node(c, o), 301 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 302 "[node: %d != %d]. Ignoring dependency.\n", 303 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 304 } 305 306 #define link_mask(mfunc, c1, c2) \ 307 do { \ 308 cpumask_set_cpu((c1), mfunc(c2)); \ 309 cpumask_set_cpu((c2), mfunc(c1)); \ 310 } while (0) 311 312 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 313 { 314 if (cpu_has_topoext) { 315 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 316 317 if (c->phys_proc_id == o->phys_proc_id && 318 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 319 c->compute_unit_id == o->compute_unit_id) 320 return topology_sane(c, o, "smt"); 321 322 } else if (c->phys_proc_id == o->phys_proc_id && 323 c->cpu_core_id == o->cpu_core_id) { 324 return topology_sane(c, o, "smt"); 325 } 326 327 return false; 328 } 329 330 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 331 { 332 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 333 334 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 335 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 336 return topology_sane(c, o, "llc"); 337 338 return false; 339 } 340 341 /* 342 * Unlike the other levels, we do not enforce keeping a 343 * multicore group inside a NUMA node. If this happens, we will 344 * discard the MC level of the topology later. 345 */ 346 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 347 { 348 if (c->phys_proc_id == o->phys_proc_id) 349 return true; 350 return false; 351 } 352 353 static struct sched_domain_topology_level numa_inside_package_topology[] = { 354 #ifdef CONFIG_SCHED_SMT 355 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 356 #endif 357 #ifdef CONFIG_SCHED_MC 358 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 359 #endif 360 { NULL, }, 361 }; 362 /* 363 * set_sched_topology() sets the topology internal to a CPU. The 364 * NUMA topologies are layered on top of it to build the full 365 * system topology. 366 * 367 * If NUMA nodes are observed to occur within a CPU package, this 368 * function should be called. It forces the sched domain code to 369 * only use the SMT level for the CPU portion of the topology. 370 * This essentially falls back to relying on NUMA information 371 * from the SRAT table to describe the entire system topology 372 * (except for hyperthreads). 373 */ 374 static void primarily_use_numa_for_topology(void) 375 { 376 set_sched_topology(numa_inside_package_topology); 377 } 378 379 void set_cpu_sibling_map(int cpu) 380 { 381 bool has_smt = smp_num_siblings > 1; 382 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 383 struct cpuinfo_x86 *c = &cpu_data(cpu); 384 struct cpuinfo_x86 *o; 385 int i; 386 387 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 388 389 if (!has_mp) { 390 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 391 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 392 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 393 c->booted_cores = 1; 394 return; 395 } 396 397 for_each_cpu(i, cpu_sibling_setup_mask) { 398 o = &cpu_data(i); 399 400 if ((i == cpu) || (has_smt && match_smt(c, o))) 401 link_mask(topology_sibling_cpumask, cpu, i); 402 403 if ((i == cpu) || (has_mp && match_llc(c, o))) 404 link_mask(cpu_llc_shared_mask, cpu, i); 405 406 } 407 408 /* 409 * This needs a separate iteration over the cpus because we rely on all 410 * topology_sibling_cpumask links to be set-up. 411 */ 412 for_each_cpu(i, cpu_sibling_setup_mask) { 413 o = &cpu_data(i); 414 415 if ((i == cpu) || (has_mp && match_die(c, o))) { 416 link_mask(topology_core_cpumask, cpu, i); 417 418 /* 419 * Does this new cpu bringup a new core? 420 */ 421 if (cpumask_weight( 422 topology_sibling_cpumask(cpu)) == 1) { 423 /* 424 * for each core in package, increment 425 * the booted_cores for this new cpu 426 */ 427 if (cpumask_first( 428 topology_sibling_cpumask(i)) == i) 429 c->booted_cores++; 430 /* 431 * increment the core count for all 432 * the other cpus in this package 433 */ 434 if (i != cpu) 435 cpu_data(i).booted_cores++; 436 } else if (i != cpu && !c->booted_cores) 437 c->booted_cores = cpu_data(i).booted_cores; 438 } 439 if (match_die(c, o) && !topology_same_node(c, o)) 440 primarily_use_numa_for_topology(); 441 } 442 } 443 444 /* maps the cpu to the sched domain representing multi-core */ 445 const struct cpumask *cpu_coregroup_mask(int cpu) 446 { 447 return cpu_llc_shared_mask(cpu); 448 } 449 450 static void impress_friends(void) 451 { 452 int cpu; 453 unsigned long bogosum = 0; 454 /* 455 * Allow the user to impress friends. 456 */ 457 pr_debug("Before bogomips\n"); 458 for_each_possible_cpu(cpu) 459 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 460 bogosum += cpu_data(cpu).loops_per_jiffy; 461 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 462 num_online_cpus(), 463 bogosum/(500000/HZ), 464 (bogosum/(5000/HZ))%100); 465 466 pr_debug("Before bogocount - setting activated=1\n"); 467 } 468 469 void __inquire_remote_apic(int apicid) 470 { 471 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 472 const char * const names[] = { "ID", "VERSION", "SPIV" }; 473 int timeout; 474 u32 status; 475 476 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 477 478 for (i = 0; i < ARRAY_SIZE(regs); i++) { 479 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 480 481 /* 482 * Wait for idle. 483 */ 484 status = safe_apic_wait_icr_idle(); 485 if (status) 486 pr_cont("a previous APIC delivery may have failed\n"); 487 488 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 489 490 timeout = 0; 491 do { 492 udelay(100); 493 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 494 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 495 496 switch (status) { 497 case APIC_ICR_RR_VALID: 498 status = apic_read(APIC_RRR); 499 pr_cont("%08x\n", status); 500 break; 501 default: 502 pr_cont("failed\n"); 503 } 504 } 505 } 506 507 /* 508 * The Multiprocessor Specification 1.4 (1997) example code suggests 509 * that there should be a 10ms delay between the BSP asserting INIT 510 * and de-asserting INIT, when starting a remote processor. 511 * But that slows boot and resume on modern processors, which include 512 * many cores and don't require that delay. 513 * 514 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 515 * Modern processor families are quirked to remove the delay entirely. 516 */ 517 #define UDELAY_10MS_DEFAULT 10000 518 519 static unsigned int init_udelay = UDELAY_10MS_DEFAULT; 520 521 static int __init cpu_init_udelay(char *str) 522 { 523 get_option(&str, &init_udelay); 524 525 return 0; 526 } 527 early_param("cpu_init_udelay", cpu_init_udelay); 528 529 static void __init smp_quirk_init_udelay(void) 530 { 531 /* if cmdline changed it from default, leave it alone */ 532 if (init_udelay != UDELAY_10MS_DEFAULT) 533 return; 534 535 /* if modern processor, use no delay */ 536 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 537 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) 538 init_udelay = 0; 539 } 540 541 /* 542 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 543 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 544 * won't ... remember to clear down the APIC, etc later. 545 */ 546 int 547 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 548 { 549 unsigned long send_status, accept_status = 0; 550 int maxlvt; 551 552 /* Target chip */ 553 /* Boot on the stack */ 554 /* Kick the second */ 555 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 556 557 pr_debug("Waiting for send to finish...\n"); 558 send_status = safe_apic_wait_icr_idle(); 559 560 /* 561 * Give the other CPU some time to accept the IPI. 562 */ 563 udelay(200); 564 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 565 maxlvt = lapic_get_maxlvt(); 566 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 567 apic_write(APIC_ESR, 0); 568 accept_status = (apic_read(APIC_ESR) & 0xEF); 569 } 570 pr_debug("NMI sent\n"); 571 572 if (send_status) 573 pr_err("APIC never delivered???\n"); 574 if (accept_status) 575 pr_err("APIC delivery error (%lx)\n", accept_status); 576 577 return (send_status | accept_status); 578 } 579 580 static int 581 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 582 { 583 unsigned long send_status = 0, accept_status = 0; 584 int maxlvt, num_starts, j; 585 586 maxlvt = lapic_get_maxlvt(); 587 588 /* 589 * Be paranoid about clearing APIC errors. 590 */ 591 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 592 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 593 apic_write(APIC_ESR, 0); 594 apic_read(APIC_ESR); 595 } 596 597 pr_debug("Asserting INIT\n"); 598 599 /* 600 * Turn INIT on target chip 601 */ 602 /* 603 * Send IPI 604 */ 605 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 606 phys_apicid); 607 608 pr_debug("Waiting for send to finish...\n"); 609 send_status = safe_apic_wait_icr_idle(); 610 611 udelay(init_udelay); 612 613 pr_debug("Deasserting INIT\n"); 614 615 /* Target chip */ 616 /* Send IPI */ 617 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 618 619 pr_debug("Waiting for send to finish...\n"); 620 send_status = safe_apic_wait_icr_idle(); 621 622 mb(); 623 atomic_set(&init_deasserted, 1); 624 625 /* 626 * Should we send STARTUP IPIs ? 627 * 628 * Determine this based on the APIC version. 629 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 630 */ 631 if (APIC_INTEGRATED(apic_version[phys_apicid])) 632 num_starts = 2; 633 else 634 num_starts = 0; 635 636 /* 637 * Paravirt / VMI wants a startup IPI hook here to set up the 638 * target processor state. 639 */ 640 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 641 stack_start); 642 643 /* 644 * Run STARTUP IPI loop. 645 */ 646 pr_debug("#startup loops: %d\n", num_starts); 647 648 for (j = 1; j <= num_starts; j++) { 649 pr_debug("Sending STARTUP #%d\n", j); 650 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 651 apic_write(APIC_ESR, 0); 652 apic_read(APIC_ESR); 653 pr_debug("After apic_write\n"); 654 655 /* 656 * STARTUP IPI 657 */ 658 659 /* Target chip */ 660 /* Boot on the stack */ 661 /* Kick the second */ 662 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 663 phys_apicid); 664 665 /* 666 * Give the other CPU some time to accept the IPI. 667 */ 668 udelay(300); 669 670 pr_debug("Startup point 1\n"); 671 672 pr_debug("Waiting for send to finish...\n"); 673 send_status = safe_apic_wait_icr_idle(); 674 675 /* 676 * Give the other CPU some time to accept the IPI. 677 */ 678 udelay(200); 679 680 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 681 apic_write(APIC_ESR, 0); 682 accept_status = (apic_read(APIC_ESR) & 0xEF); 683 if (send_status || accept_status) 684 break; 685 } 686 pr_debug("After Startup\n"); 687 688 if (send_status) 689 pr_err("APIC never delivered???\n"); 690 if (accept_status) 691 pr_err("APIC delivery error (%lx)\n", accept_status); 692 693 return (send_status | accept_status); 694 } 695 696 void smp_announce(void) 697 { 698 int num_nodes = num_online_nodes(); 699 700 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 701 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 702 } 703 704 /* reduce the number of lines printed when booting a large cpu count system */ 705 static void announce_cpu(int cpu, int apicid) 706 { 707 static int current_node = -1; 708 int node = early_cpu_to_node(cpu); 709 static int width, node_width; 710 711 if (!width) 712 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 713 714 if (!node_width) 715 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 716 717 if (cpu == 1) 718 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 719 720 if (system_state == SYSTEM_BOOTING) { 721 if (node != current_node) { 722 if (current_node > (-1)) 723 pr_cont("\n"); 724 current_node = node; 725 726 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 727 node_width - num_digits(node), " ", node); 728 } 729 730 /* Add padding for the BSP */ 731 if (cpu == 1) 732 pr_cont("%*s", width + 1, " "); 733 734 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 735 736 } else 737 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 738 node, cpu, apicid); 739 } 740 741 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 742 { 743 int cpu; 744 745 cpu = smp_processor_id(); 746 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 747 return NMI_HANDLED; 748 749 return NMI_DONE; 750 } 751 752 /* 753 * Wake up AP by INIT, INIT, STARTUP sequence. 754 * 755 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 756 * boot-strap code which is not a desired behavior for waking up BSP. To 757 * void the boot-strap code, wake up CPU0 by NMI instead. 758 * 759 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 760 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 761 * We'll change this code in the future to wake up hard offlined CPU0 if 762 * real platform and request are available. 763 */ 764 static int 765 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 766 int *cpu0_nmi_registered) 767 { 768 int id; 769 int boot_error; 770 771 preempt_disable(); 772 773 /* 774 * Wake up AP by INIT, INIT, STARTUP sequence. 775 */ 776 if (cpu) { 777 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 778 goto out; 779 } 780 781 /* 782 * Wake up BSP by nmi. 783 * 784 * Register a NMI handler to help wake up CPU0. 785 */ 786 boot_error = register_nmi_handler(NMI_LOCAL, 787 wakeup_cpu0_nmi, 0, "wake_cpu0"); 788 789 if (!boot_error) { 790 enable_start_cpu0 = 1; 791 *cpu0_nmi_registered = 1; 792 if (apic->dest_logical == APIC_DEST_LOGICAL) 793 id = cpu0_logical_apicid; 794 else 795 id = apicid; 796 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 797 } 798 799 out: 800 preempt_enable(); 801 802 return boot_error; 803 } 804 805 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 806 { 807 /* Just in case we booted with a single CPU. */ 808 alternatives_enable_smp(); 809 810 per_cpu(current_task, cpu) = idle; 811 812 #ifdef CONFIG_X86_32 813 /* Stack for startup_32 can be just as for start_secondary onwards */ 814 irq_ctx_init(cpu); 815 per_cpu(cpu_current_top_of_stack, cpu) = 816 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 817 #else 818 clear_tsk_thread_flag(idle, TIF_FORK); 819 initial_gs = per_cpu_offset(cpu); 820 #endif 821 } 822 823 /* 824 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 825 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 826 * Returns zero if CPU booted OK, else error code from 827 * ->wakeup_secondary_cpu. 828 */ 829 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 830 { 831 volatile u32 *trampoline_status = 832 (volatile u32 *) __va(real_mode_header->trampoline_status); 833 /* start_ip had better be page-aligned! */ 834 unsigned long start_ip = real_mode_header->trampoline_start; 835 836 unsigned long boot_error = 0; 837 int cpu0_nmi_registered = 0; 838 unsigned long timeout; 839 840 idle->thread.sp = (unsigned long) (((struct pt_regs *) 841 (THREAD_SIZE + task_stack_page(idle))) - 1); 842 843 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 844 initial_code = (unsigned long)start_secondary; 845 stack_start = idle->thread.sp; 846 847 /* 848 * Enable the espfix hack for this CPU 849 */ 850 #ifdef CONFIG_X86_ESPFIX64 851 init_espfix_ap(cpu); 852 #endif 853 854 /* So we see what's up */ 855 announce_cpu(cpu, apicid); 856 857 /* 858 * This grunge runs the startup process for 859 * the targeted processor. 860 */ 861 862 atomic_set(&init_deasserted, 0); 863 864 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 865 866 pr_debug("Setting warm reset code and vector.\n"); 867 868 smpboot_setup_warm_reset_vector(start_ip); 869 /* 870 * Be paranoid about clearing APIC errors. 871 */ 872 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 873 apic_write(APIC_ESR, 0); 874 apic_read(APIC_ESR); 875 } 876 } 877 878 /* 879 * AP might wait on cpu_callout_mask in cpu_init() with 880 * cpu_initialized_mask set if previous attempt to online 881 * it timed-out. Clear cpu_initialized_mask so that after 882 * INIT/SIPI it could start with a clean state. 883 */ 884 cpumask_clear_cpu(cpu, cpu_initialized_mask); 885 smp_mb(); 886 887 /* 888 * Wake up a CPU in difference cases: 889 * - Use the method in the APIC driver if it's defined 890 * Otherwise, 891 * - Use an INIT boot APIC message for APs or NMI for BSP. 892 */ 893 if (apic->wakeup_secondary_cpu) 894 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 895 else 896 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 897 &cpu0_nmi_registered); 898 899 if (!boot_error) { 900 /* 901 * Wait 10s total for first sign of life from AP 902 */ 903 boot_error = -1; 904 timeout = jiffies + 10*HZ; 905 while (time_before(jiffies, timeout)) { 906 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 907 /* 908 * Tell AP to proceed with initialization 909 */ 910 cpumask_set_cpu(cpu, cpu_callout_mask); 911 boot_error = 0; 912 break; 913 } 914 schedule(); 915 } 916 } 917 918 if (!boot_error) { 919 /* 920 * Wait till AP completes initial initialization 921 */ 922 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 923 /* 924 * Allow other tasks to run while we wait for the 925 * AP to come online. This also gives a chance 926 * for the MTRR work(triggered by the AP coming online) 927 * to be completed in the stop machine context. 928 */ 929 udelay(100); 930 schedule(); 931 } 932 } 933 934 /* mark "stuck" area as not stuck */ 935 *trampoline_status = 0; 936 937 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 938 /* 939 * Cleanup possible dangling ends... 940 */ 941 smpboot_restore_warm_reset_vector(); 942 } 943 /* 944 * Clean up the nmi handler. Do this after the callin and callout sync 945 * to avoid impact of possible long unregister time. 946 */ 947 if (cpu0_nmi_registered) 948 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 949 950 return boot_error; 951 } 952 953 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 954 { 955 int apicid = apic->cpu_present_to_apicid(cpu); 956 unsigned long flags; 957 int err; 958 959 WARN_ON(irqs_disabled()); 960 961 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 962 963 if (apicid == BAD_APICID || 964 !physid_isset(apicid, phys_cpu_present_map) || 965 !apic->apic_id_valid(apicid)) { 966 pr_err("%s: bad cpu %d\n", __func__, cpu); 967 return -EINVAL; 968 } 969 970 /* 971 * Already booted CPU? 972 */ 973 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 974 pr_debug("do_boot_cpu %d Already started\n", cpu); 975 return -ENOSYS; 976 } 977 978 /* 979 * Save current MTRR state in case it was changed since early boot 980 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 981 */ 982 mtrr_save_state(); 983 984 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 985 err = cpu_check_up_prepare(cpu); 986 if (err && err != -EBUSY) 987 return err; 988 989 /* the FPU context is blank, nobody can own it */ 990 __cpu_disable_lazy_restore(cpu); 991 992 common_cpu_up(cpu, tidle); 993 994 /* 995 * We have to walk the irq descriptors to setup the vector 996 * space for the cpu which comes online. Prevent irq 997 * alloc/free across the bringup. 998 */ 999 irq_lock_sparse(); 1000 1001 err = do_boot_cpu(apicid, cpu, tidle); 1002 1003 if (err) { 1004 irq_unlock_sparse(); 1005 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1006 return -EIO; 1007 } 1008 1009 /* 1010 * Check TSC synchronization with the AP (keep irqs disabled 1011 * while doing so): 1012 */ 1013 local_irq_save(flags); 1014 check_tsc_sync_source(cpu); 1015 local_irq_restore(flags); 1016 1017 while (!cpu_online(cpu)) { 1018 cpu_relax(); 1019 touch_nmi_watchdog(); 1020 } 1021 1022 irq_unlock_sparse(); 1023 1024 return 0; 1025 } 1026 1027 /** 1028 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1029 */ 1030 void arch_disable_smp_support(void) 1031 { 1032 disable_ioapic_support(); 1033 } 1034 1035 /* 1036 * Fall back to non SMP mode after errors. 1037 * 1038 * RED-PEN audit/test this more. I bet there is more state messed up here. 1039 */ 1040 static __init void disable_smp(void) 1041 { 1042 pr_info("SMP disabled\n"); 1043 1044 disable_ioapic_support(); 1045 1046 init_cpu_present(cpumask_of(0)); 1047 init_cpu_possible(cpumask_of(0)); 1048 1049 if (smp_found_config) 1050 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1051 else 1052 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1053 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1054 cpumask_set_cpu(0, topology_core_cpumask(0)); 1055 } 1056 1057 enum { 1058 SMP_OK, 1059 SMP_NO_CONFIG, 1060 SMP_NO_APIC, 1061 SMP_FORCE_UP, 1062 }; 1063 1064 /* 1065 * Various sanity checks. 1066 */ 1067 static int __init smp_sanity_check(unsigned max_cpus) 1068 { 1069 preempt_disable(); 1070 1071 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1072 if (def_to_bigsmp && nr_cpu_ids > 8) { 1073 unsigned int cpu; 1074 unsigned nr; 1075 1076 pr_warn("More than 8 CPUs detected - skipping them\n" 1077 "Use CONFIG_X86_BIGSMP\n"); 1078 1079 nr = 0; 1080 for_each_present_cpu(cpu) { 1081 if (nr >= 8) 1082 set_cpu_present(cpu, false); 1083 nr++; 1084 } 1085 1086 nr = 0; 1087 for_each_possible_cpu(cpu) { 1088 if (nr >= 8) 1089 set_cpu_possible(cpu, false); 1090 nr++; 1091 } 1092 1093 nr_cpu_ids = 8; 1094 } 1095 #endif 1096 1097 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1098 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1099 hard_smp_processor_id()); 1100 1101 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1102 } 1103 1104 /* 1105 * If we couldn't find an SMP configuration at boot time, 1106 * get out of here now! 1107 */ 1108 if (!smp_found_config && !acpi_lapic) { 1109 preempt_enable(); 1110 pr_notice("SMP motherboard not detected\n"); 1111 return SMP_NO_CONFIG; 1112 } 1113 1114 /* 1115 * Should not be necessary because the MP table should list the boot 1116 * CPU too, but we do it for the sake of robustness anyway. 1117 */ 1118 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1119 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1120 boot_cpu_physical_apicid); 1121 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1122 } 1123 preempt_enable(); 1124 1125 /* 1126 * If we couldn't find a local APIC, then get out of here now! 1127 */ 1128 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1129 !cpu_has_apic) { 1130 if (!disable_apic) { 1131 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1132 boot_cpu_physical_apicid); 1133 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1134 } 1135 return SMP_NO_APIC; 1136 } 1137 1138 /* 1139 * If SMP should be disabled, then really disable it! 1140 */ 1141 if (!max_cpus) { 1142 pr_info("SMP mode deactivated\n"); 1143 return SMP_FORCE_UP; 1144 } 1145 1146 return SMP_OK; 1147 } 1148 1149 static void __init smp_cpu_index_default(void) 1150 { 1151 int i; 1152 struct cpuinfo_x86 *c; 1153 1154 for_each_possible_cpu(i) { 1155 c = &cpu_data(i); 1156 /* mark all to hotplug */ 1157 c->cpu_index = nr_cpu_ids; 1158 } 1159 } 1160 1161 /* 1162 * Prepare for SMP bootup. The MP table or ACPI has been read 1163 * earlier. Just do some sanity checking here and enable APIC mode. 1164 */ 1165 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1166 { 1167 unsigned int i; 1168 1169 smp_cpu_index_default(); 1170 1171 /* 1172 * Setup boot CPU information 1173 */ 1174 smp_store_boot_cpu_info(); /* Final full version of the data */ 1175 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1176 mb(); 1177 1178 current_thread_info()->cpu = 0; /* needed? */ 1179 for_each_possible_cpu(i) { 1180 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1181 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1182 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1183 } 1184 set_cpu_sibling_map(0); 1185 1186 switch (smp_sanity_check(max_cpus)) { 1187 case SMP_NO_CONFIG: 1188 disable_smp(); 1189 if (APIC_init_uniprocessor()) 1190 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1191 return; 1192 case SMP_NO_APIC: 1193 disable_smp(); 1194 return; 1195 case SMP_FORCE_UP: 1196 disable_smp(); 1197 apic_bsp_setup(false); 1198 return; 1199 case SMP_OK: 1200 break; 1201 } 1202 1203 default_setup_apic_routing(); 1204 1205 if (read_apic_id() != boot_cpu_physical_apicid) { 1206 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1207 read_apic_id(), boot_cpu_physical_apicid); 1208 /* Or can we switch back to PIC here? */ 1209 } 1210 1211 cpu0_logical_apicid = apic_bsp_setup(false); 1212 1213 pr_info("CPU%d: ", 0); 1214 print_cpu_info(&cpu_data(0)); 1215 1216 if (is_uv_system()) 1217 uv_system_init(); 1218 1219 set_mtrr_aps_delayed_init(); 1220 1221 smp_quirk_init_udelay(); 1222 } 1223 1224 void arch_enable_nonboot_cpus_begin(void) 1225 { 1226 set_mtrr_aps_delayed_init(); 1227 } 1228 1229 void arch_enable_nonboot_cpus_end(void) 1230 { 1231 mtrr_aps_init(); 1232 } 1233 1234 /* 1235 * Early setup to make printk work. 1236 */ 1237 void __init native_smp_prepare_boot_cpu(void) 1238 { 1239 int me = smp_processor_id(); 1240 switch_to_new_gdt(me); 1241 /* already set me in cpu_online_mask in boot_cpu_init() */ 1242 cpumask_set_cpu(me, cpu_callout_mask); 1243 cpu_set_state_online(me); 1244 } 1245 1246 void __init native_smp_cpus_done(unsigned int max_cpus) 1247 { 1248 pr_debug("Boot done\n"); 1249 1250 nmi_selftest(); 1251 impress_friends(); 1252 setup_ioapic_dest(); 1253 mtrr_aps_init(); 1254 } 1255 1256 static int __initdata setup_possible_cpus = -1; 1257 static int __init _setup_possible_cpus(char *str) 1258 { 1259 get_option(&str, &setup_possible_cpus); 1260 return 0; 1261 } 1262 early_param("possible_cpus", _setup_possible_cpus); 1263 1264 1265 /* 1266 * cpu_possible_mask should be static, it cannot change as cpu's 1267 * are onlined, or offlined. The reason is per-cpu data-structures 1268 * are allocated by some modules at init time, and dont expect to 1269 * do this dynamically on cpu arrival/departure. 1270 * cpu_present_mask on the other hand can change dynamically. 1271 * In case when cpu_hotplug is not compiled, then we resort to current 1272 * behaviour, which is cpu_possible == cpu_present. 1273 * - Ashok Raj 1274 * 1275 * Three ways to find out the number of additional hotplug CPUs: 1276 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1277 * - The user can overwrite it with possible_cpus=NUM 1278 * - Otherwise don't reserve additional CPUs. 1279 * We do this because additional CPUs waste a lot of memory. 1280 * -AK 1281 */ 1282 __init void prefill_possible_map(void) 1283 { 1284 int i, possible; 1285 1286 /* no processor from mptable or madt */ 1287 if (!num_processors) 1288 num_processors = 1; 1289 1290 i = setup_max_cpus ?: 1; 1291 if (setup_possible_cpus == -1) { 1292 possible = num_processors; 1293 #ifdef CONFIG_HOTPLUG_CPU 1294 if (setup_max_cpus) 1295 possible += disabled_cpus; 1296 #else 1297 if (possible > i) 1298 possible = i; 1299 #endif 1300 } else 1301 possible = setup_possible_cpus; 1302 1303 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1304 1305 /* nr_cpu_ids could be reduced via nr_cpus= */ 1306 if (possible > nr_cpu_ids) { 1307 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1308 possible, nr_cpu_ids); 1309 possible = nr_cpu_ids; 1310 } 1311 1312 #ifdef CONFIG_HOTPLUG_CPU 1313 if (!setup_max_cpus) 1314 #endif 1315 if (possible > i) { 1316 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1317 possible, setup_max_cpus); 1318 possible = i; 1319 } 1320 1321 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1322 possible, max_t(int, possible - num_processors, 0)); 1323 1324 for (i = 0; i < possible; i++) 1325 set_cpu_possible(i, true); 1326 for (; i < NR_CPUS; i++) 1327 set_cpu_possible(i, false); 1328 1329 nr_cpu_ids = possible; 1330 } 1331 1332 #ifdef CONFIG_HOTPLUG_CPU 1333 1334 static void remove_siblinginfo(int cpu) 1335 { 1336 int sibling; 1337 struct cpuinfo_x86 *c = &cpu_data(cpu); 1338 1339 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1340 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1341 /*/ 1342 * last thread sibling in this cpu core going down 1343 */ 1344 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1345 cpu_data(sibling).booted_cores--; 1346 } 1347 1348 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1349 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1350 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1351 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1352 cpumask_clear(cpu_llc_shared_mask(cpu)); 1353 cpumask_clear(topology_sibling_cpumask(cpu)); 1354 cpumask_clear(topology_core_cpumask(cpu)); 1355 c->phys_proc_id = 0; 1356 c->cpu_core_id = 0; 1357 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1358 } 1359 1360 static void __ref remove_cpu_from_maps(int cpu) 1361 { 1362 set_cpu_online(cpu, false); 1363 cpumask_clear_cpu(cpu, cpu_callout_mask); 1364 cpumask_clear_cpu(cpu, cpu_callin_mask); 1365 /* was set by cpu_init() */ 1366 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1367 numa_remove_cpu(cpu); 1368 } 1369 1370 void cpu_disable_common(void) 1371 { 1372 int cpu = smp_processor_id(); 1373 1374 remove_siblinginfo(cpu); 1375 1376 /* It's now safe to remove this processor from the online map */ 1377 lock_vector_lock(); 1378 remove_cpu_from_maps(cpu); 1379 unlock_vector_lock(); 1380 fixup_irqs(); 1381 } 1382 1383 int native_cpu_disable(void) 1384 { 1385 int ret; 1386 1387 ret = check_irq_vectors_for_cpu_disable(); 1388 if (ret) 1389 return ret; 1390 1391 clear_local_APIC(); 1392 cpu_disable_common(); 1393 1394 return 0; 1395 } 1396 1397 int common_cpu_die(unsigned int cpu) 1398 { 1399 int ret = 0; 1400 1401 /* We don't do anything here: idle task is faking death itself. */ 1402 1403 /* They ack this in play_dead() by setting CPU_DEAD */ 1404 if (cpu_wait_death(cpu, 5)) { 1405 if (system_state == SYSTEM_RUNNING) 1406 pr_info("CPU %u is now offline\n", cpu); 1407 } else { 1408 pr_err("CPU %u didn't die...\n", cpu); 1409 ret = -1; 1410 } 1411 1412 return ret; 1413 } 1414 1415 void native_cpu_die(unsigned int cpu) 1416 { 1417 common_cpu_die(cpu); 1418 } 1419 1420 void play_dead_common(void) 1421 { 1422 idle_task_exit(); 1423 reset_lazy_tlbstate(); 1424 amd_e400_remove_cpu(raw_smp_processor_id()); 1425 1426 /* Ack it */ 1427 (void)cpu_report_death(); 1428 1429 /* 1430 * With physical CPU hotplug, we should halt the cpu 1431 */ 1432 local_irq_disable(); 1433 } 1434 1435 static bool wakeup_cpu0(void) 1436 { 1437 if (smp_processor_id() == 0 && enable_start_cpu0) 1438 return true; 1439 1440 return false; 1441 } 1442 1443 /* 1444 * We need to flush the caches before going to sleep, lest we have 1445 * dirty data in our caches when we come back up. 1446 */ 1447 static inline void mwait_play_dead(void) 1448 { 1449 unsigned int eax, ebx, ecx, edx; 1450 unsigned int highest_cstate = 0; 1451 unsigned int highest_subcstate = 0; 1452 void *mwait_ptr; 1453 int i; 1454 1455 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1456 return; 1457 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1458 return; 1459 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1460 return; 1461 1462 eax = CPUID_MWAIT_LEAF; 1463 ecx = 0; 1464 native_cpuid(&eax, &ebx, &ecx, &edx); 1465 1466 /* 1467 * eax will be 0 if EDX enumeration is not valid. 1468 * Initialized below to cstate, sub_cstate value when EDX is valid. 1469 */ 1470 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1471 eax = 0; 1472 } else { 1473 edx >>= MWAIT_SUBSTATE_SIZE; 1474 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1475 if (edx & MWAIT_SUBSTATE_MASK) { 1476 highest_cstate = i; 1477 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1478 } 1479 } 1480 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1481 (highest_subcstate - 1); 1482 } 1483 1484 /* 1485 * This should be a memory location in a cache line which is 1486 * unlikely to be touched by other processors. The actual 1487 * content is immaterial as it is not actually modified in any way. 1488 */ 1489 mwait_ptr = ¤t_thread_info()->flags; 1490 1491 wbinvd(); 1492 1493 while (1) { 1494 /* 1495 * The CLFLUSH is a workaround for erratum AAI65 for 1496 * the Xeon 7400 series. It's not clear it is actually 1497 * needed, but it should be harmless in either case. 1498 * The WBINVD is insufficient due to the spurious-wakeup 1499 * case where we return around the loop. 1500 */ 1501 mb(); 1502 clflush(mwait_ptr); 1503 mb(); 1504 __monitor(mwait_ptr, 0, 0); 1505 mb(); 1506 __mwait(eax, 0); 1507 /* 1508 * If NMI wants to wake up CPU0, start CPU0. 1509 */ 1510 if (wakeup_cpu0()) 1511 start_cpu0(); 1512 } 1513 } 1514 1515 static inline void hlt_play_dead(void) 1516 { 1517 if (__this_cpu_read(cpu_info.x86) >= 4) 1518 wbinvd(); 1519 1520 while (1) { 1521 native_halt(); 1522 /* 1523 * If NMI wants to wake up CPU0, start CPU0. 1524 */ 1525 if (wakeup_cpu0()) 1526 start_cpu0(); 1527 } 1528 } 1529 1530 void native_play_dead(void) 1531 { 1532 play_dead_common(); 1533 tboot_shutdown(TB_SHUTDOWN_WFS); 1534 1535 mwait_play_dead(); /* Only returns on failure */ 1536 if (cpuidle_play_dead()) 1537 hlt_play_dead(); 1538 } 1539 1540 #else /* ... !CONFIG_HOTPLUG_CPU */ 1541 int native_cpu_disable(void) 1542 { 1543 return -ENOSYS; 1544 } 1545 1546 void native_cpu_die(unsigned int cpu) 1547 { 1548 /* We said "no" in __cpu_disable */ 1549 BUG(); 1550 } 1551 1552 void native_play_dead(void) 1553 { 1554 BUG(); 1555 } 1556 1557 #endif 1558