1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/desc.h> 64 #include <asm/nmi.h> 65 #include <asm/irq.h> 66 #include <asm/realmode.h> 67 #include <asm/cpu.h> 68 #include <asm/numa.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/api.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 #include <asm/stackprotector.h> 86 #include <asm/sev.h> 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 /* representing HT, core, and die siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* All of these masks are initialized in setup_cpu_local_masks() */ 105 static cpumask_var_t cpu_initialized_mask; 106 static cpumask_var_t cpu_callout_mask; 107 static cpumask_var_t cpu_callin_mask; 108 /* Representing CPUs for which sibling maps can be computed */ 109 static cpumask_var_t cpu_sibling_setup_mask; 110 111 /* Logical package management. We might want to allocate that dynamically */ 112 unsigned int __max_logical_packages __read_mostly; 113 EXPORT_SYMBOL(__max_logical_packages); 114 static unsigned int logical_packages __read_mostly; 115 static unsigned int logical_die __read_mostly; 116 117 /* Maximum number of SMT threads on any online core */ 118 int __read_mostly __max_smt_threads = 1; 119 120 /* Flag to indicate if a complete sched domain rebuild is required */ 121 bool x86_topology_update; 122 123 int arch_update_cpu_topology(void) 124 { 125 int retval = x86_topology_update; 126 127 x86_topology_update = false; 128 return retval; 129 } 130 131 132 static unsigned int smpboot_warm_reset_vector_count; 133 134 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 135 { 136 unsigned long flags; 137 138 spin_lock_irqsave(&rtc_lock, flags); 139 if (!smpboot_warm_reset_vector_count++) { 140 CMOS_WRITE(0xa, 0xf); 141 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 142 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 143 } 144 spin_unlock_irqrestore(&rtc_lock, flags); 145 } 146 147 static inline void smpboot_restore_warm_reset_vector(void) 148 { 149 unsigned long flags; 150 151 /* 152 * Paranoid: Set warm reset code and vector here back 153 * to default values. 154 */ 155 spin_lock_irqsave(&rtc_lock, flags); 156 if (!--smpboot_warm_reset_vector_count) { 157 CMOS_WRITE(0, 0xf); 158 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 159 } 160 spin_unlock_irqrestore(&rtc_lock, flags); 161 162 } 163 164 /* 165 * Report back to the Boot Processor during boot time or to the caller processor 166 * during CPU online. 167 */ 168 static void smp_callin(void) 169 { 170 int cpuid; 171 172 /* 173 * If waken up by an INIT in an 82489DX configuration 174 * cpu_callout_mask guarantees we don't get here before 175 * an INIT_deassert IPI reaches our local APIC, so it is 176 * now safe to touch our local APIC. 177 */ 178 cpuid = smp_processor_id(); 179 180 /* 181 * the boot CPU has finished the init stage and is spinning 182 * on callin_map until we finish. We are free to set up this 183 * CPU, first the APIC. (this is probably redundant on most 184 * boards) 185 */ 186 apic_ap_setup(); 187 188 /* Save our processor parameters. */ 189 smp_store_cpu_info(cpuid); 190 191 /* 192 * The topology information must be up to date before 193 * notify_cpu_starting(). 194 */ 195 set_cpu_sibling_map(raw_smp_processor_id()); 196 197 ap_init_aperfmperf(); 198 199 pr_debug("Stack at about %p\n", &cpuid); 200 201 wmb(); 202 203 /* 204 * This runs the AP through all the cpuhp states to its target 205 * state CPUHP_ONLINE. 206 */ 207 notify_cpu_starting(cpuid); 208 209 /* 210 * Allow the master to continue. 211 */ 212 cpumask_set_cpu(cpuid, cpu_callin_mask); 213 } 214 215 static void ap_calibrate_delay(void) 216 { 217 /* 218 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 219 * smp_store_cpu_info() stored a value that is close but not as 220 * accurate as the value just calculated. 221 * 222 * As this is invoked after the TSC synchronization check, 223 * calibrate_delay_is_known() will skip the calibration routine 224 * when TSC is synchronized across sockets. 225 */ 226 calibrate_delay(); 227 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 228 } 229 230 static void wait_for_master_cpu(int cpu) 231 { 232 /* 233 * Wait for release by control CPU before continuing with AP 234 * initialization. 235 */ 236 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 237 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 238 cpu_relax(); 239 } 240 241 /* 242 * Activate a secondary processor. 243 */ 244 static void notrace start_secondary(void *unused) 245 { 246 /* 247 * Don't put *anything* except direct CPU state initialization 248 * before cpu_init(), SMP booting is too fragile that we want to 249 * limit the things done here to the most necessary things. 250 */ 251 cr4_init(); 252 253 #ifdef CONFIG_X86_32 254 /* switch away from the initial page table */ 255 load_cr3(swapper_pg_dir); 256 __flush_tlb_all(); 257 #endif 258 cpu_init_exception_handling(); 259 260 /* 261 * Sync point with wait_cpu_initialized(). Sets AP in 262 * cpu_initialized_mask and then waits for the control CPU 263 * to release it. 264 */ 265 wait_for_master_cpu(raw_smp_processor_id()); 266 267 cpu_init(); 268 rcu_cpu_starting(raw_smp_processor_id()); 269 x86_cpuinit.early_percpu_clock_init(); 270 271 /* 272 * Sync point with wait_cpu_callin(). The AP doesn't wait here 273 * but just sets the bit to let the controlling CPU (BSP) know that 274 * it's got this far. 275 */ 276 smp_callin(); 277 278 /* 279 * Check TSC synchronization with the control CPU, which will do 280 * its part of this from wait_cpu_online(), making it an implicit 281 * synchronization point. 282 */ 283 check_tsc_sync_target(); 284 285 /* 286 * Calibrate the delay loop after the TSC synchronization check. 287 * This allows to skip the calibration when TSC is synchronized 288 * across sockets. 289 */ 290 ap_calibrate_delay(); 291 292 speculative_store_bypass_ht_init(); 293 294 /* 295 * Lock vector_lock, set CPU online and bring the vector 296 * allocator online. Online must be set with vector_lock held 297 * to prevent a concurrent irq setup/teardown from seeing a 298 * half valid vector space. 299 */ 300 lock_vector_lock(); 301 /* Sync point with do_wait_cpu_online() */ 302 set_cpu_online(smp_processor_id(), true); 303 lapic_online(); 304 unlock_vector_lock(); 305 cpu_set_state_online(smp_processor_id()); 306 x86_platform.nmi_init(); 307 308 /* enable local interrupts */ 309 local_irq_enable(); 310 311 x86_cpuinit.setup_percpu_clockev(); 312 313 wmb(); 314 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 315 } 316 317 /** 318 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 319 * @cpu: CPU to check 320 */ 321 bool topology_is_primary_thread(unsigned int cpu) 322 { 323 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 324 } 325 326 /** 327 * topology_smt_supported - Check whether SMT is supported by the CPUs 328 */ 329 bool topology_smt_supported(void) 330 { 331 return smp_num_siblings > 1; 332 } 333 334 /** 335 * topology_phys_to_logical_pkg - Map a physical package id to a logical 336 * @phys_pkg: The physical package id to map 337 * 338 * Returns logical package id or -1 if not found 339 */ 340 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 341 { 342 int cpu; 343 344 for_each_possible_cpu(cpu) { 345 struct cpuinfo_x86 *c = &cpu_data(cpu); 346 347 if (c->initialized && c->phys_proc_id == phys_pkg) 348 return c->logical_proc_id; 349 } 350 return -1; 351 } 352 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 353 354 /** 355 * topology_phys_to_logical_die - Map a physical die id to logical 356 * @die_id: The physical die id to map 357 * @cur_cpu: The CPU for which the mapping is done 358 * 359 * Returns logical die id or -1 if not found 360 */ 361 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 362 { 363 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 364 365 for_each_possible_cpu(cpu) { 366 struct cpuinfo_x86 *c = &cpu_data(cpu); 367 368 if (c->initialized && c->cpu_die_id == die_id && 369 c->phys_proc_id == proc_id) 370 return c->logical_die_id; 371 } 372 return -1; 373 } 374 375 /** 376 * topology_update_package_map - Update the physical to logical package map 377 * @pkg: The physical package id as retrieved via CPUID 378 * @cpu: The cpu for which this is updated 379 */ 380 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 381 { 382 int new; 383 384 /* Already available somewhere? */ 385 new = topology_phys_to_logical_pkg(pkg); 386 if (new >= 0) 387 goto found; 388 389 new = logical_packages++; 390 if (new != pkg) { 391 pr_info("CPU %u Converting physical %u to logical package %u\n", 392 cpu, pkg, new); 393 } 394 found: 395 cpu_data(cpu).logical_proc_id = new; 396 return 0; 397 } 398 /** 399 * topology_update_die_map - Update the physical to logical die map 400 * @die: The die id as retrieved via CPUID 401 * @cpu: The cpu for which this is updated 402 */ 403 int topology_update_die_map(unsigned int die, unsigned int cpu) 404 { 405 int new; 406 407 /* Already available somewhere? */ 408 new = topology_phys_to_logical_die(die, cpu); 409 if (new >= 0) 410 goto found; 411 412 new = logical_die++; 413 if (new != die) { 414 pr_info("CPU %u Converting physical %u to logical die %u\n", 415 cpu, die, new); 416 } 417 found: 418 cpu_data(cpu).logical_die_id = new; 419 return 0; 420 } 421 422 void __init smp_store_boot_cpu_info(void) 423 { 424 int id = 0; /* CPU 0 */ 425 struct cpuinfo_x86 *c = &cpu_data(id); 426 427 *c = boot_cpu_data; 428 c->cpu_index = id; 429 topology_update_package_map(c->phys_proc_id, id); 430 topology_update_die_map(c->cpu_die_id, id); 431 c->initialized = true; 432 } 433 434 /* 435 * The bootstrap kernel entry code has set these up. Save them for 436 * a given CPU 437 */ 438 void smp_store_cpu_info(int id) 439 { 440 struct cpuinfo_x86 *c = &cpu_data(id); 441 442 /* Copy boot_cpu_data only on the first bringup */ 443 if (!c->initialized) 444 *c = boot_cpu_data; 445 c->cpu_index = id; 446 /* 447 * During boot time, CPU0 has this setup already. Save the info when 448 * bringing up an AP. 449 */ 450 identify_secondary_cpu(c); 451 c->initialized = true; 452 } 453 454 static bool 455 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 456 { 457 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 458 459 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 460 } 461 462 static bool 463 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 464 { 465 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 466 467 return !WARN_ONCE(!topology_same_node(c, o), 468 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 469 "[node: %d != %d]. Ignoring dependency.\n", 470 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 471 } 472 473 #define link_mask(mfunc, c1, c2) \ 474 do { \ 475 cpumask_set_cpu((c1), mfunc(c2)); \ 476 cpumask_set_cpu((c2), mfunc(c1)); \ 477 } while (0) 478 479 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 480 { 481 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 482 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 483 484 if (c->phys_proc_id == o->phys_proc_id && 485 c->cpu_die_id == o->cpu_die_id && 486 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 487 if (c->cpu_core_id == o->cpu_core_id) 488 return topology_sane(c, o, "smt"); 489 490 if ((c->cu_id != 0xff) && 491 (o->cu_id != 0xff) && 492 (c->cu_id == o->cu_id)) 493 return topology_sane(c, o, "smt"); 494 } 495 496 } else if (c->phys_proc_id == o->phys_proc_id && 497 c->cpu_die_id == o->cpu_die_id && 498 c->cpu_core_id == o->cpu_core_id) { 499 return topology_sane(c, o, "smt"); 500 } 501 502 return false; 503 } 504 505 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 506 { 507 if (c->phys_proc_id == o->phys_proc_id && 508 c->cpu_die_id == o->cpu_die_id) 509 return true; 510 return false; 511 } 512 513 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 514 { 515 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 516 517 /* If the arch didn't set up l2c_id, fall back to SMT */ 518 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 519 return match_smt(c, o); 520 521 /* Do not match if L2 cache id does not match: */ 522 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 523 return false; 524 525 return topology_sane(c, o, "l2c"); 526 } 527 528 /* 529 * Unlike the other levels, we do not enforce keeping a 530 * multicore group inside a NUMA node. If this happens, we will 531 * discard the MC level of the topology later. 532 */ 533 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 534 { 535 if (c->phys_proc_id == o->phys_proc_id) 536 return true; 537 return false; 538 } 539 540 /* 541 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 542 * 543 * Any Intel CPU that has multiple nodes per package and does not 544 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 545 * 546 * When in SNC mode, these CPUs enumerate an LLC that is shared 547 * by multiple NUMA nodes. The LLC is shared for off-package data 548 * access but private to the NUMA node (half of the package) for 549 * on-package access. CPUID (the source of the information about 550 * the LLC) can only enumerate the cache as shared or unshared, 551 * but not this particular configuration. 552 */ 553 554 static const struct x86_cpu_id intel_cod_cpu[] = { 555 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 556 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 557 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 558 {} 559 }; 560 561 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 562 { 563 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 564 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 565 bool intel_snc = id && id->driver_data; 566 567 /* Do not match if we do not have a valid APICID for cpu: */ 568 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 569 return false; 570 571 /* Do not match if LLC id does not match: */ 572 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 573 return false; 574 575 /* 576 * Allow the SNC topology without warning. Return of false 577 * means 'c' does not share the LLC of 'o'. This will be 578 * reflected to userspace. 579 */ 580 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 581 return false; 582 583 return topology_sane(c, o, "llc"); 584 } 585 586 587 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 588 static inline int x86_sched_itmt_flags(void) 589 { 590 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 591 } 592 593 #ifdef CONFIG_SCHED_MC 594 static int x86_core_flags(void) 595 { 596 return cpu_core_flags() | x86_sched_itmt_flags(); 597 } 598 #endif 599 #ifdef CONFIG_SCHED_SMT 600 static int x86_smt_flags(void) 601 { 602 return cpu_smt_flags() | x86_sched_itmt_flags(); 603 } 604 #endif 605 #ifdef CONFIG_SCHED_CLUSTER 606 static int x86_cluster_flags(void) 607 { 608 return cpu_cluster_flags() | x86_sched_itmt_flags(); 609 } 610 #endif 611 #endif 612 613 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 614 #ifdef CONFIG_SCHED_SMT 615 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 616 #endif 617 #ifdef CONFIG_SCHED_CLUSTER 618 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 619 #endif 620 #ifdef CONFIG_SCHED_MC 621 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 622 #endif 623 { NULL, }, 624 }; 625 626 static struct sched_domain_topology_level x86_hybrid_topology[] = { 627 #ifdef CONFIG_SCHED_SMT 628 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 629 #endif 630 #ifdef CONFIG_SCHED_MC 631 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 632 #endif 633 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 634 { NULL, }, 635 }; 636 637 static struct sched_domain_topology_level x86_topology[] = { 638 #ifdef CONFIG_SCHED_SMT 639 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 640 #endif 641 #ifdef CONFIG_SCHED_CLUSTER 642 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 643 #endif 644 #ifdef CONFIG_SCHED_MC 645 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 646 #endif 647 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 648 { NULL, }, 649 }; 650 651 /* 652 * Set if a package/die has multiple NUMA nodes inside. 653 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 654 * Sub-NUMA Clustering have this. 655 */ 656 static bool x86_has_numa_in_package; 657 658 void set_cpu_sibling_map(int cpu) 659 { 660 bool has_smt = smp_num_siblings > 1; 661 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 662 struct cpuinfo_x86 *c = &cpu_data(cpu); 663 struct cpuinfo_x86 *o; 664 int i, threads; 665 666 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 667 668 if (!has_mp) { 669 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 670 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 671 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 672 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 673 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 674 c->booted_cores = 1; 675 return; 676 } 677 678 for_each_cpu(i, cpu_sibling_setup_mask) { 679 o = &cpu_data(i); 680 681 if (match_pkg(c, o) && !topology_same_node(c, o)) 682 x86_has_numa_in_package = true; 683 684 if ((i == cpu) || (has_smt && match_smt(c, o))) 685 link_mask(topology_sibling_cpumask, cpu, i); 686 687 if ((i == cpu) || (has_mp && match_llc(c, o))) 688 link_mask(cpu_llc_shared_mask, cpu, i); 689 690 if ((i == cpu) || (has_mp && match_l2c(c, o))) 691 link_mask(cpu_l2c_shared_mask, cpu, i); 692 693 if ((i == cpu) || (has_mp && match_die(c, o))) 694 link_mask(topology_die_cpumask, cpu, i); 695 } 696 697 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 698 if (threads > __max_smt_threads) 699 __max_smt_threads = threads; 700 701 for_each_cpu(i, topology_sibling_cpumask(cpu)) 702 cpu_data(i).smt_active = threads > 1; 703 704 /* 705 * This needs a separate iteration over the cpus because we rely on all 706 * topology_sibling_cpumask links to be set-up. 707 */ 708 for_each_cpu(i, cpu_sibling_setup_mask) { 709 o = &cpu_data(i); 710 711 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 712 link_mask(topology_core_cpumask, cpu, i); 713 714 /* 715 * Does this new cpu bringup a new core? 716 */ 717 if (threads == 1) { 718 /* 719 * for each core in package, increment 720 * the booted_cores for this new cpu 721 */ 722 if (cpumask_first( 723 topology_sibling_cpumask(i)) == i) 724 c->booted_cores++; 725 /* 726 * increment the core count for all 727 * the other cpus in this package 728 */ 729 if (i != cpu) 730 cpu_data(i).booted_cores++; 731 } else if (i != cpu && !c->booted_cores) 732 c->booted_cores = cpu_data(i).booted_cores; 733 } 734 } 735 } 736 737 /* maps the cpu to the sched domain representing multi-core */ 738 const struct cpumask *cpu_coregroup_mask(int cpu) 739 { 740 return cpu_llc_shared_mask(cpu); 741 } 742 743 const struct cpumask *cpu_clustergroup_mask(int cpu) 744 { 745 return cpu_l2c_shared_mask(cpu); 746 } 747 748 static void impress_friends(void) 749 { 750 int cpu; 751 unsigned long bogosum = 0; 752 /* 753 * Allow the user to impress friends. 754 */ 755 pr_debug("Before bogomips\n"); 756 for_each_possible_cpu(cpu) 757 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 758 bogosum += cpu_data(cpu).loops_per_jiffy; 759 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 760 num_online_cpus(), 761 bogosum/(500000/HZ), 762 (bogosum/(5000/HZ))%100); 763 764 pr_debug("Before bogocount - setting activated=1\n"); 765 } 766 767 void __inquire_remote_apic(int apicid) 768 { 769 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 770 const char * const names[] = { "ID", "VERSION", "SPIV" }; 771 int timeout; 772 u32 status; 773 774 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 775 776 for (i = 0; i < ARRAY_SIZE(regs); i++) { 777 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 778 779 /* 780 * Wait for idle. 781 */ 782 status = safe_apic_wait_icr_idle(); 783 if (status) 784 pr_cont("a previous APIC delivery may have failed\n"); 785 786 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 787 788 timeout = 0; 789 do { 790 udelay(100); 791 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 792 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 793 794 switch (status) { 795 case APIC_ICR_RR_VALID: 796 status = apic_read(APIC_RRR); 797 pr_cont("%08x\n", status); 798 break; 799 default: 800 pr_cont("failed\n"); 801 } 802 } 803 } 804 805 /* 806 * The Multiprocessor Specification 1.4 (1997) example code suggests 807 * that there should be a 10ms delay between the BSP asserting INIT 808 * and de-asserting INIT, when starting a remote processor. 809 * But that slows boot and resume on modern processors, which include 810 * many cores and don't require that delay. 811 * 812 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 813 * Modern processor families are quirked to remove the delay entirely. 814 */ 815 #define UDELAY_10MS_DEFAULT 10000 816 817 static unsigned int init_udelay = UINT_MAX; 818 819 static int __init cpu_init_udelay(char *str) 820 { 821 get_option(&str, &init_udelay); 822 823 return 0; 824 } 825 early_param("cpu_init_udelay", cpu_init_udelay); 826 827 static void __init smp_quirk_init_udelay(void) 828 { 829 /* if cmdline changed it from default, leave it alone */ 830 if (init_udelay != UINT_MAX) 831 return; 832 833 /* if modern processor, use no delay */ 834 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 835 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 836 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 837 init_udelay = 0; 838 return; 839 } 840 /* else, use legacy delay */ 841 init_udelay = UDELAY_10MS_DEFAULT; 842 } 843 844 /* 845 * Wake up AP by INIT, INIT, STARTUP sequence. 846 */ 847 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 848 { 849 unsigned long send_status = 0, accept_status = 0; 850 int maxlvt, num_starts, j; 851 852 preempt_disable(); 853 maxlvt = lapic_get_maxlvt(); 854 855 /* 856 * Be paranoid about clearing APIC errors. 857 */ 858 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 859 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 860 apic_write(APIC_ESR, 0); 861 apic_read(APIC_ESR); 862 } 863 864 pr_debug("Asserting INIT\n"); 865 866 /* 867 * Turn INIT on target chip 868 */ 869 /* 870 * Send IPI 871 */ 872 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 873 phys_apicid); 874 875 pr_debug("Waiting for send to finish...\n"); 876 send_status = safe_apic_wait_icr_idle(); 877 878 udelay(init_udelay); 879 880 pr_debug("Deasserting INIT\n"); 881 882 /* Target chip */ 883 /* Send IPI */ 884 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 885 886 pr_debug("Waiting for send to finish...\n"); 887 send_status = safe_apic_wait_icr_idle(); 888 889 mb(); 890 891 /* 892 * Should we send STARTUP IPIs ? 893 * 894 * Determine this based on the APIC version. 895 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 896 */ 897 if (APIC_INTEGRATED(boot_cpu_apic_version)) 898 num_starts = 2; 899 else 900 num_starts = 0; 901 902 /* 903 * Run STARTUP IPI loop. 904 */ 905 pr_debug("#startup loops: %d\n", num_starts); 906 907 for (j = 1; j <= num_starts; j++) { 908 pr_debug("Sending STARTUP #%d\n", j); 909 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 910 apic_write(APIC_ESR, 0); 911 apic_read(APIC_ESR); 912 pr_debug("After apic_write\n"); 913 914 /* 915 * STARTUP IPI 916 */ 917 918 /* Target chip */ 919 /* Boot on the stack */ 920 /* Kick the second */ 921 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 922 phys_apicid); 923 924 /* 925 * Give the other CPU some time to accept the IPI. 926 */ 927 if (init_udelay == 0) 928 udelay(10); 929 else 930 udelay(300); 931 932 pr_debug("Startup point 1\n"); 933 934 pr_debug("Waiting for send to finish...\n"); 935 send_status = safe_apic_wait_icr_idle(); 936 937 /* 938 * Give the other CPU some time to accept the IPI. 939 */ 940 if (init_udelay == 0) 941 udelay(10); 942 else 943 udelay(200); 944 945 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 946 apic_write(APIC_ESR, 0); 947 accept_status = (apic_read(APIC_ESR) & 0xEF); 948 if (send_status || accept_status) 949 break; 950 } 951 pr_debug("After Startup\n"); 952 953 if (send_status) 954 pr_err("APIC never delivered???\n"); 955 if (accept_status) 956 pr_err("APIC delivery error (%lx)\n", accept_status); 957 958 preempt_enable(); 959 return (send_status | accept_status); 960 } 961 962 /* reduce the number of lines printed when booting a large cpu count system */ 963 static void announce_cpu(int cpu, int apicid) 964 { 965 static int current_node = NUMA_NO_NODE; 966 int node = early_cpu_to_node(cpu); 967 static int width, node_width; 968 969 if (!width) 970 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 971 972 if (!node_width) 973 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 974 975 if (cpu == 1) 976 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 977 978 if (system_state < SYSTEM_RUNNING) { 979 if (node != current_node) { 980 if (current_node > (-1)) 981 pr_cont("\n"); 982 current_node = node; 983 984 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 985 node_width - num_digits(node), " ", node); 986 } 987 988 /* Add padding for the BSP */ 989 if (cpu == 1) 990 pr_cont("%*s", width + 1, " "); 991 992 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 993 994 } else 995 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 996 node, cpu, apicid); 997 } 998 999 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1000 { 1001 int ret; 1002 1003 /* Just in case we booted with a single CPU. */ 1004 alternatives_enable_smp(); 1005 1006 per_cpu(pcpu_hot.current_task, cpu) = idle; 1007 cpu_init_stack_canary(cpu, idle); 1008 1009 /* Initialize the interrupt stack(s) */ 1010 ret = irq_init_percpu_irqstack(cpu); 1011 if (ret) 1012 return ret; 1013 1014 #ifdef CONFIG_X86_32 1015 /* Stack for startup_32 can be just as for start_secondary onwards */ 1016 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1017 #endif 1018 return 0; 1019 } 1020 1021 /* 1022 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1023 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1024 * Returns zero if startup was successfully sent, else error code from 1025 * ->wakeup_secondary_cpu. 1026 */ 1027 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 1028 { 1029 unsigned long start_ip = real_mode_header->trampoline_start; 1030 1031 #ifdef CONFIG_X86_64 1032 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1033 if (apic->wakeup_secondary_cpu_64) 1034 start_ip = real_mode_header->trampoline_start64; 1035 #endif 1036 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1037 initial_code = (unsigned long)start_secondary; 1038 1039 if (IS_ENABLED(CONFIG_X86_32)) { 1040 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1041 initial_stack = idle->thread.sp; 1042 } else { 1043 smpboot_control = cpu; 1044 } 1045 1046 /* Enable the espfix hack for this CPU */ 1047 init_espfix_ap(cpu); 1048 1049 /* So we see what's up */ 1050 announce_cpu(cpu, apicid); 1051 1052 /* 1053 * This grunge runs the startup process for 1054 * the targeted processor. 1055 */ 1056 if (x86_platform.legacy.warm_reset) { 1057 1058 pr_debug("Setting warm reset code and vector.\n"); 1059 1060 smpboot_setup_warm_reset_vector(start_ip); 1061 /* 1062 * Be paranoid about clearing APIC errors. 1063 */ 1064 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1065 apic_write(APIC_ESR, 0); 1066 apic_read(APIC_ESR); 1067 } 1068 } 1069 1070 /* 1071 * AP might wait on cpu_callout_mask in cpu_init() with 1072 * cpu_initialized_mask set if previous attempt to online 1073 * it timed-out. Clear cpu_initialized_mask so that after 1074 * INIT/SIPI it could start with a clean state. 1075 */ 1076 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1077 smp_mb(); 1078 1079 /* 1080 * Wake up a CPU in difference cases: 1081 * - Use a method from the APIC driver if one defined, with wakeup 1082 * straight to 64-bit mode preferred over wakeup to RM. 1083 * Otherwise, 1084 * - Use an INIT boot APIC message 1085 */ 1086 if (apic->wakeup_secondary_cpu_64) 1087 return apic->wakeup_secondary_cpu_64(apicid, start_ip); 1088 else if (apic->wakeup_secondary_cpu) 1089 return apic->wakeup_secondary_cpu(apicid, start_ip); 1090 1091 return wakeup_secondary_cpu_via_init(apicid, start_ip); 1092 } 1093 1094 static int wait_cpu_cpumask(unsigned int cpu, const struct cpumask *mask) 1095 { 1096 unsigned long timeout; 1097 1098 /* 1099 * Wait up to 10s for the CPU to report in. 1100 */ 1101 timeout = jiffies + 10*HZ; 1102 while (time_before(jiffies, timeout)) { 1103 if (cpumask_test_cpu(cpu, mask)) 1104 return 0; 1105 1106 schedule(); 1107 } 1108 return -1; 1109 } 1110 1111 /* 1112 * Bringup step two: Wait for the target AP to reach cpu_init_secondary() 1113 * and thus wait_for_master_cpu(), then set cpu_callout_mask to allow it 1114 * to proceed. The AP will then proceed past setting its 'callin' bit 1115 * and end up waiting in check_tsc_sync_target() until we reach 1116 * do_wait_cpu_online() to tend to it. 1117 */ 1118 static int wait_cpu_initialized(unsigned int cpu) 1119 { 1120 /* 1121 * Wait for first sign of life from AP. 1122 */ 1123 if (wait_cpu_cpumask(cpu, cpu_initialized_mask)) 1124 return -1; 1125 1126 cpumask_set_cpu(cpu, cpu_callout_mask); 1127 return 0; 1128 } 1129 1130 /* 1131 * Bringup step three: Wait for the target AP to reach smp_callin(). 1132 * The AP is not waiting for us here so we don't need to parallelise 1133 * this step. Not entirely clear why we care about this, since we just 1134 * proceed directly to TSC synchronization which is the next sync 1135 * point with the AP anyway. 1136 */ 1137 static void wait_cpu_callin(unsigned int cpu) 1138 { 1139 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) 1140 schedule(); 1141 } 1142 1143 /* 1144 * Bringup step four: Synchronize the TSC and wait for the target AP 1145 * to reach set_cpu_online() in start_secondary(). 1146 */ 1147 static void wait_cpu_online(unsigned int cpu) 1148 { 1149 unsigned long flags; 1150 1151 /* 1152 * Check TSC synchronization with the AP (keep irqs disabled 1153 * while doing so): 1154 */ 1155 local_irq_save(flags); 1156 check_tsc_sync_source(cpu); 1157 local_irq_restore(flags); 1158 1159 /* 1160 * Wait for the AP to mark itself online, so the core caller 1161 * can drop sparse_irq_lock. 1162 */ 1163 while (!cpu_online(cpu)) 1164 schedule(); 1165 } 1166 1167 static int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1168 { 1169 int apicid = apic->cpu_present_to_apicid(cpu); 1170 int err; 1171 1172 lockdep_assert_irqs_enabled(); 1173 1174 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1175 1176 if (apicid == BAD_APICID || 1177 !physid_isset(apicid, phys_cpu_present_map) || 1178 !apic->apic_id_valid(apicid)) { 1179 pr_err("%s: bad cpu %d\n", __func__, cpu); 1180 return -EINVAL; 1181 } 1182 1183 /* 1184 * Already booted CPU? 1185 */ 1186 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1187 pr_debug("do_boot_cpu %d Already started\n", cpu); 1188 return -ENOSYS; 1189 } 1190 1191 /* 1192 * Save current MTRR state in case it was changed since early boot 1193 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1194 */ 1195 mtrr_save_state(); 1196 1197 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1198 err = cpu_check_up_prepare(cpu); 1199 if (err && err != -EBUSY) 1200 return err; 1201 1202 /* the FPU context is blank, nobody can own it */ 1203 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1204 1205 err = common_cpu_up(cpu, tidle); 1206 if (err) 1207 return err; 1208 1209 err = do_boot_cpu(apicid, cpu, tidle); 1210 if (err) 1211 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1212 1213 return err; 1214 } 1215 1216 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1217 { 1218 int ret; 1219 1220 ret = native_kick_ap(cpu, tidle); 1221 if (ret) 1222 goto out; 1223 1224 ret = wait_cpu_initialized(cpu); 1225 if (ret) 1226 goto out; 1227 1228 wait_cpu_callin(cpu); 1229 wait_cpu_online(cpu); 1230 1231 out: 1232 /* Cleanup possible dangling ends... */ 1233 if (x86_platform.legacy.warm_reset) 1234 smpboot_restore_warm_reset_vector(); 1235 1236 return ret; 1237 } 1238 1239 /** 1240 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1241 */ 1242 void __init arch_disable_smp_support(void) 1243 { 1244 disable_ioapic_support(); 1245 } 1246 1247 /* 1248 * Fall back to non SMP mode after errors. 1249 * 1250 * RED-PEN audit/test this more. I bet there is more state messed up here. 1251 */ 1252 static __init void disable_smp(void) 1253 { 1254 pr_info("SMP disabled\n"); 1255 1256 disable_ioapic_support(); 1257 1258 init_cpu_present(cpumask_of(0)); 1259 init_cpu_possible(cpumask_of(0)); 1260 1261 if (smp_found_config) 1262 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1263 else 1264 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1265 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1266 cpumask_set_cpu(0, topology_core_cpumask(0)); 1267 cpumask_set_cpu(0, topology_die_cpumask(0)); 1268 } 1269 1270 /* 1271 * Various sanity checks. 1272 */ 1273 static void __init smp_sanity_check(void) 1274 { 1275 preempt_disable(); 1276 1277 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1278 if (def_to_bigsmp && nr_cpu_ids > 8) { 1279 unsigned int cpu; 1280 unsigned nr; 1281 1282 pr_warn("More than 8 CPUs detected - skipping them\n" 1283 "Use CONFIG_X86_BIGSMP\n"); 1284 1285 nr = 0; 1286 for_each_present_cpu(cpu) { 1287 if (nr >= 8) 1288 set_cpu_present(cpu, false); 1289 nr++; 1290 } 1291 1292 nr = 0; 1293 for_each_possible_cpu(cpu) { 1294 if (nr >= 8) 1295 set_cpu_possible(cpu, false); 1296 nr++; 1297 } 1298 1299 set_nr_cpu_ids(8); 1300 } 1301 #endif 1302 1303 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1304 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1305 hard_smp_processor_id()); 1306 1307 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1308 } 1309 1310 /* 1311 * Should not be necessary because the MP table should list the boot 1312 * CPU too, but we do it for the sake of robustness anyway. 1313 */ 1314 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1315 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1316 boot_cpu_physical_apicid); 1317 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1318 } 1319 preempt_enable(); 1320 } 1321 1322 static void __init smp_cpu_index_default(void) 1323 { 1324 int i; 1325 struct cpuinfo_x86 *c; 1326 1327 for_each_possible_cpu(i) { 1328 c = &cpu_data(i); 1329 /* mark all to hotplug */ 1330 c->cpu_index = nr_cpu_ids; 1331 } 1332 } 1333 1334 void __init smp_prepare_cpus_common(void) 1335 { 1336 unsigned int i; 1337 1338 smp_cpu_index_default(); 1339 1340 /* 1341 * Setup boot CPU information 1342 */ 1343 smp_store_boot_cpu_info(); /* Final full version of the data */ 1344 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1345 mb(); 1346 1347 for_each_possible_cpu(i) { 1348 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1349 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1350 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1351 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1352 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1353 } 1354 1355 /* 1356 * Set 'default' x86 topology, this matches default_topology() in that 1357 * it has NUMA nodes as a topology level. See also 1358 * native_smp_cpus_done(). 1359 * 1360 * Must be done before set_cpus_sibling_map() is ran. 1361 */ 1362 set_sched_topology(x86_topology); 1363 1364 set_cpu_sibling_map(0); 1365 } 1366 1367 /* 1368 * Prepare for SMP bootup. 1369 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1370 * for common interface support. 1371 */ 1372 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1373 { 1374 smp_prepare_cpus_common(); 1375 1376 smp_sanity_check(); 1377 1378 switch (apic_intr_mode) { 1379 case APIC_PIC: 1380 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1381 disable_smp(); 1382 return; 1383 case APIC_SYMMETRIC_IO_NO_ROUTING: 1384 disable_smp(); 1385 /* Setup local timer */ 1386 x86_init.timers.setup_percpu_clockev(); 1387 return; 1388 case APIC_VIRTUAL_WIRE: 1389 case APIC_SYMMETRIC_IO: 1390 break; 1391 } 1392 1393 /* Setup local timer */ 1394 x86_init.timers.setup_percpu_clockev(); 1395 1396 pr_info("CPU0: "); 1397 print_cpu_info(&cpu_data(0)); 1398 1399 uv_system_init(); 1400 1401 smp_quirk_init_udelay(); 1402 1403 speculative_store_bypass_ht_init(); 1404 1405 snp_set_wakeup_secondary_cpu(); 1406 } 1407 1408 void arch_thaw_secondary_cpus_begin(void) 1409 { 1410 set_cache_aps_delayed_init(true); 1411 } 1412 1413 void arch_thaw_secondary_cpus_end(void) 1414 { 1415 cache_aps_init(); 1416 } 1417 1418 /* 1419 * Early setup to make printk work. 1420 */ 1421 void __init native_smp_prepare_boot_cpu(void) 1422 { 1423 int me = smp_processor_id(); 1424 1425 /* SMP handles this from setup_per_cpu_areas() */ 1426 if (!IS_ENABLED(CONFIG_SMP)) 1427 switch_gdt_and_percpu_base(me); 1428 1429 /* already set me in cpu_online_mask in boot_cpu_init() */ 1430 cpumask_set_cpu(me, cpu_callout_mask); 1431 cpu_set_state_online(me); 1432 native_pv_lock_init(); 1433 } 1434 1435 void __init calculate_max_logical_packages(void) 1436 { 1437 int ncpus; 1438 1439 /* 1440 * Today neither Intel nor AMD support heterogeneous systems so 1441 * extrapolate the boot cpu's data to all packages. 1442 */ 1443 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1444 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1445 pr_info("Max logical packages: %u\n", __max_logical_packages); 1446 } 1447 1448 void __init native_smp_cpus_done(unsigned int max_cpus) 1449 { 1450 pr_debug("Boot done\n"); 1451 1452 calculate_max_logical_packages(); 1453 1454 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1455 if (x86_has_numa_in_package) 1456 set_sched_topology(x86_numa_in_package_topology); 1457 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1458 set_sched_topology(x86_hybrid_topology); 1459 1460 nmi_selftest(); 1461 impress_friends(); 1462 cache_aps_init(); 1463 } 1464 1465 static int __initdata setup_possible_cpus = -1; 1466 static int __init _setup_possible_cpus(char *str) 1467 { 1468 get_option(&str, &setup_possible_cpus); 1469 return 0; 1470 } 1471 early_param("possible_cpus", _setup_possible_cpus); 1472 1473 1474 /* 1475 * cpu_possible_mask should be static, it cannot change as cpu's 1476 * are onlined, or offlined. The reason is per-cpu data-structures 1477 * are allocated by some modules at init time, and don't expect to 1478 * do this dynamically on cpu arrival/departure. 1479 * cpu_present_mask on the other hand can change dynamically. 1480 * In case when cpu_hotplug is not compiled, then we resort to current 1481 * behaviour, which is cpu_possible == cpu_present. 1482 * - Ashok Raj 1483 * 1484 * Three ways to find out the number of additional hotplug CPUs: 1485 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1486 * - The user can overwrite it with possible_cpus=NUM 1487 * - Otherwise don't reserve additional CPUs. 1488 * We do this because additional CPUs waste a lot of memory. 1489 * -AK 1490 */ 1491 __init void prefill_possible_map(void) 1492 { 1493 int i, possible; 1494 1495 /* No boot processor was found in mptable or ACPI MADT */ 1496 if (!num_processors) { 1497 if (boot_cpu_has(X86_FEATURE_APIC)) { 1498 int apicid = boot_cpu_physical_apicid; 1499 int cpu = hard_smp_processor_id(); 1500 1501 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1502 1503 /* Make sure boot cpu is enumerated */ 1504 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1505 apic->apic_id_valid(apicid)) 1506 generic_processor_info(apicid, boot_cpu_apic_version); 1507 } 1508 1509 if (!num_processors) 1510 num_processors = 1; 1511 } 1512 1513 i = setup_max_cpus ?: 1; 1514 if (setup_possible_cpus == -1) { 1515 possible = num_processors; 1516 #ifdef CONFIG_HOTPLUG_CPU 1517 if (setup_max_cpus) 1518 possible += disabled_cpus; 1519 #else 1520 if (possible > i) 1521 possible = i; 1522 #endif 1523 } else 1524 possible = setup_possible_cpus; 1525 1526 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1527 1528 /* nr_cpu_ids could be reduced via nr_cpus= */ 1529 if (possible > nr_cpu_ids) { 1530 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1531 possible, nr_cpu_ids); 1532 possible = nr_cpu_ids; 1533 } 1534 1535 #ifdef CONFIG_HOTPLUG_CPU 1536 if (!setup_max_cpus) 1537 #endif 1538 if (possible > i) { 1539 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1540 possible, setup_max_cpus); 1541 possible = i; 1542 } 1543 1544 set_nr_cpu_ids(possible); 1545 1546 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1547 possible, max_t(int, possible - num_processors, 0)); 1548 1549 reset_cpu_possible_mask(); 1550 1551 for (i = 0; i < possible; i++) 1552 set_cpu_possible(i, true); 1553 } 1554 1555 /* correctly size the local cpu masks */ 1556 void __init setup_cpu_local_masks(void) 1557 { 1558 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 1559 alloc_bootmem_cpumask_var(&cpu_callin_mask); 1560 alloc_bootmem_cpumask_var(&cpu_callout_mask); 1561 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1562 } 1563 1564 #ifdef CONFIG_HOTPLUG_CPU 1565 1566 /* Recompute SMT state for all CPUs on offline */ 1567 static void recompute_smt_state(void) 1568 { 1569 int max_threads, cpu; 1570 1571 max_threads = 0; 1572 for_each_online_cpu (cpu) { 1573 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1574 1575 if (threads > max_threads) 1576 max_threads = threads; 1577 } 1578 __max_smt_threads = max_threads; 1579 } 1580 1581 static void remove_siblinginfo(int cpu) 1582 { 1583 int sibling; 1584 struct cpuinfo_x86 *c = &cpu_data(cpu); 1585 1586 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1587 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1588 /*/ 1589 * last thread sibling in this cpu core going down 1590 */ 1591 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1592 cpu_data(sibling).booted_cores--; 1593 } 1594 1595 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1596 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1597 1598 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1599 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1600 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1601 cpu_data(sibling).smt_active = false; 1602 } 1603 1604 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1605 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1606 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1607 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1608 cpumask_clear(cpu_llc_shared_mask(cpu)); 1609 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1610 cpumask_clear(topology_sibling_cpumask(cpu)); 1611 cpumask_clear(topology_core_cpumask(cpu)); 1612 cpumask_clear(topology_die_cpumask(cpu)); 1613 c->cpu_core_id = 0; 1614 c->booted_cores = 0; 1615 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1616 recompute_smt_state(); 1617 } 1618 1619 static void remove_cpu_from_maps(int cpu) 1620 { 1621 set_cpu_online(cpu, false); 1622 cpumask_clear_cpu(cpu, cpu_callout_mask); 1623 cpumask_clear_cpu(cpu, cpu_callin_mask); 1624 /* was set by cpu_init() */ 1625 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1626 numa_remove_cpu(cpu); 1627 } 1628 1629 void cpu_disable_common(void) 1630 { 1631 int cpu = smp_processor_id(); 1632 1633 remove_siblinginfo(cpu); 1634 1635 /* It's now safe to remove this processor from the online map */ 1636 lock_vector_lock(); 1637 remove_cpu_from_maps(cpu); 1638 unlock_vector_lock(); 1639 fixup_irqs(); 1640 lapic_offline(); 1641 } 1642 1643 int native_cpu_disable(void) 1644 { 1645 int ret; 1646 1647 ret = lapic_can_unplug_cpu(); 1648 if (ret) 1649 return ret; 1650 1651 cpu_disable_common(); 1652 1653 /* 1654 * Disable the local APIC. Otherwise IPI broadcasts will reach 1655 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1656 * messages. 1657 * 1658 * Disabling the APIC must happen after cpu_disable_common() 1659 * which invokes fixup_irqs(). 1660 * 1661 * Disabling the APIC preserves already set bits in IRR, but 1662 * an interrupt arriving after disabling the local APIC does not 1663 * set the corresponding IRR bit. 1664 * 1665 * fixup_irqs() scans IRR for set bits so it can raise a not 1666 * yet handled interrupt on the new destination CPU via an IPI 1667 * but obviously it can't do so for IRR bits which are not set. 1668 * IOW, interrupts arriving after disabling the local APIC will 1669 * be lost. 1670 */ 1671 apic_soft_disable(); 1672 1673 return 0; 1674 } 1675 1676 int common_cpu_die(unsigned int cpu) 1677 { 1678 int ret = 0; 1679 1680 /* We don't do anything here: idle task is faking death itself. */ 1681 1682 /* They ack this in play_dead() by setting CPU_DEAD */ 1683 if (cpu_wait_death(cpu, 5)) { 1684 if (system_state == SYSTEM_RUNNING) 1685 pr_info("CPU %u is now offline\n", cpu); 1686 } else { 1687 pr_err("CPU %u didn't die...\n", cpu); 1688 ret = -1; 1689 } 1690 1691 return ret; 1692 } 1693 1694 void native_cpu_die(unsigned int cpu) 1695 { 1696 common_cpu_die(cpu); 1697 } 1698 1699 void play_dead_common(void) 1700 { 1701 idle_task_exit(); 1702 1703 /* Ack it */ 1704 (void)cpu_report_death(); 1705 1706 /* 1707 * With physical CPU hotplug, we should halt the cpu 1708 */ 1709 local_irq_disable(); 1710 } 1711 1712 /* 1713 * We need to flush the caches before going to sleep, lest we have 1714 * dirty data in our caches when we come back up. 1715 */ 1716 static inline void mwait_play_dead(void) 1717 { 1718 unsigned int eax, ebx, ecx, edx; 1719 unsigned int highest_cstate = 0; 1720 unsigned int highest_subcstate = 0; 1721 void *mwait_ptr; 1722 int i; 1723 1724 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1725 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1726 return; 1727 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1728 return; 1729 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1730 return; 1731 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1732 return; 1733 1734 eax = CPUID_MWAIT_LEAF; 1735 ecx = 0; 1736 native_cpuid(&eax, &ebx, &ecx, &edx); 1737 1738 /* 1739 * eax will be 0 if EDX enumeration is not valid. 1740 * Initialized below to cstate, sub_cstate value when EDX is valid. 1741 */ 1742 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1743 eax = 0; 1744 } else { 1745 edx >>= MWAIT_SUBSTATE_SIZE; 1746 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1747 if (edx & MWAIT_SUBSTATE_MASK) { 1748 highest_cstate = i; 1749 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1750 } 1751 } 1752 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1753 (highest_subcstate - 1); 1754 } 1755 1756 /* 1757 * This should be a memory location in a cache line which is 1758 * unlikely to be touched by other processors. The actual 1759 * content is immaterial as it is not actually modified in any way. 1760 */ 1761 mwait_ptr = ¤t_thread_info()->flags; 1762 1763 wbinvd(); 1764 1765 while (1) { 1766 /* 1767 * The CLFLUSH is a workaround for erratum AAI65 for 1768 * the Xeon 7400 series. It's not clear it is actually 1769 * needed, but it should be harmless in either case. 1770 * The WBINVD is insufficient due to the spurious-wakeup 1771 * case where we return around the loop. 1772 */ 1773 mb(); 1774 clflush(mwait_ptr); 1775 mb(); 1776 __monitor(mwait_ptr, 0, 0); 1777 mb(); 1778 __mwait(eax, 0); 1779 } 1780 } 1781 1782 void __noreturn hlt_play_dead(void) 1783 { 1784 if (__this_cpu_read(cpu_info.x86) >= 4) 1785 wbinvd(); 1786 1787 while (1) 1788 native_halt(); 1789 } 1790 1791 void native_play_dead(void) 1792 { 1793 play_dead_common(); 1794 tboot_shutdown(TB_SHUTDOWN_WFS); 1795 1796 mwait_play_dead(); 1797 if (cpuidle_play_dead()) 1798 hlt_play_dead(); 1799 } 1800 1801 #else /* ... !CONFIG_HOTPLUG_CPU */ 1802 int native_cpu_disable(void) 1803 { 1804 return -ENOSYS; 1805 } 1806 1807 void native_cpu_die(unsigned int cpu) 1808 { 1809 /* We said "no" in __cpu_disable */ 1810 BUG(); 1811 } 1812 1813 void native_play_dead(void) 1814 { 1815 BUG(); 1816 } 1817 1818 #endif 1819