1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/desc.h> 64 #include <asm/nmi.h> 65 #include <asm/irq.h> 66 #include <asm/realmode.h> 67 #include <asm/cpu.h> 68 #include <asm/numa.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/api.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 #include <asm/stackprotector.h> 86 #include <asm/sev.h> 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 /* representing HT, core, and die siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* All of these masks are initialized in setup_cpu_local_masks() */ 105 static cpumask_var_t cpu_initialized_mask; 106 static cpumask_var_t cpu_callout_mask; 107 /* Representing CPUs for which sibling maps can be computed */ 108 static cpumask_var_t cpu_sibling_setup_mask; 109 110 /* Logical package management. We might want to allocate that dynamically */ 111 unsigned int __max_logical_packages __read_mostly; 112 EXPORT_SYMBOL(__max_logical_packages); 113 static unsigned int logical_packages __read_mostly; 114 static unsigned int logical_die __read_mostly; 115 116 /* Maximum number of SMT threads on any online core */ 117 int __read_mostly __max_smt_threads = 1; 118 119 /* Flag to indicate if a complete sched domain rebuild is required */ 120 bool x86_topology_update; 121 122 int arch_update_cpu_topology(void) 123 { 124 int retval = x86_topology_update; 125 126 x86_topology_update = false; 127 return retval; 128 } 129 130 131 static unsigned int smpboot_warm_reset_vector_count; 132 133 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 134 { 135 unsigned long flags; 136 137 spin_lock_irqsave(&rtc_lock, flags); 138 if (!smpboot_warm_reset_vector_count++) { 139 CMOS_WRITE(0xa, 0xf); 140 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 141 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 142 } 143 spin_unlock_irqrestore(&rtc_lock, flags); 144 } 145 146 static inline void smpboot_restore_warm_reset_vector(void) 147 { 148 unsigned long flags; 149 150 /* 151 * Paranoid: Set warm reset code and vector here back 152 * to default values. 153 */ 154 spin_lock_irqsave(&rtc_lock, flags); 155 if (!--smpboot_warm_reset_vector_count) { 156 CMOS_WRITE(0, 0xf); 157 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 158 } 159 spin_unlock_irqrestore(&rtc_lock, flags); 160 161 } 162 163 /* Run the next set of setup steps for the upcoming CPU */ 164 static void ap_starting(void) 165 { 166 int cpuid = smp_processor_id(); 167 168 /* 169 * If woken up by an INIT in an 82489DX configuration 170 * cpu_callout_mask guarantees the CPU does not reach this point 171 * before an INIT_deassert IPI reaches the local APIC, so it is now 172 * safe to touch the local APIC. 173 * 174 * Set up this CPU, first the APIC, which is probably redundant on 175 * most boards. 176 */ 177 apic_ap_setup(); 178 179 /* Save the processor parameters. */ 180 smp_store_cpu_info(cpuid); 181 182 /* 183 * The topology information must be up to date before 184 * notify_cpu_starting(). 185 */ 186 set_cpu_sibling_map(cpuid); 187 188 ap_init_aperfmperf(); 189 190 pr_debug("Stack at about %p\n", &cpuid); 191 192 wmb(); 193 194 /* 195 * This runs the AP through all the cpuhp states to its target 196 * state CPUHP_ONLINE. 197 */ 198 notify_cpu_starting(cpuid); 199 } 200 201 static void ap_calibrate_delay(void) 202 { 203 /* 204 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 205 * smp_store_cpu_info() stored a value that is close but not as 206 * accurate as the value just calculated. 207 * 208 * As this is invoked after the TSC synchronization check, 209 * calibrate_delay_is_known() will skip the calibration routine 210 * when TSC is synchronized across sockets. 211 */ 212 calibrate_delay(); 213 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 214 } 215 216 static void wait_for_master_cpu(int cpu) 217 { 218 /* 219 * Wait for release by control CPU before continuing with AP 220 * initialization. 221 */ 222 WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); 223 while (!cpumask_test_cpu(cpu, cpu_callout_mask)) 224 cpu_relax(); 225 } 226 227 /* 228 * Activate a secondary processor. 229 */ 230 static void notrace start_secondary(void *unused) 231 { 232 /* 233 * Don't put *anything* except direct CPU state initialization 234 * before cpu_init(), SMP booting is too fragile that we want to 235 * limit the things done here to the most necessary things. 236 */ 237 cr4_init(); 238 239 #ifdef CONFIG_X86_32 240 /* switch away from the initial page table */ 241 load_cr3(swapper_pg_dir); 242 __flush_tlb_all(); 243 #endif 244 cpu_init_exception_handling(); 245 246 /* 247 * Sync point with wait_cpu_initialized(). Sets AP in 248 * cpu_initialized_mask and then waits for the control CPU 249 * to release it. 250 */ 251 wait_for_master_cpu(raw_smp_processor_id()); 252 253 cpu_init(); 254 rcu_cpu_starting(raw_smp_processor_id()); 255 x86_cpuinit.early_percpu_clock_init(); 256 257 ap_starting(); 258 259 /* Check TSC synchronization with the control CPU. */ 260 check_tsc_sync_target(); 261 262 /* 263 * Calibrate the delay loop after the TSC synchronization check. 264 * This allows to skip the calibration when TSC is synchronized 265 * across sockets. 266 */ 267 ap_calibrate_delay(); 268 269 speculative_store_bypass_ht_init(); 270 271 /* 272 * Lock vector_lock, set CPU online and bring the vector 273 * allocator online. Online must be set with vector_lock held 274 * to prevent a concurrent irq setup/teardown from seeing a 275 * half valid vector space. 276 */ 277 lock_vector_lock(); 278 set_cpu_online(smp_processor_id(), true); 279 lapic_online(); 280 unlock_vector_lock(); 281 cpu_set_state_online(smp_processor_id()); 282 x86_platform.nmi_init(); 283 284 /* enable local interrupts */ 285 local_irq_enable(); 286 287 x86_cpuinit.setup_percpu_clockev(); 288 289 wmb(); 290 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 291 } 292 293 /** 294 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 295 * @cpu: CPU to check 296 */ 297 bool topology_is_primary_thread(unsigned int cpu) 298 { 299 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 300 } 301 302 /** 303 * topology_smt_supported - Check whether SMT is supported by the CPUs 304 */ 305 bool topology_smt_supported(void) 306 { 307 return smp_num_siblings > 1; 308 } 309 310 /** 311 * topology_phys_to_logical_pkg - Map a physical package id to a logical 312 * @phys_pkg: The physical package id to map 313 * 314 * Returns logical package id or -1 if not found 315 */ 316 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 317 { 318 int cpu; 319 320 for_each_possible_cpu(cpu) { 321 struct cpuinfo_x86 *c = &cpu_data(cpu); 322 323 if (c->initialized && c->phys_proc_id == phys_pkg) 324 return c->logical_proc_id; 325 } 326 return -1; 327 } 328 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 329 330 /** 331 * topology_phys_to_logical_die - Map a physical die id to logical 332 * @die_id: The physical die id to map 333 * @cur_cpu: The CPU for which the mapping is done 334 * 335 * Returns logical die id or -1 if not found 336 */ 337 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 338 { 339 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 340 341 for_each_possible_cpu(cpu) { 342 struct cpuinfo_x86 *c = &cpu_data(cpu); 343 344 if (c->initialized && c->cpu_die_id == die_id && 345 c->phys_proc_id == proc_id) 346 return c->logical_die_id; 347 } 348 return -1; 349 } 350 351 /** 352 * topology_update_package_map - Update the physical to logical package map 353 * @pkg: The physical package id as retrieved via CPUID 354 * @cpu: The cpu for which this is updated 355 */ 356 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 357 { 358 int new; 359 360 /* Already available somewhere? */ 361 new = topology_phys_to_logical_pkg(pkg); 362 if (new >= 0) 363 goto found; 364 365 new = logical_packages++; 366 if (new != pkg) { 367 pr_info("CPU %u Converting physical %u to logical package %u\n", 368 cpu, pkg, new); 369 } 370 found: 371 cpu_data(cpu).logical_proc_id = new; 372 return 0; 373 } 374 /** 375 * topology_update_die_map - Update the physical to logical die map 376 * @die: The die id as retrieved via CPUID 377 * @cpu: The cpu for which this is updated 378 */ 379 int topology_update_die_map(unsigned int die, unsigned int cpu) 380 { 381 int new; 382 383 /* Already available somewhere? */ 384 new = topology_phys_to_logical_die(die, cpu); 385 if (new >= 0) 386 goto found; 387 388 new = logical_die++; 389 if (new != die) { 390 pr_info("CPU %u Converting physical %u to logical die %u\n", 391 cpu, die, new); 392 } 393 found: 394 cpu_data(cpu).logical_die_id = new; 395 return 0; 396 } 397 398 void __init smp_store_boot_cpu_info(void) 399 { 400 int id = 0; /* CPU 0 */ 401 struct cpuinfo_x86 *c = &cpu_data(id); 402 403 *c = boot_cpu_data; 404 c->cpu_index = id; 405 topology_update_package_map(c->phys_proc_id, id); 406 topology_update_die_map(c->cpu_die_id, id); 407 c->initialized = true; 408 } 409 410 /* 411 * The bootstrap kernel entry code has set these up. Save them for 412 * a given CPU 413 */ 414 void smp_store_cpu_info(int id) 415 { 416 struct cpuinfo_x86 *c = &cpu_data(id); 417 418 /* Copy boot_cpu_data only on the first bringup */ 419 if (!c->initialized) 420 *c = boot_cpu_data; 421 c->cpu_index = id; 422 /* 423 * During boot time, CPU0 has this setup already. Save the info when 424 * bringing up an AP. 425 */ 426 identify_secondary_cpu(c); 427 c->initialized = true; 428 } 429 430 static bool 431 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 432 { 433 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 434 435 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 436 } 437 438 static bool 439 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 440 { 441 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 442 443 return !WARN_ONCE(!topology_same_node(c, o), 444 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 445 "[node: %d != %d]. Ignoring dependency.\n", 446 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 447 } 448 449 #define link_mask(mfunc, c1, c2) \ 450 do { \ 451 cpumask_set_cpu((c1), mfunc(c2)); \ 452 cpumask_set_cpu((c2), mfunc(c1)); \ 453 } while (0) 454 455 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 456 { 457 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 458 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 459 460 if (c->phys_proc_id == o->phys_proc_id && 461 c->cpu_die_id == o->cpu_die_id && 462 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 463 if (c->cpu_core_id == o->cpu_core_id) 464 return topology_sane(c, o, "smt"); 465 466 if ((c->cu_id != 0xff) && 467 (o->cu_id != 0xff) && 468 (c->cu_id == o->cu_id)) 469 return topology_sane(c, o, "smt"); 470 } 471 472 } else if (c->phys_proc_id == o->phys_proc_id && 473 c->cpu_die_id == o->cpu_die_id && 474 c->cpu_core_id == o->cpu_core_id) { 475 return topology_sane(c, o, "smt"); 476 } 477 478 return false; 479 } 480 481 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 482 { 483 if (c->phys_proc_id == o->phys_proc_id && 484 c->cpu_die_id == o->cpu_die_id) 485 return true; 486 return false; 487 } 488 489 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 490 { 491 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 492 493 /* If the arch didn't set up l2c_id, fall back to SMT */ 494 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 495 return match_smt(c, o); 496 497 /* Do not match if L2 cache id does not match: */ 498 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 499 return false; 500 501 return topology_sane(c, o, "l2c"); 502 } 503 504 /* 505 * Unlike the other levels, we do not enforce keeping a 506 * multicore group inside a NUMA node. If this happens, we will 507 * discard the MC level of the topology later. 508 */ 509 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 510 { 511 if (c->phys_proc_id == o->phys_proc_id) 512 return true; 513 return false; 514 } 515 516 /* 517 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 518 * 519 * Any Intel CPU that has multiple nodes per package and does not 520 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 521 * 522 * When in SNC mode, these CPUs enumerate an LLC that is shared 523 * by multiple NUMA nodes. The LLC is shared for off-package data 524 * access but private to the NUMA node (half of the package) for 525 * on-package access. CPUID (the source of the information about 526 * the LLC) can only enumerate the cache as shared or unshared, 527 * but not this particular configuration. 528 */ 529 530 static const struct x86_cpu_id intel_cod_cpu[] = { 531 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 532 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 533 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 534 {} 535 }; 536 537 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 538 { 539 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 540 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 541 bool intel_snc = id && id->driver_data; 542 543 /* Do not match if we do not have a valid APICID for cpu: */ 544 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 545 return false; 546 547 /* Do not match if LLC id does not match: */ 548 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 549 return false; 550 551 /* 552 * Allow the SNC topology without warning. Return of false 553 * means 'c' does not share the LLC of 'o'. This will be 554 * reflected to userspace. 555 */ 556 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 557 return false; 558 559 return topology_sane(c, o, "llc"); 560 } 561 562 563 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 564 static inline int x86_sched_itmt_flags(void) 565 { 566 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 567 } 568 569 #ifdef CONFIG_SCHED_MC 570 static int x86_core_flags(void) 571 { 572 return cpu_core_flags() | x86_sched_itmt_flags(); 573 } 574 #endif 575 #ifdef CONFIG_SCHED_SMT 576 static int x86_smt_flags(void) 577 { 578 return cpu_smt_flags() | x86_sched_itmt_flags(); 579 } 580 #endif 581 #ifdef CONFIG_SCHED_CLUSTER 582 static int x86_cluster_flags(void) 583 { 584 return cpu_cluster_flags() | x86_sched_itmt_flags(); 585 } 586 #endif 587 #endif 588 589 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 590 #ifdef CONFIG_SCHED_SMT 591 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 592 #endif 593 #ifdef CONFIG_SCHED_CLUSTER 594 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 595 #endif 596 #ifdef CONFIG_SCHED_MC 597 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 598 #endif 599 { NULL, }, 600 }; 601 602 static struct sched_domain_topology_level x86_hybrid_topology[] = { 603 #ifdef CONFIG_SCHED_SMT 604 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 605 #endif 606 #ifdef CONFIG_SCHED_MC 607 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 608 #endif 609 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 610 { NULL, }, 611 }; 612 613 static struct sched_domain_topology_level x86_topology[] = { 614 #ifdef CONFIG_SCHED_SMT 615 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 616 #endif 617 #ifdef CONFIG_SCHED_CLUSTER 618 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 619 #endif 620 #ifdef CONFIG_SCHED_MC 621 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 622 #endif 623 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 624 { NULL, }, 625 }; 626 627 /* 628 * Set if a package/die has multiple NUMA nodes inside. 629 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 630 * Sub-NUMA Clustering have this. 631 */ 632 static bool x86_has_numa_in_package; 633 634 void set_cpu_sibling_map(int cpu) 635 { 636 bool has_smt = smp_num_siblings > 1; 637 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 638 struct cpuinfo_x86 *c = &cpu_data(cpu); 639 struct cpuinfo_x86 *o; 640 int i, threads; 641 642 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 643 644 if (!has_mp) { 645 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 646 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 647 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 648 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 649 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 650 c->booted_cores = 1; 651 return; 652 } 653 654 for_each_cpu(i, cpu_sibling_setup_mask) { 655 o = &cpu_data(i); 656 657 if (match_pkg(c, o) && !topology_same_node(c, o)) 658 x86_has_numa_in_package = true; 659 660 if ((i == cpu) || (has_smt && match_smt(c, o))) 661 link_mask(topology_sibling_cpumask, cpu, i); 662 663 if ((i == cpu) || (has_mp && match_llc(c, o))) 664 link_mask(cpu_llc_shared_mask, cpu, i); 665 666 if ((i == cpu) || (has_mp && match_l2c(c, o))) 667 link_mask(cpu_l2c_shared_mask, cpu, i); 668 669 if ((i == cpu) || (has_mp && match_die(c, o))) 670 link_mask(topology_die_cpumask, cpu, i); 671 } 672 673 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 674 if (threads > __max_smt_threads) 675 __max_smt_threads = threads; 676 677 for_each_cpu(i, topology_sibling_cpumask(cpu)) 678 cpu_data(i).smt_active = threads > 1; 679 680 /* 681 * This needs a separate iteration over the cpus because we rely on all 682 * topology_sibling_cpumask links to be set-up. 683 */ 684 for_each_cpu(i, cpu_sibling_setup_mask) { 685 o = &cpu_data(i); 686 687 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 688 link_mask(topology_core_cpumask, cpu, i); 689 690 /* 691 * Does this new cpu bringup a new core? 692 */ 693 if (threads == 1) { 694 /* 695 * for each core in package, increment 696 * the booted_cores for this new cpu 697 */ 698 if (cpumask_first( 699 topology_sibling_cpumask(i)) == i) 700 c->booted_cores++; 701 /* 702 * increment the core count for all 703 * the other cpus in this package 704 */ 705 if (i != cpu) 706 cpu_data(i).booted_cores++; 707 } else if (i != cpu && !c->booted_cores) 708 c->booted_cores = cpu_data(i).booted_cores; 709 } 710 } 711 } 712 713 /* maps the cpu to the sched domain representing multi-core */ 714 const struct cpumask *cpu_coregroup_mask(int cpu) 715 { 716 return cpu_llc_shared_mask(cpu); 717 } 718 719 const struct cpumask *cpu_clustergroup_mask(int cpu) 720 { 721 return cpu_l2c_shared_mask(cpu); 722 } 723 724 static void impress_friends(void) 725 { 726 int cpu; 727 unsigned long bogosum = 0; 728 /* 729 * Allow the user to impress friends. 730 */ 731 pr_debug("Before bogomips\n"); 732 for_each_possible_cpu(cpu) 733 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 734 bogosum += cpu_data(cpu).loops_per_jiffy; 735 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 736 num_online_cpus(), 737 bogosum/(500000/HZ), 738 (bogosum/(5000/HZ))%100); 739 740 pr_debug("Before bogocount - setting activated=1\n"); 741 } 742 743 void __inquire_remote_apic(int apicid) 744 { 745 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 746 const char * const names[] = { "ID", "VERSION", "SPIV" }; 747 int timeout; 748 u32 status; 749 750 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 751 752 for (i = 0; i < ARRAY_SIZE(regs); i++) { 753 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 754 755 /* 756 * Wait for idle. 757 */ 758 status = safe_apic_wait_icr_idle(); 759 if (status) 760 pr_cont("a previous APIC delivery may have failed\n"); 761 762 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 763 764 timeout = 0; 765 do { 766 udelay(100); 767 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 768 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 769 770 switch (status) { 771 case APIC_ICR_RR_VALID: 772 status = apic_read(APIC_RRR); 773 pr_cont("%08x\n", status); 774 break; 775 default: 776 pr_cont("failed\n"); 777 } 778 } 779 } 780 781 /* 782 * The Multiprocessor Specification 1.4 (1997) example code suggests 783 * that there should be a 10ms delay between the BSP asserting INIT 784 * and de-asserting INIT, when starting a remote processor. 785 * But that slows boot and resume on modern processors, which include 786 * many cores and don't require that delay. 787 * 788 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 789 * Modern processor families are quirked to remove the delay entirely. 790 */ 791 #define UDELAY_10MS_DEFAULT 10000 792 793 static unsigned int init_udelay = UINT_MAX; 794 795 static int __init cpu_init_udelay(char *str) 796 { 797 get_option(&str, &init_udelay); 798 799 return 0; 800 } 801 early_param("cpu_init_udelay", cpu_init_udelay); 802 803 static void __init smp_quirk_init_udelay(void) 804 { 805 /* if cmdline changed it from default, leave it alone */ 806 if (init_udelay != UINT_MAX) 807 return; 808 809 /* if modern processor, use no delay */ 810 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 811 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 812 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 813 init_udelay = 0; 814 return; 815 } 816 /* else, use legacy delay */ 817 init_udelay = UDELAY_10MS_DEFAULT; 818 } 819 820 /* 821 * Wake up AP by INIT, INIT, STARTUP sequence. 822 */ 823 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 824 { 825 unsigned long send_status = 0, accept_status = 0; 826 int maxlvt, num_starts, j; 827 828 preempt_disable(); 829 maxlvt = lapic_get_maxlvt(); 830 831 /* 832 * Be paranoid about clearing APIC errors. 833 */ 834 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 835 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 836 apic_write(APIC_ESR, 0); 837 apic_read(APIC_ESR); 838 } 839 840 pr_debug("Asserting INIT\n"); 841 842 /* 843 * Turn INIT on target chip 844 */ 845 /* 846 * Send IPI 847 */ 848 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 849 phys_apicid); 850 851 pr_debug("Waiting for send to finish...\n"); 852 send_status = safe_apic_wait_icr_idle(); 853 854 udelay(init_udelay); 855 856 pr_debug("Deasserting INIT\n"); 857 858 /* Target chip */ 859 /* Send IPI */ 860 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 861 862 pr_debug("Waiting for send to finish...\n"); 863 send_status = safe_apic_wait_icr_idle(); 864 865 mb(); 866 867 /* 868 * Should we send STARTUP IPIs ? 869 * 870 * Determine this based on the APIC version. 871 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 872 */ 873 if (APIC_INTEGRATED(boot_cpu_apic_version)) 874 num_starts = 2; 875 else 876 num_starts = 0; 877 878 /* 879 * Run STARTUP IPI loop. 880 */ 881 pr_debug("#startup loops: %d\n", num_starts); 882 883 for (j = 1; j <= num_starts; j++) { 884 pr_debug("Sending STARTUP #%d\n", j); 885 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 886 apic_write(APIC_ESR, 0); 887 apic_read(APIC_ESR); 888 pr_debug("After apic_write\n"); 889 890 /* 891 * STARTUP IPI 892 */ 893 894 /* Target chip */ 895 /* Boot on the stack */ 896 /* Kick the second */ 897 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 898 phys_apicid); 899 900 /* 901 * Give the other CPU some time to accept the IPI. 902 */ 903 if (init_udelay == 0) 904 udelay(10); 905 else 906 udelay(300); 907 908 pr_debug("Startup point 1\n"); 909 910 pr_debug("Waiting for send to finish...\n"); 911 send_status = safe_apic_wait_icr_idle(); 912 913 /* 914 * Give the other CPU some time to accept the IPI. 915 */ 916 if (init_udelay == 0) 917 udelay(10); 918 else 919 udelay(200); 920 921 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 922 apic_write(APIC_ESR, 0); 923 accept_status = (apic_read(APIC_ESR) & 0xEF); 924 if (send_status || accept_status) 925 break; 926 } 927 pr_debug("After Startup\n"); 928 929 if (send_status) 930 pr_err("APIC never delivered???\n"); 931 if (accept_status) 932 pr_err("APIC delivery error (%lx)\n", accept_status); 933 934 preempt_enable(); 935 return (send_status | accept_status); 936 } 937 938 /* reduce the number of lines printed when booting a large cpu count system */ 939 static void announce_cpu(int cpu, int apicid) 940 { 941 static int current_node = NUMA_NO_NODE; 942 int node = early_cpu_to_node(cpu); 943 static int width, node_width; 944 945 if (!width) 946 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 947 948 if (!node_width) 949 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 950 951 if (cpu == 1) 952 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 953 954 if (system_state < SYSTEM_RUNNING) { 955 if (node != current_node) { 956 if (current_node > (-1)) 957 pr_cont("\n"); 958 current_node = node; 959 960 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 961 node_width - num_digits(node), " ", node); 962 } 963 964 /* Add padding for the BSP */ 965 if (cpu == 1) 966 pr_cont("%*s", width + 1, " "); 967 968 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 969 970 } else 971 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 972 node, cpu, apicid); 973 } 974 975 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 976 { 977 int ret; 978 979 /* Just in case we booted with a single CPU. */ 980 alternatives_enable_smp(); 981 982 per_cpu(pcpu_hot.current_task, cpu) = idle; 983 cpu_init_stack_canary(cpu, idle); 984 985 /* Initialize the interrupt stack(s) */ 986 ret = irq_init_percpu_irqstack(cpu); 987 if (ret) 988 return ret; 989 990 #ifdef CONFIG_X86_32 991 /* Stack for startup_32 can be just as for start_secondary onwards */ 992 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 993 #endif 994 return 0; 995 } 996 997 /* 998 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 999 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1000 * Returns zero if startup was successfully sent, else error code from 1001 * ->wakeup_secondary_cpu. 1002 */ 1003 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 1004 { 1005 unsigned long start_ip = real_mode_header->trampoline_start; 1006 1007 #ifdef CONFIG_X86_64 1008 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1009 if (apic->wakeup_secondary_cpu_64) 1010 start_ip = real_mode_header->trampoline_start64; 1011 #endif 1012 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1013 initial_code = (unsigned long)start_secondary; 1014 1015 if (IS_ENABLED(CONFIG_X86_32)) { 1016 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1017 initial_stack = idle->thread.sp; 1018 } else { 1019 smpboot_control = cpu; 1020 } 1021 1022 /* Enable the espfix hack for this CPU */ 1023 init_espfix_ap(cpu); 1024 1025 /* So we see what's up */ 1026 announce_cpu(cpu, apicid); 1027 1028 /* 1029 * This grunge runs the startup process for 1030 * the targeted processor. 1031 */ 1032 if (x86_platform.legacy.warm_reset) { 1033 1034 pr_debug("Setting warm reset code and vector.\n"); 1035 1036 smpboot_setup_warm_reset_vector(start_ip); 1037 /* 1038 * Be paranoid about clearing APIC errors. 1039 */ 1040 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1041 apic_write(APIC_ESR, 0); 1042 apic_read(APIC_ESR); 1043 } 1044 } 1045 1046 /* 1047 * AP might wait on cpu_callout_mask in cpu_init() with 1048 * cpu_initialized_mask set if previous attempt to online 1049 * it timed-out. Clear cpu_initialized_mask so that after 1050 * INIT/SIPI it could start with a clean state. 1051 */ 1052 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1053 smp_mb(); 1054 1055 /* 1056 * Wake up a CPU in difference cases: 1057 * - Use a method from the APIC driver if one defined, with wakeup 1058 * straight to 64-bit mode preferred over wakeup to RM. 1059 * Otherwise, 1060 * - Use an INIT boot APIC message 1061 */ 1062 if (apic->wakeup_secondary_cpu_64) 1063 return apic->wakeup_secondary_cpu_64(apicid, start_ip); 1064 else if (apic->wakeup_secondary_cpu) 1065 return apic->wakeup_secondary_cpu(apicid, start_ip); 1066 1067 return wakeup_secondary_cpu_via_init(apicid, start_ip); 1068 } 1069 1070 static int wait_cpu_cpumask(unsigned int cpu, const struct cpumask *mask) 1071 { 1072 unsigned long timeout; 1073 1074 /* 1075 * Wait up to 10s for the CPU to report in. 1076 */ 1077 timeout = jiffies + 10*HZ; 1078 while (time_before(jiffies, timeout)) { 1079 if (cpumask_test_cpu(cpu, mask)) 1080 return 0; 1081 1082 schedule(); 1083 } 1084 return -1; 1085 } 1086 1087 /* 1088 * Bringup step two: Wait for the target AP to reach cpu_init_secondary() 1089 * and thus wait_for_master_cpu(), then set cpu_callout_mask to allow it 1090 * to proceed. The AP will then proceed past setting its 'callin' bit 1091 * and end up waiting in check_tsc_sync_target() until we reach 1092 * wait_cpu_online() to tend to it. 1093 */ 1094 static int wait_cpu_initialized(unsigned int cpu) 1095 { 1096 /* 1097 * Wait for first sign of life from AP. 1098 */ 1099 if (wait_cpu_cpumask(cpu, cpu_initialized_mask)) 1100 return -1; 1101 1102 cpumask_set_cpu(cpu, cpu_callout_mask); 1103 return 0; 1104 } 1105 1106 static int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1107 { 1108 int apicid = apic->cpu_present_to_apicid(cpu); 1109 int err; 1110 1111 lockdep_assert_irqs_enabled(); 1112 1113 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1114 1115 if (apicid == BAD_APICID || 1116 !physid_isset(apicid, phys_cpu_present_map) || 1117 !apic->apic_id_valid(apicid)) { 1118 pr_err("%s: bad cpu %d\n", __func__, cpu); 1119 return -EINVAL; 1120 } 1121 1122 /* 1123 * Save current MTRR state in case it was changed since early boot 1124 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1125 */ 1126 mtrr_save_state(); 1127 1128 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1129 err = cpu_check_up_prepare(cpu); 1130 if (err && err != -EBUSY) 1131 return err; 1132 1133 /* the FPU context is blank, nobody can own it */ 1134 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1135 1136 err = common_cpu_up(cpu, tidle); 1137 if (err) 1138 return err; 1139 1140 err = do_boot_cpu(apicid, cpu, tidle); 1141 if (err) 1142 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1143 1144 return err; 1145 } 1146 1147 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1148 { 1149 int ret; 1150 1151 ret = native_kick_ap(cpu, tidle); 1152 if (!ret) 1153 ret = wait_cpu_initialized(cpu); 1154 1155 /* Cleanup possible dangling ends... */ 1156 if (x86_platform.legacy.warm_reset) 1157 smpboot_restore_warm_reset_vector(); 1158 1159 return ret; 1160 } 1161 1162 /** 1163 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1164 */ 1165 void __init arch_disable_smp_support(void) 1166 { 1167 disable_ioapic_support(); 1168 } 1169 1170 /* 1171 * Fall back to non SMP mode after errors. 1172 * 1173 * RED-PEN audit/test this more. I bet there is more state messed up here. 1174 */ 1175 static __init void disable_smp(void) 1176 { 1177 pr_info("SMP disabled\n"); 1178 1179 disable_ioapic_support(); 1180 1181 init_cpu_present(cpumask_of(0)); 1182 init_cpu_possible(cpumask_of(0)); 1183 1184 if (smp_found_config) 1185 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1186 else 1187 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1188 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1189 cpumask_set_cpu(0, topology_core_cpumask(0)); 1190 cpumask_set_cpu(0, topology_die_cpumask(0)); 1191 } 1192 1193 /* 1194 * Various sanity checks. 1195 */ 1196 static void __init smp_sanity_check(void) 1197 { 1198 preempt_disable(); 1199 1200 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1201 if (def_to_bigsmp && nr_cpu_ids > 8) { 1202 unsigned int cpu; 1203 unsigned nr; 1204 1205 pr_warn("More than 8 CPUs detected - skipping them\n" 1206 "Use CONFIG_X86_BIGSMP\n"); 1207 1208 nr = 0; 1209 for_each_present_cpu(cpu) { 1210 if (nr >= 8) 1211 set_cpu_present(cpu, false); 1212 nr++; 1213 } 1214 1215 nr = 0; 1216 for_each_possible_cpu(cpu) { 1217 if (nr >= 8) 1218 set_cpu_possible(cpu, false); 1219 nr++; 1220 } 1221 1222 set_nr_cpu_ids(8); 1223 } 1224 #endif 1225 1226 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1227 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1228 hard_smp_processor_id()); 1229 1230 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1231 } 1232 1233 /* 1234 * Should not be necessary because the MP table should list the boot 1235 * CPU too, but we do it for the sake of robustness anyway. 1236 */ 1237 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1238 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1239 boot_cpu_physical_apicid); 1240 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1241 } 1242 preempt_enable(); 1243 } 1244 1245 static void __init smp_cpu_index_default(void) 1246 { 1247 int i; 1248 struct cpuinfo_x86 *c; 1249 1250 for_each_possible_cpu(i) { 1251 c = &cpu_data(i); 1252 /* mark all to hotplug */ 1253 c->cpu_index = nr_cpu_ids; 1254 } 1255 } 1256 1257 void __init smp_prepare_cpus_common(void) 1258 { 1259 unsigned int i; 1260 1261 smp_cpu_index_default(); 1262 1263 /* 1264 * Setup boot CPU information 1265 */ 1266 smp_store_boot_cpu_info(); /* Final full version of the data */ 1267 mb(); 1268 1269 for_each_possible_cpu(i) { 1270 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1271 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1272 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1273 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1274 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1275 } 1276 1277 /* 1278 * Set 'default' x86 topology, this matches default_topology() in that 1279 * it has NUMA nodes as a topology level. See also 1280 * native_smp_cpus_done(). 1281 * 1282 * Must be done before set_cpus_sibling_map() is ran. 1283 */ 1284 set_sched_topology(x86_topology); 1285 1286 set_cpu_sibling_map(0); 1287 } 1288 1289 /* 1290 * Prepare for SMP bootup. 1291 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1292 * for common interface support. 1293 */ 1294 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1295 { 1296 smp_prepare_cpus_common(); 1297 1298 smp_sanity_check(); 1299 1300 switch (apic_intr_mode) { 1301 case APIC_PIC: 1302 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1303 disable_smp(); 1304 return; 1305 case APIC_SYMMETRIC_IO_NO_ROUTING: 1306 disable_smp(); 1307 /* Setup local timer */ 1308 x86_init.timers.setup_percpu_clockev(); 1309 return; 1310 case APIC_VIRTUAL_WIRE: 1311 case APIC_SYMMETRIC_IO: 1312 break; 1313 } 1314 1315 /* Setup local timer */ 1316 x86_init.timers.setup_percpu_clockev(); 1317 1318 pr_info("CPU0: "); 1319 print_cpu_info(&cpu_data(0)); 1320 1321 uv_system_init(); 1322 1323 smp_quirk_init_udelay(); 1324 1325 speculative_store_bypass_ht_init(); 1326 1327 snp_set_wakeup_secondary_cpu(); 1328 } 1329 1330 void arch_thaw_secondary_cpus_begin(void) 1331 { 1332 set_cache_aps_delayed_init(true); 1333 } 1334 1335 void arch_thaw_secondary_cpus_end(void) 1336 { 1337 cache_aps_init(); 1338 } 1339 1340 /* 1341 * Early setup to make printk work. 1342 */ 1343 void __init native_smp_prepare_boot_cpu(void) 1344 { 1345 int me = smp_processor_id(); 1346 1347 /* SMP handles this from setup_per_cpu_areas() */ 1348 if (!IS_ENABLED(CONFIG_SMP)) 1349 switch_gdt_and_percpu_base(me); 1350 1351 /* already set me in cpu_online_mask in boot_cpu_init() */ 1352 cpumask_set_cpu(me, cpu_callout_mask); 1353 cpu_set_state_online(me); 1354 native_pv_lock_init(); 1355 } 1356 1357 void __init calculate_max_logical_packages(void) 1358 { 1359 int ncpus; 1360 1361 /* 1362 * Today neither Intel nor AMD support heterogeneous systems so 1363 * extrapolate the boot cpu's data to all packages. 1364 */ 1365 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1366 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1367 pr_info("Max logical packages: %u\n", __max_logical_packages); 1368 } 1369 1370 void __init native_smp_cpus_done(unsigned int max_cpus) 1371 { 1372 pr_debug("Boot done\n"); 1373 1374 calculate_max_logical_packages(); 1375 1376 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1377 if (x86_has_numa_in_package) 1378 set_sched_topology(x86_numa_in_package_topology); 1379 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1380 set_sched_topology(x86_hybrid_topology); 1381 1382 nmi_selftest(); 1383 impress_friends(); 1384 cache_aps_init(); 1385 } 1386 1387 static int __initdata setup_possible_cpus = -1; 1388 static int __init _setup_possible_cpus(char *str) 1389 { 1390 get_option(&str, &setup_possible_cpus); 1391 return 0; 1392 } 1393 early_param("possible_cpus", _setup_possible_cpus); 1394 1395 1396 /* 1397 * cpu_possible_mask should be static, it cannot change as cpu's 1398 * are onlined, or offlined. The reason is per-cpu data-structures 1399 * are allocated by some modules at init time, and don't expect to 1400 * do this dynamically on cpu arrival/departure. 1401 * cpu_present_mask on the other hand can change dynamically. 1402 * In case when cpu_hotplug is not compiled, then we resort to current 1403 * behaviour, which is cpu_possible == cpu_present. 1404 * - Ashok Raj 1405 * 1406 * Three ways to find out the number of additional hotplug CPUs: 1407 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1408 * - The user can overwrite it with possible_cpus=NUM 1409 * - Otherwise don't reserve additional CPUs. 1410 * We do this because additional CPUs waste a lot of memory. 1411 * -AK 1412 */ 1413 __init void prefill_possible_map(void) 1414 { 1415 int i, possible; 1416 1417 /* No boot processor was found in mptable or ACPI MADT */ 1418 if (!num_processors) { 1419 if (boot_cpu_has(X86_FEATURE_APIC)) { 1420 int apicid = boot_cpu_physical_apicid; 1421 int cpu = hard_smp_processor_id(); 1422 1423 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1424 1425 /* Make sure boot cpu is enumerated */ 1426 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1427 apic->apic_id_valid(apicid)) 1428 generic_processor_info(apicid, boot_cpu_apic_version); 1429 } 1430 1431 if (!num_processors) 1432 num_processors = 1; 1433 } 1434 1435 i = setup_max_cpus ?: 1; 1436 if (setup_possible_cpus == -1) { 1437 possible = num_processors; 1438 #ifdef CONFIG_HOTPLUG_CPU 1439 if (setup_max_cpus) 1440 possible += disabled_cpus; 1441 #else 1442 if (possible > i) 1443 possible = i; 1444 #endif 1445 } else 1446 possible = setup_possible_cpus; 1447 1448 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1449 1450 /* nr_cpu_ids could be reduced via nr_cpus= */ 1451 if (possible > nr_cpu_ids) { 1452 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1453 possible, nr_cpu_ids); 1454 possible = nr_cpu_ids; 1455 } 1456 1457 #ifdef CONFIG_HOTPLUG_CPU 1458 if (!setup_max_cpus) 1459 #endif 1460 if (possible > i) { 1461 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1462 possible, setup_max_cpus); 1463 possible = i; 1464 } 1465 1466 set_nr_cpu_ids(possible); 1467 1468 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1469 possible, max_t(int, possible - num_processors, 0)); 1470 1471 reset_cpu_possible_mask(); 1472 1473 for (i = 0; i < possible; i++) 1474 set_cpu_possible(i, true); 1475 } 1476 1477 /* correctly size the local cpu masks */ 1478 void __init setup_cpu_local_masks(void) 1479 { 1480 alloc_bootmem_cpumask_var(&cpu_initialized_mask); 1481 alloc_bootmem_cpumask_var(&cpu_callout_mask); 1482 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1483 } 1484 1485 #ifdef CONFIG_HOTPLUG_CPU 1486 1487 /* Recompute SMT state for all CPUs on offline */ 1488 static void recompute_smt_state(void) 1489 { 1490 int max_threads, cpu; 1491 1492 max_threads = 0; 1493 for_each_online_cpu (cpu) { 1494 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1495 1496 if (threads > max_threads) 1497 max_threads = threads; 1498 } 1499 __max_smt_threads = max_threads; 1500 } 1501 1502 static void remove_siblinginfo(int cpu) 1503 { 1504 int sibling; 1505 struct cpuinfo_x86 *c = &cpu_data(cpu); 1506 1507 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1508 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1509 /*/ 1510 * last thread sibling in this cpu core going down 1511 */ 1512 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1513 cpu_data(sibling).booted_cores--; 1514 } 1515 1516 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1517 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1518 1519 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1520 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1521 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1522 cpu_data(sibling).smt_active = false; 1523 } 1524 1525 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1526 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1527 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1528 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1529 cpumask_clear(cpu_llc_shared_mask(cpu)); 1530 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1531 cpumask_clear(topology_sibling_cpumask(cpu)); 1532 cpumask_clear(topology_core_cpumask(cpu)); 1533 cpumask_clear(topology_die_cpumask(cpu)); 1534 c->cpu_core_id = 0; 1535 c->booted_cores = 0; 1536 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1537 recompute_smt_state(); 1538 } 1539 1540 static void remove_cpu_from_maps(int cpu) 1541 { 1542 set_cpu_online(cpu, false); 1543 cpumask_clear_cpu(cpu, cpu_callout_mask); 1544 /* was set by cpu_init() */ 1545 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1546 numa_remove_cpu(cpu); 1547 } 1548 1549 void cpu_disable_common(void) 1550 { 1551 int cpu = smp_processor_id(); 1552 1553 remove_siblinginfo(cpu); 1554 1555 /* It's now safe to remove this processor from the online map */ 1556 lock_vector_lock(); 1557 remove_cpu_from_maps(cpu); 1558 unlock_vector_lock(); 1559 fixup_irqs(); 1560 lapic_offline(); 1561 } 1562 1563 int native_cpu_disable(void) 1564 { 1565 int ret; 1566 1567 ret = lapic_can_unplug_cpu(); 1568 if (ret) 1569 return ret; 1570 1571 cpu_disable_common(); 1572 1573 /* 1574 * Disable the local APIC. Otherwise IPI broadcasts will reach 1575 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1576 * messages. 1577 * 1578 * Disabling the APIC must happen after cpu_disable_common() 1579 * which invokes fixup_irqs(). 1580 * 1581 * Disabling the APIC preserves already set bits in IRR, but 1582 * an interrupt arriving after disabling the local APIC does not 1583 * set the corresponding IRR bit. 1584 * 1585 * fixup_irqs() scans IRR for set bits so it can raise a not 1586 * yet handled interrupt on the new destination CPU via an IPI 1587 * but obviously it can't do so for IRR bits which are not set. 1588 * IOW, interrupts arriving after disabling the local APIC will 1589 * be lost. 1590 */ 1591 apic_soft_disable(); 1592 1593 return 0; 1594 } 1595 1596 int common_cpu_die(unsigned int cpu) 1597 { 1598 int ret = 0; 1599 1600 /* We don't do anything here: idle task is faking death itself. */ 1601 1602 /* They ack this in play_dead() by setting CPU_DEAD */ 1603 if (cpu_wait_death(cpu, 5)) { 1604 if (system_state == SYSTEM_RUNNING) 1605 pr_info("CPU %u is now offline\n", cpu); 1606 } else { 1607 pr_err("CPU %u didn't die...\n", cpu); 1608 ret = -1; 1609 } 1610 1611 return ret; 1612 } 1613 1614 void native_cpu_die(unsigned int cpu) 1615 { 1616 common_cpu_die(cpu); 1617 } 1618 1619 void play_dead_common(void) 1620 { 1621 idle_task_exit(); 1622 1623 /* Ack it */ 1624 (void)cpu_report_death(); 1625 1626 /* 1627 * With physical CPU hotplug, we should halt the cpu 1628 */ 1629 local_irq_disable(); 1630 } 1631 1632 /* 1633 * We need to flush the caches before going to sleep, lest we have 1634 * dirty data in our caches when we come back up. 1635 */ 1636 static inline void mwait_play_dead(void) 1637 { 1638 unsigned int eax, ebx, ecx, edx; 1639 unsigned int highest_cstate = 0; 1640 unsigned int highest_subcstate = 0; 1641 void *mwait_ptr; 1642 int i; 1643 1644 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1645 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1646 return; 1647 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1648 return; 1649 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1650 return; 1651 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1652 return; 1653 1654 eax = CPUID_MWAIT_LEAF; 1655 ecx = 0; 1656 native_cpuid(&eax, &ebx, &ecx, &edx); 1657 1658 /* 1659 * eax will be 0 if EDX enumeration is not valid. 1660 * Initialized below to cstate, sub_cstate value when EDX is valid. 1661 */ 1662 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1663 eax = 0; 1664 } else { 1665 edx >>= MWAIT_SUBSTATE_SIZE; 1666 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1667 if (edx & MWAIT_SUBSTATE_MASK) { 1668 highest_cstate = i; 1669 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1670 } 1671 } 1672 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1673 (highest_subcstate - 1); 1674 } 1675 1676 /* 1677 * This should be a memory location in a cache line which is 1678 * unlikely to be touched by other processors. The actual 1679 * content is immaterial as it is not actually modified in any way. 1680 */ 1681 mwait_ptr = ¤t_thread_info()->flags; 1682 1683 wbinvd(); 1684 1685 while (1) { 1686 /* 1687 * The CLFLUSH is a workaround for erratum AAI65 for 1688 * the Xeon 7400 series. It's not clear it is actually 1689 * needed, but it should be harmless in either case. 1690 * The WBINVD is insufficient due to the spurious-wakeup 1691 * case where we return around the loop. 1692 */ 1693 mb(); 1694 clflush(mwait_ptr); 1695 mb(); 1696 __monitor(mwait_ptr, 0, 0); 1697 mb(); 1698 __mwait(eax, 0); 1699 } 1700 } 1701 1702 void __noreturn hlt_play_dead(void) 1703 { 1704 if (__this_cpu_read(cpu_info.x86) >= 4) 1705 wbinvd(); 1706 1707 while (1) 1708 native_halt(); 1709 } 1710 1711 void native_play_dead(void) 1712 { 1713 play_dead_common(); 1714 tboot_shutdown(TB_SHUTDOWN_WFS); 1715 1716 mwait_play_dead(); 1717 if (cpuidle_play_dead()) 1718 hlt_play_dead(); 1719 } 1720 1721 #else /* ... !CONFIG_HOTPLUG_CPU */ 1722 int native_cpu_disable(void) 1723 { 1724 return -ENOSYS; 1725 } 1726 1727 void native_cpu_die(unsigned int cpu) 1728 { 1729 /* We said "no" in __cpu_disable */ 1730 BUG(); 1731 } 1732 1733 void native_play_dead(void) 1734 { 1735 BUG(); 1736 } 1737 1738 #endif 1739