1*57b55c76SYu Tu /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2*57b55c76SYu Tu /* 3*57b55c76SYu Tu * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved 4*57b55c76SYu Tu * Author: Yu Tu <yu.tu@amlogic.com> 5*57b55c76SYu Tu */ 6*57b55c76SYu Tu 7*57b55c76SYu Tu #ifndef __MESON_S4_PERIPHERALS_H__ 8*57b55c76SYu Tu #define __MESON_S4_PERIPHERALS_H__ 9*57b55c76SYu Tu 10*57b55c76SYu Tu #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 11*57b55c76SYu Tu #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 12*57b55c76SYu Tu #define CLKCTRL_RTC_CTRL 0x010 13*57b55c76SYu Tu #define CLKCTRL_SYS_CLK_CTRL0 0x040 14*57b55c76SYu Tu #define CLKCTRL_SYS_CLK_EN0_REG0 0x044 15*57b55c76SYu Tu #define CLKCTRL_SYS_CLK_EN0_REG1 0x048 16*57b55c76SYu Tu #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 17*57b55c76SYu Tu #define CLKCTRL_SYS_CLK_EN0_REG3 0x050 18*57b55c76SYu Tu #define CLKCTRL_CECA_CTRL0 0x088 19*57b55c76SYu Tu #define CLKCTRL_CECA_CTRL1 0x08c 20*57b55c76SYu Tu #define CLKCTRL_CECB_CTRL0 0x090 21*57b55c76SYu Tu #define CLKCTRL_CECB_CTRL1 0x094 22*57b55c76SYu Tu #define CLKCTRL_SC_CLK_CTRL 0x098 23*57b55c76SYu Tu #define CLKCTRL_CLK12_24_CTRL 0x0a8 24*57b55c76SYu Tu #define CLKCTRL_VID_CLK_CTRL 0x0c0 25*57b55c76SYu Tu #define CLKCTRL_VID_CLK_CTRL2 0x0c4 26*57b55c76SYu Tu #define CLKCTRL_VID_CLK_DIV 0x0c8 27*57b55c76SYu Tu #define CLKCTRL_VIID_CLK_DIV 0x0cc 28*57b55c76SYu Tu #define CLKCTRL_VIID_CLK_CTRL 0x0d0 29*57b55c76SYu Tu #define CLKCTRL_HDMI_CLK_CTRL 0x0e0 30*57b55c76SYu Tu #define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 31*57b55c76SYu Tu #define CLKCTRL_VPU_CLK_CTRL 0x0e8 32*57b55c76SYu Tu #define CLKCTRL_VPU_CLKB_CTRL 0x0ec 33*57b55c76SYu Tu #define CLKCTRL_VPU_CLKC_CTRL 0x0f0 34*57b55c76SYu Tu #define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 35*57b55c76SYu Tu #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 36*57b55c76SYu Tu #define CLKCTRL_VAPBCLK_CTRL 0x0fc 37*57b55c76SYu Tu #define CLKCTRL_HDCP22_CTRL 0x100 38*57b55c76SYu Tu #define CLKCTRL_VDEC_CLK_CTRL 0x140 39*57b55c76SYu Tu #define CLKCTRL_VDEC2_CLK_CTRL 0x144 40*57b55c76SYu Tu #define CLKCTRL_VDEC3_CLK_CTRL 0x148 41*57b55c76SYu Tu #define CLKCTRL_VDEC4_CLK_CTRL 0x14c 42*57b55c76SYu Tu #define CLKCTRL_TS_CLK_CTRL 0x158 43*57b55c76SYu Tu #define CLKCTRL_MALI_CLK_CTRL 0x15c 44*57b55c76SYu Tu #define CLKCTRL_NAND_CLK_CTRL 0x168 45*57b55c76SYu Tu #define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c 46*57b55c76SYu Tu #define CLKCTRL_SPICC_CLK_CTRL 0x174 47*57b55c76SYu Tu #define CLKCTRL_GEN_CLK_CTRL 0x178 48*57b55c76SYu Tu #define CLKCTRL_SAR_CLK_CTRL 0x17c 49*57b55c76SYu Tu #define CLKCTRL_PWM_CLK_AB_CTRL 0x180 50*57b55c76SYu Tu #define CLKCTRL_PWM_CLK_CD_CTRL 0x184 51*57b55c76SYu Tu #define CLKCTRL_PWM_CLK_EF_CTRL 0x188 52*57b55c76SYu Tu #define CLKCTRL_PWM_CLK_GH_CTRL 0x18c 53*57b55c76SYu Tu #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 54*57b55c76SYu Tu #define CLKCTRL_DEMOD_CLK_CTRL 0x200 55*57b55c76SYu Tu 56*57b55c76SYu Tu #endif /* __MESON_S4_PERIPHERALS_H__ */ 57