1*fb038ce4SYangtao Li /* SPDX-License-Identifier: GPL-2.0 */ 2*fb038ce4SYangtao Li /* 3*fb038ce4SYangtao Li * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4*fb038ce4SYangtao Li */ 5*fb038ce4SYangtao Li 6*fb038ce4SYangtao Li #ifndef _CCU_SUN50I_A100_H_ 7*fb038ce4SYangtao Li #define _CCU_SUN50I_A100_H_ 8*fb038ce4SYangtao Li 9*fb038ce4SYangtao Li #include <dt-bindings/clock/sun50i-a100-ccu.h> 10*fb038ce4SYangtao Li #include <dt-bindings/reset/sun50i-a100-ccu.h> 11*fb038ce4SYangtao Li 12*fb038ce4SYangtao Li #define CLK_OSC12M 0 13*fb038ce4SYangtao Li #define CLK_PLL_CPUX 1 14*fb038ce4SYangtao Li #define CLK_PLL_DDR0 2 15*fb038ce4SYangtao Li 16*fb038ce4SYangtao Li /* PLL_PERIPH0 exported for PRCM */ 17*fb038ce4SYangtao Li 18*fb038ce4SYangtao Li #define CLK_PLL_PERIPH0_2X 4 19*fb038ce4SYangtao Li #define CLK_PLL_PERIPH1 5 20*fb038ce4SYangtao Li #define CLK_PLL_PERIPH1_2X 6 21*fb038ce4SYangtao Li #define CLK_PLL_GPU 7 22*fb038ce4SYangtao Li #define CLK_PLL_VIDEO0 8 23*fb038ce4SYangtao Li #define CLK_PLL_VIDEO0_2X 9 24*fb038ce4SYangtao Li #define CLK_PLL_VIDEO0_4X 10 25*fb038ce4SYangtao Li #define CLK_PLL_VIDEO1 11 26*fb038ce4SYangtao Li #define CLK_PLL_VIDEO1_2X 12 27*fb038ce4SYangtao Li #define CLK_PLL_VIDEO1_4X 13 28*fb038ce4SYangtao Li #define CLK_PLL_VIDEO2 14 29*fb038ce4SYangtao Li #define CLK_PLL_VIDEO2_2X 15 30*fb038ce4SYangtao Li #define CLK_PLL_VIDEO2_4X 16 31*fb038ce4SYangtao Li #define CLK_PLL_VIDEO3 17 32*fb038ce4SYangtao Li #define CLK_PLL_VIDEO3_2X 18 33*fb038ce4SYangtao Li #define CLK_PLL_VIDEO3_4X 19 34*fb038ce4SYangtao Li #define CLK_PLL_VE 20 35*fb038ce4SYangtao Li #define CLK_PLL_COM 21 36*fb038ce4SYangtao Li #define CLK_PLL_COM_AUDIO 22 37*fb038ce4SYangtao Li #define CLK_PLL_AUDIO 23 38*fb038ce4SYangtao Li 39*fb038ce4SYangtao Li /* CPUX clock exported for DVFS */ 40*fb038ce4SYangtao Li 41*fb038ce4SYangtao Li #define CLK_AXI 25 42*fb038ce4SYangtao Li #define CLK_CPUX_APB 26 43*fb038ce4SYangtao Li #define CLK_PSI_AHB1_AHB2 27 44*fb038ce4SYangtao Li #define CLK_AHB3 28 45*fb038ce4SYangtao Li 46*fb038ce4SYangtao Li /* APB1 clock exported for PIO */ 47*fb038ce4SYangtao Li 48*fb038ce4SYangtao Li #define CLK_APB2 30 49*fb038ce4SYangtao Li 50*fb038ce4SYangtao Li /* All module clocks and bus gates are exported except DRAM */ 51*fb038ce4SYangtao Li 52*fb038ce4SYangtao Li #define CLK_BUS_DRAM 58 53*fb038ce4SYangtao Li 54*fb038ce4SYangtao Li #define CLK_NUMBER (CLK_CSI_ISP + 1) 55*fb038ce4SYangtao Li 56*fb038ce4SYangtao Li #endif /* _CCU_SUN50I_A100_H_ */ 57