1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 20b7402dcSSudeep Holla /* 30b7402dcSSudeep Holla * ARM timer implementation, found in Integrator, Versatile and Realview 40b7402dcSSudeep Holla * platforms. Not all platforms support all registers and bits in these 50b7402dcSSudeep Holla * registers, so we mark them with A for Integrator AP, C for Integrator 60b7402dcSSudeep Holla * CP, V for Versatile and R for Realview. 70b7402dcSSudeep Holla * 80b7402dcSSudeep Holla * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview 90b7402dcSSudeep Holla * can have 16-bit or 32-bit selectable via a bit in the control register. 100b7402dcSSudeep Holla * 110b7402dcSSudeep Holla * Every SP804 contains two identical timers. 120b7402dcSSudeep Holla */ 1323c788cdSZhen Lei #define NR_TIMERS 2 140b7402dcSSudeep Holla #define TIMER_1_BASE 0x00 150b7402dcSSudeep Holla #define TIMER_2_BASE 0x20 160b7402dcSSudeep Holla 170b7402dcSSudeep Holla #define TIMER_LOAD 0x00 /* ACVR rw */ 180b7402dcSSudeep Holla #define TIMER_VALUE 0x04 /* ACVR ro */ 190b7402dcSSudeep Holla #define TIMER_CTRL 0x08 /* ACVR rw */ 200b7402dcSSudeep Holla #define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */ 210b7402dcSSudeep Holla #define TIMER_CTRL_32BIT (1 << 1) /* CVR */ 220b7402dcSSudeep Holla #define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */ 230b7402dcSSudeep Holla #define TIMER_CTRL_DIV16 (1 << 2) /* ACVR */ 240b7402dcSSudeep Holla #define TIMER_CTRL_DIV256 (2 << 2) /* ACVR */ 250b7402dcSSudeep Holla #define TIMER_CTRL_IE (1 << 5) /* VR */ 260b7402dcSSudeep Holla #define TIMER_CTRL_PERIODIC (1 << 6) /* ACVR */ 270b7402dcSSudeep Holla #define TIMER_CTRL_ENABLE (1 << 7) /* ACVR */ 280b7402dcSSudeep Holla 290b7402dcSSudeep Holla #define TIMER_INTCLR 0x0c /* ACVR wo */ 300b7402dcSSudeep Holla #define TIMER_RIS 0x10 /* CVR ro */ 310b7402dcSSudeep Holla #define TIMER_MIS 0x14 /* CVR ro */ 320b7402dcSSudeep Holla #define TIMER_BGLOAD 0x18 /* CVR rw */ 3323c788cdSZhen Lei 3423c788cdSZhen Lei struct sp804_timer { 3523c788cdSZhen Lei int load; 36*549437a4SZhen Lei int load_h; 3723c788cdSZhen Lei int value; 38*549437a4SZhen Lei int value_h; 3923c788cdSZhen Lei int ctrl; 4023c788cdSZhen Lei int intclr; 4123c788cdSZhen Lei int ris; 4223c788cdSZhen Lei int mis; 4323c788cdSZhen Lei int bgload; 44*549437a4SZhen Lei int bgload_h; 4523c788cdSZhen Lei int timer_base[NR_TIMERS]; 4623c788cdSZhen Lei int width; 4723c788cdSZhen Lei }; 4823c788cdSZhen Lei 4923c788cdSZhen Lei struct sp804_clkevt { 5023c788cdSZhen Lei void __iomem *base; 5123c788cdSZhen Lei void __iomem *load; 52*549437a4SZhen Lei void __iomem *load_h; 5323c788cdSZhen Lei void __iomem *value; 54*549437a4SZhen Lei void __iomem *value_h; 5523c788cdSZhen Lei void __iomem *ctrl; 5623c788cdSZhen Lei void __iomem *intclr; 5723c788cdSZhen Lei void __iomem *ris; 5823c788cdSZhen Lei void __iomem *mis; 5923c788cdSZhen Lei void __iomem *bgload; 60*549437a4SZhen Lei void __iomem *bgload_h; 6123c788cdSZhen Lei unsigned long reload; 6223c788cdSZhen Lei int width; 6323c788cdSZhen Lei }; 64