1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_DEV_H 3 #define __NITROX_DEV_H 4 5 #include <linux/dma-mapping.h> 6 #include <linux/interrupt.h> 7 #include <linux/pci.h> 8 #include <linux/if.h> 9 10 #define VERSION_LEN 32 11 12 /** 13 * struct nitrox_cmdq - NITROX command queue 14 * @cmd_qlock: command queue lock 15 * @resp_qlock: response queue lock 16 * @backlog_qlock: backlog queue lock 17 * @ndev: NITROX device 18 * @response_head: submitted request list 19 * @backlog_head: backlog queue 20 * @dbell_csr_addr: doorbell register address for this queue 21 * @base: command queue base address 22 * @dma: dma address of the base 23 * @pending_count: request pending at device 24 * @backlog_count: backlog request count 25 * @write_idx: next write index for the command 26 * @instr_size: command size 27 * @qno: command queue number 28 * @qsize: command queue size 29 * @unalign_base: unaligned base address 30 * @unalign_dma: unaligned dma address 31 */ 32 struct nitrox_cmdq { 33 spinlock_t cmd_qlock; 34 spinlock_t resp_qlock; 35 spinlock_t backlog_qlock; 36 37 struct nitrox_device *ndev; 38 struct list_head response_head; 39 struct list_head backlog_head; 40 41 u8 __iomem *dbell_csr_addr; 42 u8 *base; 43 dma_addr_t dma; 44 45 struct work_struct backlog_qflush; 46 47 atomic_t pending_count; 48 atomic_t backlog_count; 49 50 int write_idx; 51 u8 instr_size; 52 u8 qno; 53 u32 qsize; 54 55 u8 *unalign_base; 56 dma_addr_t unalign_dma; 57 }; 58 59 /** 60 * struct nitrox_hw - NITROX hardware information 61 * @partname: partname ex: CNN55xxx-xxx 62 * @fw_name: firmware version 63 * @freq: NITROX frequency 64 * @vendor_id: vendor ID 65 * @device_id: device ID 66 * @revision_id: revision ID 67 * @se_cores: number of symmetric cores 68 * @ae_cores: number of asymmetric cores 69 * @zip_cores: number of zip cores 70 */ 71 struct nitrox_hw { 72 char partname[IFNAMSIZ * 2]; 73 char fw_name[VERSION_LEN]; 74 75 int freq; 76 u16 vendor_id; 77 u16 device_id; 78 u8 revision_id; 79 80 u8 se_cores; 81 u8 ae_cores; 82 u8 zip_cores; 83 }; 84 85 struct nitrox_stats { 86 atomic64_t posted; 87 atomic64_t completed; 88 atomic64_t dropped; 89 }; 90 91 #define MAX_MSIX_VECTOR_NAME 20 92 /** 93 * vectors for queues (64 AE, 64 SE and 64 ZIP) and 94 * error condition/mailbox. 95 */ 96 #define MAX_MSIX_VECTORS 192 97 98 struct nitrox_msix { 99 struct msix_entry *entries; 100 char **names; 101 DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS); 102 u32 nr_entries; 103 }; 104 105 struct bh_data { 106 /* slc port completion count address */ 107 u8 __iomem *completion_cnt_csr_addr; 108 109 struct nitrox_cmdq *cmdq; 110 struct tasklet_struct resp_handler; 111 }; 112 113 struct nitrox_bh { 114 struct bh_data *slc; 115 }; 116 117 /* 118 * NITROX Device states 119 */ 120 enum ndev_state { 121 __NDEV_NOT_READY, 122 __NDEV_READY, 123 __NDEV_IN_RESET, 124 }; 125 126 /* NITROX support modes for VF(s) */ 127 enum vf_mode { 128 __NDEV_MODE_PF, 129 __NDEV_MODE_VF16, 130 __NDEV_MODE_VF32, 131 __NDEV_MODE_VF64, 132 __NDEV_MODE_VF128, 133 }; 134 135 #define __NDEV_SRIOV_BIT 0 136 137 /* command queue size */ 138 #define DEFAULT_CMD_QLEN 2048 139 /* command timeout in milliseconds */ 140 #define CMD_TIMEOUT 2000 141 142 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 143 144 #define NITROX_CSR_ADDR(ndev, offset) \ 145 ((ndev)->bar_addr + (offset)) 146 147 /** 148 * struct nitrox_device - NITROX Device Information. 149 * @list: pointer to linked list of devices 150 * @bar_addr: iomap address 151 * @pdev: PCI device information 152 * @state: NITROX device state 153 * @flags: flags to indicate device the features 154 * @timeout: Request timeout in jiffies 155 * @refcnt: Device usage count 156 * @idx: device index (0..N) 157 * @node: NUMA node id attached 158 * @qlen: Command queue length 159 * @nr_queues: Number of command queues 160 * @mode: Device mode PF/VF 161 * @ctx_pool: DMA pool for crypto context 162 * @pkt_inq: Packet input rings 163 * @msix: MSI-X information 164 * @bh: post processing work 165 * @hw: hardware information 166 * @debugfs_dir: debugfs directory 167 */ 168 struct nitrox_device { 169 struct list_head list; 170 171 u8 __iomem *bar_addr; 172 struct pci_dev *pdev; 173 174 atomic_t state; 175 unsigned long flags; 176 unsigned long timeout; 177 refcount_t refcnt; 178 179 u8 idx; 180 int node; 181 u16 qlen; 182 u16 nr_queues; 183 int num_vfs; 184 enum vf_mode mode; 185 186 struct dma_pool *ctx_pool; 187 struct nitrox_cmdq *pkt_inq; 188 189 struct nitrox_msix msix; 190 struct nitrox_bh bh; 191 192 struct nitrox_stats stats; 193 struct nitrox_hw hw; 194 #if IS_ENABLED(CONFIG_DEBUG_FS) 195 struct dentry *debugfs_dir; 196 #endif 197 }; 198 199 /** 200 * nitrox_read_csr - Read from device register 201 * @ndev: NITROX device 202 * @offset: offset of the register to read 203 * 204 * Returns: value read 205 */ 206 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 207 { 208 return readq(ndev->bar_addr + offset); 209 } 210 211 /** 212 * nitrox_write_csr - Write to device register 213 * @ndev: NITROX device 214 * @offset: offset of the register to write 215 * @value: value to write 216 */ 217 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 218 u64 value) 219 { 220 writeq(value, (ndev->bar_addr + offset)); 221 } 222 223 static inline bool nitrox_ready(struct nitrox_device *ndev) 224 { 225 return atomic_read(&ndev->state) == __NDEV_READY; 226 } 227 228 #ifdef CONFIG_DEBUG_FS 229 int nitrox_debugfs_init(struct nitrox_device *ndev); 230 void nitrox_debugfs_exit(struct nitrox_device *ndev); 231 #else 232 static inline int nitrox_debugfs_init(struct nitrox_device *ndev) 233 { 234 return 0; 235 } 236 237 static inline void nitrox_debugfs_exit(struct nitrox_device *ndev) 238 { } 239 #endif 240 241 #endif /* __NITROX_DEV_H */ 242