1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __NITROX_DEV_H 3 #define __NITROX_DEV_H 4 5 #include <linux/dma-mapping.h> 6 #include <linux/interrupt.h> 7 #include <linux/pci.h> 8 #include <linux/if.h> 9 10 #define VERSION_LEN 32 11 12 struct nitrox_cmdq { 13 /* command queue lock */ 14 spinlock_t cmdq_lock; 15 /* response list lock */ 16 spinlock_t response_lock; 17 /* backlog list lock */ 18 spinlock_t backlog_lock; 19 20 /* request submitted to chip, in progress */ 21 struct list_head response_head; 22 /* hw queue full, hold in backlog list */ 23 struct list_head backlog_head; 24 25 /* doorbell address */ 26 u8 __iomem *dbell_csr_addr; 27 /* base address of the queue */ 28 u8 *head; 29 30 struct nitrox_device *ndev; 31 /* flush pending backlog commands */ 32 struct work_struct backlog_qflush; 33 34 /* requests posted waiting for completion */ 35 atomic_t pending_count; 36 /* requests in backlog queues */ 37 atomic_t backlog_count; 38 39 int write_idx; 40 /* command size 32B/64B */ 41 u8 instr_size; 42 u8 qno; 43 u32 qsize; 44 45 /* unaligned addresses */ 46 u8 *head_unaligned; 47 dma_addr_t dma_unaligned; 48 /* dma address of the base */ 49 dma_addr_t dma; 50 }; 51 52 /** 53 * struct nitrox_hw - NITROX hardware information 54 * @partname: partname ex: CNN55xxx-xxx 55 * @fw_name: firmware version 56 * @freq: NITROX frequency 57 * @vendor_id: vendor ID 58 * @device_id: device ID 59 * @revision_id: revision ID 60 * @se_cores: number of symmetric cores 61 * @ae_cores: number of asymmetric cores 62 * @zip_cores: number of zip cores 63 */ 64 struct nitrox_hw { 65 char partname[IFNAMSIZ * 2]; 66 char fw_name[VERSION_LEN]; 67 68 int freq; 69 u16 vendor_id; 70 u16 device_id; 71 u8 revision_id; 72 73 u8 se_cores; 74 u8 ae_cores; 75 u8 zip_cores; 76 }; 77 78 struct nitrox_stats { 79 atomic64_t posted; 80 atomic64_t completed; 81 atomic64_t dropped; 82 }; 83 84 #define MAX_MSIX_VECTOR_NAME 20 85 /** 86 * vectors for queues (64 AE, 64 SE and 64 ZIP) and 87 * error condition/mailbox. 88 */ 89 #define MAX_MSIX_VECTORS 192 90 91 struct nitrox_msix { 92 struct msix_entry *entries; 93 char **names; 94 DECLARE_BITMAP(irqs, MAX_MSIX_VECTORS); 95 u32 nr_entries; 96 }; 97 98 struct bh_data { 99 /* slc port completion count address */ 100 u8 __iomem *completion_cnt_csr_addr; 101 102 struct nitrox_cmdq *cmdq; 103 struct tasklet_struct resp_handler; 104 }; 105 106 struct nitrox_bh { 107 struct bh_data *slc; 108 }; 109 110 /* 111 * NITROX Device states 112 */ 113 enum ndev_state { 114 __NDEV_NOT_READY, 115 __NDEV_READY, 116 __NDEV_IN_RESET, 117 }; 118 119 /* NITROX support modes for VF(s) */ 120 enum vf_mode { 121 __NDEV_MODE_PF, 122 __NDEV_MODE_VF16, 123 __NDEV_MODE_VF32, 124 __NDEV_MODE_VF64, 125 __NDEV_MODE_VF128, 126 }; 127 128 #define __NDEV_SRIOV_BIT 0 129 130 /* command queue size */ 131 #define DEFAULT_CMD_QLEN 2048 132 /* command timeout in milliseconds */ 133 #define CMD_TIMEOUT 2000 134 135 #define DEV(ndev) ((struct device *)(&(ndev)->pdev->dev)) 136 137 #define NITROX_CSR_ADDR(ndev, offset) \ 138 ((ndev)->bar_addr + (offset)) 139 140 /** 141 * struct nitrox_device - NITROX Device Information. 142 * @list: pointer to linked list of devices 143 * @bar_addr: iomap address 144 * @pdev: PCI device information 145 * @state: NITROX device state 146 * @flags: flags to indicate device the features 147 * @timeout: Request timeout in jiffies 148 * @refcnt: Device usage count 149 * @idx: device index (0..N) 150 * @node: NUMA node id attached 151 * @qlen: Command queue length 152 * @nr_queues: Number of command queues 153 * @mode: Device mode PF/VF 154 * @ctx_pool: DMA pool for crypto context 155 * @pkt_cmdqs: SE Command queues 156 * @msix: MSI-X information 157 * @bh: post processing work 158 * @hw: hardware information 159 * @debugfs_dir: debugfs directory 160 */ 161 struct nitrox_device { 162 struct list_head list; 163 164 u8 __iomem *bar_addr; 165 struct pci_dev *pdev; 166 167 atomic_t state; 168 unsigned long flags; 169 unsigned long timeout; 170 refcount_t refcnt; 171 172 u8 idx; 173 int node; 174 u16 qlen; 175 u16 nr_queues; 176 int num_vfs; 177 enum vf_mode mode; 178 179 struct dma_pool *ctx_pool; 180 struct nitrox_cmdq *pkt_cmdqs; 181 182 struct nitrox_msix msix; 183 struct nitrox_bh bh; 184 185 struct nitrox_stats stats; 186 struct nitrox_hw hw; 187 #if IS_ENABLED(CONFIG_DEBUG_FS) 188 struct dentry *debugfs_dir; 189 #endif 190 }; 191 192 /** 193 * nitrox_read_csr - Read from device register 194 * @ndev: NITROX device 195 * @offset: offset of the register to read 196 * 197 * Returns: value read 198 */ 199 static inline u64 nitrox_read_csr(struct nitrox_device *ndev, u64 offset) 200 { 201 return readq(ndev->bar_addr + offset); 202 } 203 204 /** 205 * nitrox_write_csr - Write to device register 206 * @ndev: NITROX device 207 * @offset: offset of the register to write 208 * @value: value to write 209 */ 210 static inline void nitrox_write_csr(struct nitrox_device *ndev, u64 offset, 211 u64 value) 212 { 213 writeq(value, (ndev->bar_addr + offset)); 214 } 215 216 static inline bool nitrox_ready(struct nitrox_device *ndev) 217 { 218 return atomic_read(&ndev->state) == __NDEV_READY; 219 } 220 221 #endif /* __NITROX_DEV_H */ 222