12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2ca2a07e4SChanwoo Choi /* 3ca2a07e4SChanwoo Choi * sm5502.h 4ca2a07e4SChanwoo Choi * 5ca2a07e4SChanwoo Choi * Copyright (c) 2014 Samsung Electronics Co., Ltd 6ca2a07e4SChanwoo Choi */ 7ca2a07e4SChanwoo Choi 8ca2a07e4SChanwoo Choi #ifndef __LINUX_EXTCON_SM5502_H 9ca2a07e4SChanwoo Choi #define __LINUX_EXTCON_SM5502_H 10ca2a07e4SChanwoo Choi 11ca2a07e4SChanwoo Choi /* SM5502 registers */ 12ca2a07e4SChanwoo Choi enum sm5502_reg { 13ca2a07e4SChanwoo Choi SM5502_REG_DEVICE_ID = 0x01, 14ca2a07e4SChanwoo Choi SM5502_REG_CONTROL, 15ca2a07e4SChanwoo Choi SM5502_REG_INT1, 16ca2a07e4SChanwoo Choi SM5502_REG_INT2, 17ca2a07e4SChanwoo Choi SM5502_REG_INTMASK1, 18ca2a07e4SChanwoo Choi SM5502_REG_INTMASK2, 19ca2a07e4SChanwoo Choi SM5502_REG_ADC, 20ca2a07e4SChanwoo Choi SM5502_REG_TIMING_SET1, 21ca2a07e4SChanwoo Choi SM5502_REG_TIMING_SET2, 22ca2a07e4SChanwoo Choi SM5502_REG_DEV_TYPE1, 23ca2a07e4SChanwoo Choi SM5502_REG_DEV_TYPE2, 24ca2a07e4SChanwoo Choi SM5502_REG_BUTTON1, 25ca2a07e4SChanwoo Choi SM5502_REG_BUTTON2, 26ca2a07e4SChanwoo Choi SM5502_REG_CAR_KIT_STATUS, 27ca2a07e4SChanwoo Choi SM5502_REG_RSVD1, 28ca2a07e4SChanwoo Choi SM5502_REG_RSVD2, 29ca2a07e4SChanwoo Choi SM5502_REG_RSVD3, 30ca2a07e4SChanwoo Choi SM5502_REG_RSVD4, 31ca2a07e4SChanwoo Choi SM5502_REG_MANUAL_SW1, 32ca2a07e4SChanwoo Choi SM5502_REG_MANUAL_SW2, 33ca2a07e4SChanwoo Choi SM5502_REG_DEV_TYPE3, 34ca2a07e4SChanwoo Choi SM5502_REG_RSVD5, 35ca2a07e4SChanwoo Choi SM5502_REG_RSVD6, 36ca2a07e4SChanwoo Choi SM5502_REG_RSVD7, 37ca2a07e4SChanwoo Choi SM5502_REG_RSVD8, 38ca2a07e4SChanwoo Choi SM5502_REG_RSVD9, 39ca2a07e4SChanwoo Choi SM5502_REG_RESET, 40ca2a07e4SChanwoo Choi SM5502_REG_RSVD10, 41ca2a07e4SChanwoo Choi SM5502_REG_RESERVED_ID1, 42ca2a07e4SChanwoo Choi SM5502_REG_RSVD11, 43ca2a07e4SChanwoo Choi SM5502_REG_RSVD12, 44ca2a07e4SChanwoo Choi SM5502_REG_RESERVED_ID2, 45ca2a07e4SChanwoo Choi SM5502_REG_RSVD13, 46ca2a07e4SChanwoo Choi SM5502_REG_OCP, 47ca2a07e4SChanwoo Choi SM5502_REG_RSVD14, 48ca2a07e4SChanwoo Choi SM5502_REG_RSVD15, 49ca2a07e4SChanwoo Choi SM5502_REG_RSVD16, 50ca2a07e4SChanwoo Choi SM5502_REG_RSVD17, 51ca2a07e4SChanwoo Choi SM5502_REG_RSVD18, 52ca2a07e4SChanwoo Choi SM5502_REG_RSVD19, 53ca2a07e4SChanwoo Choi SM5502_REG_RSVD20, 54ca2a07e4SChanwoo Choi SM5502_REG_RSVD21, 55ca2a07e4SChanwoo Choi SM5502_REG_RSVD22, 56ca2a07e4SChanwoo Choi SM5502_REG_RSVD23, 57ca2a07e4SChanwoo Choi SM5502_REG_RSVD24, 58ca2a07e4SChanwoo Choi SM5502_REG_RSVD25, 59ca2a07e4SChanwoo Choi SM5502_REG_RSVD26, 60ca2a07e4SChanwoo Choi SM5502_REG_RSVD27, 61ca2a07e4SChanwoo Choi SM5502_REG_RSVD28, 62ca2a07e4SChanwoo Choi SM5502_REG_RSVD29, 63ca2a07e4SChanwoo Choi SM5502_REG_RSVD30, 64ca2a07e4SChanwoo Choi SM5502_REG_RSVD31, 65ca2a07e4SChanwoo Choi SM5502_REG_RSVD32, 66ca2a07e4SChanwoo Choi SM5502_REG_RSVD33, 67ca2a07e4SChanwoo Choi SM5502_REG_RSVD34, 68ca2a07e4SChanwoo Choi SM5502_REG_RSVD35, 69ca2a07e4SChanwoo Choi SM5502_REG_RSVD36, 70ca2a07e4SChanwoo Choi SM5502_REG_RESERVED_ID3, 71ca2a07e4SChanwoo Choi 72ca2a07e4SChanwoo Choi SM5502_REG_END, 73ca2a07e4SChanwoo Choi }; 74ca2a07e4SChanwoo Choi 75ca2a07e4SChanwoo Choi /* Define SM5502 MASK/SHIFT constant */ 76ca2a07e4SChanwoo Choi #define SM5502_REG_DEVICE_ID_VENDOR_SHIFT 0 77ca2a07e4SChanwoo Choi #define SM5502_REG_DEVICE_ID_VERSION_SHIFT 3 78ca2a07e4SChanwoo Choi #define SM5502_REG_DEVICE_ID_VENDOR_MASK (0x3 << SM5502_REG_DEVICE_ID_VENDOR_SHIFT) 79ca2a07e4SChanwoo Choi #define SM5502_REG_DEVICE_ID_VERSION_MASK (0x1f << SM5502_REG_DEVICE_ID_VERSION_SHIFT) 80ca2a07e4SChanwoo Choi 81ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_MASK_INT_SHIFT 0 82ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_WAIT_SHIFT 1 83ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_MANUAL_SW_SHIFT 2 84ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_RAW_DATA_SHIFT 3 85ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_SW_OPEN_SHIFT 4 86ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT) 87ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT) 88ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT) 89ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT) 90ca2a07e4SChanwoo Choi #define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT) 91ca2a07e4SChanwoo Choi 92*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_CHGTYP_SHIFT 5 93*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_USBCHDEN_SHIFT 6 94*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_ADC_EN_SHIFT 7 95*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_CHGTYP_MASK (0x1 << SM5504_REG_CONTROL_CHGTYP_SHIFT) 96*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_USBCHDEN_MASK (0x1 << SM5504_REG_CONTROL_USBCHDEN_SHIFT) 97*d97c0ff5SStephan Gerhold #define SM5504_REG_CONTROL_ADC_EN_MASK (0x1 << SM5504_REG_CONTROL_ADC_EN_SHIFT) 98*d97c0ff5SStephan Gerhold 99ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_ATTACH_SHIFT 0 100ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_DETACH_SHIFT 1 101ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_KP_SHIFT 2 102ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_LKP_SHIFT 3 103ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_LKR_SHIFT 4 104ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OVP_EVENT_SHIFT 5 105ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OCP_EVENT_SHIFT 6 106ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT 7 107ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT) 108ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIFT) 109ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_KP_MASK (0x1 << SM5502_REG_INTM1_KP_SHIFT) 110ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_LKP_MASK (0x1 << SM5502_REG_INTM1_LKP_SHIFT) 111ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_LKR_MASK (0x1 << SM5502_REG_INTM1_LKR_SHIFT) 112ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OVP_EVENT_SHIFT) 113ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OCP_EVENT_MASK (0x1 << SM5502_REG_INTM1_OCP_EVENT_SHIFT) 114ca2a07e4SChanwoo Choi #define SM5502_REG_INTM1_OVP_OCP_DIS_MASK (0x1 << SM5502_REG_INTM1_OVP_OCP_DIS_SHIFT) 115ca2a07e4SChanwoo Choi 116ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_VBUS_DET_SHIFT 0 117ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_REV_ACCE_SHIFT 1 118ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_ADC_CHG_SHIFT 2 119ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_STUCK_KEY_SHIFT 3 120ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT 4 121ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_MHL_SHIFT 5 122ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_VBUS_DET_MASK (0x1 << SM5502_REG_INTM2_VBUS_DET_SHIFT) 123ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_REV_ACCE_MASK (0x1 << SM5502_REG_INTM2_REV_ACCE_SHIFT) 124ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_ADC_CHG_MASK (0x1 << SM5502_REG_INTM2_ADC_CHG_SHIFT) 125ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_STUCK_KEY_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_SHIFT) 126ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_STUCK_KEY_RCV_MASK (0x1 << SM5502_REG_INTM2_STUCK_KEY_RCV_SHIFT) 127ca2a07e4SChanwoo Choi #define SM5502_REG_INTM2_MHL_MASK (0x1 << SM5502_REG_INTM2_MHL_SHIFT) 128ca2a07e4SChanwoo Choi 129*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_ATTACH_SHIFT 0 130*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_DETACH_SHIFT 1 131*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_CHG_DET_SHIFT 2 132*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_DCD_OUT_SHIFT 3 133*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_OVP_EVENT_SHIFT 4 134*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_CONNECT_SHIFT 5 135*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_ADC_CHG_SHIFT 6 136*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_ATTACH_MASK (0x1 << SM5504_REG_INTM1_ATTACH_SHIFT) 137*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_DETACH_MASK (0x1 << SM5504_REG_INTM1_DETACH_SHIFT) 138*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_CHG_DET_MASK (0x1 << SM5504_REG_INTM1_CHG_DET_SHIFT) 139*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_DCD_OUT_MASK (0x1 << SM5504_REG_INTM1_DCD_OUT_SHIFT) 140*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_OVP_EVENT_MASK (0x1 << SM5504_REG_INTM1_OVP_EVENT_SHIFT) 141*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_CONNECT_MASK (0x1 << SM5504_REG_INTM1_CONNECT_SHIFT) 142*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM1_ADC_CHG_MASK (0x1 << SM5504_REG_INTM1_ADC_CHG_SHIFT) 143*d97c0ff5SStephan Gerhold 144*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_RID_CHG_SHIFT 0 145*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_UVLO_SHIFT 1 146*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_POR_SHIFT 2 147*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OVP_FET_SHIFT 4 148*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OCP_LATCH_SHIFT 5 149*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OCP_EVENT_SHIFT 6 150*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT 7 151*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_RID_CHG_MASK (0x1 << SM5504_REG_INTM2_RID_CHG_SHIFT) 152*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_UVLO_MASK (0x1 << SM5504_REG_INTM2_UVLO_SHIFT) 153*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_POR_MASK (0x1 << SM5504_REG_INTM2_POR_SHIFT) 154*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OVP_FET_MASK (0x1 << SM5504_REG_INTM2_OVP_FET_SHIFT) 155*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OCP_LATCH_MASK (0x1 << SM5504_REG_INTM2_OCP_LATCH_SHIFT) 156*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OCP_EVENT_SHIFT) 157*d97c0ff5SStephan Gerhold #define SM5504_REG_INTM2_OVP_OCP_EVENT_MASK (0x1 << SM5504_REG_INTM2_OVP_OCP_EVENT_SHIFT) 158*d97c0ff5SStephan Gerhold 159ca2a07e4SChanwoo Choi #define SM5502_REG_ADC_SHIFT 0 160ca2a07e4SChanwoo Choi #define SM5502_REG_ADC_MASK (0x1f << SM5502_REG_ADC_SHIFT) 161ca2a07e4SChanwoo Choi 162ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT 4 163ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET1_KEY_PRESS_MASK (0xf << SM5502_REG_TIMING_SET1_KEY_PRESS_SHIFT) 164ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_100MS 0x0 165ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_200MS 0x1 166ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_300MS 0x2 167ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_400MS 0x3 168ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_500MS 0x4 169ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_600MS 0x5 170ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_700MS 0x6 171ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_800MS 0x7 172ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_900MS 0x8 173ca2a07e4SChanwoo Choi #define TIMING_KEY_PRESS_1000MS 0x9 174ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET1_ADC_DET_SHIFT 0 175ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET1_ADC_DET_MASK (0xf << SM5502_REG_TIMING_SET1_ADC_DET_SHIFT) 176ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_50MS 0x0 177ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_100MS 0x1 178ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_150MS 0x2 179ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_200MS 0x3 180ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_300MS 0x4 181ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_400MS 0x5 182ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_500MS 0x6 183ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_600MS 0x7 184ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_700MS 0x8 185ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_800MS 0x9 186ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_900MS 0xA 187ca2a07e4SChanwoo Choi #define TIMING_ADC_DET_1000MS 0xB 188ca2a07e4SChanwoo Choi 189ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT 4 190ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET2_SW_WAIT_MASK (0xf << SM5502_REG_TIMING_SET2_SW_WAIT_SHIFT) 191ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_10MS 0x0 192ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_30MS 0x1 193ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_50MS 0x2 194ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_70MS 0x3 195ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_90MS 0x4 196ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_110MS 0x5 197ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_130MS 0x6 198ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_150MS 0x7 199ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_170MS 0x8 200ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_190MS 0x9 201ca2a07e4SChanwoo Choi #define TIMING_SW_WAIT_210MS 0xA 202ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT 0 203ca2a07e4SChanwoo Choi #define SM5502_REG_TIMING_SET2_LONG_KEY_MASK (0xf << SM5502_REG_TIMING_SET2_LONG_KEY_SHIFT) 204ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_300MS 0x0 205ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_400MS 0x1 206ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_500MS 0x2 207ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_600MS 0x3 208ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_700MS 0x4 209ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_800MS 0x5 210ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_900MS 0x6 211ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1000MS 0x7 212ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1100MS 0x8 213ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1200MS 0x9 214ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1300MS 0xA 215ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1400MS 0xB 216ca2a07e4SChanwoo Choi #define TIMING_LONG_KEY_1500MS 0xC 217ca2a07e4SChanwoo Choi 218ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT 0 219ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT 1 220ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT 2 221ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_UART_SHIFT 3 222ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT 4 223ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT 5 224ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT 6 225ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT 7 226ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE1_SHIFT) 227ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_AUDIO_TYPE1__MASK (0x1 << SM5502_REG_DEV_TYPE1_AUDIO_TYPE2_SHIFT) 228ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_SDP_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_SDP_SHIFT) 229ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_UART_MASK (0x1 << SM5502_REG_DEV_TYPE1_UART_SHIFT) 230ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_MASK (0x1 << SM5502_REG_DEV_TYPE1_CAR_KIT_CHARGER_SHIFT) 231ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_CHG_SHIFT) 232ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_DEDICATED_CHG_MASK (0x1 << SM5502_REG_DEV_TYPE1_DEDICATED_CHG_SHIFT) 233ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5502_REG_DEV_TYPE1_USB_OTG_SHIFT) 234ca2a07e4SChanwoo Choi 235*d97c0ff5SStephan Gerhold #define SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT 0 236*d97c0ff5SStephan Gerhold #define SM5504_REG_DEV_TYPE1_USB_OTG_MASK (0x1 << SM5504_REG_DEV_TYPE1_USB_OTG_SHIFT) 237*d97c0ff5SStephan Gerhold 238ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT 0 239ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT 1 240ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT 2 241ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT 3 242ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_PPD_SHIFT 4 243ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_TTY_SHIFT 5 244ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT 6 245ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_USB_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_ON_SHIFT) 246ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_USB_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_USB_OFF_SHIFT) 247ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_UART_ON_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_ON_SHIFT) 248ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_JIG_UART_OFF_MASK (0x1 << SM5502_REG_DEV_TYPE2_JIG_UART_OFF_SHIFT) 249ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_PPD_MASK (0x1 << SM5502_REG_DEV_TYPE2_PPD_SHIFT) 250ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_TTY_MASK (0x1 << SM5502_REG_DEV_TYPE2_TTY_SHIFT) 251ca2a07e4SChanwoo Choi #define SM5502_REG_DEV_TYPE2_AV_CABLE_MASK (0x1 << SM5502_REG_DEV_TYPE2_AV_CABLE_SHIFT) 252ca2a07e4SChanwoo Choi 253ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT 0 254ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_DP_SHIFT 2 255ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_DM_SHIFT 5 256ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_VBUSIN_MASK (0x3 << SM5502_REG_MANUAL_SW1_VBUSIN_SHIFT) 257ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_DP_MASK (0x7 << SM5502_REG_MANUAL_SW1_DP_SHIFT) 258ca2a07e4SChanwoo Choi #define SM5502_REG_MANUAL_SW1_DM_MASK (0x7 << SM5502_REG_MANUAL_SW1_DM_SHIFT) 259ca2a07e4SChanwoo Choi #define VBUSIN_SWITCH_OPEN 0x0 260ca2a07e4SChanwoo Choi #define VBUSIN_SWITCH_VBUSOUT 0x1 261ca2a07e4SChanwoo Choi #define VBUSIN_SWITCH_MIC 0x2 262ca2a07e4SChanwoo Choi #define VBUSIN_SWITCH_VBUSOUT_WITH_USB 0x3 263ca2a07e4SChanwoo Choi #define DM_DP_CON_SWITCH_OPEN 0x0 264ca2a07e4SChanwoo Choi #define DM_DP_CON_SWITCH_USB 0x1 265ca2a07e4SChanwoo Choi #define DM_DP_CON_SWITCH_AUDIO 0x2 266ca2a07e4SChanwoo Choi #define DM_DP_CON_SWITCH_UART 0x3 267ca2a07e4SChanwoo Choi #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 268ca2a07e4SChanwoo Choi | (DM_DP_CON_SWITCH_OPEN <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 269ca2a07e4SChanwoo Choi #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 270ca2a07e4SChanwoo Choi | (DM_DP_CON_SWITCH_USB <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 271ca2a07e4SChanwoo Choi #define DM_DP_SWITCH_AUDIO ((DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 272ca2a07e4SChanwoo Choi | (DM_DP_CON_SWITCH_AUDIO <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 273ca2a07e4SChanwoo Choi #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DP_SHIFT) \ 274ca2a07e4SChanwoo Choi | (DM_DP_CON_SWITCH_UART <<SM5502_REG_MANUAL_SW1_DM_SHIFT)) 275ca2a07e4SChanwoo Choi 27669426350SStephan Gerhold #define SM5502_REG_RESET_MASK (0x1) 27769426350SStephan Gerhold 278ca2a07e4SChanwoo Choi /* SM5502 Interrupts */ 279ca2a07e4SChanwoo Choi enum sm5502_irq { 280ca2a07e4SChanwoo Choi /* INT1 */ 281ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_ATTACH, 282ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_DETACH, 283ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_KP, 284ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_LKP, 285ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_LKR, 286ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_OVP_EVENT, 287ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_OCP_EVENT, 288ca2a07e4SChanwoo Choi SM5502_IRQ_INT1_OVP_OCP_DIS, 289ca2a07e4SChanwoo Choi 290ca2a07e4SChanwoo Choi /* INT2 */ 291ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_VBUS_DET, 292ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_REV_ACCE, 293ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_ADC_CHG, 294ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_STUCK_KEY, 295ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_STUCK_KEY_RCV, 296ca2a07e4SChanwoo Choi SM5502_IRQ_INT2_MHL, 297ca2a07e4SChanwoo Choi 298ca2a07e4SChanwoo Choi SM5502_IRQ_NUM, 299ca2a07e4SChanwoo Choi }; 300ca2a07e4SChanwoo Choi 301ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_ATTACH_MASK BIT(0) 302ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_DETACH_MASK BIT(1) 303ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_KP_MASK BIT(2) 304ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_LKP_MASK BIT(3) 305ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_LKR_MASK BIT(4) 306ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_OVP_EVENT_MASK BIT(5) 307ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_OCP_EVENT_MASK BIT(6) 308ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT1_OVP_OCP_DIS_MASK BIT(7) 309ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_VBUS_DET_MASK BIT(0) 310ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_REV_ACCE_MASK BIT(1) 311ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_ADC_CHG_MASK BIT(2) 312ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_STUCK_KEY_MASK BIT(3) 313ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_STUCK_KEY_RCV_MASK BIT(4) 314ca2a07e4SChanwoo Choi #define SM5502_IRQ_INT2_MHL_MASK BIT(5) 315ca2a07e4SChanwoo Choi 316*d97c0ff5SStephan Gerhold /* SM5504 Interrupts */ 317*d97c0ff5SStephan Gerhold enum sm5504_irq { 318*d97c0ff5SStephan Gerhold /* INT1 */ 319*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_ATTACH, 320*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_DETACH, 321*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_CHG_DET, 322*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_DCD_OUT, 323*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_OVP_EVENT, 324*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_CONNECT, 325*d97c0ff5SStephan Gerhold SM5504_IRQ_INT1_ADC_CHG, 326*d97c0ff5SStephan Gerhold 327*d97c0ff5SStephan Gerhold /* INT2 */ 328*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_RID_CHG, 329*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_UVLO, 330*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_POR, 331*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_OVP_FET, 332*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_OCP_LATCH, 333*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_OCP_EVENT, 334*d97c0ff5SStephan Gerhold SM5504_IRQ_INT2_OVP_OCP_EVENT, 335*d97c0ff5SStephan Gerhold 336*d97c0ff5SStephan Gerhold SM5504_IRQ_NUM, 337*d97c0ff5SStephan Gerhold }; 338*d97c0ff5SStephan Gerhold 339*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_ATTACH_MASK BIT(0) 340*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_DETACH_MASK BIT(1) 341*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_CHG_DET_MASK BIT(2) 342*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_DCD_OUT_MASK BIT(3) 343*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_OVP_MASK BIT(4) 344*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_CONNECT_MASK BIT(5) 345*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT1_ADC_CHG_MASK BIT(6) 346*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_RID_CHG_MASK BIT(0) 347*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_UVLO_MASK BIT(1) 348*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_POR_MASK BIT(2) 349*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_OVP_FET_MASK BIT(4) 350*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_OCP_LATCH_MASK BIT(5) 351*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_OCP_EVENT_MASK BIT(6) 352*d97c0ff5SStephan Gerhold #define SM5504_IRQ_INT2_OVP_OCP_EVENT_MASK BIT(7) 353*d97c0ff5SStephan Gerhold 354ca2a07e4SChanwoo Choi #endif /* __LINUX_EXTCON_SM5502_H */ 355