1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include <subdev/bios.h> 25 #include <subdev/bios/bit.h> 26 #include <subdev/bios/bmp.h> 27 #include <subdev/bios/conn.h> 28 #include <subdev/bios/dcb.h> 29 #include <subdev/bios/dp.h> 30 #include <subdev/bios/gpio.h> 31 #include <subdev/bios/init.h> 32 #include <subdev/bios/ramcfg.h> 33 34 #include <subdev/devinit.h> 35 #include <subdev/gpio.h> 36 #include <subdev/i2c.h> 37 #include <subdev/vga.h> 38 39 #define bioslog(lvl, fmt, args...) do { \ 40 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \ 41 init->offset, init_exec(init) ? \ 42 '0' + (init->nested - 1) : ' ', ##args); \ 43 } while(0) 44 #define cont(fmt, args...) do { \ 45 if (init->subdev->debug >= NV_DBG_TRACE) \ 46 printk(fmt, ##args); \ 47 } while(0) 48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args) 49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args) 50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args) 51 52 /****************************************************************************** 53 * init parser control flow helpers 54 *****************************************************************************/ 55 56 static inline bool 57 init_exec(struct nvbios_init *init) 58 { 59 return (init->execute == 1) || ((init->execute & 5) == 5); 60 } 61 62 static inline void 63 init_exec_set(struct nvbios_init *init, bool exec) 64 { 65 if (exec) init->execute &= 0xfd; 66 else init->execute |= 0x02; 67 } 68 69 static inline void 70 init_exec_inv(struct nvbios_init *init) 71 { 72 init->execute ^= 0x02; 73 } 74 75 static inline void 76 init_exec_force(struct nvbios_init *init, bool exec) 77 { 78 if (exec) init->execute |= 0x04; 79 else init->execute &= 0xfb; 80 } 81 82 /****************************************************************************** 83 * init parser wrappers for normal register/i2c/whatever accessors 84 *****************************************************************************/ 85 86 static inline int 87 init_or(struct nvbios_init *init) 88 { 89 if (init_exec(init)) { 90 if (init->outp) 91 return ffs(init->outp->or) - 1; 92 error("script needs OR!!\n"); 93 } 94 return 0; 95 } 96 97 static inline int 98 init_link(struct nvbios_init *init) 99 { 100 if (init_exec(init)) { 101 if (init->outp) 102 return !(init->outp->sorconf.link & 1); 103 error("script needs OR link\n"); 104 } 105 return 0; 106 } 107 108 static inline int 109 init_head(struct nvbios_init *init) 110 { 111 if (init_exec(init)) { 112 if (init->head >= 0) 113 return init->head; 114 error("script needs head\n"); 115 } 116 return 0; 117 } 118 119 static u8 120 init_conn(struct nvbios_init *init) 121 { 122 struct nvkm_bios *bios = init->subdev->device->bios; 123 struct nvbios_connE connE; 124 u8 ver, hdr; 125 u32 conn; 126 127 if (init_exec(init)) { 128 if (init->outp) { 129 conn = init->outp->connector; 130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); 131 if (conn) 132 return connE.type; 133 } 134 135 error("script needs connector type\n"); 136 } 137 138 return 0xff; 139 } 140 141 static inline u32 142 init_nvreg(struct nvbios_init *init, u32 reg) 143 { 144 struct nvkm_devinit *devinit = init->subdev->device->devinit; 145 146 /* C51 (at least) sometimes has the lower bits set which the VBIOS 147 * interprets to mean that access needs to go through certain IO 148 * ports instead. The NVIDIA binary driver has been seen to access 149 * these through the NV register address, so lets assume we can 150 * do the same 151 */ 152 reg &= ~0x00000003; 153 154 /* GF8+ display scripts need register addresses mangled a bit to 155 * select a specific CRTC/OR 156 */ 157 if (init->subdev->device->card_type >= NV_50) { 158 if (reg & 0x80000000) { 159 reg += init_head(init) * 0x800; 160 reg &= ~0x80000000; 161 } 162 163 if (reg & 0x40000000) { 164 reg += init_or(init) * 0x800; 165 reg &= ~0x40000000; 166 if (reg & 0x20000000) { 167 reg += init_link(init) * 0x80; 168 reg &= ~0x20000000; 169 } 170 } 171 } 172 173 if (reg & ~0x00fffffc) 174 warn("unknown bits in register 0x%08x\n", reg); 175 176 return nvkm_devinit_mmio(devinit, reg); 177 } 178 179 static u32 180 init_rd32(struct nvbios_init *init, u32 reg) 181 { 182 struct nvkm_device *device = init->subdev->device; 183 reg = init_nvreg(init, reg); 184 if (reg != ~0 && init_exec(init)) 185 return nvkm_rd32(device, reg); 186 return 0x00000000; 187 } 188 189 static void 190 init_wr32(struct nvbios_init *init, u32 reg, u32 val) 191 { 192 struct nvkm_device *device = init->subdev->device; 193 reg = init_nvreg(init, reg); 194 if (reg != ~0 && init_exec(init)) 195 nvkm_wr32(device, reg, val); 196 } 197 198 static u32 199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) 200 { 201 struct nvkm_device *device = init->subdev->device; 202 reg = init_nvreg(init, reg); 203 if (reg != ~0 && init_exec(init)) { 204 u32 tmp = nvkm_rd32(device, reg); 205 nvkm_wr32(device, reg, (tmp & ~mask) | val); 206 return tmp; 207 } 208 return 0x00000000; 209 } 210 211 static u8 212 init_rdport(struct nvbios_init *init, u16 port) 213 { 214 if (init_exec(init)) 215 return nvkm_rdport(init->subdev->device, init->head, port); 216 return 0x00; 217 } 218 219 static void 220 init_wrport(struct nvbios_init *init, u16 port, u8 value) 221 { 222 if (init_exec(init)) 223 nvkm_wrport(init->subdev->device, init->head, port, value); 224 } 225 226 static u8 227 init_rdvgai(struct nvbios_init *init, u16 port, u8 index) 228 { 229 struct nvkm_subdev *subdev = init->subdev; 230 if (init_exec(init)) { 231 int head = init->head < 0 ? 0 : init->head; 232 return nvkm_rdvgai(subdev->device, head, port, index); 233 } 234 return 0x00; 235 } 236 237 static void 238 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) 239 { 240 struct nvkm_device *device = init->subdev->device; 241 242 /* force head 0 for updates to cr44, it only exists on first head */ 243 if (device->card_type < NV_50) { 244 if (port == 0x03d4 && index == 0x44) 245 init->head = 0; 246 } 247 248 if (init_exec(init)) { 249 int head = init->head < 0 ? 0 : init->head; 250 nvkm_wrvgai(device, head, port, index, value); 251 } 252 253 /* select head 1 if cr44 write selected it */ 254 if (device->card_type < NV_50) { 255 if (port == 0x03d4 && index == 0x44 && value == 3) 256 init->head = 1; 257 } 258 } 259 260 static struct i2c_adapter * 261 init_i2c(struct nvbios_init *init, int index) 262 { 263 struct nvkm_i2c *i2c = init->subdev->device->i2c; 264 struct nvkm_i2c_bus *bus; 265 266 if (index == 0xff) { 267 index = NVKM_I2C_BUS_PRI; 268 if (init->outp && init->outp->i2c_upper_default) 269 index = NVKM_I2C_BUS_SEC; 270 } else 271 if (index == 0x80) { 272 index = NVKM_I2C_BUS_PRI; 273 } else 274 if (index == 0x81) { 275 index = NVKM_I2C_BUS_SEC; 276 } 277 278 bus = nvkm_i2c_bus_find(i2c, index); 279 return bus ? &bus->i2c : NULL; 280 } 281 282 static int 283 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) 284 { 285 struct i2c_adapter *adap = init_i2c(init, index); 286 if (adap && init_exec(init)) 287 return nvkm_rdi2cr(adap, addr, reg); 288 return -ENODEV; 289 } 290 291 static int 292 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) 293 { 294 struct i2c_adapter *adap = init_i2c(init, index); 295 if (adap && init_exec(init)) 296 return nvkm_wri2cr(adap, addr, reg, val); 297 return -ENODEV; 298 } 299 300 static struct nvkm_i2c_aux * 301 init_aux(struct nvbios_init *init) 302 { 303 struct nvkm_i2c *i2c = init->subdev->device->i2c; 304 if (!init->outp) { 305 if (init_exec(init)) 306 error("script needs output for aux\n"); 307 return NULL; 308 } 309 return nvkm_i2c_aux_find(i2c, init->outp->i2c_index); 310 } 311 312 static u8 313 init_rdauxr(struct nvbios_init *init, u32 addr) 314 { 315 struct nvkm_i2c_aux *aux = init_aux(init); 316 u8 data; 317 318 if (aux && init_exec(init)) { 319 int ret = nvkm_rdaux(aux, addr, &data, 1); 320 if (ret == 0) 321 return data; 322 trace("auxch read failed with %d\n", ret); 323 } 324 325 return 0x00; 326 } 327 328 static int 329 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) 330 { 331 struct nvkm_i2c_aux *aux = init_aux(init); 332 if (aux && init_exec(init)) { 333 int ret = nvkm_wraux(aux, addr, &data, 1); 334 if (ret) 335 trace("auxch write failed with %d\n", ret); 336 return ret; 337 } 338 return -ENODEV; 339 } 340 341 static void 342 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) 343 { 344 struct nvkm_devinit *devinit = init->subdev->device->devinit; 345 if (init_exec(init)) { 346 int ret = nvkm_devinit_pll_set(devinit, id, freq); 347 if (ret) 348 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); 349 } 350 } 351 352 /****************************************************************************** 353 * parsing of bios structures that are required to execute init tables 354 *****************************************************************************/ 355 356 static u16 357 init_table(struct nvkm_bios *bios, u16 *len) 358 { 359 struct bit_entry bit_I; 360 361 if (!bit_entry(bios, 'I', &bit_I)) { 362 *len = bit_I.length; 363 return bit_I.offset; 364 } 365 366 if (bmp_version(bios) >= 0x0510) { 367 *len = 14; 368 return bios->bmp_offset + 75; 369 } 370 371 return 0x0000; 372 } 373 374 static u16 375 init_table_(struct nvbios_init *init, u16 offset, const char *name) 376 { 377 struct nvkm_bios *bios = init->subdev->device->bios; 378 u16 len, data = init_table(bios, &len); 379 if (data) { 380 if (len >= offset + 2) { 381 data = nvbios_rd16(bios, data + offset); 382 if (data) 383 return data; 384 385 warn("%s pointer invalid\n", name); 386 return 0x0000; 387 } 388 389 warn("init data too short for %s pointer", name); 390 return 0x0000; 391 } 392 393 warn("init data not found\n"); 394 return 0x0000; 395 } 396 397 #define init_script_table(b) init_table_((b), 0x00, "script table") 398 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") 399 #define init_macro_table(b) init_table_((b), 0x04, "macro table") 400 #define init_condition_table(b) init_table_((b), 0x06, "condition table") 401 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") 402 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") 403 #define init_function_table(b) init_table_((b), 0x0c, "function table") 404 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); 405 406 static u16 407 init_script(struct nvkm_bios *bios, int index) 408 { 409 struct nvbios_init init = { .subdev = &bios->subdev }; 410 u16 bmp_ver = bmp_version(bios), data; 411 412 if (bmp_ver && bmp_ver < 0x0510) { 413 if (index > 1 || bmp_ver < 0x0100) 414 return 0x0000; 415 416 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); 417 return nvbios_rd16(bios, data + (index * 2)); 418 } 419 420 data = init_script_table(&init); 421 if (data) 422 return nvbios_rd16(bios, data + (index * 2)); 423 424 return 0x0000; 425 } 426 427 static u16 428 init_unknown_script(struct nvkm_bios *bios) 429 { 430 u16 len, data = init_table(bios, &len); 431 if (data && len >= 16) 432 return nvbios_rd16(bios, data + 14); 433 return 0x0000; 434 } 435 436 static u8 437 init_ram_restrict_group_count(struct nvbios_init *init) 438 { 439 return nvbios_ramcfg_count(init->subdev->device->bios); 440 } 441 442 static u8 443 init_ram_restrict(struct nvbios_init *init) 444 { 445 /* This appears to be the behaviour of the VBIOS parser, and *is* 446 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to 447 * avoid fucking up the memory controller (somehow) by reading it 448 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. 449 * 450 * Preserving the non-caching behaviour on earlier chipsets just 451 * in case *not* re-reading the strap causes similar breakage. 452 */ 453 if (!init->ramcfg || init->subdev->device->bios->version.major < 0x70) 454 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); 455 return (init->ramcfg & 0x7fffffff); 456 } 457 458 static u8 459 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) 460 { 461 struct nvkm_bios *bios = init->subdev->device->bios; 462 u16 table = init_xlat_table(init); 463 if (table) { 464 u16 data = nvbios_rd16(bios, table + (index * 2)); 465 if (data) 466 return nvbios_rd08(bios, data + offset); 467 warn("xlat table pointer %d invalid\n", index); 468 } 469 return 0x00; 470 } 471 472 /****************************************************************************** 473 * utility functions used by various init opcode handlers 474 *****************************************************************************/ 475 476 static bool 477 init_condition_met(struct nvbios_init *init, u8 cond) 478 { 479 struct nvkm_bios *bios = init->subdev->device->bios; 480 u16 table = init_condition_table(init); 481 if (table) { 482 u32 reg = nvbios_rd32(bios, table + (cond * 12) + 0); 483 u32 msk = nvbios_rd32(bios, table + (cond * 12) + 4); 484 u32 val = nvbios_rd32(bios, table + (cond * 12) + 8); 485 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", 486 cond, reg, msk, val); 487 return (init_rd32(init, reg) & msk) == val; 488 } 489 return false; 490 } 491 492 static bool 493 init_io_condition_met(struct nvbios_init *init, u8 cond) 494 { 495 struct nvkm_bios *bios = init->subdev->device->bios; 496 u16 table = init_io_condition_table(init); 497 if (table) { 498 u16 port = nvbios_rd16(bios, table + (cond * 5) + 0); 499 u8 index = nvbios_rd08(bios, table + (cond * 5) + 2); 500 u8 mask = nvbios_rd08(bios, table + (cond * 5) + 3); 501 u8 value = nvbios_rd08(bios, table + (cond * 5) + 4); 502 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", 503 cond, port, index, mask, value); 504 return (init_rdvgai(init, port, index) & mask) == value; 505 } 506 return false; 507 } 508 509 static bool 510 init_io_flag_condition_met(struct nvbios_init *init, u8 cond) 511 { 512 struct nvkm_bios *bios = init->subdev->device->bios; 513 u16 table = init_io_flag_condition_table(init); 514 if (table) { 515 u16 port = nvbios_rd16(bios, table + (cond * 9) + 0); 516 u8 index = nvbios_rd08(bios, table + (cond * 9) + 2); 517 u8 mask = nvbios_rd08(bios, table + (cond * 9) + 3); 518 u8 shift = nvbios_rd08(bios, table + (cond * 9) + 4); 519 u16 data = nvbios_rd16(bios, table + (cond * 9) + 5); 520 u8 dmask = nvbios_rd08(bios, table + (cond * 9) + 7); 521 u8 value = nvbios_rd08(bios, table + (cond * 9) + 8); 522 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; 523 return (nvbios_rd08(bios, data + ioval) & dmask) == value; 524 } 525 return false; 526 } 527 528 static inline u32 529 init_shift(u32 data, u8 shift) 530 { 531 if (shift < 0x80) 532 return data >> shift; 533 return data << (0x100 - shift); 534 } 535 536 static u32 537 init_tmds_reg(struct nvbios_init *init, u8 tmds) 538 { 539 /* For mlv < 0x80, it is an index into a table of TMDS base addresses. 540 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by 541 * CR58 for CR57 = 0 to index a table of offsets to the basic 542 * 0x6808b0 address. 543 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by 544 * CR58 for CR57 = 0 to index a table of offsets to the basic 545 * 0x6808b0 address, and then flip the offset by 8. 546 */ 547 const int pramdac_offset[13] = { 548 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; 549 const u32 pramdac_table[4] = { 550 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; 551 552 if (tmds >= 0x80) { 553 if (init->outp) { 554 u32 dacoffset = pramdac_offset[init->outp->or]; 555 if (tmds == 0x81) 556 dacoffset ^= 8; 557 return 0x6808b0 + dacoffset; 558 } 559 560 if (init_exec(init)) 561 error("tmds opcodes need dcb\n"); 562 } else { 563 if (tmds < ARRAY_SIZE(pramdac_table)) 564 return pramdac_table[tmds]; 565 566 error("tmds selector 0x%02x unknown\n", tmds); 567 } 568 569 return 0; 570 } 571 572 /****************************************************************************** 573 * init opcode handlers 574 *****************************************************************************/ 575 576 /** 577 * init_reserved - stub for various unknown/unused single-byte opcodes 578 * 579 */ 580 static void 581 init_reserved(struct nvbios_init *init) 582 { 583 struct nvkm_bios *bios = init->subdev->device->bios; 584 u8 opcode = nvbios_rd08(bios, init->offset); 585 u8 length, i; 586 587 switch (opcode) { 588 case 0xaa: 589 length = 4; 590 break; 591 default: 592 length = 1; 593 break; 594 } 595 596 trace("RESERVED 0x%02x\t", opcode); 597 for (i = 1; i < length; i++) 598 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i)); 599 cont("\n"); 600 init->offset += length; 601 } 602 603 /** 604 * INIT_DONE - opcode 0x71 605 * 606 */ 607 static void 608 init_done(struct nvbios_init *init) 609 { 610 trace("DONE\n"); 611 init->offset = 0x0000; 612 } 613 614 /** 615 * INIT_IO_RESTRICT_PROG - opcode 0x32 616 * 617 */ 618 static void 619 init_io_restrict_prog(struct nvbios_init *init) 620 { 621 struct nvkm_bios *bios = init->subdev->device->bios; 622 u16 port = nvbios_rd16(bios, init->offset + 1); 623 u8 index = nvbios_rd08(bios, init->offset + 3); 624 u8 mask = nvbios_rd08(bios, init->offset + 4); 625 u8 shift = nvbios_rd08(bios, init->offset + 5); 626 u8 count = nvbios_rd08(bios, init->offset + 6); 627 u32 reg = nvbios_rd32(bios, init->offset + 7); 628 u8 conf, i; 629 630 trace("IO_RESTRICT_PROG\tR[0x%06x] = " 631 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", 632 reg, port, index, mask, shift); 633 init->offset += 11; 634 635 conf = (init_rdvgai(init, port, index) & mask) >> shift; 636 for (i = 0; i < count; i++) { 637 u32 data = nvbios_rd32(bios, init->offset); 638 639 if (i == conf) { 640 trace("\t0x%08x *\n", data); 641 init_wr32(init, reg, data); 642 } else { 643 trace("\t0x%08x\n", data); 644 } 645 646 init->offset += 4; 647 } 648 trace("}]\n"); 649 } 650 651 /** 652 * INIT_REPEAT - opcode 0x33 653 * 654 */ 655 static void 656 init_repeat(struct nvbios_init *init) 657 { 658 struct nvkm_bios *bios = init->subdev->device->bios; 659 u8 count = nvbios_rd08(bios, init->offset + 1); 660 u16 repeat = init->repeat; 661 662 trace("REPEAT\t0x%02x\n", count); 663 init->offset += 2; 664 665 init->repeat = init->offset; 666 init->repend = init->offset; 667 while (count--) { 668 init->offset = init->repeat; 669 nvbios_exec(init); 670 if (count) 671 trace("REPEAT\t0x%02x\n", count); 672 } 673 init->offset = init->repend; 674 init->repeat = repeat; 675 } 676 677 /** 678 * INIT_IO_RESTRICT_PLL - opcode 0x34 679 * 680 */ 681 static void 682 init_io_restrict_pll(struct nvbios_init *init) 683 { 684 struct nvkm_bios *bios = init->subdev->device->bios; 685 u16 port = nvbios_rd16(bios, init->offset + 1); 686 u8 index = nvbios_rd08(bios, init->offset + 3); 687 u8 mask = nvbios_rd08(bios, init->offset + 4); 688 u8 shift = nvbios_rd08(bios, init->offset + 5); 689 s8 iofc = nvbios_rd08(bios, init->offset + 6); 690 u8 count = nvbios_rd08(bios, init->offset + 7); 691 u32 reg = nvbios_rd32(bios, init->offset + 8); 692 u8 conf, i; 693 694 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " 695 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", 696 reg, port, index, mask, shift, iofc); 697 init->offset += 12; 698 699 conf = (init_rdvgai(init, port, index) & mask) >> shift; 700 for (i = 0; i < count; i++) { 701 u32 freq = nvbios_rd16(bios, init->offset) * 10; 702 703 if (i == conf) { 704 trace("\t%dkHz *\n", freq); 705 if (iofc > 0 && init_io_flag_condition_met(init, iofc)) 706 freq *= 2; 707 init_prog_pll(init, reg, freq); 708 } else { 709 trace("\t%dkHz\n", freq); 710 } 711 712 init->offset += 2; 713 } 714 trace("}]\n"); 715 } 716 717 /** 718 * INIT_END_REPEAT - opcode 0x36 719 * 720 */ 721 static void 722 init_end_repeat(struct nvbios_init *init) 723 { 724 trace("END_REPEAT\n"); 725 init->offset += 1; 726 727 if (init->repeat) { 728 init->repend = init->offset; 729 init->offset = 0; 730 } 731 } 732 733 /** 734 * INIT_COPY - opcode 0x37 735 * 736 */ 737 static void 738 init_copy(struct nvbios_init *init) 739 { 740 struct nvkm_bios *bios = init->subdev->device->bios; 741 u32 reg = nvbios_rd32(bios, init->offset + 1); 742 u8 shift = nvbios_rd08(bios, init->offset + 5); 743 u8 smask = nvbios_rd08(bios, init->offset + 6); 744 u16 port = nvbios_rd16(bios, init->offset + 7); 745 u8 index = nvbios_rd08(bios, init->offset + 9); 746 u8 mask = nvbios_rd08(bios, init->offset + 10); 747 u8 data; 748 749 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " 750 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", 751 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", 752 (shift & 0x80) ? (0x100 - shift) : shift, smask); 753 init->offset += 11; 754 755 data = init_rdvgai(init, port, index) & mask; 756 data |= init_shift(init_rd32(init, reg), shift) & smask; 757 init_wrvgai(init, port, index, data); 758 } 759 760 /** 761 * INIT_NOT - opcode 0x38 762 * 763 */ 764 static void 765 init_not(struct nvbios_init *init) 766 { 767 trace("NOT\n"); 768 init->offset += 1; 769 init_exec_inv(init); 770 } 771 772 /** 773 * INIT_IO_FLAG_CONDITION - opcode 0x39 774 * 775 */ 776 static void 777 init_io_flag_condition(struct nvbios_init *init) 778 { 779 struct nvkm_bios *bios = init->subdev->device->bios; 780 u8 cond = nvbios_rd08(bios, init->offset + 1); 781 782 trace("IO_FLAG_CONDITION\t0x%02x\n", cond); 783 init->offset += 2; 784 785 if (!init_io_flag_condition_met(init, cond)) 786 init_exec_set(init, false); 787 } 788 789 /** 790 * INIT_GENERIC_CONDITION - opcode 0x3a 791 * 792 */ 793 static void 794 init_generic_condition(struct nvbios_init *init) 795 { 796 struct nvkm_bios *bios = init->subdev->device->bios; 797 struct nvbios_dpout info; 798 u8 cond = nvbios_rd08(bios, init->offset + 1); 799 u8 size = nvbios_rd08(bios, init->offset + 2); 800 u8 ver, hdr, cnt, len; 801 u16 data; 802 803 trace("GENERIC_CONDITION\t0x%02x 0x%02x\n", cond, size); 804 init->offset += 3; 805 806 switch (cond) { 807 case 0: 808 if (init_conn(init) != DCB_CONNECTOR_eDP) 809 init_exec_set(init, false); 810 break; 811 case 1: 812 case 2: 813 if ( init->outp && 814 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, 815 (init->outp->or << 0) | 816 (init->outp->sorconf.link << 6), 817 &ver, &hdr, &cnt, &len, &info))) 818 { 819 if (!(info.flags & cond)) 820 init_exec_set(init, false); 821 break; 822 } 823 824 if (init_exec(init)) 825 warn("script needs dp output table data\n"); 826 break; 827 case 5: 828 if (!(init_rdauxr(init, 0x0d) & 1)) 829 init_exec_set(init, false); 830 break; 831 default: 832 warn("INIT_GENERIC_CONDITON: unknown 0x%02x\n", cond); 833 init->offset += size; 834 break; 835 } 836 } 837 838 /** 839 * INIT_IO_MASK_OR - opcode 0x3b 840 * 841 */ 842 static void 843 init_io_mask_or(struct nvbios_init *init) 844 { 845 struct nvkm_bios *bios = init->subdev->device->bios; 846 u8 index = nvbios_rd08(bios, init->offset + 1); 847 u8 or = init_or(init); 848 u8 data; 849 850 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); 851 init->offset += 2; 852 853 data = init_rdvgai(init, 0x03d4, index); 854 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); 855 } 856 857 /** 858 * INIT_IO_OR - opcode 0x3c 859 * 860 */ 861 static void 862 init_io_or(struct nvbios_init *init) 863 { 864 struct nvkm_bios *bios = init->subdev->device->bios; 865 u8 index = nvbios_rd08(bios, init->offset + 1); 866 u8 or = init_or(init); 867 u8 data; 868 869 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); 870 init->offset += 2; 871 872 data = init_rdvgai(init, 0x03d4, index); 873 init_wrvgai(init, 0x03d4, index, data | (1 << or)); 874 } 875 876 /** 877 * INIT_ANDN_REG - opcode 0x47 878 * 879 */ 880 static void 881 init_andn_reg(struct nvbios_init *init) 882 { 883 struct nvkm_bios *bios = init->subdev->device->bios; 884 u32 reg = nvbios_rd32(bios, init->offset + 1); 885 u32 mask = nvbios_rd32(bios, init->offset + 5); 886 887 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask); 888 init->offset += 9; 889 890 init_mask(init, reg, mask, 0); 891 } 892 893 /** 894 * INIT_OR_REG - opcode 0x48 895 * 896 */ 897 static void 898 init_or_reg(struct nvbios_init *init) 899 { 900 struct nvkm_bios *bios = init->subdev->device->bios; 901 u32 reg = nvbios_rd32(bios, init->offset + 1); 902 u32 mask = nvbios_rd32(bios, init->offset + 5); 903 904 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask); 905 init->offset += 9; 906 907 init_mask(init, reg, 0, mask); 908 } 909 910 /** 911 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 912 * 913 */ 914 static void 915 init_idx_addr_latched(struct nvbios_init *init) 916 { 917 struct nvkm_bios *bios = init->subdev->device->bios; 918 u32 creg = nvbios_rd32(bios, init->offset + 1); 919 u32 dreg = nvbios_rd32(bios, init->offset + 5); 920 u32 mask = nvbios_rd32(bios, init->offset + 9); 921 u32 data = nvbios_rd32(bios, init->offset + 13); 922 u8 count = nvbios_rd08(bios, init->offset + 17); 923 924 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); 925 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); 926 init->offset += 18; 927 928 while (count--) { 929 u8 iaddr = nvbios_rd08(bios, init->offset + 0); 930 u8 idata = nvbios_rd08(bios, init->offset + 1); 931 932 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); 933 init->offset += 2; 934 935 init_wr32(init, dreg, idata); 936 init_mask(init, creg, ~mask, data | iaddr); 937 } 938 } 939 940 /** 941 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a 942 * 943 */ 944 static void 945 init_io_restrict_pll2(struct nvbios_init *init) 946 { 947 struct nvkm_bios *bios = init->subdev->device->bios; 948 u16 port = nvbios_rd16(bios, init->offset + 1); 949 u8 index = nvbios_rd08(bios, init->offset + 3); 950 u8 mask = nvbios_rd08(bios, init->offset + 4); 951 u8 shift = nvbios_rd08(bios, init->offset + 5); 952 u8 count = nvbios_rd08(bios, init->offset + 6); 953 u32 reg = nvbios_rd32(bios, init->offset + 7); 954 u8 conf, i; 955 956 trace("IO_RESTRICT_PLL2\t" 957 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", 958 reg, port, index, mask, shift); 959 init->offset += 11; 960 961 conf = (init_rdvgai(init, port, index) & mask) >> shift; 962 for (i = 0; i < count; i++) { 963 u32 freq = nvbios_rd32(bios, init->offset); 964 if (i == conf) { 965 trace("\t%dkHz *\n", freq); 966 init_prog_pll(init, reg, freq); 967 } else { 968 trace("\t%dkHz\n", freq); 969 } 970 init->offset += 4; 971 } 972 trace("}]\n"); 973 } 974 975 /** 976 * INIT_PLL2 - opcode 0x4b 977 * 978 */ 979 static void 980 init_pll2(struct nvbios_init *init) 981 { 982 struct nvkm_bios *bios = init->subdev->device->bios; 983 u32 reg = nvbios_rd32(bios, init->offset + 1); 984 u32 freq = nvbios_rd32(bios, init->offset + 5); 985 986 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 987 init->offset += 9; 988 989 init_prog_pll(init, reg, freq); 990 } 991 992 /** 993 * INIT_I2C_BYTE - opcode 0x4c 994 * 995 */ 996 static void 997 init_i2c_byte(struct nvbios_init *init) 998 { 999 struct nvkm_bios *bios = init->subdev->device->bios; 1000 u8 index = nvbios_rd08(bios, init->offset + 1); 1001 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1002 u8 count = nvbios_rd08(bios, init->offset + 3); 1003 1004 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1005 init->offset += 4; 1006 1007 while (count--) { 1008 u8 reg = nvbios_rd08(bios, init->offset + 0); 1009 u8 mask = nvbios_rd08(bios, init->offset + 1); 1010 u8 data = nvbios_rd08(bios, init->offset + 2); 1011 int val; 1012 1013 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); 1014 init->offset += 3; 1015 1016 val = init_rdi2cr(init, index, addr, reg); 1017 if (val < 0) 1018 continue; 1019 init_wri2cr(init, index, addr, reg, (val & mask) | data); 1020 } 1021 } 1022 1023 /** 1024 * INIT_ZM_I2C_BYTE - opcode 0x4d 1025 * 1026 */ 1027 static void 1028 init_zm_i2c_byte(struct nvbios_init *init) 1029 { 1030 struct nvkm_bios *bios = init->subdev->device->bios; 1031 u8 index = nvbios_rd08(bios, init->offset + 1); 1032 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1033 u8 count = nvbios_rd08(bios, init->offset + 3); 1034 1035 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); 1036 init->offset += 4; 1037 1038 while (count--) { 1039 u8 reg = nvbios_rd08(bios, init->offset + 0); 1040 u8 data = nvbios_rd08(bios, init->offset + 1); 1041 1042 trace("\t[0x%02x] = 0x%02x\n", reg, data); 1043 init->offset += 2; 1044 1045 init_wri2cr(init, index, addr, reg, data); 1046 } 1047 } 1048 1049 /** 1050 * INIT_ZM_I2C - opcode 0x4e 1051 * 1052 */ 1053 static void 1054 init_zm_i2c(struct nvbios_init *init) 1055 { 1056 struct nvkm_bios *bios = init->subdev->device->bios; 1057 u8 index = nvbios_rd08(bios, init->offset + 1); 1058 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 1059 u8 count = nvbios_rd08(bios, init->offset + 3); 1060 u8 data[256], i; 1061 1062 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); 1063 init->offset += 4; 1064 1065 for (i = 0; i < count; i++) { 1066 data[i] = nvbios_rd08(bios, init->offset); 1067 trace("\t0x%02x\n", data[i]); 1068 init->offset++; 1069 } 1070 1071 if (init_exec(init)) { 1072 struct i2c_adapter *adap = init_i2c(init, index); 1073 struct i2c_msg msg = { 1074 .addr = addr, .flags = 0, .len = count, .buf = data, 1075 }; 1076 int ret; 1077 1078 if (adap && (ret = i2c_transfer(adap, &msg, 1)) != 1) 1079 warn("i2c wr failed, %d\n", ret); 1080 } 1081 } 1082 1083 /** 1084 * INIT_TMDS - opcode 0x4f 1085 * 1086 */ 1087 static void 1088 init_tmds(struct nvbios_init *init) 1089 { 1090 struct nvkm_bios *bios = init->subdev->device->bios; 1091 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1092 u8 addr = nvbios_rd08(bios, init->offset + 2); 1093 u8 mask = nvbios_rd08(bios, init->offset + 3); 1094 u8 data = nvbios_rd08(bios, init->offset + 4); 1095 u32 reg = init_tmds_reg(init, tmds); 1096 1097 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", 1098 tmds, addr, mask, data); 1099 init->offset += 5; 1100 1101 if (reg == 0) 1102 return; 1103 1104 init_wr32(init, reg + 0, addr | 0x00010000); 1105 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); 1106 init_wr32(init, reg + 0, addr); 1107 } 1108 1109 /** 1110 * INIT_ZM_TMDS_GROUP - opcode 0x50 1111 * 1112 */ 1113 static void 1114 init_zm_tmds_group(struct nvbios_init *init) 1115 { 1116 struct nvkm_bios *bios = init->subdev->device->bios; 1117 u8 tmds = nvbios_rd08(bios, init->offset + 1); 1118 u8 count = nvbios_rd08(bios, init->offset + 2); 1119 u32 reg = init_tmds_reg(init, tmds); 1120 1121 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); 1122 init->offset += 3; 1123 1124 while (count--) { 1125 u8 addr = nvbios_rd08(bios, init->offset + 0); 1126 u8 data = nvbios_rd08(bios, init->offset + 1); 1127 1128 trace("\t[0x%02x] = 0x%02x\n", addr, data); 1129 init->offset += 2; 1130 1131 init_wr32(init, reg + 4, data); 1132 init_wr32(init, reg + 0, addr); 1133 } 1134 } 1135 1136 /** 1137 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 1138 * 1139 */ 1140 static void 1141 init_cr_idx_adr_latch(struct nvbios_init *init) 1142 { 1143 struct nvkm_bios *bios = init->subdev->device->bios; 1144 u8 addr0 = nvbios_rd08(bios, init->offset + 1); 1145 u8 addr1 = nvbios_rd08(bios, init->offset + 2); 1146 u8 base = nvbios_rd08(bios, init->offset + 3); 1147 u8 count = nvbios_rd08(bios, init->offset + 4); 1148 u8 save0; 1149 1150 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); 1151 init->offset += 5; 1152 1153 save0 = init_rdvgai(init, 0x03d4, addr0); 1154 while (count--) { 1155 u8 data = nvbios_rd08(bios, init->offset); 1156 1157 trace("\t\t[0x%02x] = 0x%02x\n", base, data); 1158 init->offset += 1; 1159 1160 init_wrvgai(init, 0x03d4, addr0, base++); 1161 init_wrvgai(init, 0x03d4, addr1, data); 1162 } 1163 init_wrvgai(init, 0x03d4, addr0, save0); 1164 } 1165 1166 /** 1167 * INIT_CR - opcode 0x52 1168 * 1169 */ 1170 static void 1171 init_cr(struct nvbios_init *init) 1172 { 1173 struct nvkm_bios *bios = init->subdev->device->bios; 1174 u8 addr = nvbios_rd08(bios, init->offset + 1); 1175 u8 mask = nvbios_rd08(bios, init->offset + 2); 1176 u8 data = nvbios_rd08(bios, init->offset + 3); 1177 u8 val; 1178 1179 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 1180 init->offset += 4; 1181 1182 val = init_rdvgai(init, 0x03d4, addr) & mask; 1183 init_wrvgai(init, 0x03d4, addr, val | data); 1184 } 1185 1186 /** 1187 * INIT_ZM_CR - opcode 0x53 1188 * 1189 */ 1190 static void 1191 init_zm_cr(struct nvbios_init *init) 1192 { 1193 struct nvkm_bios *bios = init->subdev->device->bios; 1194 u8 addr = nvbios_rd08(bios, init->offset + 1); 1195 u8 data = nvbios_rd08(bios, init->offset + 2); 1196 1197 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); 1198 init->offset += 3; 1199 1200 init_wrvgai(init, 0x03d4, addr, data); 1201 } 1202 1203 /** 1204 * INIT_ZM_CR_GROUP - opcode 0x54 1205 * 1206 */ 1207 static void 1208 init_zm_cr_group(struct nvbios_init *init) 1209 { 1210 struct nvkm_bios *bios = init->subdev->device->bios; 1211 u8 count = nvbios_rd08(bios, init->offset + 1); 1212 1213 trace("ZM_CR_GROUP\n"); 1214 init->offset += 2; 1215 1216 while (count--) { 1217 u8 addr = nvbios_rd08(bios, init->offset + 0); 1218 u8 data = nvbios_rd08(bios, init->offset + 1); 1219 1220 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); 1221 init->offset += 2; 1222 1223 init_wrvgai(init, 0x03d4, addr, data); 1224 } 1225 } 1226 1227 /** 1228 * INIT_CONDITION_TIME - opcode 0x56 1229 * 1230 */ 1231 static void 1232 init_condition_time(struct nvbios_init *init) 1233 { 1234 struct nvkm_bios *bios = init->subdev->device->bios; 1235 u8 cond = nvbios_rd08(bios, init->offset + 1); 1236 u8 retry = nvbios_rd08(bios, init->offset + 2); 1237 u8 wait = min((u16)retry * 50, 100); 1238 1239 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); 1240 init->offset += 3; 1241 1242 if (!init_exec(init)) 1243 return; 1244 1245 while (wait--) { 1246 if (init_condition_met(init, cond)) 1247 return; 1248 mdelay(20); 1249 } 1250 1251 init_exec_set(init, false); 1252 } 1253 1254 /** 1255 * INIT_LTIME - opcode 0x57 1256 * 1257 */ 1258 static void 1259 init_ltime(struct nvbios_init *init) 1260 { 1261 struct nvkm_bios *bios = init->subdev->device->bios; 1262 u16 msec = nvbios_rd16(bios, init->offset + 1); 1263 1264 trace("LTIME\t0x%04x\n", msec); 1265 init->offset += 3; 1266 1267 if (init_exec(init)) 1268 mdelay(msec); 1269 } 1270 1271 /** 1272 * INIT_ZM_REG_SEQUENCE - opcode 0x58 1273 * 1274 */ 1275 static void 1276 init_zm_reg_sequence(struct nvbios_init *init) 1277 { 1278 struct nvkm_bios *bios = init->subdev->device->bios; 1279 u32 base = nvbios_rd32(bios, init->offset + 1); 1280 u8 count = nvbios_rd08(bios, init->offset + 5); 1281 1282 trace("ZM_REG_SEQUENCE\t0x%02x\n", count); 1283 init->offset += 6; 1284 1285 while (count--) { 1286 u32 data = nvbios_rd32(bios, init->offset); 1287 1288 trace("\t\tR[0x%06x] = 0x%08x\n", base, data); 1289 init->offset += 4; 1290 1291 init_wr32(init, base, data); 1292 base += 4; 1293 } 1294 } 1295 1296 /** 1297 * INIT_PLL_INDIRECT - opcode 0x59 1298 * 1299 */ 1300 static void 1301 init_pll_indirect(struct nvbios_init *init) 1302 { 1303 struct nvkm_bios *bios = init->subdev->device->bios; 1304 u32 reg = nvbios_rd32(bios, init->offset + 1); 1305 u16 addr = nvbios_rd16(bios, init->offset + 5); 1306 u32 freq = (u32)nvbios_rd16(bios, addr) * 1000; 1307 1308 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n", 1309 reg, addr, freq); 1310 init->offset += 7; 1311 1312 init_prog_pll(init, reg, freq); 1313 } 1314 1315 /** 1316 * INIT_ZM_REG_INDIRECT - opcode 0x5a 1317 * 1318 */ 1319 static void 1320 init_zm_reg_indirect(struct nvbios_init *init) 1321 { 1322 struct nvkm_bios *bios = init->subdev->device->bios; 1323 u32 reg = nvbios_rd32(bios, init->offset + 1); 1324 u16 addr = nvbios_rd16(bios, init->offset + 5); 1325 u32 data = nvbios_rd32(bios, addr); 1326 1327 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n", 1328 reg, addr, data); 1329 init->offset += 7; 1330 1331 init_wr32(init, addr, data); 1332 } 1333 1334 /** 1335 * INIT_SUB_DIRECT - opcode 0x5b 1336 * 1337 */ 1338 static void 1339 init_sub_direct(struct nvbios_init *init) 1340 { 1341 struct nvkm_bios *bios = init->subdev->device->bios; 1342 u16 addr = nvbios_rd16(bios, init->offset + 1); 1343 u16 save; 1344 1345 trace("SUB_DIRECT\t0x%04x\n", addr); 1346 1347 if (init_exec(init)) { 1348 save = init->offset; 1349 init->offset = addr; 1350 if (nvbios_exec(init)) { 1351 error("error parsing sub-table\n"); 1352 return; 1353 } 1354 init->offset = save; 1355 } 1356 1357 init->offset += 3; 1358 } 1359 1360 /** 1361 * INIT_JUMP - opcode 0x5c 1362 * 1363 */ 1364 static void 1365 init_jump(struct nvbios_init *init) 1366 { 1367 struct nvkm_bios *bios = init->subdev->device->bios; 1368 u16 offset = nvbios_rd16(bios, init->offset + 1); 1369 1370 trace("JUMP\t0x%04x\n", offset); 1371 1372 if (init_exec(init)) 1373 init->offset = offset; 1374 else 1375 init->offset += 3; 1376 } 1377 1378 /** 1379 * INIT_I2C_IF - opcode 0x5e 1380 * 1381 */ 1382 static void 1383 init_i2c_if(struct nvbios_init *init) 1384 { 1385 struct nvkm_bios *bios = init->subdev->device->bios; 1386 u8 index = nvbios_rd08(bios, init->offset + 1); 1387 u8 addr = nvbios_rd08(bios, init->offset + 2); 1388 u8 reg = nvbios_rd08(bios, init->offset + 3); 1389 u8 mask = nvbios_rd08(bios, init->offset + 4); 1390 u8 data = nvbios_rd08(bios, init->offset + 5); 1391 u8 value; 1392 1393 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", 1394 index, addr, reg, mask, data); 1395 init->offset += 6; 1396 init_exec_force(init, true); 1397 1398 value = init_rdi2cr(init, index, addr, reg); 1399 if ((value & mask) != data) 1400 init_exec_set(init, false); 1401 1402 init_exec_force(init, false); 1403 } 1404 1405 /** 1406 * INIT_COPY_NV_REG - opcode 0x5f 1407 * 1408 */ 1409 static void 1410 init_copy_nv_reg(struct nvbios_init *init) 1411 { 1412 struct nvkm_bios *bios = init->subdev->device->bios; 1413 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1414 u8 shift = nvbios_rd08(bios, init->offset + 5); 1415 u32 smask = nvbios_rd32(bios, init->offset + 6); 1416 u32 sxor = nvbios_rd32(bios, init->offset + 10); 1417 u32 dreg = nvbios_rd32(bios, init->offset + 14); 1418 u32 dmask = nvbios_rd32(bios, init->offset + 18); 1419 u32 data; 1420 1421 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " 1422 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", 1423 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", 1424 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); 1425 init->offset += 22; 1426 1427 data = init_shift(init_rd32(init, sreg), shift); 1428 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); 1429 } 1430 1431 /** 1432 * INIT_ZM_INDEX_IO - opcode 0x62 1433 * 1434 */ 1435 static void 1436 init_zm_index_io(struct nvbios_init *init) 1437 { 1438 struct nvkm_bios *bios = init->subdev->device->bios; 1439 u16 port = nvbios_rd16(bios, init->offset + 1); 1440 u8 index = nvbios_rd08(bios, init->offset + 3); 1441 u8 data = nvbios_rd08(bios, init->offset + 4); 1442 1443 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); 1444 init->offset += 5; 1445 1446 init_wrvgai(init, port, index, data); 1447 } 1448 1449 /** 1450 * INIT_COMPUTE_MEM - opcode 0x63 1451 * 1452 */ 1453 static void 1454 init_compute_mem(struct nvbios_init *init) 1455 { 1456 struct nvkm_devinit *devinit = init->subdev->device->devinit; 1457 1458 trace("COMPUTE_MEM\n"); 1459 init->offset += 1; 1460 1461 init_exec_force(init, true); 1462 if (init_exec(init)) 1463 nvkm_devinit_meminit(devinit); 1464 init_exec_force(init, false); 1465 } 1466 1467 /** 1468 * INIT_RESET - opcode 0x65 1469 * 1470 */ 1471 static void 1472 init_reset(struct nvbios_init *init) 1473 { 1474 struct nvkm_bios *bios = init->subdev->device->bios; 1475 u32 reg = nvbios_rd32(bios, init->offset + 1); 1476 u32 data1 = nvbios_rd32(bios, init->offset + 5); 1477 u32 data2 = nvbios_rd32(bios, init->offset + 9); 1478 u32 savepci19; 1479 1480 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); 1481 init->offset += 13; 1482 init_exec_force(init, true); 1483 1484 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); 1485 init_wr32(init, reg, data1); 1486 udelay(10); 1487 init_wr32(init, reg, data2); 1488 init_wr32(init, 0x00184c, savepci19); 1489 init_mask(init, 0x001850, 0x00000001, 0x00000000); 1490 1491 init_exec_force(init, false); 1492 } 1493 1494 /** 1495 * INIT_CONFIGURE_MEM - opcode 0x66 1496 * 1497 */ 1498 static u16 1499 init_configure_mem_clk(struct nvbios_init *init) 1500 { 1501 u16 mdata = bmp_mem_init_table(init->subdev->device->bios); 1502 if (mdata) 1503 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; 1504 return mdata; 1505 } 1506 1507 static void 1508 init_configure_mem(struct nvbios_init *init) 1509 { 1510 struct nvkm_bios *bios = init->subdev->device->bios; 1511 u16 mdata, sdata; 1512 u32 addr, data; 1513 1514 trace("CONFIGURE_MEM\n"); 1515 init->offset += 1; 1516 1517 if (bios->version.major > 2) { 1518 init_done(init); 1519 return; 1520 } 1521 init_exec_force(init, true); 1522 1523 mdata = init_configure_mem_clk(init); 1524 sdata = bmp_sdr_seq_table(bios); 1525 if (nvbios_rd08(bios, mdata) & 0x01) 1526 sdata = bmp_ddr_seq_table(bios); 1527 mdata += 6; /* skip to data */ 1528 1529 data = init_rdvgai(init, 0x03c4, 0x01); 1530 init_wrvgai(init, 0x03c4, 0x01, data | 0x20); 1531 1532 for (; (addr = nvbios_rd32(bios, sdata)) != 0xffffffff; sdata += 4) { 1533 switch (addr) { 1534 case 0x10021c: /* CKE_NORMAL */ 1535 case 0x1002d0: /* CMD_REFRESH */ 1536 case 0x1002d4: /* CMD_PRECHARGE */ 1537 data = 0x00000001; 1538 break; 1539 default: 1540 data = nvbios_rd32(bios, mdata); 1541 mdata += 4; 1542 if (data == 0xffffffff) 1543 continue; 1544 break; 1545 } 1546 1547 init_wr32(init, addr, data); 1548 } 1549 1550 init_exec_force(init, false); 1551 } 1552 1553 /** 1554 * INIT_CONFIGURE_CLK - opcode 0x67 1555 * 1556 */ 1557 static void 1558 init_configure_clk(struct nvbios_init *init) 1559 { 1560 struct nvkm_bios *bios = init->subdev->device->bios; 1561 u16 mdata, clock; 1562 1563 trace("CONFIGURE_CLK\n"); 1564 init->offset += 1; 1565 1566 if (bios->version.major > 2) { 1567 init_done(init); 1568 return; 1569 } 1570 init_exec_force(init, true); 1571 1572 mdata = init_configure_mem_clk(init); 1573 1574 /* NVPLL */ 1575 clock = nvbios_rd16(bios, mdata + 4) * 10; 1576 init_prog_pll(init, 0x680500, clock); 1577 1578 /* MPLL */ 1579 clock = nvbios_rd16(bios, mdata + 2) * 10; 1580 if (nvbios_rd08(bios, mdata) & 0x01) 1581 clock *= 2; 1582 init_prog_pll(init, 0x680504, clock); 1583 1584 init_exec_force(init, false); 1585 } 1586 1587 /** 1588 * INIT_CONFIGURE_PREINIT - opcode 0x68 1589 * 1590 */ 1591 static void 1592 init_configure_preinit(struct nvbios_init *init) 1593 { 1594 struct nvkm_bios *bios = init->subdev->device->bios; 1595 u32 strap; 1596 1597 trace("CONFIGURE_PREINIT\n"); 1598 init->offset += 1; 1599 1600 if (bios->version.major > 2) { 1601 init_done(init); 1602 return; 1603 } 1604 init_exec_force(init, true); 1605 1606 strap = init_rd32(init, 0x101000); 1607 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); 1608 init_wrvgai(init, 0x03d4, 0x3c, strap); 1609 1610 init_exec_force(init, false); 1611 } 1612 1613 /** 1614 * INIT_IO - opcode 0x69 1615 * 1616 */ 1617 static void 1618 init_io(struct nvbios_init *init) 1619 { 1620 struct nvkm_bios *bios = init->subdev->device->bios; 1621 u16 port = nvbios_rd16(bios, init->offset + 1); 1622 u8 mask = nvbios_rd16(bios, init->offset + 3); 1623 u8 data = nvbios_rd16(bios, init->offset + 4); 1624 u8 value; 1625 1626 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); 1627 init->offset += 5; 1628 1629 /* ummm.. yes.. should really figure out wtf this is and why it's 1630 * needed some day.. it's almost certainly wrong, but, it also 1631 * somehow makes things work... 1632 */ 1633 if (bios->subdev.device->card_type >= NV_50 && 1634 port == 0x03c3 && data == 0x01) { 1635 init_mask(init, 0x614100, 0xf0800000, 0x00800000); 1636 init_mask(init, 0x00e18c, 0x00020000, 0x00020000); 1637 init_mask(init, 0x614900, 0xf0800000, 0x00800000); 1638 init_mask(init, 0x000200, 0x40000000, 0x00000000); 1639 mdelay(10); 1640 init_mask(init, 0x00e18c, 0x00020000, 0x00000000); 1641 init_mask(init, 0x000200, 0x40000000, 0x40000000); 1642 init_wr32(init, 0x614100, 0x00800018); 1643 init_wr32(init, 0x614900, 0x00800018); 1644 mdelay(10); 1645 init_wr32(init, 0x614100, 0x10000018); 1646 init_wr32(init, 0x614900, 0x10000018); 1647 } 1648 1649 value = init_rdport(init, port) & mask; 1650 init_wrport(init, port, data | value); 1651 } 1652 1653 /** 1654 * INIT_SUB - opcode 0x6b 1655 * 1656 */ 1657 static void 1658 init_sub(struct nvbios_init *init) 1659 { 1660 struct nvkm_bios *bios = init->subdev->device->bios; 1661 u8 index = nvbios_rd08(bios, init->offset + 1); 1662 u16 addr, save; 1663 1664 trace("SUB\t0x%02x\n", index); 1665 1666 addr = init_script(bios, index); 1667 if (addr && init_exec(init)) { 1668 save = init->offset; 1669 init->offset = addr; 1670 if (nvbios_exec(init)) { 1671 error("error parsing sub-table\n"); 1672 return; 1673 } 1674 init->offset = save; 1675 } 1676 1677 init->offset += 2; 1678 } 1679 1680 /** 1681 * INIT_RAM_CONDITION - opcode 0x6d 1682 * 1683 */ 1684 static void 1685 init_ram_condition(struct nvbios_init *init) 1686 { 1687 struct nvkm_bios *bios = init->subdev->device->bios; 1688 u8 mask = nvbios_rd08(bios, init->offset + 1); 1689 u8 value = nvbios_rd08(bios, init->offset + 2); 1690 1691 trace("RAM_CONDITION\t" 1692 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); 1693 init->offset += 3; 1694 1695 if ((init_rd32(init, 0x100000) & mask) != value) 1696 init_exec_set(init, false); 1697 } 1698 1699 /** 1700 * INIT_NV_REG - opcode 0x6e 1701 * 1702 */ 1703 static void 1704 init_nv_reg(struct nvbios_init *init) 1705 { 1706 struct nvkm_bios *bios = init->subdev->device->bios; 1707 u32 reg = nvbios_rd32(bios, init->offset + 1); 1708 u32 mask = nvbios_rd32(bios, init->offset + 5); 1709 u32 data = nvbios_rd32(bios, init->offset + 9); 1710 1711 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); 1712 init->offset += 13; 1713 1714 init_mask(init, reg, ~mask, data); 1715 } 1716 1717 /** 1718 * INIT_MACRO - opcode 0x6f 1719 * 1720 */ 1721 static void 1722 init_macro(struct nvbios_init *init) 1723 { 1724 struct nvkm_bios *bios = init->subdev->device->bios; 1725 u8 macro = nvbios_rd08(bios, init->offset + 1); 1726 u16 table; 1727 1728 trace("MACRO\t0x%02x\n", macro); 1729 1730 table = init_macro_table(init); 1731 if (table) { 1732 u32 addr = nvbios_rd32(bios, table + (macro * 8) + 0); 1733 u32 data = nvbios_rd32(bios, table + (macro * 8) + 4); 1734 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); 1735 init_wr32(init, addr, data); 1736 } 1737 1738 init->offset += 2; 1739 } 1740 1741 /** 1742 * INIT_RESUME - opcode 0x72 1743 * 1744 */ 1745 static void 1746 init_resume(struct nvbios_init *init) 1747 { 1748 trace("RESUME\n"); 1749 init->offset += 1; 1750 init_exec_set(init, true); 1751 } 1752 1753 /** 1754 * INIT_STRAP_CONDITION - opcode 0x73 1755 * 1756 */ 1757 static void 1758 init_strap_condition(struct nvbios_init *init) 1759 { 1760 struct nvkm_bios *bios = init->subdev->device->bios; 1761 u32 mask = nvbios_rd32(bios, init->offset + 1); 1762 u32 value = nvbios_rd32(bios, init->offset + 5); 1763 1764 trace("STRAP_CONDITION\t(R[0x101000] & 0x%08x) == 0x%08x\n", mask, value); 1765 init->offset += 9; 1766 1767 if ((init_rd32(init, 0x101000) & mask) != value) 1768 init_exec_set(init, false); 1769 } 1770 1771 /** 1772 * INIT_TIME - opcode 0x74 1773 * 1774 */ 1775 static void 1776 init_time(struct nvbios_init *init) 1777 { 1778 struct nvkm_bios *bios = init->subdev->device->bios; 1779 u16 usec = nvbios_rd16(bios, init->offset + 1); 1780 1781 trace("TIME\t0x%04x\n", usec); 1782 init->offset += 3; 1783 1784 if (init_exec(init)) { 1785 if (usec < 1000) 1786 udelay(usec); 1787 else 1788 mdelay((usec + 900) / 1000); 1789 } 1790 } 1791 1792 /** 1793 * INIT_CONDITION - opcode 0x75 1794 * 1795 */ 1796 static void 1797 init_condition(struct nvbios_init *init) 1798 { 1799 struct nvkm_bios *bios = init->subdev->device->bios; 1800 u8 cond = nvbios_rd08(bios, init->offset + 1); 1801 1802 trace("CONDITION\t0x%02x\n", cond); 1803 init->offset += 2; 1804 1805 if (!init_condition_met(init, cond)) 1806 init_exec_set(init, false); 1807 } 1808 1809 /** 1810 * INIT_IO_CONDITION - opcode 0x76 1811 * 1812 */ 1813 static void 1814 init_io_condition(struct nvbios_init *init) 1815 { 1816 struct nvkm_bios *bios = init->subdev->device->bios; 1817 u8 cond = nvbios_rd08(bios, init->offset + 1); 1818 1819 trace("IO_CONDITION\t0x%02x\n", cond); 1820 init->offset += 2; 1821 1822 if (!init_io_condition_met(init, cond)) 1823 init_exec_set(init, false); 1824 } 1825 1826 /** 1827 * INIT_ZM_REG16 - opcode 0x77 1828 * 1829 */ 1830 static void 1831 init_zm_reg16(struct nvbios_init *init) 1832 { 1833 struct nvkm_bios *bios = init->subdev->device->bios; 1834 u32 addr = nvbios_rd32(bios, init->offset + 1); 1835 u16 data = nvbios_rd16(bios, init->offset + 5); 1836 1837 trace("ZM_REG\tR[0x%06x] = 0x%04x\n", addr, data); 1838 init->offset += 7; 1839 1840 init_wr32(init, addr, data); 1841 } 1842 1843 /** 1844 * INIT_INDEX_IO - opcode 0x78 1845 * 1846 */ 1847 static void 1848 init_index_io(struct nvbios_init *init) 1849 { 1850 struct nvkm_bios *bios = init->subdev->device->bios; 1851 u16 port = nvbios_rd16(bios, init->offset + 1); 1852 u8 index = nvbios_rd16(bios, init->offset + 3); 1853 u8 mask = nvbios_rd08(bios, init->offset + 4); 1854 u8 data = nvbios_rd08(bios, init->offset + 5); 1855 u8 value; 1856 1857 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", 1858 port, index, mask, data); 1859 init->offset += 6; 1860 1861 value = init_rdvgai(init, port, index) & mask; 1862 init_wrvgai(init, port, index, data | value); 1863 } 1864 1865 /** 1866 * INIT_PLL - opcode 0x79 1867 * 1868 */ 1869 static void 1870 init_pll(struct nvbios_init *init) 1871 { 1872 struct nvkm_bios *bios = init->subdev->device->bios; 1873 u32 reg = nvbios_rd32(bios, init->offset + 1); 1874 u32 freq = nvbios_rd16(bios, init->offset + 5) * 10; 1875 1876 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); 1877 init->offset += 7; 1878 1879 init_prog_pll(init, reg, freq); 1880 } 1881 1882 /** 1883 * INIT_ZM_REG - opcode 0x7a 1884 * 1885 */ 1886 static void 1887 init_zm_reg(struct nvbios_init *init) 1888 { 1889 struct nvkm_bios *bios = init->subdev->device->bios; 1890 u32 addr = nvbios_rd32(bios, init->offset + 1); 1891 u32 data = nvbios_rd32(bios, init->offset + 5); 1892 1893 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); 1894 init->offset += 9; 1895 1896 if (addr == 0x000200) 1897 data |= 0x00000001; 1898 1899 init_wr32(init, addr, data); 1900 } 1901 1902 /** 1903 * INIT_RAM_RESTRICT_PLL - opcde 0x87 1904 * 1905 */ 1906 static void 1907 init_ram_restrict_pll(struct nvbios_init *init) 1908 { 1909 struct nvkm_bios *bios = init->subdev->device->bios; 1910 u8 type = nvbios_rd08(bios, init->offset + 1); 1911 u8 count = init_ram_restrict_group_count(init); 1912 u8 strap = init_ram_restrict(init); 1913 u8 cconf; 1914 1915 trace("RAM_RESTRICT_PLL\t0x%02x\n", type); 1916 init->offset += 2; 1917 1918 for (cconf = 0; cconf < count; cconf++) { 1919 u32 freq = nvbios_rd32(bios, init->offset); 1920 1921 if (cconf == strap) { 1922 trace("%dkHz *\n", freq); 1923 init_prog_pll(init, type, freq); 1924 } else { 1925 trace("%dkHz\n", freq); 1926 } 1927 1928 init->offset += 4; 1929 } 1930 } 1931 1932 /** 1933 * INIT_GPIO - opcode 0x8e 1934 * 1935 */ 1936 static void 1937 init_gpio(struct nvbios_init *init) 1938 { 1939 struct nvkm_gpio *gpio = init->subdev->device->gpio; 1940 1941 trace("GPIO\n"); 1942 init->offset += 1; 1943 1944 if (init_exec(init)) 1945 nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED); 1946 } 1947 1948 /** 1949 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f 1950 * 1951 */ 1952 static void 1953 init_ram_restrict_zm_reg_group(struct nvbios_init *init) 1954 { 1955 struct nvkm_bios *bios = init->subdev->device->bios; 1956 u32 addr = nvbios_rd32(bios, init->offset + 1); 1957 u8 incr = nvbios_rd08(bios, init->offset + 5); 1958 u8 num = nvbios_rd08(bios, init->offset + 6); 1959 u8 count = init_ram_restrict_group_count(init); 1960 u8 index = init_ram_restrict(init); 1961 u8 i, j; 1962 1963 trace("RAM_RESTRICT_ZM_REG_GROUP\t" 1964 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); 1965 init->offset += 7; 1966 1967 for (i = 0; i < num; i++) { 1968 trace("\tR[0x%06x] = {\n", addr); 1969 for (j = 0; j < count; j++) { 1970 u32 data = nvbios_rd32(bios, init->offset); 1971 1972 if (j == index) { 1973 trace("\t\t0x%08x *\n", data); 1974 init_wr32(init, addr, data); 1975 } else { 1976 trace("\t\t0x%08x\n", data); 1977 } 1978 1979 init->offset += 4; 1980 } 1981 trace("\t}\n"); 1982 addr += incr; 1983 } 1984 } 1985 1986 /** 1987 * INIT_COPY_ZM_REG - opcode 0x90 1988 * 1989 */ 1990 static void 1991 init_copy_zm_reg(struct nvbios_init *init) 1992 { 1993 struct nvkm_bios *bios = init->subdev->device->bios; 1994 u32 sreg = nvbios_rd32(bios, init->offset + 1); 1995 u32 dreg = nvbios_rd32(bios, init->offset + 5); 1996 1997 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); 1998 init->offset += 9; 1999 2000 init_wr32(init, dreg, init_rd32(init, sreg)); 2001 } 2002 2003 /** 2004 * INIT_ZM_REG_GROUP - opcode 0x91 2005 * 2006 */ 2007 static void 2008 init_zm_reg_group(struct nvbios_init *init) 2009 { 2010 struct nvkm_bios *bios = init->subdev->device->bios; 2011 u32 addr = nvbios_rd32(bios, init->offset + 1); 2012 u8 count = nvbios_rd08(bios, init->offset + 5); 2013 2014 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); 2015 init->offset += 6; 2016 2017 while (count--) { 2018 u32 data = nvbios_rd32(bios, init->offset); 2019 trace("\t0x%08x\n", data); 2020 init_wr32(init, addr, data); 2021 init->offset += 4; 2022 } 2023 } 2024 2025 /** 2026 * INIT_XLAT - opcode 0x96 2027 * 2028 */ 2029 static void 2030 init_xlat(struct nvbios_init *init) 2031 { 2032 struct nvkm_bios *bios = init->subdev->device->bios; 2033 u32 saddr = nvbios_rd32(bios, init->offset + 1); 2034 u8 sshift = nvbios_rd08(bios, init->offset + 5); 2035 u8 smask = nvbios_rd08(bios, init->offset + 6); 2036 u8 index = nvbios_rd08(bios, init->offset + 7); 2037 u32 daddr = nvbios_rd32(bios, init->offset + 8); 2038 u32 dmask = nvbios_rd32(bios, init->offset + 12); 2039 u8 shift = nvbios_rd08(bios, init->offset + 16); 2040 u32 data; 2041 2042 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " 2043 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", 2044 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", 2045 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); 2046 init->offset += 17; 2047 2048 data = init_shift(init_rd32(init, saddr), sshift) & smask; 2049 data = init_xlat_(init, index, data) << shift; 2050 init_mask(init, daddr, ~dmask, data); 2051 } 2052 2053 /** 2054 * INIT_ZM_MASK_ADD - opcode 0x97 2055 * 2056 */ 2057 static void 2058 init_zm_mask_add(struct nvbios_init *init) 2059 { 2060 struct nvkm_bios *bios = init->subdev->device->bios; 2061 u32 addr = nvbios_rd32(bios, init->offset + 1); 2062 u32 mask = nvbios_rd32(bios, init->offset + 5); 2063 u32 add = nvbios_rd32(bios, init->offset + 9); 2064 u32 data; 2065 2066 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); 2067 init->offset += 13; 2068 2069 data = init_rd32(init, addr); 2070 data = (data & mask) | ((data + add) & ~mask); 2071 init_wr32(init, addr, data); 2072 } 2073 2074 /** 2075 * INIT_AUXCH - opcode 0x98 2076 * 2077 */ 2078 static void 2079 init_auxch(struct nvbios_init *init) 2080 { 2081 struct nvkm_bios *bios = init->subdev->device->bios; 2082 u32 addr = nvbios_rd32(bios, init->offset + 1); 2083 u8 count = nvbios_rd08(bios, init->offset + 5); 2084 2085 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2086 init->offset += 6; 2087 2088 while (count--) { 2089 u8 mask = nvbios_rd08(bios, init->offset + 0); 2090 u8 data = nvbios_rd08(bios, init->offset + 1); 2091 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); 2092 mask = init_rdauxr(init, addr) & mask; 2093 init_wrauxr(init, addr, mask | data); 2094 init->offset += 2; 2095 } 2096 } 2097 2098 /** 2099 * INIT_AUXCH - opcode 0x99 2100 * 2101 */ 2102 static void 2103 init_zm_auxch(struct nvbios_init *init) 2104 { 2105 struct nvkm_bios *bios = init->subdev->device->bios; 2106 u32 addr = nvbios_rd32(bios, init->offset + 1); 2107 u8 count = nvbios_rd08(bios, init->offset + 5); 2108 2109 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); 2110 init->offset += 6; 2111 2112 while (count--) { 2113 u8 data = nvbios_rd08(bios, init->offset + 0); 2114 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); 2115 init_wrauxr(init, addr, data); 2116 init->offset += 1; 2117 } 2118 } 2119 2120 /** 2121 * INIT_I2C_LONG_IF - opcode 0x9a 2122 * 2123 */ 2124 static void 2125 init_i2c_long_if(struct nvbios_init *init) 2126 { 2127 struct nvkm_bios *bios = init->subdev->device->bios; 2128 u8 index = nvbios_rd08(bios, init->offset + 1); 2129 u8 addr = nvbios_rd08(bios, init->offset + 2) >> 1; 2130 u8 reglo = nvbios_rd08(bios, init->offset + 3); 2131 u8 reghi = nvbios_rd08(bios, init->offset + 4); 2132 u8 mask = nvbios_rd08(bios, init->offset + 5); 2133 u8 data = nvbios_rd08(bios, init->offset + 6); 2134 struct i2c_adapter *adap; 2135 2136 trace("I2C_LONG_IF\t" 2137 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", 2138 index, addr, reglo, reghi, mask, data); 2139 init->offset += 7; 2140 2141 adap = init_i2c(init, index); 2142 if (adap) { 2143 u8 i[2] = { reghi, reglo }; 2144 u8 o[1] = {}; 2145 struct i2c_msg msg[] = { 2146 { .addr = addr, .flags = 0, .len = 2, .buf = i }, 2147 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } 2148 }; 2149 int ret; 2150 2151 ret = i2c_transfer(adap, msg, 2); 2152 if (ret == 2 && ((o[0] & mask) == data)) 2153 return; 2154 } 2155 2156 init_exec_set(init, false); 2157 } 2158 2159 /** 2160 * INIT_GPIO_NE - opcode 0xa9 2161 * 2162 */ 2163 static void 2164 init_gpio_ne(struct nvbios_init *init) 2165 { 2166 struct nvkm_bios *bios = init->subdev->device->bios; 2167 struct nvkm_gpio *gpio = bios->subdev.device->gpio; 2168 struct dcb_gpio_func func; 2169 u8 count = nvbios_rd08(bios, init->offset + 1); 2170 u8 idx = 0, ver, len; 2171 u16 data, i; 2172 2173 trace("GPIO_NE\t"); 2174 init->offset += 2; 2175 2176 for (i = init->offset; i < init->offset + count; i++) 2177 cont("0x%02x ", nvbios_rd08(bios, i)); 2178 cont("\n"); 2179 2180 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { 2181 if (func.func != DCB_GPIO_UNUSED) { 2182 for (i = init->offset; i < init->offset + count; i++) { 2183 if (func.func == nvbios_rd08(bios, i)) 2184 break; 2185 } 2186 2187 trace("\tFUNC[0x%02x]", func.func); 2188 if (i == (init->offset + count)) { 2189 cont(" *"); 2190 if (init_exec(init)) 2191 nvkm_gpio_reset(gpio, func.func); 2192 } 2193 cont("\n"); 2194 } 2195 } 2196 2197 init->offset += count; 2198 } 2199 2200 static struct nvbios_init_opcode { 2201 void (*exec)(struct nvbios_init *); 2202 } init_opcode[] = { 2203 [0x32] = { init_io_restrict_prog }, 2204 [0x33] = { init_repeat }, 2205 [0x34] = { init_io_restrict_pll }, 2206 [0x36] = { init_end_repeat }, 2207 [0x37] = { init_copy }, 2208 [0x38] = { init_not }, 2209 [0x39] = { init_io_flag_condition }, 2210 [0x3a] = { init_generic_condition }, 2211 [0x3b] = { init_io_mask_or }, 2212 [0x3c] = { init_io_or }, 2213 [0x47] = { init_andn_reg }, 2214 [0x48] = { init_or_reg }, 2215 [0x49] = { init_idx_addr_latched }, 2216 [0x4a] = { init_io_restrict_pll2 }, 2217 [0x4b] = { init_pll2 }, 2218 [0x4c] = { init_i2c_byte }, 2219 [0x4d] = { init_zm_i2c_byte }, 2220 [0x4e] = { init_zm_i2c }, 2221 [0x4f] = { init_tmds }, 2222 [0x50] = { init_zm_tmds_group }, 2223 [0x51] = { init_cr_idx_adr_latch }, 2224 [0x52] = { init_cr }, 2225 [0x53] = { init_zm_cr }, 2226 [0x54] = { init_zm_cr_group }, 2227 [0x56] = { init_condition_time }, 2228 [0x57] = { init_ltime }, 2229 [0x58] = { init_zm_reg_sequence }, 2230 [0x59] = { init_pll_indirect }, 2231 [0x5a] = { init_zm_reg_indirect }, 2232 [0x5b] = { init_sub_direct }, 2233 [0x5c] = { init_jump }, 2234 [0x5e] = { init_i2c_if }, 2235 [0x5f] = { init_copy_nv_reg }, 2236 [0x62] = { init_zm_index_io }, 2237 [0x63] = { init_compute_mem }, 2238 [0x65] = { init_reset }, 2239 [0x66] = { init_configure_mem }, 2240 [0x67] = { init_configure_clk }, 2241 [0x68] = { init_configure_preinit }, 2242 [0x69] = { init_io }, 2243 [0x6b] = { init_sub }, 2244 [0x6d] = { init_ram_condition }, 2245 [0x6e] = { init_nv_reg }, 2246 [0x6f] = { init_macro }, 2247 [0x71] = { init_done }, 2248 [0x72] = { init_resume }, 2249 [0x73] = { init_strap_condition }, 2250 [0x74] = { init_time }, 2251 [0x75] = { init_condition }, 2252 [0x76] = { init_io_condition }, 2253 [0x77] = { init_zm_reg16 }, 2254 [0x78] = { init_index_io }, 2255 [0x79] = { init_pll }, 2256 [0x7a] = { init_zm_reg }, 2257 [0x87] = { init_ram_restrict_pll }, 2258 [0x8c] = { init_reserved }, 2259 [0x8d] = { init_reserved }, 2260 [0x8e] = { init_gpio }, 2261 [0x8f] = { init_ram_restrict_zm_reg_group }, 2262 [0x90] = { init_copy_zm_reg }, 2263 [0x91] = { init_zm_reg_group }, 2264 [0x92] = { init_reserved }, 2265 [0x96] = { init_xlat }, 2266 [0x97] = { init_zm_mask_add }, 2267 [0x98] = { init_auxch }, 2268 [0x99] = { init_zm_auxch }, 2269 [0x9a] = { init_i2c_long_if }, 2270 [0xa9] = { init_gpio_ne }, 2271 [0xaa] = { init_reserved }, 2272 }; 2273 2274 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) 2275 2276 int 2277 nvbios_exec(struct nvbios_init *init) 2278 { 2279 struct nvkm_bios *bios = init->subdev->device->bios; 2280 init->nested++; 2281 while (init->offset) { 2282 u8 opcode = nvbios_rd08(bios, init->offset); 2283 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { 2284 error("unknown opcode 0x%02x\n", opcode); 2285 return -EINVAL; 2286 } 2287 2288 init_opcode[opcode].exec(init); 2289 } 2290 init->nested--; 2291 return 0; 2292 } 2293 2294 int 2295 nvbios_post(struct nvkm_subdev *subdev, bool execute) 2296 { 2297 struct nvkm_bios *bios = subdev->device->bios; 2298 int ret = 0; 2299 int i = -1; 2300 u16 data; 2301 2302 if (execute) 2303 nvkm_debug(subdev, "running init tables\n"); 2304 while (!ret && (data = (init_script(bios, ++i)))) { 2305 struct nvbios_init init = { 2306 .subdev = subdev, 2307 .bios = bios, 2308 .offset = data, 2309 .outp = NULL, 2310 .head = -1, 2311 .execute = execute ? 1 : 0, 2312 }; 2313 2314 ret = nvbios_exec(&init); 2315 } 2316 2317 /* the vbios parser will run this right after the normal init 2318 * tables, whereas the binary driver appears to run it later. 2319 */ 2320 if (!ret && (data = init_unknown_script(bios))) { 2321 struct nvbios_init init = { 2322 .subdev = subdev, 2323 .bios = bios, 2324 .offset = data, 2325 .outp = NULL, 2326 .head = -1, 2327 .execute = execute ? 1 : 0, 2328 }; 2329 2330 ret = nvbios_exec(&init); 2331 } 2332 2333 return ret; 2334 } 2335