1*b7019ac5SIlia Mirkin /* SPDX-License-Identifier: MIT */ 2c39f472eSBen Skeggs #ifndef __NVKM_FBRAM_SEQ_H__ 3c39f472eSBen Skeggs #define __NVKM_FBRAM_SEQ_H__ 4c39f472eSBen Skeggs #include <subdev/bus/hwsq.h> 5c39f472eSBen Skeggs 6c39f472eSBen Skeggs #define ram_init(s,p) hwsq_init(&(s)->base, (p)) 7c39f472eSBen Skeggs #define ram_exec(s,e) hwsq_exec(&(s)->base, (e)) 8c39f472eSBen Skeggs #define ram_have(s,r) ((s)->r_##r.addr != 0x000000) 9c39f472eSBen Skeggs #define ram_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) 10c39f472eSBen Skeggs #define ram_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) 11c39f472eSBen Skeggs #define ram_nuke(s,r) hwsq_nuke(&(s)->base, &(s)->r_##r) 12c39f472eSBen Skeggs #define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) 13c39f472eSBen Skeggs #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) 14c39f472eSBen Skeggs #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) 15271c2766SRoy Spliet #define ram_wait_vblank(s) hwsq_wait_vblank(&(s)->base) 16c39f472eSBen Skeggs #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) 17c39f472eSBen Skeggs #endif 18