1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/i2c-smbus.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pinctrl/consumer.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/pm_wakeirq.h> 34 #include <linux/regmap.h> 35 #include <linux/reset.h> 36 #include <linux/slab.h> 37 38 #include "i2c-stm32.h" 39 40 /* STM32F7 I2C registers */ 41 #define STM32F7_I2C_CR1 0x00 42 #define STM32F7_I2C_CR2 0x04 43 #define STM32F7_I2C_OAR1 0x08 44 #define STM32F7_I2C_OAR2 0x0C 45 #define STM32F7_I2C_PECR 0x20 46 #define STM32F7_I2C_TIMINGR 0x10 47 #define STM32F7_I2C_ISR 0x18 48 #define STM32F7_I2C_ICR 0x1C 49 #define STM32F7_I2C_RXDR 0x24 50 #define STM32F7_I2C_TXDR 0x28 51 52 /* STM32F7 I2C control 1 */ 53 #define STM32F7_I2C_CR1_PECEN BIT(23) 54 #define STM32F7_I2C_CR1_ALERTEN BIT(22) 55 #define STM32F7_I2C_CR1_SMBHEN BIT(20) 56 #define STM32F7_I2C_CR1_WUPEN BIT(18) 57 #define STM32F7_I2C_CR1_SBC BIT(16) 58 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 59 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 60 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 61 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8) 62 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8) 63 #define STM32F7_I2C_CR1_ERRIE BIT(7) 64 #define STM32F7_I2C_CR1_TCIE BIT(6) 65 #define STM32F7_I2C_CR1_STOPIE BIT(5) 66 #define STM32F7_I2C_CR1_NACKIE BIT(4) 67 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 68 #define STM32F7_I2C_CR1_RXIE BIT(2) 69 #define STM32F7_I2C_CR1_TXIE BIT(1) 70 #define STM32F7_I2C_CR1_PE BIT(0) 71 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 72 | STM32F7_I2C_CR1_TCIE \ 73 | STM32F7_I2C_CR1_STOPIE \ 74 | STM32F7_I2C_CR1_NACKIE \ 75 | STM32F7_I2C_CR1_RXIE \ 76 | STM32F7_I2C_CR1_TXIE) 77 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 78 | STM32F7_I2C_CR1_STOPIE \ 79 | STM32F7_I2C_CR1_NACKIE \ 80 | STM32F7_I2C_CR1_RXIE \ 81 | STM32F7_I2C_CR1_TXIE) 82 83 /* STM32F7 I2C control 2 */ 84 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 85 #define STM32F7_I2C_CR2_RELOAD BIT(24) 86 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 87 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 88 #define STM32F7_I2C_CR2_NACK BIT(15) 89 #define STM32F7_I2C_CR2_STOP BIT(14) 90 #define STM32F7_I2C_CR2_START BIT(13) 91 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 92 #define STM32F7_I2C_CR2_ADD10 BIT(11) 93 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 94 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 95 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 96 STM32F7_I2C_CR2_SADD10_MASK)) 97 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 98 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 99 100 /* STM32F7 I2C Own Address 1 */ 101 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 102 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 103 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 104 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 105 STM32F7_I2C_OAR1_OA1_10_MASK)) 106 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 107 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 108 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 109 | STM32F7_I2C_OAR1_OA1_10_MASK \ 110 | STM32F7_I2C_OAR1_OA1EN \ 111 | STM32F7_I2C_OAR1_OA1MODE) 112 113 /* STM32F7 I2C Own Address 2 */ 114 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 115 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 116 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 117 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 118 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 119 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 120 | STM32F7_I2C_OAR2_OA2_7_MASK \ 121 | STM32F7_I2C_OAR2_OA2EN) 122 123 /* STM32F7 I2C Interrupt Status */ 124 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 125 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 126 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 127 #define STM32F7_I2C_ISR_DIR BIT(16) 128 #define STM32F7_I2C_ISR_BUSY BIT(15) 129 #define STM32F7_I2C_ISR_ALERT BIT(13) 130 #define STM32F7_I2C_ISR_PECERR BIT(11) 131 #define STM32F7_I2C_ISR_ARLO BIT(9) 132 #define STM32F7_I2C_ISR_BERR BIT(8) 133 #define STM32F7_I2C_ISR_TCR BIT(7) 134 #define STM32F7_I2C_ISR_TC BIT(6) 135 #define STM32F7_I2C_ISR_STOPF BIT(5) 136 #define STM32F7_I2C_ISR_NACKF BIT(4) 137 #define STM32F7_I2C_ISR_ADDR BIT(3) 138 #define STM32F7_I2C_ISR_RXNE BIT(2) 139 #define STM32F7_I2C_ISR_TXIS BIT(1) 140 #define STM32F7_I2C_ISR_TXE BIT(0) 141 142 /* STM32F7 I2C Interrupt Clear */ 143 #define STM32F7_I2C_ICR_ALERTCF BIT(13) 144 #define STM32F7_I2C_ICR_PECCF BIT(11) 145 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 146 #define STM32F7_I2C_ICR_BERRCF BIT(8) 147 #define STM32F7_I2C_ICR_STOPCF BIT(5) 148 #define STM32F7_I2C_ICR_NACKCF BIT(4) 149 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 150 151 /* STM32F7 I2C Timing */ 152 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 153 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 154 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 155 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 156 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 157 158 #define STM32F7_I2C_MAX_LEN 0xff 159 #define STM32F7_I2C_DMA_LEN_MIN 0x16 160 enum { 161 STM32F7_SLAVE_HOSTNOTIFY, 162 STM32F7_SLAVE_7_10_BITS_ADDR, 163 STM32F7_SLAVE_7_BITS_ADDR, 164 STM32F7_I2C_MAX_SLAVE 165 }; 166 167 #define STM32F7_I2C_DNF_DEFAULT 0 168 #define STM32F7_I2C_DNF_MAX 15 169 170 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 171 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 172 173 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 174 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 175 176 #define STM32F7_PRESC_MAX BIT(4) 177 #define STM32F7_SCLDEL_MAX BIT(4) 178 #define STM32F7_SDADEL_MAX BIT(4) 179 #define STM32F7_SCLH_MAX BIT(8) 180 #define STM32F7_SCLL_MAX BIT(8) 181 182 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 183 184 /** 185 * struct stm32f7_i2c_regs - i2c f7 registers backup 186 * @cr1: Control register 1 187 * @cr2: Control register 2 188 * @oar1: Own address 1 register 189 * @oar2: Own address 2 register 190 * @tmgr: Timing register 191 */ 192 struct stm32f7_i2c_regs { 193 u32 cr1; 194 u32 cr2; 195 u32 oar1; 196 u32 oar2; 197 u32 tmgr; 198 }; 199 200 /** 201 * struct stm32f7_i2c_spec - private i2c specification timing 202 * @rate: I2C bus speed (Hz) 203 * @fall_max: Max fall time of both SDA and SCL signals (ns) 204 * @rise_max: Max rise time of both SDA and SCL signals (ns) 205 * @hddat_min: Min data hold time (ns) 206 * @vddat_max: Max data valid time (ns) 207 * @sudat_min: Min data setup time (ns) 208 * @l_min: Min low period of the SCL clock (ns) 209 * @h_min: Min high period of the SCL clock (ns) 210 */ 211 struct stm32f7_i2c_spec { 212 u32 rate; 213 u32 fall_max; 214 u32 rise_max; 215 u32 hddat_min; 216 u32 vddat_max; 217 u32 sudat_min; 218 u32 l_min; 219 u32 h_min; 220 }; 221 222 /** 223 * struct stm32f7_i2c_setup - private I2C timing setup parameters 224 * @speed_freq: I2C speed frequency (Hz) 225 * @clock_src: I2C clock source frequency (Hz) 226 * @rise_time: Rise time (ns) 227 * @fall_time: Fall time (ns) 228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register 229 */ 230 struct stm32f7_i2c_setup { 231 u32 speed_freq; 232 u32 clock_src; 233 u32 rise_time; 234 u32 fall_time; 235 u32 fmp_clr_offset; 236 }; 237 238 /** 239 * struct stm32f7_i2c_timings - private I2C output parameters 240 * @node: List entry 241 * @presc: Prescaler value 242 * @scldel: Data setup time 243 * @sdadel: Data hold time 244 * @sclh: SCL high period (master mode) 245 * @scll: SCL low period (master mode) 246 */ 247 struct stm32f7_i2c_timings { 248 struct list_head node; 249 u8 presc; 250 u8 scldel; 251 u8 sdadel; 252 u8 sclh; 253 u8 scll; 254 }; 255 256 /** 257 * struct stm32f7_i2c_msg - client specific data 258 * @addr: 8-bit or 10-bit slave addr, including r/w bit 259 * @count: number of bytes to be transferred 260 * @buf: data buffer 261 * @result: result of the transfer 262 * @stop: last I2C msg to be sent, i.e. STOP to be generated 263 * @smbus: boolean to know if the I2C IP is used in SMBus mode 264 * @size: type of SMBus protocol 265 * @read_write: direction of SMBus protocol 266 * SMBus block read and SMBus block write - block read process call protocols 267 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 268 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 269 * This buffer has to be 32-bit aligned to be compliant with memory address 270 * register in DMA mode. 271 */ 272 struct stm32f7_i2c_msg { 273 u16 addr; 274 u32 count; 275 u8 *buf; 276 int result; 277 bool stop; 278 bool smbus; 279 int size; 280 char read_write; 281 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 282 }; 283 284 /** 285 * struct stm32f7_i2c_alert - SMBus alert specific data 286 * @setup: platform data for the smbus_alert i2c client 287 * @ara: I2C slave device used to respond to the SMBus Alert with Alert 288 * Response Address 289 */ 290 struct stm32f7_i2c_alert { 291 struct i2c_smbus_alert_setup setup; 292 struct i2c_client *ara; 293 }; 294 295 /** 296 * struct stm32f7_i2c_dev - private data of the controller 297 * @adap: I2C adapter for this controller 298 * @dev: device for this controller 299 * @base: virtual memory area 300 * @complete: completion of I2C message 301 * @clk: hw i2c clock 302 * @bus_rate: I2C clock frequency of the controller 303 * @msg: Pointer to data to be written 304 * @msg_num: number of I2C messages to be executed 305 * @msg_id: message identifiant 306 * @f7_msg: customized i2c msg for driver usage 307 * @setup: I2C timing input setup 308 * @timing: I2C computed timings 309 * @slave: list of slave devices registered on the I2C bus 310 * @slave_running: slave device currently used 311 * @backup_regs: backup of i2c controller registers (for suspend/resume) 312 * @slave_dir: transfer direction for the current slave device 313 * @master_mode: boolean to know in which mode the I2C is running (master or 314 * slave) 315 * @dma: dma data 316 * @use_dma: boolean to know if dma is used in the current transfer 317 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 318 * @fmp_sreg: register address for setting Fast Mode Plus bits 319 * @fmp_creg: register address for clearing Fast Mode Plus bits 320 * @fmp_mask: mask for Fast Mode Plus bits in set register 321 * @wakeup_src: boolean to know if the device is a wakeup source 322 * @smbus_mode: states that the controller is configured in SMBus mode 323 * @host_notify_client: SMBus host-notify client 324 * @analog_filter: boolean to indicate enabling of the analog filter 325 * @dnf_dt: value of digital filter requested via dt 326 * @dnf: value of digital filter to apply 327 * @alert: SMBus alert specific data 328 * @atomic: boolean indicating that current transfer is atomic 329 */ 330 struct stm32f7_i2c_dev { 331 struct i2c_adapter adap; 332 struct device *dev; 333 void __iomem *base; 334 struct completion complete; 335 struct clk *clk; 336 unsigned int bus_rate; 337 struct i2c_msg *msg; 338 unsigned int msg_num; 339 unsigned int msg_id; 340 struct stm32f7_i2c_msg f7_msg; 341 struct stm32f7_i2c_setup setup; 342 struct stm32f7_i2c_timings timing; 343 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 344 struct i2c_client *slave_running; 345 struct stm32f7_i2c_regs backup_regs; 346 u32 slave_dir; 347 bool master_mode; 348 struct stm32_i2c_dma *dma; 349 bool use_dma; 350 struct regmap *regmap; 351 u32 fmp_sreg; 352 u32 fmp_creg; 353 u32 fmp_mask; 354 bool wakeup_src; 355 bool smbus_mode; 356 struct i2c_client *host_notify_client; 357 bool analog_filter; 358 u32 dnf_dt; 359 u32 dnf; 360 struct stm32f7_i2c_alert *alert; 361 bool atomic; 362 }; 363 364 /* 365 * All these values are coming from I2C Specification, Version 6.0, 4th of 366 * April 2014. 367 * 368 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 369 * and Fast-mode Plus I2C-bus devices 370 */ 371 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = { 372 { 373 .rate = I2C_MAX_STANDARD_MODE_FREQ, 374 .fall_max = 300, 375 .rise_max = 1000, 376 .hddat_min = 0, 377 .vddat_max = 3450, 378 .sudat_min = 250, 379 .l_min = 4700, 380 .h_min = 4000, 381 }, 382 { 383 .rate = I2C_MAX_FAST_MODE_FREQ, 384 .fall_max = 300, 385 .rise_max = 300, 386 .hddat_min = 0, 387 .vddat_max = 900, 388 .sudat_min = 100, 389 .l_min = 1300, 390 .h_min = 600, 391 }, 392 { 393 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ, 394 .fall_max = 100, 395 .rise_max = 120, 396 .hddat_min = 0, 397 .vddat_max = 450, 398 .sudat_min = 50, 399 .l_min = 500, 400 .h_min = 260, 401 }, 402 }; 403 404 static const struct stm32f7_i2c_setup stm32f7_setup = { 405 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 406 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 407 }; 408 409 static const struct stm32f7_i2c_setup stm32mp15_setup = { 410 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 411 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 412 .fmp_clr_offset = 0x40, 413 }; 414 415 static const struct stm32f7_i2c_setup stm32mp13_setup = { 416 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 417 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 418 .fmp_clr_offset = 0x4, 419 }; 420 421 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 422 { 423 writel_relaxed(readl_relaxed(reg) | mask, reg); 424 } 425 426 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 427 { 428 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 429 } 430 431 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 432 { 433 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 434 } 435 436 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate) 437 { 438 int i; 439 440 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++) 441 if (rate <= stm32f7_i2c_specs[i].rate) 442 return &stm32f7_i2c_specs[i]; 443 444 return ERR_PTR(-EINVAL); 445 } 446 447 #define RATE_MIN(rate) ((rate) * 8 / 10) 448 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 449 struct stm32f7_i2c_setup *setup, 450 struct stm32f7_i2c_timings *output) 451 { 452 struct stm32f7_i2c_spec *specs; 453 u32 p_prev = STM32F7_PRESC_MAX; 454 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 455 setup->clock_src); 456 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 457 setup->speed_freq); 458 u32 clk_error_prev = i2cbus; 459 u32 tsync; 460 u32 af_delay_min, af_delay_max; 461 u32 dnf_delay; 462 u32 clk_min, clk_max; 463 int sdadel_min, sdadel_max; 464 int scldel_min; 465 struct stm32f7_i2c_timings *v, *_v, *s; 466 struct list_head solutions; 467 u16 p, l, a, h; 468 int ret = 0; 469 470 specs = stm32f7_get_specs(setup->speed_freq); 471 if (specs == ERR_PTR(-EINVAL)) { 472 dev_err(i2c_dev->dev, "speed out of bound {%d}\n", 473 setup->speed_freq); 474 return -EINVAL; 475 } 476 477 if ((setup->rise_time > specs->rise_max) || 478 (setup->fall_time > specs->fall_max)) { 479 dev_err(i2c_dev->dev, 480 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 481 setup->rise_time, specs->rise_max, 482 setup->fall_time, specs->fall_max); 483 return -EINVAL; 484 } 485 486 i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk); 487 if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) { 488 dev_err(i2c_dev->dev, 489 "DNF out of bound %d/%d\n", 490 i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk); 491 return -EINVAL; 492 } 493 494 /* Analog and Digital Filters */ 495 af_delay_min = 496 (i2c_dev->analog_filter ? 497 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 498 af_delay_max = 499 (i2c_dev->analog_filter ? 500 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 501 dnf_delay = i2c_dev->dnf * i2cclk; 502 503 sdadel_min = specs->hddat_min + setup->fall_time - 504 af_delay_min - (i2c_dev->dnf + 3) * i2cclk; 505 506 sdadel_max = specs->vddat_max - setup->rise_time - 507 af_delay_max - (i2c_dev->dnf + 4) * i2cclk; 508 509 scldel_min = setup->rise_time + specs->sudat_min; 510 511 if (sdadel_min < 0) 512 sdadel_min = 0; 513 if (sdadel_max < 0) 514 sdadel_max = 0; 515 516 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 517 sdadel_min, sdadel_max, scldel_min); 518 519 INIT_LIST_HEAD(&solutions); 520 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 521 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 522 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 523 u32 scldel = (l + 1) * (p + 1) * i2cclk; 524 525 if (scldel < scldel_min) 526 continue; 527 528 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 529 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 530 531 if (((sdadel >= sdadel_min) && 532 (sdadel <= sdadel_max)) && 533 (p != p_prev)) { 534 v = kmalloc(sizeof(*v), GFP_KERNEL); 535 if (!v) { 536 ret = -ENOMEM; 537 goto exit; 538 } 539 540 v->presc = p; 541 v->scldel = l; 542 v->sdadel = a; 543 p_prev = p; 544 545 list_add_tail(&v->node, 546 &solutions); 547 break; 548 } 549 } 550 551 if (p_prev == p) 552 break; 553 } 554 } 555 556 if (list_empty(&solutions)) { 557 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 558 ret = -EPERM; 559 goto exit; 560 } 561 562 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 563 s = NULL; 564 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq); 565 clk_min = NSEC_PER_SEC / setup->speed_freq; 566 567 /* 568 * Among Prescaler possibilities discovered above figures out SCL Low 569 * and High Period. Provided: 570 * - SCL Low Period has to be higher than SCL Clock Low Period 571 * defined by I2C Specification. I2C Clock has to be lower than 572 * (SCL Low Period - Analog/Digital filters) / 4. 573 * - SCL High Period has to be lower than SCL Clock High Period 574 * defined by I2C Specification 575 * - I2C Clock has to be lower than SCL High Period 576 */ 577 list_for_each_entry(v, &solutions, node) { 578 u32 prescaler = (v->presc + 1) * i2cclk; 579 580 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 581 u32 tscl_l = (l + 1) * prescaler + tsync; 582 583 if ((tscl_l < specs->l_min) || 584 (i2cclk >= 585 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 586 continue; 587 } 588 589 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 590 u32 tscl_h = (h + 1) * prescaler + tsync; 591 u32 tscl = tscl_l + tscl_h + 592 setup->rise_time + setup->fall_time; 593 594 if ((tscl >= clk_min) && (tscl <= clk_max) && 595 (tscl_h >= specs->h_min) && 596 (i2cclk < tscl_h)) { 597 int clk_error = tscl - i2cbus; 598 599 if (clk_error < 0) 600 clk_error = -clk_error; 601 602 if (clk_error < clk_error_prev) { 603 clk_error_prev = clk_error; 604 v->scll = l; 605 v->sclh = h; 606 s = v; 607 } 608 } 609 } 610 } 611 } 612 613 if (!s) { 614 dev_err(i2c_dev->dev, "no solution at all\n"); 615 ret = -EPERM; 616 goto exit; 617 } 618 619 output->presc = s->presc; 620 output->scldel = s->scldel; 621 output->sdadel = s->sdadel; 622 output->scll = s->scll; 623 output->sclh = s->sclh; 624 625 dev_dbg(i2c_dev->dev, 626 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 627 output->presc, 628 output->scldel, output->sdadel, 629 output->scll, output->sclh); 630 631 exit: 632 /* Release list and memory */ 633 list_for_each_entry_safe(v, _v, &solutions, node) { 634 list_del(&v->node); 635 kfree(v); 636 } 637 638 return ret; 639 } 640 641 static u32 stm32f7_get_lower_rate(u32 rate) 642 { 643 int i = ARRAY_SIZE(stm32f7_i2c_specs); 644 645 while (--i) 646 if (stm32f7_i2c_specs[i].rate < rate) 647 break; 648 649 return stm32f7_i2c_specs[i].rate; 650 } 651 652 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 653 struct stm32f7_i2c_setup *setup) 654 { 655 struct i2c_timings timings, *t = &timings; 656 int ret = 0; 657 658 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 659 t->scl_rise_ns = i2c_dev->setup.rise_time; 660 t->scl_fall_ns = i2c_dev->setup.fall_time; 661 662 i2c_parse_fw_timings(i2c_dev->dev, t, false); 663 664 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) { 665 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n", 666 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ); 667 return -EINVAL; 668 } 669 670 setup->speed_freq = t->bus_freq_hz; 671 i2c_dev->setup.rise_time = t->scl_rise_ns; 672 i2c_dev->setup.fall_time = t->scl_fall_ns; 673 i2c_dev->dnf_dt = t->digital_filter_width_ns; 674 setup->clock_src = clk_get_rate(i2c_dev->clk); 675 676 if (!setup->clock_src) { 677 dev_err(i2c_dev->dev, "clock rate is 0\n"); 678 return -EINVAL; 679 } 680 681 if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter")) 682 i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT; 683 684 do { 685 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 686 &i2c_dev->timing); 687 if (ret) { 688 dev_err(i2c_dev->dev, 689 "failed to compute I2C timings.\n"); 690 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ) 691 break; 692 setup->speed_freq = 693 stm32f7_get_lower_rate(setup->speed_freq); 694 dev_warn(i2c_dev->dev, 695 "downgrade I2C Speed Freq to (%i)\n", 696 setup->speed_freq); 697 } 698 } while (ret); 699 700 if (ret) { 701 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 702 return ret; 703 } 704 705 i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node, 706 "i2c-analog-filter"); 707 708 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n", 709 setup->speed_freq, setup->clock_src); 710 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 711 setup->rise_time, setup->fall_time); 712 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 713 (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf); 714 715 i2c_dev->bus_rate = setup->speed_freq; 716 717 return 0; 718 } 719 720 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 721 { 722 void __iomem *base = i2c_dev->base; 723 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 724 725 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 726 } 727 728 static void stm32f7_i2c_dma_callback(void *arg) 729 { 730 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 731 struct stm32_i2c_dma *dma = i2c_dev->dma; 732 struct device *dev = dma->chan_using->device->dev; 733 734 stm32f7_i2c_disable_dma_req(i2c_dev); 735 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 736 complete(&dma->dma_complete); 737 } 738 739 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 740 { 741 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 742 u32 timing = 0; 743 744 /* Timing settings */ 745 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 746 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 747 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 748 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 749 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 750 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 751 752 /* Configure the Analog Filter */ 753 if (i2c_dev->analog_filter) 754 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 755 STM32F7_I2C_CR1_ANFOFF); 756 else 757 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 758 STM32F7_I2C_CR1_ANFOFF); 759 760 /* Program the Digital Filter */ 761 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 762 STM32F7_I2C_CR1_DNF_MASK); 763 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 764 STM32F7_I2C_CR1_DNF(i2c_dev->dnf)); 765 766 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 767 STM32F7_I2C_CR1_PE); 768 } 769 770 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 771 { 772 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 773 void __iomem *base = i2c_dev->base; 774 775 if (f7_msg->count) { 776 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 777 f7_msg->count--; 778 } 779 } 780 781 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 782 { 783 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 784 void __iomem *base = i2c_dev->base; 785 786 if (f7_msg->count) { 787 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 788 f7_msg->count--; 789 } else { 790 /* Flush RX buffer has no data is expected */ 791 readb_relaxed(base + STM32F7_I2C_RXDR); 792 } 793 } 794 795 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 796 { 797 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 798 u32 cr2; 799 800 if (i2c_dev->use_dma) 801 f7_msg->count -= STM32F7_I2C_MAX_LEN; 802 803 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 804 805 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 806 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 807 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 808 } else { 809 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 810 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 811 } 812 813 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 814 } 815 816 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 817 { 818 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 819 u32 cr2; 820 u8 *val; 821 822 /* 823 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 824 * data received inform us how many data will follow. 825 */ 826 stm32f7_i2c_read_rx_data(i2c_dev); 827 828 /* 829 * Update NBYTES with the value read to continue the transfer 830 */ 831 val = f7_msg->buf - sizeof(u8); 832 f7_msg->count = *val; 833 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 834 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 835 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 836 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 837 } 838 839 static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 840 { 841 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 842 843 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 844 STM32F7_I2C_CR1_PE); 845 846 stm32f7_i2c_hw_config(i2c_dev); 847 } 848 849 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 850 { 851 u32 status; 852 int ret; 853 854 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 855 status, 856 !(status & STM32F7_I2C_ISR_BUSY), 857 10, 1000); 858 if (!ret) 859 return 0; 860 861 stm32f7_i2c_release_bus(&i2c_dev->adap); 862 863 return -EBUSY; 864 } 865 866 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 867 struct i2c_msg *msg) 868 { 869 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 870 void __iomem *base = i2c_dev->base; 871 u32 cr1, cr2; 872 int ret; 873 874 f7_msg->addr = msg->addr; 875 f7_msg->buf = msg->buf; 876 f7_msg->count = msg->len; 877 f7_msg->result = 0; 878 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 879 880 reinit_completion(&i2c_dev->complete); 881 882 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 883 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 884 885 /* Set transfer direction */ 886 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 887 if (msg->flags & I2C_M_RD) 888 cr2 |= STM32F7_I2C_CR2_RD_WRN; 889 890 /* Set slave address */ 891 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 892 if (msg->flags & I2C_M_TEN) { 893 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 894 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 895 cr2 |= STM32F7_I2C_CR2_ADD10; 896 } else { 897 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 898 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 899 } 900 901 /* Set nb bytes to transfer and reload if needed */ 902 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 903 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 904 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 905 cr2 |= STM32F7_I2C_CR2_RELOAD; 906 } else { 907 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 908 } 909 910 /* Enable NACK, STOP, error and transfer complete interrupts */ 911 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 912 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 913 914 /* Clear DMA req and TX/RX interrupt */ 915 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 916 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 917 918 /* Configure DMA or enable RX/TX interrupt */ 919 i2c_dev->use_dma = false; 920 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN 921 && !i2c_dev->atomic) { 922 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 923 msg->flags & I2C_M_RD, 924 f7_msg->count, f7_msg->buf, 925 stm32f7_i2c_dma_callback, 926 i2c_dev); 927 if (!ret) 928 i2c_dev->use_dma = true; 929 else 930 dev_warn(i2c_dev->dev, "can't use DMA\n"); 931 } 932 933 if (!i2c_dev->use_dma) { 934 if (msg->flags & I2C_M_RD) 935 cr1 |= STM32F7_I2C_CR1_RXIE; 936 else 937 cr1 |= STM32F7_I2C_CR1_TXIE; 938 } else { 939 if (msg->flags & I2C_M_RD) 940 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 941 else 942 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 943 } 944 945 if (i2c_dev->atomic) 946 cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */ 947 948 /* Configure Start/Repeated Start */ 949 cr2 |= STM32F7_I2C_CR2_START; 950 951 i2c_dev->master_mode = true; 952 953 /* Write configurations registers */ 954 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 955 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 956 } 957 958 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 959 unsigned short flags, u8 command, 960 union i2c_smbus_data *data) 961 { 962 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 963 struct device *dev = i2c_dev->dev; 964 void __iomem *base = i2c_dev->base; 965 u32 cr1, cr2; 966 int i, ret; 967 968 f7_msg->result = 0; 969 reinit_completion(&i2c_dev->complete); 970 971 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 972 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 973 974 /* Set transfer direction */ 975 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 976 if (f7_msg->read_write) 977 cr2 |= STM32F7_I2C_CR2_RD_WRN; 978 979 /* Set slave address */ 980 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 981 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 982 983 f7_msg->smbus_buf[0] = command; 984 switch (f7_msg->size) { 985 case I2C_SMBUS_QUICK: 986 f7_msg->stop = true; 987 f7_msg->count = 0; 988 break; 989 case I2C_SMBUS_BYTE: 990 f7_msg->stop = true; 991 f7_msg->count = 1; 992 break; 993 case I2C_SMBUS_BYTE_DATA: 994 if (f7_msg->read_write) { 995 f7_msg->stop = false; 996 f7_msg->count = 1; 997 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 998 } else { 999 f7_msg->stop = true; 1000 f7_msg->count = 2; 1001 f7_msg->smbus_buf[1] = data->byte; 1002 } 1003 break; 1004 case I2C_SMBUS_WORD_DATA: 1005 if (f7_msg->read_write) { 1006 f7_msg->stop = false; 1007 f7_msg->count = 1; 1008 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1009 } else { 1010 f7_msg->stop = true; 1011 f7_msg->count = 3; 1012 f7_msg->smbus_buf[1] = data->word & 0xff; 1013 f7_msg->smbus_buf[2] = data->word >> 8; 1014 } 1015 break; 1016 case I2C_SMBUS_BLOCK_DATA: 1017 if (f7_msg->read_write) { 1018 f7_msg->stop = false; 1019 f7_msg->count = 1; 1020 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1021 } else { 1022 f7_msg->stop = true; 1023 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 1024 !data->block[0]) { 1025 dev_err(dev, "Invalid block write size %d\n", 1026 data->block[0]); 1027 return -EINVAL; 1028 } 1029 f7_msg->count = data->block[0] + 2; 1030 for (i = 1; i < f7_msg->count; i++) 1031 f7_msg->smbus_buf[i] = data->block[i - 1]; 1032 } 1033 break; 1034 case I2C_SMBUS_PROC_CALL: 1035 f7_msg->stop = false; 1036 f7_msg->count = 3; 1037 f7_msg->smbus_buf[1] = data->word & 0xff; 1038 f7_msg->smbus_buf[2] = data->word >> 8; 1039 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1040 f7_msg->read_write = I2C_SMBUS_READ; 1041 break; 1042 case I2C_SMBUS_BLOCK_PROC_CALL: 1043 f7_msg->stop = false; 1044 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 1045 dev_err(dev, "Invalid block write size %d\n", 1046 data->block[0]); 1047 return -EINVAL; 1048 } 1049 f7_msg->count = data->block[0] + 2; 1050 for (i = 1; i < f7_msg->count; i++) 1051 f7_msg->smbus_buf[i] = data->block[i - 1]; 1052 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 1053 f7_msg->read_write = I2C_SMBUS_READ; 1054 break; 1055 case I2C_SMBUS_I2C_BLOCK_DATA: 1056 /* Rely on emulated i2c transfer (through master_xfer) */ 1057 return -EOPNOTSUPP; 1058 default: 1059 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 1060 return -EOPNOTSUPP; 1061 } 1062 1063 f7_msg->buf = f7_msg->smbus_buf; 1064 1065 /* Configure PEC */ 1066 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 1067 cr1 |= STM32F7_I2C_CR1_PECEN; 1068 if (!f7_msg->read_write) { 1069 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1070 f7_msg->count++; 1071 } 1072 } else { 1073 cr1 &= ~STM32F7_I2C_CR1_PECEN; 1074 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 1075 } 1076 1077 /* Set number of bytes to be transferred */ 1078 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 1079 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1080 1081 /* Enable NACK, STOP, error and transfer complete interrupts */ 1082 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 1083 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 1084 1085 /* Clear DMA req and TX/RX interrupt */ 1086 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1087 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1088 1089 /* Configure DMA or enable RX/TX interrupt */ 1090 i2c_dev->use_dma = false; 1091 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 1092 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1093 cr2 & STM32F7_I2C_CR2_RD_WRN, 1094 f7_msg->count, f7_msg->buf, 1095 stm32f7_i2c_dma_callback, 1096 i2c_dev); 1097 if (!ret) 1098 i2c_dev->use_dma = true; 1099 else 1100 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1101 } 1102 1103 if (!i2c_dev->use_dma) { 1104 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1105 cr1 |= STM32F7_I2C_CR1_RXIE; 1106 else 1107 cr1 |= STM32F7_I2C_CR1_TXIE; 1108 } else { 1109 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1110 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1111 else 1112 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1113 } 1114 1115 /* Set Start bit */ 1116 cr2 |= STM32F7_I2C_CR2_START; 1117 1118 i2c_dev->master_mode = true; 1119 1120 /* Write configurations registers */ 1121 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1122 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1123 1124 return 0; 1125 } 1126 1127 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1128 { 1129 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1130 void __iomem *base = i2c_dev->base; 1131 u32 cr1, cr2; 1132 int ret; 1133 1134 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1135 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1136 1137 /* Set transfer direction */ 1138 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1139 1140 switch (f7_msg->size) { 1141 case I2C_SMBUS_BYTE_DATA: 1142 f7_msg->count = 1; 1143 break; 1144 case I2C_SMBUS_WORD_DATA: 1145 case I2C_SMBUS_PROC_CALL: 1146 f7_msg->count = 2; 1147 break; 1148 case I2C_SMBUS_BLOCK_DATA: 1149 case I2C_SMBUS_BLOCK_PROC_CALL: 1150 f7_msg->count = 1; 1151 cr2 |= STM32F7_I2C_CR2_RELOAD; 1152 break; 1153 } 1154 1155 f7_msg->buf = f7_msg->smbus_buf; 1156 f7_msg->stop = true; 1157 1158 /* Add one byte for PEC if needed */ 1159 if (cr1 & STM32F7_I2C_CR1_PECEN) { 1160 cr2 |= STM32F7_I2C_CR2_PECBYTE; 1161 f7_msg->count++; 1162 } 1163 1164 /* Set number of bytes to be transferred */ 1165 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1166 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1167 1168 /* 1169 * Configure RX/TX interrupt: 1170 */ 1171 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1172 cr1 |= STM32F7_I2C_CR1_RXIE; 1173 1174 /* 1175 * Configure DMA or enable RX/TX interrupt: 1176 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1177 * dma as we don't know in advance how many data will be received 1178 */ 1179 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1180 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1181 1182 i2c_dev->use_dma = false; 1183 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1184 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1185 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1186 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1187 cr2 & STM32F7_I2C_CR2_RD_WRN, 1188 f7_msg->count, f7_msg->buf, 1189 stm32f7_i2c_dma_callback, 1190 i2c_dev); 1191 1192 if (!ret) 1193 i2c_dev->use_dma = true; 1194 else 1195 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1196 } 1197 1198 if (!i2c_dev->use_dma) 1199 cr1 |= STM32F7_I2C_CR1_RXIE; 1200 else 1201 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1202 1203 /* Configure Repeated Start */ 1204 cr2 |= STM32F7_I2C_CR2_START; 1205 1206 /* Write configurations registers */ 1207 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1208 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1209 } 1210 1211 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1212 { 1213 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1214 u8 count, internal_pec, received_pec; 1215 1216 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1217 1218 switch (f7_msg->size) { 1219 case I2C_SMBUS_BYTE: 1220 case I2C_SMBUS_BYTE_DATA: 1221 received_pec = f7_msg->smbus_buf[1]; 1222 break; 1223 case I2C_SMBUS_WORD_DATA: 1224 case I2C_SMBUS_PROC_CALL: 1225 received_pec = f7_msg->smbus_buf[2]; 1226 break; 1227 case I2C_SMBUS_BLOCK_DATA: 1228 case I2C_SMBUS_BLOCK_PROC_CALL: 1229 count = f7_msg->smbus_buf[0]; 1230 received_pec = f7_msg->smbus_buf[count]; 1231 break; 1232 default: 1233 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1234 return -EINVAL; 1235 } 1236 1237 if (internal_pec != received_pec) { 1238 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1239 internal_pec, received_pec); 1240 return -EBADMSG; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1247 { 1248 u32 addr; 1249 1250 if (!slave) 1251 return false; 1252 1253 if (slave->flags & I2C_CLIENT_TEN) { 1254 /* 1255 * For 10-bit addr, addcode = 11110XY with 1256 * X = Bit 9 of slave address 1257 * Y = Bit 8 of slave address 1258 */ 1259 addr = slave->addr >> 8; 1260 addr |= 0x78; 1261 if (addr == addcode) 1262 return true; 1263 } else { 1264 addr = slave->addr & 0x7f; 1265 if (addr == addcode) 1266 return true; 1267 } 1268 1269 return false; 1270 } 1271 1272 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1273 { 1274 struct i2c_client *slave = i2c_dev->slave_running; 1275 void __iomem *base = i2c_dev->base; 1276 u32 mask; 1277 u8 value = 0; 1278 1279 if (i2c_dev->slave_dir) { 1280 /* Notify i2c slave that new read transfer is starting */ 1281 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1282 1283 /* 1284 * Disable slave TX config in case of I2C combined message 1285 * (I2C Write followed by I2C Read) 1286 */ 1287 mask = STM32F7_I2C_CR2_RELOAD; 1288 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1289 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1290 STM32F7_I2C_CR1_TCIE; 1291 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1292 1293 /* Enable TX empty, STOP, NACK interrupts */ 1294 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1295 STM32F7_I2C_CR1_TXIE; 1296 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1297 1298 /* Write 1st data byte */ 1299 writel_relaxed(value, base + STM32F7_I2C_TXDR); 1300 } else { 1301 /* Notify i2c slave that new write transfer is starting */ 1302 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1303 1304 /* Set reload mode to be able to ACK/NACK each received byte */ 1305 mask = STM32F7_I2C_CR2_RELOAD; 1306 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1307 1308 /* 1309 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1310 * Set Slave Byte Control to be able to ACK/NACK each data 1311 * byte received 1312 */ 1313 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1314 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1315 STM32F7_I2C_CR1_TCIE; 1316 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1317 } 1318 } 1319 1320 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1321 { 1322 void __iomem *base = i2c_dev->base; 1323 u32 isr, addcode, dir, mask; 1324 int i; 1325 1326 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1327 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1328 dir = isr & STM32F7_I2C_ISR_DIR; 1329 1330 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1331 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1332 i2c_dev->slave_running = i2c_dev->slave[i]; 1333 i2c_dev->slave_dir = dir; 1334 1335 /* Start I2C slave processing */ 1336 stm32f7_i2c_slave_start(i2c_dev); 1337 1338 /* Clear ADDR flag */ 1339 mask = STM32F7_I2C_ICR_ADDRCF; 1340 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1341 break; 1342 } 1343 } 1344 } 1345 1346 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1347 struct i2c_client *slave, int *id) 1348 { 1349 int i; 1350 1351 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1352 if (i2c_dev->slave[i] == slave) { 1353 *id = i; 1354 return 0; 1355 } 1356 } 1357 1358 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1359 1360 return -ENODEV; 1361 } 1362 1363 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1364 struct i2c_client *slave, int *id) 1365 { 1366 struct device *dev = i2c_dev->dev; 1367 int i; 1368 1369 /* 1370 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8) 1371 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address 1372 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only 1373 */ 1374 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) { 1375 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY]) 1376 goto fail; 1377 *id = STM32F7_SLAVE_HOSTNOTIFY; 1378 return 0; 1379 } 1380 1381 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) { 1382 if ((i == STM32F7_SLAVE_7_BITS_ADDR) && 1383 (slave->flags & I2C_CLIENT_TEN)) 1384 continue; 1385 if (!i2c_dev->slave[i]) { 1386 *id = i; 1387 return 0; 1388 } 1389 } 1390 1391 fail: 1392 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1393 1394 return -EINVAL; 1395 } 1396 1397 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1398 { 1399 int i; 1400 1401 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1402 if (i2c_dev->slave[i]) 1403 return true; 1404 } 1405 1406 return false; 1407 } 1408 1409 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1410 { 1411 int i, busy; 1412 1413 busy = 0; 1414 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1415 if (i2c_dev->slave[i]) 1416 busy++; 1417 } 1418 1419 return i == busy; 1420 } 1421 1422 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1423 { 1424 void __iomem *base = i2c_dev->base; 1425 u32 cr2, status, mask; 1426 u8 val; 1427 int ret; 1428 1429 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1430 1431 /* Slave transmitter mode */ 1432 if (status & STM32F7_I2C_ISR_TXIS) { 1433 i2c_slave_event(i2c_dev->slave_running, 1434 I2C_SLAVE_READ_PROCESSED, 1435 &val); 1436 1437 /* Write data byte */ 1438 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1439 } 1440 1441 /* Transfer Complete Reload for Slave receiver mode */ 1442 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1443 /* 1444 * Read data byte then set NBYTES to receive next byte or NACK 1445 * the current received byte 1446 */ 1447 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1448 ret = i2c_slave_event(i2c_dev->slave_running, 1449 I2C_SLAVE_WRITE_RECEIVED, 1450 &val); 1451 if (!ret) { 1452 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1453 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1454 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1455 } else { 1456 mask = STM32F7_I2C_CR2_NACK; 1457 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1458 } 1459 } 1460 1461 /* NACK received */ 1462 if (status & STM32F7_I2C_ISR_NACKF) { 1463 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1464 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1465 } 1466 1467 /* STOP received */ 1468 if (status & STM32F7_I2C_ISR_STOPF) { 1469 /* Disable interrupts */ 1470 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1471 1472 if (i2c_dev->slave_dir) { 1473 /* 1474 * Flush TX buffer in order to not used the byte in 1475 * TXDR for the next transfer 1476 */ 1477 mask = STM32F7_I2C_ISR_TXE; 1478 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1479 } 1480 1481 /* Clear STOP flag */ 1482 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1483 1484 /* Notify i2c slave that a STOP flag has been detected */ 1485 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1486 1487 i2c_dev->slave_running = NULL; 1488 } 1489 1490 /* Address match received */ 1491 if (status & STM32F7_I2C_ISR_ADDR) 1492 stm32f7_i2c_slave_addr(i2c_dev); 1493 1494 return IRQ_HANDLED; 1495 } 1496 1497 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1498 { 1499 struct stm32f7_i2c_dev *i2c_dev = data; 1500 u32 status; 1501 1502 /* Check if the interrupt is for a slave device */ 1503 if (!i2c_dev->master_mode) 1504 return IRQ_WAKE_THREAD; 1505 1506 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1507 1508 /* Tx empty */ 1509 if (status & STM32F7_I2C_ISR_TXIS) 1510 stm32f7_i2c_write_tx_data(i2c_dev); 1511 1512 /* RX not empty */ 1513 if (status & STM32F7_I2C_ISR_RXNE) 1514 stm32f7_i2c_read_rx_data(i2c_dev); 1515 1516 /* Wake up the thread if other flags are raised */ 1517 if (status & 1518 (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF | 1519 STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR)) 1520 return IRQ_WAKE_THREAD; 1521 1522 return IRQ_HANDLED; 1523 } 1524 1525 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1526 { 1527 struct stm32f7_i2c_dev *i2c_dev = data; 1528 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1529 struct stm32_i2c_dma *dma = i2c_dev->dma; 1530 void __iomem *base = i2c_dev->base; 1531 u32 status, mask; 1532 int ret; 1533 1534 if (!i2c_dev->master_mode) 1535 return stm32f7_i2c_slave_isr_event(i2c_dev); 1536 1537 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1538 1539 /* NACK received */ 1540 if (status & STM32F7_I2C_ISR_NACKF) { 1541 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n", 1542 __func__, f7_msg->addr); 1543 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1544 if (i2c_dev->use_dma) { 1545 stm32f7_i2c_disable_dma_req(i2c_dev); 1546 dmaengine_terminate_async(dma->chan_using); 1547 } 1548 f7_msg->result = -ENXIO; 1549 } 1550 1551 if (status & STM32F7_I2C_ISR_TCR) { 1552 if (f7_msg->smbus) 1553 stm32f7_i2c_smbus_reload(i2c_dev); 1554 else 1555 stm32f7_i2c_reload(i2c_dev); 1556 } 1557 1558 /* Transfer complete */ 1559 if (status & STM32F7_I2C_ISR_TC) { 1560 /* Wait for dma transfer completion before sending next message */ 1561 if (i2c_dev->use_dma && !f7_msg->result) { 1562 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1563 if (!ret) { 1564 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1565 stm32f7_i2c_disable_dma_req(i2c_dev); 1566 dmaengine_terminate_async(dma->chan_using); 1567 f7_msg->result = -ETIMEDOUT; 1568 } 1569 } 1570 if (f7_msg->stop) { 1571 mask = STM32F7_I2C_CR2_STOP; 1572 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1573 } else if (f7_msg->smbus) { 1574 stm32f7_i2c_smbus_rep_start(i2c_dev); 1575 } else { 1576 i2c_dev->msg_id++; 1577 i2c_dev->msg++; 1578 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1579 } 1580 } 1581 1582 /* STOP detection flag */ 1583 if (status & STM32F7_I2C_ISR_STOPF) { 1584 /* Disable interrupts */ 1585 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1586 mask = STM32F7_I2C_XFER_IRQ_MASK; 1587 else 1588 mask = STM32F7_I2C_ALL_IRQ_MASK; 1589 stm32f7_i2c_disable_irq(i2c_dev, mask); 1590 1591 /* Clear STOP flag */ 1592 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1593 1594 i2c_dev->master_mode = false; 1595 complete(&i2c_dev->complete); 1596 } 1597 1598 return IRQ_HANDLED; 1599 } 1600 1601 static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data) 1602 { 1603 struct stm32f7_i2c_dev *i2c_dev = data; 1604 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1605 u16 addr = f7_msg->addr; 1606 void __iomem *base = i2c_dev->base; 1607 struct device *dev = i2c_dev->dev; 1608 struct stm32_i2c_dma *dma = i2c_dev->dma; 1609 u32 status; 1610 1611 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1612 1613 /* Bus error */ 1614 if (status & STM32F7_I2C_ISR_BERR) { 1615 dev_err(dev, "Bus error accessing addr 0x%x\n", addr); 1616 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1617 stm32f7_i2c_release_bus(&i2c_dev->adap); 1618 f7_msg->result = -EIO; 1619 } 1620 1621 /* Arbitration loss */ 1622 if (status & STM32F7_I2C_ISR_ARLO) { 1623 dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr); 1624 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1625 f7_msg->result = -EAGAIN; 1626 } 1627 1628 if (status & STM32F7_I2C_ISR_PECERR) { 1629 dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr); 1630 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1631 f7_msg->result = -EINVAL; 1632 } 1633 1634 if (status & STM32F7_I2C_ISR_ALERT) { 1635 dev_dbg(dev, "SMBus alert received\n"); 1636 writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR); 1637 i2c_handle_smbus_alert(i2c_dev->alert->ara); 1638 return IRQ_HANDLED; 1639 } 1640 1641 if (!i2c_dev->slave_running) { 1642 u32 mask; 1643 /* Disable interrupts */ 1644 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1645 mask = STM32F7_I2C_XFER_IRQ_MASK; 1646 else 1647 mask = STM32F7_I2C_ALL_IRQ_MASK; 1648 stm32f7_i2c_disable_irq(i2c_dev, mask); 1649 } 1650 1651 /* Disable dma */ 1652 if (i2c_dev->use_dma) { 1653 stm32f7_i2c_disable_dma_req(i2c_dev); 1654 dmaengine_terminate_async(dma->chan_using); 1655 } 1656 1657 i2c_dev->master_mode = false; 1658 complete(&i2c_dev->complete); 1659 1660 return IRQ_HANDLED; 1661 } 1662 1663 static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev) 1664 { 1665 ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout); 1666 1667 while (ktime_compare(ktime_get(), timeout) < 0) { 1668 udelay(5); 1669 stm32f7_i2c_isr_event(0, i2c_dev); 1670 1671 if (completion_done(&i2c_dev->complete)) 1672 return 1; 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap, 1679 struct i2c_msg msgs[], int num) 1680 { 1681 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1682 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1683 struct stm32_i2c_dma *dma = i2c_dev->dma; 1684 unsigned long time_left; 1685 int ret; 1686 1687 i2c_dev->msg = msgs; 1688 i2c_dev->msg_num = num; 1689 i2c_dev->msg_id = 0; 1690 f7_msg->smbus = false; 1691 1692 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1693 if (ret < 0) 1694 return ret; 1695 1696 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1697 if (ret) 1698 goto pm_free; 1699 1700 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1701 1702 if (!i2c_dev->atomic) 1703 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1704 i2c_dev->adap.timeout); 1705 else 1706 time_left = stm32f7_i2c_wait_polling(i2c_dev); 1707 1708 ret = f7_msg->result; 1709 if (ret) { 1710 if (i2c_dev->use_dma) 1711 dmaengine_synchronize(dma->chan_using); 1712 1713 /* 1714 * It is possible that some unsent data have already been 1715 * written into TXDR. To avoid sending old data in a 1716 * further transfer, flush TXDR in case of any error 1717 */ 1718 writel_relaxed(STM32F7_I2C_ISR_TXE, 1719 i2c_dev->base + STM32F7_I2C_ISR); 1720 goto pm_free; 1721 } 1722 1723 if (!time_left) { 1724 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1725 i2c_dev->msg->addr); 1726 if (i2c_dev->use_dma) 1727 dmaengine_terminate_sync(dma->chan_using); 1728 stm32f7_i2c_wait_free_bus(i2c_dev); 1729 ret = -ETIMEDOUT; 1730 } 1731 1732 pm_free: 1733 pm_runtime_mark_last_busy(i2c_dev->dev); 1734 pm_runtime_put_autosuspend(i2c_dev->dev); 1735 1736 return (ret < 0) ? ret : num; 1737 } 1738 1739 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1740 struct i2c_msg msgs[], int num) 1741 { 1742 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1743 1744 i2c_dev->atomic = false; 1745 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1746 } 1747 1748 static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap, 1749 struct i2c_msg msgs[], int num) 1750 { 1751 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1752 1753 i2c_dev->atomic = true; 1754 return stm32f7_i2c_xfer_core(i2c_adap, msgs, num); 1755 } 1756 1757 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1758 unsigned short flags, char read_write, 1759 u8 command, int size, 1760 union i2c_smbus_data *data) 1761 { 1762 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1763 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1764 struct stm32_i2c_dma *dma = i2c_dev->dma; 1765 struct device *dev = i2c_dev->dev; 1766 unsigned long timeout; 1767 int i, ret; 1768 1769 f7_msg->addr = addr; 1770 f7_msg->size = size; 1771 f7_msg->read_write = read_write; 1772 f7_msg->smbus = true; 1773 1774 ret = pm_runtime_resume_and_get(dev); 1775 if (ret < 0) 1776 return ret; 1777 1778 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1779 if (ret) 1780 goto pm_free; 1781 1782 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1783 if (ret) 1784 goto pm_free; 1785 1786 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1787 i2c_dev->adap.timeout); 1788 ret = f7_msg->result; 1789 if (ret) { 1790 if (i2c_dev->use_dma) 1791 dmaengine_synchronize(dma->chan_using); 1792 1793 /* 1794 * It is possible that some unsent data have already been 1795 * written into TXDR. To avoid sending old data in a 1796 * further transfer, flush TXDR in case of any error 1797 */ 1798 writel_relaxed(STM32F7_I2C_ISR_TXE, 1799 i2c_dev->base + STM32F7_I2C_ISR); 1800 goto pm_free; 1801 } 1802 1803 if (!timeout) { 1804 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1805 if (i2c_dev->use_dma) 1806 dmaengine_terminate_sync(dma->chan_using); 1807 stm32f7_i2c_wait_free_bus(i2c_dev); 1808 ret = -ETIMEDOUT; 1809 goto pm_free; 1810 } 1811 1812 /* Check PEC */ 1813 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1814 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1815 if (ret) 1816 goto pm_free; 1817 } 1818 1819 if (read_write && size != I2C_SMBUS_QUICK) { 1820 switch (size) { 1821 case I2C_SMBUS_BYTE: 1822 case I2C_SMBUS_BYTE_DATA: 1823 data->byte = f7_msg->smbus_buf[0]; 1824 break; 1825 case I2C_SMBUS_WORD_DATA: 1826 case I2C_SMBUS_PROC_CALL: 1827 data->word = f7_msg->smbus_buf[0] | 1828 (f7_msg->smbus_buf[1] << 8); 1829 break; 1830 case I2C_SMBUS_BLOCK_DATA: 1831 case I2C_SMBUS_BLOCK_PROC_CALL: 1832 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1833 data->block[i] = f7_msg->smbus_buf[i]; 1834 break; 1835 default: 1836 dev_err(dev, "Unsupported smbus transaction\n"); 1837 ret = -EINVAL; 1838 } 1839 } 1840 1841 pm_free: 1842 pm_runtime_mark_last_busy(dev); 1843 pm_runtime_put_autosuspend(dev); 1844 return ret; 1845 } 1846 1847 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev, 1848 bool enable) 1849 { 1850 void __iomem *base = i2c_dev->base; 1851 u32 mask = STM32F7_I2C_CR1_WUPEN; 1852 1853 if (!i2c_dev->wakeup_src) 1854 return; 1855 1856 if (enable) { 1857 device_set_wakeup_enable(i2c_dev->dev, true); 1858 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1859 } else { 1860 device_set_wakeup_enable(i2c_dev->dev, false); 1861 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1862 } 1863 } 1864 1865 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1866 { 1867 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1868 void __iomem *base = i2c_dev->base; 1869 struct device *dev = i2c_dev->dev; 1870 u32 oar1, oar2, mask; 1871 int id, ret; 1872 1873 if (slave->flags & I2C_CLIENT_PEC) { 1874 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1875 return -EINVAL; 1876 } 1877 1878 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1879 dev_err(dev, "Too much slave registered\n"); 1880 return -EBUSY; 1881 } 1882 1883 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1884 if (ret) 1885 return ret; 1886 1887 ret = pm_runtime_resume_and_get(dev); 1888 if (ret < 0) 1889 return ret; 1890 1891 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1892 stm32f7_i2c_enable_wakeup(i2c_dev, true); 1893 1894 switch (id) { 1895 case 0: 1896 /* Slave SMBus Host */ 1897 i2c_dev->slave[id] = slave; 1898 break; 1899 1900 case 1: 1901 /* Configure Own Address 1 */ 1902 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1903 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1904 if (slave->flags & I2C_CLIENT_TEN) { 1905 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1906 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1907 } else { 1908 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1909 } 1910 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1911 i2c_dev->slave[id] = slave; 1912 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1913 break; 1914 1915 case 2: 1916 /* Configure Own Address 2 */ 1917 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1918 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1919 if (slave->flags & I2C_CLIENT_TEN) { 1920 ret = -EOPNOTSUPP; 1921 goto pm_free; 1922 } 1923 1924 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1925 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1926 i2c_dev->slave[id] = slave; 1927 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1928 break; 1929 1930 default: 1931 dev_err(dev, "I2C slave id not supported\n"); 1932 ret = -ENODEV; 1933 goto pm_free; 1934 } 1935 1936 /* Enable ACK */ 1937 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1938 1939 /* Enable Address match interrupt, error interrupt and enable I2C */ 1940 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1941 STM32F7_I2C_CR1_PE; 1942 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1943 1944 ret = 0; 1945 pm_free: 1946 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 1947 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1948 1949 pm_runtime_mark_last_busy(dev); 1950 pm_runtime_put_autosuspend(dev); 1951 1952 return ret; 1953 } 1954 1955 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1956 { 1957 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1958 void __iomem *base = i2c_dev->base; 1959 u32 mask; 1960 int id, ret; 1961 1962 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1963 if (ret) 1964 return ret; 1965 1966 WARN_ON(!i2c_dev->slave[id]); 1967 1968 ret = pm_runtime_resume_and_get(i2c_dev->dev); 1969 if (ret < 0) 1970 return ret; 1971 1972 if (id == 1) { 1973 mask = STM32F7_I2C_OAR1_OA1EN; 1974 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1975 } else if (id == 2) { 1976 mask = STM32F7_I2C_OAR2_OA2EN; 1977 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1978 } 1979 1980 i2c_dev->slave[id] = NULL; 1981 1982 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 1983 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1984 stm32f7_i2c_enable_wakeup(i2c_dev, false); 1985 } 1986 1987 pm_runtime_mark_last_busy(i2c_dev->dev); 1988 pm_runtime_put_autosuspend(i2c_dev->dev); 1989 1990 return 0; 1991 } 1992 1993 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev, 1994 bool enable) 1995 { 1996 int ret; 1997 1998 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ || 1999 IS_ERR_OR_NULL(i2c_dev->regmap)) 2000 /* Optional */ 2001 return 0; 2002 2003 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg) 2004 ret = regmap_update_bits(i2c_dev->regmap, 2005 i2c_dev->fmp_sreg, 2006 i2c_dev->fmp_mask, 2007 enable ? i2c_dev->fmp_mask : 0); 2008 else 2009 ret = regmap_write(i2c_dev->regmap, 2010 enable ? i2c_dev->fmp_sreg : 2011 i2c_dev->fmp_creg, 2012 i2c_dev->fmp_mask); 2013 2014 return ret; 2015 } 2016 2017 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 2018 struct stm32f7_i2c_dev *i2c_dev) 2019 { 2020 struct device_node *np = pdev->dev.of_node; 2021 int ret; 2022 2023 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 2024 if (IS_ERR(i2c_dev->regmap)) 2025 /* Optional */ 2026 return 0; 2027 2028 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, 2029 &i2c_dev->fmp_sreg); 2030 if (ret) 2031 return ret; 2032 2033 i2c_dev->fmp_creg = i2c_dev->fmp_sreg + 2034 i2c_dev->setup.fmp_clr_offset; 2035 2036 return of_property_read_u32_index(np, "st,syscfg-fmp", 2, 2037 &i2c_dev->fmp_mask); 2038 } 2039 2040 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2041 { 2042 struct i2c_adapter *adap = &i2c_dev->adap; 2043 void __iomem *base = i2c_dev->base; 2044 struct i2c_client *client; 2045 2046 client = i2c_new_slave_host_notify_device(adap); 2047 if (IS_ERR(client)) 2048 return PTR_ERR(client); 2049 2050 i2c_dev->host_notify_client = client; 2051 2052 /* Enable SMBus Host address */ 2053 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN); 2054 2055 return 0; 2056 } 2057 2058 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev) 2059 { 2060 void __iomem *base = i2c_dev->base; 2061 2062 if (i2c_dev->host_notify_client) { 2063 /* Disable SMBus Host address */ 2064 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2065 STM32F7_I2C_CR1_SMBHEN); 2066 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client); 2067 } 2068 } 2069 2070 static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2071 { 2072 struct stm32f7_i2c_alert *alert; 2073 struct i2c_adapter *adap = &i2c_dev->adap; 2074 struct device *dev = i2c_dev->dev; 2075 void __iomem *base = i2c_dev->base; 2076 2077 alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL); 2078 if (!alert) 2079 return -ENOMEM; 2080 2081 alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup); 2082 if (IS_ERR(alert->ara)) 2083 return PTR_ERR(alert->ara); 2084 2085 i2c_dev->alert = alert; 2086 2087 /* Enable SMBus Alert */ 2088 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN); 2089 2090 return 0; 2091 } 2092 2093 static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev) 2094 { 2095 struct stm32f7_i2c_alert *alert = i2c_dev->alert; 2096 void __iomem *base = i2c_dev->base; 2097 2098 if (alert) { 2099 /* Disable SMBus Alert */ 2100 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, 2101 STM32F7_I2C_CR1_ALERTEN); 2102 i2c_unregister_device(alert->ara); 2103 } 2104 } 2105 2106 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 2107 { 2108 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 2109 2110 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 2111 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 2112 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 2113 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 2114 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 2115 I2C_FUNC_SMBUS_I2C_BLOCK; 2116 2117 if (i2c_dev->smbus_mode) 2118 func |= I2C_FUNC_SMBUS_HOST_NOTIFY; 2119 2120 return func; 2121 } 2122 2123 static const struct i2c_algorithm stm32f7_i2c_algo = { 2124 .master_xfer = stm32f7_i2c_xfer, 2125 .master_xfer_atomic = stm32f7_i2c_xfer_atomic, 2126 .smbus_xfer = stm32f7_i2c_smbus_xfer, 2127 .functionality = stm32f7_i2c_func, 2128 .reg_slave = stm32f7_i2c_reg_slave, 2129 .unreg_slave = stm32f7_i2c_unreg_slave, 2130 }; 2131 2132 static int stm32f7_i2c_probe(struct platform_device *pdev) 2133 { 2134 struct stm32f7_i2c_dev *i2c_dev; 2135 const struct stm32f7_i2c_setup *setup; 2136 struct resource *res; 2137 struct i2c_adapter *adap; 2138 struct reset_control *rst; 2139 dma_addr_t phy_addr; 2140 int irq_error, irq_event, ret; 2141 2142 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 2143 if (!i2c_dev) 2144 return -ENOMEM; 2145 2146 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2147 if (IS_ERR(i2c_dev->base)) 2148 return PTR_ERR(i2c_dev->base); 2149 phy_addr = (dma_addr_t)res->start; 2150 2151 irq_event = platform_get_irq(pdev, 0); 2152 if (irq_event < 0) 2153 return irq_event; 2154 2155 irq_error = platform_get_irq(pdev, 1); 2156 if (irq_error < 0) 2157 return irq_error; 2158 2159 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node, 2160 "wakeup-source"); 2161 2162 i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL); 2163 if (IS_ERR(i2c_dev->clk)) 2164 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk), 2165 "Failed to enable controller clock\n"); 2166 2167 rst = devm_reset_control_get(&pdev->dev, NULL); 2168 if (IS_ERR(rst)) 2169 return dev_err_probe(&pdev->dev, PTR_ERR(rst), 2170 "Error: Missing reset ctrl\n"); 2171 2172 reset_control_assert(rst); 2173 udelay(2); 2174 reset_control_deassert(rst); 2175 2176 i2c_dev->dev = &pdev->dev; 2177 2178 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 2179 stm32f7_i2c_isr_event, 2180 stm32f7_i2c_isr_event_thread, 2181 IRQF_ONESHOT, 2182 pdev->name, i2c_dev); 2183 if (ret) 2184 return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n"); 2185 2186 ret = devm_request_threaded_irq(&pdev->dev, irq_error, 2187 NULL, 2188 stm32f7_i2c_isr_error_thread, 2189 IRQF_ONESHOT, 2190 pdev->name, i2c_dev); 2191 if (ret) 2192 return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n"); 2193 2194 setup = of_device_get_match_data(&pdev->dev); 2195 if (!setup) { 2196 dev_err(&pdev->dev, "Can't get device data\n"); 2197 return -ENODEV; 2198 } 2199 i2c_dev->setup = *setup; 2200 2201 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 2202 if (ret) 2203 return ret; 2204 2205 /* Setup Fast mode plus if necessary */ 2206 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) { 2207 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 2208 if (ret) 2209 return ret; 2210 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2211 if (ret) 2212 return ret; 2213 } 2214 2215 adap = &i2c_dev->adap; 2216 i2c_set_adapdata(adap, i2c_dev); 2217 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 2218 &res->start); 2219 adap->owner = THIS_MODULE; 2220 adap->timeout = 2 * HZ; 2221 adap->retries = 3; 2222 adap->algo = &stm32f7_i2c_algo; 2223 adap->dev.parent = &pdev->dev; 2224 adap->dev.of_node = pdev->dev.of_node; 2225 2226 init_completion(&i2c_dev->complete); 2227 2228 /* Init DMA config if supported */ 2229 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 2230 STM32F7_I2C_TXDR, 2231 STM32F7_I2C_RXDR); 2232 if (IS_ERR(i2c_dev->dma)) { 2233 ret = PTR_ERR(i2c_dev->dma); 2234 /* DMA support is optional, only report other errors */ 2235 if (ret != -ENODEV) 2236 goto fmp_clear; 2237 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n"); 2238 i2c_dev->dma = NULL; 2239 } 2240 2241 if (i2c_dev->wakeup_src) { 2242 device_set_wakeup_capable(i2c_dev->dev, true); 2243 2244 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event); 2245 if (ret) { 2246 dev_err(i2c_dev->dev, "Failed to set wake up irq\n"); 2247 goto clr_wakeup_capable; 2248 } 2249 } 2250 2251 platform_set_drvdata(pdev, i2c_dev); 2252 2253 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 2254 STM32F7_AUTOSUSPEND_DELAY); 2255 pm_runtime_use_autosuspend(i2c_dev->dev); 2256 pm_runtime_set_active(i2c_dev->dev); 2257 pm_runtime_enable(i2c_dev->dev); 2258 2259 pm_runtime_get_noresume(&pdev->dev); 2260 2261 stm32f7_i2c_hw_config(i2c_dev); 2262 2263 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus"); 2264 2265 ret = i2c_add_adapter(adap); 2266 if (ret) 2267 goto pm_disable; 2268 2269 if (i2c_dev->smbus_mode) { 2270 ret = stm32f7_i2c_enable_smbus_host(i2c_dev); 2271 if (ret) { 2272 dev_err(i2c_dev->dev, 2273 "failed to enable SMBus Host-Notify protocol (%d)\n", 2274 ret); 2275 goto i2c_adapter_remove; 2276 } 2277 } 2278 2279 if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) { 2280 ret = stm32f7_i2c_enable_smbus_alert(i2c_dev); 2281 if (ret) { 2282 dev_err(i2c_dev->dev, 2283 "failed to enable SMBus alert protocol (%d)\n", 2284 ret); 2285 goto i2c_disable_smbus_host; 2286 } 2287 } 2288 2289 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 2290 2291 pm_runtime_mark_last_busy(i2c_dev->dev); 2292 pm_runtime_put_autosuspend(i2c_dev->dev); 2293 2294 return 0; 2295 2296 i2c_disable_smbus_host: 2297 stm32f7_i2c_disable_smbus_host(i2c_dev); 2298 2299 i2c_adapter_remove: 2300 i2c_del_adapter(adap); 2301 2302 pm_disable: 2303 pm_runtime_put_noidle(i2c_dev->dev); 2304 pm_runtime_disable(i2c_dev->dev); 2305 pm_runtime_set_suspended(i2c_dev->dev); 2306 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2307 2308 if (i2c_dev->wakeup_src) 2309 dev_pm_clear_wake_irq(i2c_dev->dev); 2310 2311 clr_wakeup_capable: 2312 if (i2c_dev->wakeup_src) 2313 device_set_wakeup_capable(i2c_dev->dev, false); 2314 2315 if (i2c_dev->dma) { 2316 stm32_i2c_dma_free(i2c_dev->dma); 2317 i2c_dev->dma = NULL; 2318 } 2319 2320 fmp_clear: 2321 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2322 2323 return ret; 2324 } 2325 2326 static void stm32f7_i2c_remove(struct platform_device *pdev) 2327 { 2328 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 2329 2330 stm32f7_i2c_disable_smbus_alert(i2c_dev); 2331 stm32f7_i2c_disable_smbus_host(i2c_dev); 2332 2333 i2c_del_adapter(&i2c_dev->adap); 2334 pm_runtime_get_sync(i2c_dev->dev); 2335 2336 if (i2c_dev->wakeup_src) { 2337 dev_pm_clear_wake_irq(i2c_dev->dev); 2338 /* 2339 * enforce that wakeup is disabled and that the device 2340 * is marked as non wakeup capable 2341 */ 2342 device_init_wakeup(i2c_dev->dev, false); 2343 } 2344 2345 pm_runtime_put_noidle(i2c_dev->dev); 2346 pm_runtime_disable(i2c_dev->dev); 2347 pm_runtime_set_suspended(i2c_dev->dev); 2348 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2349 2350 if (i2c_dev->dma) { 2351 stm32_i2c_dma_free(i2c_dev->dma); 2352 i2c_dev->dma = NULL; 2353 } 2354 2355 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2356 } 2357 2358 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev) 2359 { 2360 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2361 2362 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2363 clk_disable_unprepare(i2c_dev->clk); 2364 2365 return 0; 2366 } 2367 2368 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev) 2369 { 2370 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2371 int ret; 2372 2373 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2374 ret = clk_prepare_enable(i2c_dev->clk); 2375 if (ret) { 2376 dev_err(dev, "failed to prepare_enable clock\n"); 2377 return ret; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev) 2385 { 2386 int ret; 2387 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2388 2389 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2390 if (ret < 0) 2391 return ret; 2392 2393 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2394 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 2395 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 2396 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 2397 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR); 2398 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false); 2399 2400 pm_runtime_put_sync(i2c_dev->dev); 2401 2402 return ret; 2403 } 2404 2405 static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev) 2406 { 2407 u32 cr1; 2408 int ret; 2409 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs; 2410 2411 ret = pm_runtime_resume_and_get(i2c_dev->dev); 2412 if (ret < 0) 2413 return ret; 2414 2415 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1); 2416 if (cr1 & STM32F7_I2C_CR1_PE) 2417 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 2418 STM32F7_I2C_CR1_PE); 2419 2420 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR); 2421 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE, 2422 i2c_dev->base + STM32F7_I2C_CR1); 2423 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE) 2424 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 2425 STM32F7_I2C_CR1_PE); 2426 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2); 2427 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1); 2428 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2); 2429 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true); 2430 2431 pm_runtime_put_sync(i2c_dev->dev); 2432 2433 return ret; 2434 } 2435 2436 static int __maybe_unused stm32f7_i2c_suspend(struct device *dev) 2437 { 2438 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2439 int ret; 2440 2441 i2c_mark_adapter_suspended(&i2c_dev->adap); 2442 2443 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2444 ret = stm32f7_i2c_regs_backup(i2c_dev); 2445 if (ret < 0) { 2446 i2c_mark_adapter_resumed(&i2c_dev->adap); 2447 return ret; 2448 } 2449 2450 pinctrl_pm_select_sleep_state(dev); 2451 pm_runtime_force_suspend(dev); 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int __maybe_unused stm32f7_i2c_resume(struct device *dev) 2458 { 2459 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2460 int ret; 2461 2462 if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) { 2463 ret = pm_runtime_force_resume(dev); 2464 if (ret < 0) 2465 return ret; 2466 pinctrl_pm_select_default_state(dev); 2467 2468 ret = stm32f7_i2c_regs_restore(i2c_dev); 2469 if (ret < 0) 2470 return ret; 2471 } 2472 2473 i2c_mark_adapter_resumed(&i2c_dev->adap); 2474 2475 return 0; 2476 } 2477 2478 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2479 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2480 stm32f7_i2c_runtime_resume, NULL) 2481 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume) 2482 }; 2483 2484 static const struct of_device_id stm32f7_i2c_match[] = { 2485 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2486 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup}, 2487 { .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup}, 2488 {}, 2489 }; 2490 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2491 2492 static struct platform_driver stm32f7_i2c_driver = { 2493 .driver = { 2494 .name = "stm32f7-i2c", 2495 .of_match_table = stm32f7_i2c_match, 2496 .pm = &stm32f7_i2c_pm_ops, 2497 }, 2498 .probe = stm32f7_i2c_probe, 2499 .remove_new = stm32f7_i2c_remove, 2500 }; 2501 2502 module_platform_driver(stm32f7_i2c_driver); 2503 2504 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2505 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2506 MODULE_LICENSE("GPL v2"); 2507