1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * 5 * Author: Vitor Soares <vitor.soares@synopsys.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/completion.h> 11 #include <linux/err.h> 12 #include <linux/errno.h> 13 #include <linux/i3c/master.h> 14 #include <linux/interrupt.h> 15 #include <linux/ioport.h> 16 #include <linux/iopoll.h> 17 #include <linux/list.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include "dw-i3c-master.h" 25 26 #define DEVICE_CTRL 0x0 27 #define DEV_CTRL_ENABLE BIT(31) 28 #define DEV_CTRL_RESUME BIT(30) 29 #define DEV_CTRL_HOT_JOIN_NACK BIT(8) 30 #define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7) 31 32 #define DEVICE_ADDR 0x4 33 #define DEV_ADDR_DYNAMIC_ADDR_VALID BIT(31) 34 #define DEV_ADDR_DYNAMIC(x) (((x) << 16) & GENMASK(22, 16)) 35 36 #define HW_CAPABILITY 0x8 37 #define COMMAND_QUEUE_PORT 0xc 38 #define COMMAND_PORT_TOC BIT(30) 39 #define COMMAND_PORT_READ_TRANSFER BIT(28) 40 #define COMMAND_PORT_SDAP BIT(27) 41 #define COMMAND_PORT_ROC BIT(26) 42 #define COMMAND_PORT_SPEED(x) (((x) << 21) & GENMASK(23, 21)) 43 #define COMMAND_PORT_DEV_INDEX(x) (((x) << 16) & GENMASK(20, 16)) 44 #define COMMAND_PORT_CP BIT(15) 45 #define COMMAND_PORT_CMD(x) (((x) << 7) & GENMASK(14, 7)) 46 #define COMMAND_PORT_TID(x) (((x) << 3) & GENMASK(6, 3)) 47 48 #define COMMAND_PORT_ARG_DATA_LEN(x) (((x) << 16) & GENMASK(31, 16)) 49 #define COMMAND_PORT_ARG_DATA_LEN_MAX 65536 50 #define COMMAND_PORT_TRANSFER_ARG 0x01 51 52 #define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24)) 53 #define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16)) 54 #define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8)) 55 #define COMMAND_PORT_SDA_BYTE_STRB_3 BIT(5) 56 #define COMMAND_PORT_SDA_BYTE_STRB_2 BIT(4) 57 #define COMMAND_PORT_SDA_BYTE_STRB_1 BIT(3) 58 #define COMMAND_PORT_SHORT_DATA_ARG 0x02 59 60 #define COMMAND_PORT_DEV_COUNT(x) (((x) << 21) & GENMASK(25, 21)) 61 #define COMMAND_PORT_ADDR_ASSGN_CMD 0x03 62 63 #define RESPONSE_QUEUE_PORT 0x10 64 #define RESPONSE_PORT_ERR_STATUS(x) (((x) & GENMASK(31, 28)) >> 28) 65 #define RESPONSE_NO_ERROR 0 66 #define RESPONSE_ERROR_CRC 1 67 #define RESPONSE_ERROR_PARITY 2 68 #define RESPONSE_ERROR_FRAME 3 69 #define RESPONSE_ERROR_IBA_NACK 4 70 #define RESPONSE_ERROR_ADDRESS_NACK 5 71 #define RESPONSE_ERROR_OVER_UNDER_FLOW 6 72 #define RESPONSE_ERROR_TRANSF_ABORT 8 73 #define RESPONSE_ERROR_I2C_W_NACK_ERR 9 74 #define RESPONSE_PORT_TID(x) (((x) & GENMASK(27, 24)) >> 24) 75 #define RESPONSE_PORT_DATA_LEN(x) ((x) & GENMASK(15, 0)) 76 77 #define RX_TX_DATA_PORT 0x14 78 #define IBI_QUEUE_STATUS 0x18 79 #define QUEUE_THLD_CTRL 0x1c 80 #define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8) 81 #define QUEUE_THLD_CTRL_RESP_BUF(x) (((x) - 1) << 8) 82 83 #define DATA_BUFFER_THLD_CTRL 0x20 84 #define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8) 85 86 #define IBI_QUEUE_CTRL 0x24 87 #define IBI_MR_REQ_REJECT 0x2C 88 #define IBI_SIR_REQ_REJECT 0x30 89 #define IBI_REQ_REJECT_ALL GENMASK(31, 0) 90 91 #define RESET_CTRL 0x34 92 #define RESET_CTRL_IBI_QUEUE BIT(5) 93 #define RESET_CTRL_RX_FIFO BIT(4) 94 #define RESET_CTRL_TX_FIFO BIT(3) 95 #define RESET_CTRL_RESP_QUEUE BIT(2) 96 #define RESET_CTRL_CMD_QUEUE BIT(1) 97 #define RESET_CTRL_SOFT BIT(0) 98 99 #define SLV_EVENT_CTRL 0x38 100 #define INTR_STATUS 0x3c 101 #define INTR_STATUS_EN 0x40 102 #define INTR_SIGNAL_EN 0x44 103 #define INTR_FORCE 0x48 104 #define INTR_BUSOWNER_UPDATE_STAT BIT(13) 105 #define INTR_IBI_UPDATED_STAT BIT(12) 106 #define INTR_READ_REQ_RECV_STAT BIT(11) 107 #define INTR_DEFSLV_STAT BIT(10) 108 #define INTR_TRANSFER_ERR_STAT BIT(9) 109 #define INTR_DYN_ADDR_ASSGN_STAT BIT(8) 110 #define INTR_CCC_UPDATED_STAT BIT(6) 111 #define INTR_TRANSFER_ABORT_STAT BIT(5) 112 #define INTR_RESP_READY_STAT BIT(4) 113 #define INTR_CMD_QUEUE_READY_STAT BIT(3) 114 #define INTR_IBI_THLD_STAT BIT(2) 115 #define INTR_RX_THLD_STAT BIT(1) 116 #define INTR_TX_THLD_STAT BIT(0) 117 #define INTR_ALL (INTR_BUSOWNER_UPDATE_STAT | \ 118 INTR_IBI_UPDATED_STAT | \ 119 INTR_READ_REQ_RECV_STAT | \ 120 INTR_DEFSLV_STAT | \ 121 INTR_TRANSFER_ERR_STAT | \ 122 INTR_DYN_ADDR_ASSGN_STAT | \ 123 INTR_CCC_UPDATED_STAT | \ 124 INTR_TRANSFER_ABORT_STAT | \ 125 INTR_RESP_READY_STAT | \ 126 INTR_CMD_QUEUE_READY_STAT | \ 127 INTR_IBI_THLD_STAT | \ 128 INTR_TX_THLD_STAT | \ 129 INTR_RX_THLD_STAT) 130 131 #define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | \ 132 INTR_RESP_READY_STAT) 133 134 #define QUEUE_STATUS_LEVEL 0x4c 135 #define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24) 136 #define QUEUE_STATUS_IBI_BUF_BLR(x) (((x) & GENMASK(23, 16)) >> 16) 137 #define QUEUE_STATUS_LEVEL_RESP(x) (((x) & GENMASK(15, 8)) >> 8) 138 #define QUEUE_STATUS_LEVEL_CMD(x) ((x) & GENMASK(7, 0)) 139 140 #define DATA_BUFFER_STATUS_LEVEL 0x50 141 #define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0)) 142 143 #define PRESENT_STATE 0x54 144 #define CCC_DEVICE_STATUS 0x58 145 #define DEVICE_ADDR_TABLE_POINTER 0x5c 146 #define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16) 147 #define DEVICE_ADDR_TABLE_ADDR(x) ((x) & GENMASK(7, 0)) 148 149 #define DEV_CHAR_TABLE_POINTER 0x60 150 #define VENDOR_SPECIFIC_REG_POINTER 0x6c 151 #define SLV_PID_VALUE 0x74 152 #define SLV_CHAR_CTRL 0x78 153 #define SLV_MAX_LEN 0x7c 154 #define MAX_READ_TURNAROUND 0x80 155 #define MAX_DATA_SPEED 0x84 156 #define SLV_DEBUG_STATUS 0x88 157 #define SLV_INTR_REQ 0x8c 158 #define DEVICE_CTRL_EXTENDED 0xb0 159 #define SCL_I3C_OD_TIMING 0xb4 160 #define SCL_I3C_PP_TIMING 0xb8 161 #define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 162 #define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0)) 163 #define SCL_I3C_TIMING_CNT_MIN 5 164 165 #define SCL_I2C_FM_TIMING 0xbc 166 #define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16)) 167 #define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 168 169 #define SCL_I2C_FMP_TIMING 0xc0 170 #define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16)) 171 #define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0)) 172 173 #define SCL_EXT_LCNT_TIMING 0xc8 174 #define SCL_EXT_LCNT_4(x) (((x) << 24) & GENMASK(31, 24)) 175 #define SCL_EXT_LCNT_3(x) (((x) << 16) & GENMASK(23, 16)) 176 #define SCL_EXT_LCNT_2(x) (((x) << 8) & GENMASK(15, 8)) 177 #define SCL_EXT_LCNT_1(x) ((x) & GENMASK(7, 0)) 178 179 #define SCL_EXT_TERMN_LCNT_TIMING 0xcc 180 #define BUS_FREE_TIMING 0xd4 181 #define BUS_I3C_MST_FREE(x) ((x) & GENMASK(15, 0)) 182 183 #define BUS_IDLE_TIMING 0xd8 184 #define I3C_VER_ID 0xe0 185 #define I3C_VER_TYPE 0xe4 186 #define EXTENDED_CAPABILITY 0xe8 187 #define SLAVE_CONFIG 0xec 188 189 #define DEV_ADDR_TABLE_LEGACY_I2C_DEV BIT(31) 190 #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) (((x) << 16) & GENMASK(23, 16)) 191 #define DEV_ADDR_TABLE_STATIC_ADDR(x) ((x) & GENMASK(6, 0)) 192 #define DEV_ADDR_TABLE_LOC(start, idx) ((start) + ((idx) << 2)) 193 194 #define I3C_BUS_SDR1_SCL_RATE 8000000 195 #define I3C_BUS_SDR2_SCL_RATE 6000000 196 #define I3C_BUS_SDR3_SCL_RATE 4000000 197 #define I3C_BUS_SDR4_SCL_RATE 2000000 198 #define I3C_BUS_I2C_FM_TLOW_MIN_NS 1300 199 #define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500 200 #define I3C_BUS_THIGH_MAX_NS 41 201 202 #define XFER_TIMEOUT (msecs_to_jiffies(1000)) 203 204 struct dw_i3c_cmd { 205 u32 cmd_lo; 206 u32 cmd_hi; 207 u16 tx_len; 208 const void *tx_buf; 209 u16 rx_len; 210 void *rx_buf; 211 u8 error; 212 }; 213 214 struct dw_i3c_xfer { 215 struct list_head node; 216 struct completion comp; 217 int ret; 218 unsigned int ncmds; 219 struct dw_i3c_cmd cmds[]; 220 }; 221 222 struct dw_i3c_i2c_dev_data { 223 u8 index; 224 }; 225 226 static u8 even_parity(u8 p) 227 { 228 p ^= p >> 4; 229 p &= 0xf; 230 231 return (0x9669 >> p) & 1; 232 } 233 234 static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 235 const struct i3c_ccc_cmd *cmd) 236 { 237 if (cmd->ndests > 1) 238 return false; 239 240 switch (cmd->id) { 241 case I3C_CCC_ENEC(true): 242 case I3C_CCC_ENEC(false): 243 case I3C_CCC_DISEC(true): 244 case I3C_CCC_DISEC(false): 245 case I3C_CCC_ENTAS(0, true): 246 case I3C_CCC_ENTAS(0, false): 247 case I3C_CCC_RSTDAA(true): 248 case I3C_CCC_RSTDAA(false): 249 case I3C_CCC_ENTDAA: 250 case I3C_CCC_SETMWL(true): 251 case I3C_CCC_SETMWL(false): 252 case I3C_CCC_SETMRL(true): 253 case I3C_CCC_SETMRL(false): 254 case I3C_CCC_ENTHDR(0): 255 case I3C_CCC_SETDASA: 256 case I3C_CCC_SETNEWDA: 257 case I3C_CCC_GETMWL: 258 case I3C_CCC_GETMRL: 259 case I3C_CCC_GETPID: 260 case I3C_CCC_GETBCR: 261 case I3C_CCC_GETDCR: 262 case I3C_CCC_GETSTATUS: 263 case I3C_CCC_GETMXDS: 264 case I3C_CCC_GETHDRCAP: 265 return true; 266 default: 267 return false; 268 } 269 } 270 271 static inline struct dw_i3c_master * 272 to_dw_i3c_master(struct i3c_master_controller *master) 273 { 274 return container_of(master, struct dw_i3c_master, base); 275 } 276 277 static void dw_i3c_master_disable(struct dw_i3c_master *master) 278 { 279 writel(readl(master->regs + DEVICE_CTRL) & ~DEV_CTRL_ENABLE, 280 master->regs + DEVICE_CTRL); 281 } 282 283 static void dw_i3c_master_enable(struct dw_i3c_master *master) 284 { 285 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_ENABLE, 286 master->regs + DEVICE_CTRL); 287 } 288 289 static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) 290 { 291 int pos; 292 293 for (pos = 0; pos < master->maxdevs; pos++) { 294 if (addr == master->addrs[pos]) 295 return pos; 296 } 297 298 return -EINVAL; 299 } 300 301 static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) 302 { 303 if (!(master->free_pos & GENMASK(master->maxdevs - 1, 0))) 304 return -ENOSPC; 305 306 return ffs(master->free_pos) - 1; 307 } 308 309 static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, 310 const u8 *bytes, int nbytes) 311 { 312 writesl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4); 313 if (nbytes & 3) { 314 u32 tmp = 0; 315 316 memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3); 317 writesl(master->regs + RX_TX_DATA_PORT, &tmp, 1); 318 } 319 } 320 321 static void dw_i3c_master_read_fifo(struct dw_i3c_master *master, 322 int reg, u8 *bytes, int nbytes) 323 { 324 readsl(master->regs + reg, bytes, nbytes / 4); 325 if (nbytes & 3) { 326 u32 tmp; 327 328 readsl(master->regs + reg, &tmp, 1); 329 memcpy(bytes + (nbytes & ~3), &tmp, nbytes & 3); 330 } 331 } 332 333 static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, 334 u8 *bytes, int nbytes) 335 { 336 return dw_i3c_master_read_fifo(master, RX_TX_DATA_PORT, bytes, nbytes); 337 } 338 339 static struct dw_i3c_xfer * 340 dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) 341 { 342 struct dw_i3c_xfer *xfer; 343 344 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 345 if (!xfer) 346 return NULL; 347 348 INIT_LIST_HEAD(&xfer->node); 349 xfer->ncmds = ncmds; 350 xfer->ret = -ETIMEDOUT; 351 352 return xfer; 353 } 354 355 static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) 356 { 357 kfree(xfer); 358 } 359 360 static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) 361 { 362 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 363 unsigned int i; 364 u32 thld_ctrl; 365 366 if (!xfer) 367 return; 368 369 for (i = 0; i < xfer->ncmds; i++) { 370 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 371 372 dw_i3c_master_wr_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 373 } 374 375 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 376 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 377 thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds); 378 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 379 380 for (i = 0; i < xfer->ncmds; i++) { 381 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 382 383 writel(cmd->cmd_hi, master->regs + COMMAND_QUEUE_PORT); 384 writel(cmd->cmd_lo, master->regs + COMMAND_QUEUE_PORT); 385 } 386 } 387 388 static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, 389 struct dw_i3c_xfer *xfer) 390 { 391 unsigned long flags; 392 393 init_completion(&xfer->comp); 394 spin_lock_irqsave(&master->xferqueue.lock, flags); 395 if (master->xferqueue.cur) { 396 list_add_tail(&xfer->node, &master->xferqueue.list); 397 } else { 398 master->xferqueue.cur = xfer; 399 dw_i3c_master_start_xfer_locked(master); 400 } 401 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 402 } 403 404 static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, 405 struct dw_i3c_xfer *xfer) 406 { 407 if (master->xferqueue.cur == xfer) { 408 u32 status; 409 410 master->xferqueue.cur = NULL; 411 412 writel(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | 413 RESET_CTRL_RESP_QUEUE | RESET_CTRL_CMD_QUEUE, 414 master->regs + RESET_CTRL); 415 416 readl_poll_timeout_atomic(master->regs + RESET_CTRL, status, 417 !status, 10, 1000000); 418 } else { 419 list_del_init(&xfer->node); 420 } 421 } 422 423 static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, 424 struct dw_i3c_xfer *xfer) 425 { 426 unsigned long flags; 427 428 spin_lock_irqsave(&master->xferqueue.lock, flags); 429 dw_i3c_master_dequeue_xfer_locked(master, xfer); 430 spin_unlock_irqrestore(&master->xferqueue.lock, flags); 431 } 432 433 static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) 434 { 435 struct dw_i3c_xfer *xfer = master->xferqueue.cur; 436 int i, ret = 0; 437 u32 nresp; 438 439 if (!xfer) 440 return; 441 442 nresp = readl(master->regs + QUEUE_STATUS_LEVEL); 443 nresp = QUEUE_STATUS_LEVEL_RESP(nresp); 444 445 for (i = 0; i < nresp; i++) { 446 struct dw_i3c_cmd *cmd; 447 u32 resp; 448 449 resp = readl(master->regs + RESPONSE_QUEUE_PORT); 450 451 cmd = &xfer->cmds[RESPONSE_PORT_TID(resp)]; 452 cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp); 453 cmd->error = RESPONSE_PORT_ERR_STATUS(resp); 454 if (cmd->rx_len && !cmd->error) 455 dw_i3c_master_read_rx_fifo(master, cmd->rx_buf, 456 cmd->rx_len); 457 } 458 459 for (i = 0; i < nresp; i++) { 460 switch (xfer->cmds[i].error) { 461 case RESPONSE_NO_ERROR: 462 break; 463 case RESPONSE_ERROR_PARITY: 464 case RESPONSE_ERROR_IBA_NACK: 465 case RESPONSE_ERROR_TRANSF_ABORT: 466 case RESPONSE_ERROR_CRC: 467 case RESPONSE_ERROR_FRAME: 468 ret = -EIO; 469 break; 470 case RESPONSE_ERROR_OVER_UNDER_FLOW: 471 ret = -ENOSPC; 472 break; 473 case RESPONSE_ERROR_I2C_W_NACK_ERR: 474 case RESPONSE_ERROR_ADDRESS_NACK: 475 default: 476 ret = -EINVAL; 477 break; 478 } 479 } 480 481 xfer->ret = ret; 482 complete(&xfer->comp); 483 484 if (ret < 0) { 485 dw_i3c_master_dequeue_xfer_locked(master, xfer); 486 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_RESUME, 487 master->regs + DEVICE_CTRL); 488 } 489 490 xfer = list_first_entry_or_null(&master->xferqueue.list, 491 struct dw_i3c_xfer, 492 node); 493 if (xfer) 494 list_del_init(&xfer->node); 495 496 master->xferqueue.cur = xfer; 497 dw_i3c_master_start_xfer_locked(master); 498 } 499 500 static int dw_i3c_clk_cfg(struct dw_i3c_master *master) 501 { 502 unsigned long core_rate, core_period; 503 u32 scl_timing; 504 u8 hcnt, lcnt; 505 506 core_rate = clk_get_rate(master->core_clk); 507 if (!core_rate) 508 return -EINVAL; 509 510 core_period = DIV_ROUND_UP(1000000000, core_rate); 511 512 hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS, core_period) - 1; 513 if (hcnt < SCL_I3C_TIMING_CNT_MIN) 514 hcnt = SCL_I3C_TIMING_CNT_MIN; 515 516 lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt; 517 if (lcnt < SCL_I3C_TIMING_CNT_MIN) 518 lcnt = SCL_I3C_TIMING_CNT_MIN; 519 520 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 521 writel(scl_timing, master->regs + SCL_I3C_PP_TIMING); 522 523 /* 524 * In pure i3c mode, MST_FREE represents tCAS. In shared mode, this 525 * will be set up by dw_i2c_clk_cfg as tLOW. 526 */ 527 if (master->base.bus.mode == I3C_BUS_MODE_PURE) 528 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 529 530 lcnt = max_t(u8, 531 DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt); 532 scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt); 533 writel(scl_timing, master->regs + SCL_I3C_OD_TIMING); 534 535 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt; 536 scl_timing = SCL_EXT_LCNT_1(lcnt); 537 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt; 538 scl_timing |= SCL_EXT_LCNT_2(lcnt); 539 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt; 540 scl_timing |= SCL_EXT_LCNT_3(lcnt); 541 lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt; 542 scl_timing |= SCL_EXT_LCNT_4(lcnt); 543 writel(scl_timing, master->regs + SCL_EXT_LCNT_TIMING); 544 545 return 0; 546 } 547 548 static int dw_i2c_clk_cfg(struct dw_i3c_master *master) 549 { 550 unsigned long core_rate, core_period; 551 u16 hcnt, lcnt; 552 u32 scl_timing; 553 554 core_rate = clk_get_rate(master->core_clk); 555 if (!core_rate) 556 return -EINVAL; 557 558 core_period = DIV_ROUND_UP(1000000000, core_rate); 559 560 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS, core_period); 561 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt; 562 scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | 563 SCL_I2C_FMP_TIMING_LCNT(lcnt); 564 writel(scl_timing, master->regs + SCL_I2C_FMP_TIMING); 565 566 lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS, core_period); 567 hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt; 568 scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | 569 SCL_I2C_FM_TIMING_LCNT(lcnt); 570 writel(scl_timing, master->regs + SCL_I2C_FM_TIMING); 571 572 writel(BUS_I3C_MST_FREE(lcnt), master->regs + BUS_FREE_TIMING); 573 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT, 574 master->regs + DEVICE_CTRL); 575 576 return 0; 577 } 578 579 static int dw_i3c_master_bus_init(struct i3c_master_controller *m) 580 { 581 struct dw_i3c_master *master = to_dw_i3c_master(m); 582 struct i3c_bus *bus = i3c_master_get_bus(m); 583 struct i3c_device_info info = { }; 584 u32 thld_ctrl; 585 int ret; 586 587 ret = master->platform_ops->init(master); 588 if (ret) 589 return ret; 590 591 switch (bus->mode) { 592 case I3C_BUS_MODE_MIXED_FAST: 593 case I3C_BUS_MODE_MIXED_LIMITED: 594 ret = dw_i2c_clk_cfg(master); 595 if (ret) 596 return ret; 597 fallthrough; 598 case I3C_BUS_MODE_PURE: 599 ret = dw_i3c_clk_cfg(master); 600 if (ret) 601 return ret; 602 break; 603 default: 604 return -EINVAL; 605 } 606 607 thld_ctrl = readl(master->regs + QUEUE_THLD_CTRL); 608 thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK; 609 writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); 610 611 thld_ctrl = readl(master->regs + DATA_BUFFER_THLD_CTRL); 612 thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF; 613 writel(thld_ctrl, master->regs + DATA_BUFFER_THLD_CTRL); 614 615 writel(INTR_ALL, master->regs + INTR_STATUS); 616 writel(INTR_MASTER_MASK, master->regs + INTR_STATUS_EN); 617 writel(INTR_MASTER_MASK, master->regs + INTR_SIGNAL_EN); 618 619 ret = i3c_master_get_free_addr(m, 0); 620 if (ret < 0) 621 return ret; 622 623 writel(DEV_ADDR_DYNAMIC_ADDR_VALID | DEV_ADDR_DYNAMIC(ret), 624 master->regs + DEVICE_ADDR); 625 626 memset(&info, 0, sizeof(info)); 627 info.dyn_addr = ret; 628 629 ret = i3c_master_set_info(&master->base, &info); 630 if (ret) 631 return ret; 632 633 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_SIR_REQ_REJECT); 634 writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); 635 636 /* For now don't support Hot-Join */ 637 writel(readl(master->regs + DEVICE_CTRL) | DEV_CTRL_HOT_JOIN_NACK, 638 master->regs + DEVICE_CTRL); 639 640 dw_i3c_master_enable(master); 641 642 return 0; 643 } 644 645 static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) 646 { 647 struct dw_i3c_master *master = to_dw_i3c_master(m); 648 649 dw_i3c_master_disable(master); 650 } 651 652 static int dw_i3c_ccc_set(struct dw_i3c_master *master, 653 struct i3c_ccc_cmd *ccc) 654 { 655 struct dw_i3c_xfer *xfer; 656 struct dw_i3c_cmd *cmd; 657 int ret, pos = 0; 658 659 if (ccc->id & I3C_CCC_DIRECT) { 660 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 661 if (pos < 0) 662 return pos; 663 } 664 665 xfer = dw_i3c_master_alloc_xfer(master, 1); 666 if (!xfer) 667 return -ENOMEM; 668 669 cmd = xfer->cmds; 670 cmd->tx_buf = ccc->dests[0].payload.data; 671 cmd->tx_len = ccc->dests[0].payload.len; 672 673 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 674 COMMAND_PORT_TRANSFER_ARG; 675 676 cmd->cmd_lo = COMMAND_PORT_CP | 677 COMMAND_PORT_DEV_INDEX(pos) | 678 COMMAND_PORT_CMD(ccc->id) | 679 COMMAND_PORT_TOC | 680 COMMAND_PORT_ROC; 681 682 dw_i3c_master_enqueue_xfer(master, xfer); 683 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 684 dw_i3c_master_dequeue_xfer(master, xfer); 685 686 ret = xfer->ret; 687 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 688 ccc->err = I3C_ERROR_M2; 689 690 dw_i3c_master_free_xfer(xfer); 691 692 return ret; 693 } 694 695 static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) 696 { 697 struct dw_i3c_xfer *xfer; 698 struct dw_i3c_cmd *cmd; 699 int ret, pos; 700 701 pos = dw_i3c_master_get_addr_pos(master, ccc->dests[0].addr); 702 if (pos < 0) 703 return pos; 704 705 xfer = dw_i3c_master_alloc_xfer(master, 1); 706 if (!xfer) 707 return -ENOMEM; 708 709 cmd = xfer->cmds; 710 cmd->rx_buf = ccc->dests[0].payload.data; 711 cmd->rx_len = ccc->dests[0].payload.len; 712 713 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(ccc->dests[0].payload.len) | 714 COMMAND_PORT_TRANSFER_ARG; 715 716 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 717 COMMAND_PORT_CP | 718 COMMAND_PORT_DEV_INDEX(pos) | 719 COMMAND_PORT_CMD(ccc->id) | 720 COMMAND_PORT_TOC | 721 COMMAND_PORT_ROC; 722 723 dw_i3c_master_enqueue_xfer(master, xfer); 724 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 725 dw_i3c_master_dequeue_xfer(master, xfer); 726 727 ret = xfer->ret; 728 if (xfer->cmds[0].error == RESPONSE_ERROR_IBA_NACK) 729 ccc->err = I3C_ERROR_M2; 730 dw_i3c_master_free_xfer(xfer); 731 732 return ret; 733 } 734 735 static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 736 struct i3c_ccc_cmd *ccc) 737 { 738 struct dw_i3c_master *master = to_dw_i3c_master(m); 739 int ret = 0; 740 741 if (ccc->id == I3C_CCC_ENTDAA) 742 return -EINVAL; 743 744 if (ccc->rnw) 745 ret = dw_i3c_ccc_get(master, ccc); 746 else 747 ret = dw_i3c_ccc_set(master, ccc); 748 749 return ret; 750 } 751 752 static int dw_i3c_master_daa(struct i3c_master_controller *m) 753 { 754 struct dw_i3c_master *master = to_dw_i3c_master(m); 755 struct dw_i3c_xfer *xfer; 756 struct dw_i3c_cmd *cmd; 757 u32 olddevs, newdevs; 758 u8 p, last_addr = 0; 759 int ret, pos; 760 761 olddevs = ~(master->free_pos); 762 763 /* Prepare DAT before launching DAA. */ 764 for (pos = 0; pos < master->maxdevs; pos++) { 765 if (olddevs & BIT(pos)) 766 continue; 767 768 ret = i3c_master_get_free_addr(m, last_addr + 1); 769 if (ret < 0) 770 return -ENOSPC; 771 772 master->addrs[pos] = ret; 773 p = even_parity(ret); 774 last_addr = ret; 775 ret |= (p << 7); 776 777 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(ret), 778 master->regs + 779 DEV_ADDR_TABLE_LOC(master->datstartaddr, pos)); 780 } 781 782 xfer = dw_i3c_master_alloc_xfer(master, 1); 783 if (!xfer) 784 return -ENOMEM; 785 786 pos = dw_i3c_master_get_free_pos(master); 787 if (pos < 0) { 788 dw_i3c_master_free_xfer(xfer); 789 return pos; 790 } 791 cmd = &xfer->cmds[0]; 792 cmd->cmd_hi = 0x1; 793 cmd->cmd_lo = COMMAND_PORT_DEV_COUNT(master->maxdevs - pos) | 794 COMMAND_PORT_DEV_INDEX(pos) | 795 COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | 796 COMMAND_PORT_ADDR_ASSGN_CMD | 797 COMMAND_PORT_TOC | 798 COMMAND_PORT_ROC; 799 800 dw_i3c_master_enqueue_xfer(master, xfer); 801 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 802 dw_i3c_master_dequeue_xfer(master, xfer); 803 804 newdevs = GENMASK(master->maxdevs - cmd->rx_len - 1, 0); 805 newdevs &= ~olddevs; 806 807 for (pos = 0; pos < master->maxdevs; pos++) { 808 if (newdevs & BIT(pos)) 809 i3c_master_add_i3c_dev_locked(m, master->addrs[pos]); 810 } 811 812 dw_i3c_master_free_xfer(xfer); 813 814 return 0; 815 } 816 817 static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, 818 struct i3c_priv_xfer *i3c_xfers, 819 int i3c_nxfers) 820 { 821 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 822 struct i3c_master_controller *m = i3c_dev_get_master(dev); 823 struct dw_i3c_master *master = to_dw_i3c_master(m); 824 unsigned int nrxwords = 0, ntxwords = 0; 825 struct dw_i3c_xfer *xfer; 826 int i, ret = 0; 827 828 if (!i3c_nxfers) 829 return 0; 830 831 if (i3c_nxfers > master->caps.cmdfifodepth) 832 return -ENOTSUPP; 833 834 for (i = 0; i < i3c_nxfers; i++) { 835 if (i3c_xfers[i].rnw) 836 nrxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 837 else 838 ntxwords += DIV_ROUND_UP(i3c_xfers[i].len, 4); 839 } 840 841 if (ntxwords > master->caps.datafifodepth || 842 nrxwords > master->caps.datafifodepth) 843 return -ENOTSUPP; 844 845 xfer = dw_i3c_master_alloc_xfer(master, i3c_nxfers); 846 if (!xfer) 847 return -ENOMEM; 848 849 for (i = 0; i < i3c_nxfers; i++) { 850 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 851 852 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i3c_xfers[i].len) | 853 COMMAND_PORT_TRANSFER_ARG; 854 855 if (i3c_xfers[i].rnw) { 856 cmd->rx_buf = i3c_xfers[i].data.in; 857 cmd->rx_len = i3c_xfers[i].len; 858 cmd->cmd_lo = COMMAND_PORT_READ_TRANSFER | 859 COMMAND_PORT_SPEED(dev->info.max_read_ds); 860 861 } else { 862 cmd->tx_buf = i3c_xfers[i].data.out; 863 cmd->tx_len = i3c_xfers[i].len; 864 cmd->cmd_lo = 865 COMMAND_PORT_SPEED(dev->info.max_write_ds); 866 } 867 868 cmd->cmd_lo |= COMMAND_PORT_TID(i) | 869 COMMAND_PORT_DEV_INDEX(data->index) | 870 COMMAND_PORT_ROC; 871 872 if (i == (i3c_nxfers - 1)) 873 cmd->cmd_lo |= COMMAND_PORT_TOC; 874 } 875 876 dw_i3c_master_enqueue_xfer(master, xfer); 877 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 878 dw_i3c_master_dequeue_xfer(master, xfer); 879 880 for (i = 0; i < i3c_nxfers; i++) { 881 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 882 883 if (i3c_xfers[i].rnw) 884 i3c_xfers[i].len = cmd->rx_len; 885 } 886 887 ret = xfer->ret; 888 dw_i3c_master_free_xfer(xfer); 889 890 return ret; 891 } 892 893 static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, 894 u8 old_dyn_addr) 895 { 896 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 897 struct i3c_master_controller *m = i3c_dev_get_master(dev); 898 struct dw_i3c_master *master = to_dw_i3c_master(m); 899 int pos; 900 901 pos = dw_i3c_master_get_free_pos(master); 902 903 if (data->index > pos && pos > 0) { 904 writel(0, 905 master->regs + 906 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 907 908 master->addrs[data->index] = 0; 909 master->free_pos |= BIT(data->index); 910 911 data->index = pos; 912 master->addrs[pos] = dev->info.dyn_addr; 913 master->free_pos &= ~BIT(pos); 914 } 915 916 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(dev->info.dyn_addr), 917 master->regs + 918 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 919 920 master->addrs[data->index] = dev->info.dyn_addr; 921 922 return 0; 923 } 924 925 static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 926 { 927 struct i3c_master_controller *m = i3c_dev_get_master(dev); 928 struct dw_i3c_master *master = to_dw_i3c_master(m); 929 struct dw_i3c_i2c_dev_data *data; 930 int pos; 931 932 pos = dw_i3c_master_get_free_pos(master); 933 if (pos < 0) 934 return pos; 935 936 data = kzalloc(sizeof(*data), GFP_KERNEL); 937 if (!data) 938 return -ENOMEM; 939 940 data->index = pos; 941 master->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr; 942 master->free_pos &= ~BIT(pos); 943 i3c_dev_set_master_data(dev, data); 944 945 writel(DEV_ADDR_TABLE_DYNAMIC_ADDR(master->addrs[pos]), 946 master->regs + 947 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 948 949 return 0; 950 } 951 952 static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 953 { 954 struct dw_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 955 struct i3c_master_controller *m = i3c_dev_get_master(dev); 956 struct dw_i3c_master *master = to_dw_i3c_master(m); 957 958 writel(0, 959 master->regs + 960 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 961 962 i3c_dev_set_master_data(dev, NULL); 963 master->addrs[data->index] = 0; 964 master->free_pos |= BIT(data->index); 965 kfree(data); 966 } 967 968 static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 969 const struct i2c_msg *i2c_xfers, 970 int i2c_nxfers) 971 { 972 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 973 struct i3c_master_controller *m = i2c_dev_get_master(dev); 974 struct dw_i3c_master *master = to_dw_i3c_master(m); 975 unsigned int nrxwords = 0, ntxwords = 0; 976 struct dw_i3c_xfer *xfer; 977 int i, ret = 0; 978 979 if (!i2c_nxfers) 980 return 0; 981 982 if (i2c_nxfers > master->caps.cmdfifodepth) 983 return -ENOTSUPP; 984 985 for (i = 0; i < i2c_nxfers; i++) { 986 if (i2c_xfers[i].flags & I2C_M_RD) 987 nrxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 988 else 989 ntxwords += DIV_ROUND_UP(i2c_xfers[i].len, 4); 990 } 991 992 if (ntxwords > master->caps.datafifodepth || 993 nrxwords > master->caps.datafifodepth) 994 return -ENOTSUPP; 995 996 xfer = dw_i3c_master_alloc_xfer(master, i2c_nxfers); 997 if (!xfer) 998 return -ENOMEM; 999 1000 for (i = 0; i < i2c_nxfers; i++) { 1001 struct dw_i3c_cmd *cmd = &xfer->cmds[i]; 1002 1003 cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(i2c_xfers[i].len) | 1004 COMMAND_PORT_TRANSFER_ARG; 1005 1006 cmd->cmd_lo = COMMAND_PORT_TID(i) | 1007 COMMAND_PORT_DEV_INDEX(data->index) | 1008 COMMAND_PORT_ROC; 1009 1010 if (i2c_xfers[i].flags & I2C_M_RD) { 1011 cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER; 1012 cmd->rx_buf = i2c_xfers[i].buf; 1013 cmd->rx_len = i2c_xfers[i].len; 1014 } else { 1015 cmd->tx_buf = i2c_xfers[i].buf; 1016 cmd->tx_len = i2c_xfers[i].len; 1017 } 1018 1019 if (i == (i2c_nxfers - 1)) 1020 cmd->cmd_lo |= COMMAND_PORT_TOC; 1021 } 1022 1023 dw_i3c_master_enqueue_xfer(master, xfer); 1024 if (!wait_for_completion_timeout(&xfer->comp, XFER_TIMEOUT)) 1025 dw_i3c_master_dequeue_xfer(master, xfer); 1026 1027 ret = xfer->ret; 1028 dw_i3c_master_free_xfer(xfer); 1029 1030 return ret; 1031 } 1032 1033 static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 1034 { 1035 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1036 struct dw_i3c_master *master = to_dw_i3c_master(m); 1037 struct dw_i3c_i2c_dev_data *data; 1038 int pos; 1039 1040 pos = dw_i3c_master_get_free_pos(master); 1041 if (pos < 0) 1042 return pos; 1043 1044 data = kzalloc(sizeof(*data), GFP_KERNEL); 1045 if (!data) 1046 return -ENOMEM; 1047 1048 data->index = pos; 1049 master->addrs[pos] = dev->addr; 1050 master->free_pos &= ~BIT(pos); 1051 i2c_dev_set_master_data(dev, data); 1052 1053 writel(DEV_ADDR_TABLE_LEGACY_I2C_DEV | 1054 DEV_ADDR_TABLE_STATIC_ADDR(dev->addr), 1055 master->regs + 1056 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1057 1058 return 0; 1059 } 1060 1061 static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 1062 { 1063 struct dw_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 1064 struct i3c_master_controller *m = i2c_dev_get_master(dev); 1065 struct dw_i3c_master *master = to_dw_i3c_master(m); 1066 1067 writel(0, 1068 master->regs + 1069 DEV_ADDR_TABLE_LOC(master->datstartaddr, data->index)); 1070 1071 i2c_dev_set_master_data(dev, NULL); 1072 master->addrs[data->index] = 0; 1073 master->free_pos |= BIT(data->index); 1074 kfree(data); 1075 } 1076 1077 static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id) 1078 { 1079 struct dw_i3c_master *master = dev_id; 1080 u32 status; 1081 1082 status = readl(master->regs + INTR_STATUS); 1083 1084 if (!(status & readl(master->regs + INTR_STATUS_EN))) { 1085 writel(INTR_ALL, master->regs + INTR_STATUS); 1086 return IRQ_NONE; 1087 } 1088 1089 spin_lock(&master->xferqueue.lock); 1090 dw_i3c_master_end_xfer_locked(master, status); 1091 if (status & INTR_TRANSFER_ERR_STAT) 1092 writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS); 1093 spin_unlock(&master->xferqueue.lock); 1094 1095 return IRQ_HANDLED; 1096 } 1097 1098 static const struct i3c_master_controller_ops dw_mipi_i3c_ops = { 1099 .bus_init = dw_i3c_master_bus_init, 1100 .bus_cleanup = dw_i3c_master_bus_cleanup, 1101 .attach_i3c_dev = dw_i3c_master_attach_i3c_dev, 1102 .reattach_i3c_dev = dw_i3c_master_reattach_i3c_dev, 1103 .detach_i3c_dev = dw_i3c_master_detach_i3c_dev, 1104 .do_daa = dw_i3c_master_daa, 1105 .supports_ccc_cmd = dw_i3c_master_supports_ccc_cmd, 1106 .send_ccc_cmd = dw_i3c_master_send_ccc_cmd, 1107 .priv_xfers = dw_i3c_master_priv_xfers, 1108 .attach_i2c_dev = dw_i3c_master_attach_i2c_dev, 1109 .detach_i2c_dev = dw_i3c_master_detach_i2c_dev, 1110 .i2c_xfers = dw_i3c_master_i2c_xfers, 1111 }; 1112 1113 /* default platform ops implementations */ 1114 static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c) 1115 { 1116 return 0; 1117 } 1118 1119 static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = { 1120 .init = dw_i3c_platform_init_nop, 1121 }; 1122 1123 int dw_i3c_common_probe(struct dw_i3c_master *master, 1124 struct platform_device *pdev) 1125 { 1126 int ret, irq; 1127 1128 if (!master->platform_ops) 1129 master->platform_ops = &dw_i3c_platform_ops_default; 1130 1131 master->regs = devm_platform_ioremap_resource(pdev, 0); 1132 if (IS_ERR(master->regs)) 1133 return PTR_ERR(master->regs); 1134 1135 master->core_clk = devm_clk_get(&pdev->dev, NULL); 1136 if (IS_ERR(master->core_clk)) 1137 return PTR_ERR(master->core_clk); 1138 1139 master->core_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, 1140 "core_rst"); 1141 if (IS_ERR(master->core_rst)) 1142 return PTR_ERR(master->core_rst); 1143 1144 ret = clk_prepare_enable(master->core_clk); 1145 if (ret) 1146 goto err_disable_core_clk; 1147 1148 reset_control_deassert(master->core_rst); 1149 1150 spin_lock_init(&master->xferqueue.lock); 1151 INIT_LIST_HEAD(&master->xferqueue.list); 1152 1153 writel(INTR_ALL, master->regs + INTR_STATUS); 1154 irq = platform_get_irq(pdev, 0); 1155 ret = devm_request_irq(&pdev->dev, irq, 1156 dw_i3c_master_irq_handler, 0, 1157 dev_name(&pdev->dev), master); 1158 if (ret) 1159 goto err_assert_rst; 1160 1161 platform_set_drvdata(pdev, master); 1162 1163 /* Information regarding the FIFOs/QUEUEs depth */ 1164 ret = readl(master->regs + QUEUE_STATUS_LEVEL); 1165 master->caps.cmdfifodepth = QUEUE_STATUS_LEVEL_CMD(ret); 1166 1167 ret = readl(master->regs + DATA_BUFFER_STATUS_LEVEL); 1168 master->caps.datafifodepth = DATA_BUFFER_STATUS_LEVEL_TX(ret); 1169 1170 ret = readl(master->regs + DEVICE_ADDR_TABLE_POINTER); 1171 master->datstartaddr = ret; 1172 master->maxdevs = ret >> 16; 1173 master->free_pos = GENMASK(master->maxdevs - 1, 0); 1174 1175 ret = i3c_master_register(&master->base, &pdev->dev, 1176 &dw_mipi_i3c_ops, false); 1177 if (ret) 1178 goto err_assert_rst; 1179 1180 return 0; 1181 1182 err_assert_rst: 1183 reset_control_assert(master->core_rst); 1184 1185 err_disable_core_clk: 1186 clk_disable_unprepare(master->core_clk); 1187 1188 return ret; 1189 } 1190 EXPORT_SYMBOL_GPL(dw_i3c_common_probe); 1191 1192 void dw_i3c_common_remove(struct dw_i3c_master *master) 1193 { 1194 i3c_master_unregister(&master->base); 1195 1196 reset_control_assert(master->core_rst); 1197 1198 clk_disable_unprepare(master->core_clk); 1199 } 1200 EXPORT_SYMBOL_GPL(dw_i3c_common_remove); 1201 1202 /* base platform implementation */ 1203 1204 static int dw_i3c_probe(struct platform_device *pdev) 1205 { 1206 struct dw_i3c_master *master; 1207 1208 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1209 if (!master) 1210 return -ENOMEM; 1211 1212 return dw_i3c_common_probe(master, pdev); 1213 } 1214 1215 static void dw_i3c_remove(struct platform_device *pdev) 1216 { 1217 struct dw_i3c_master *master = platform_get_drvdata(pdev); 1218 1219 dw_i3c_common_remove(master); 1220 } 1221 1222 static const struct of_device_id dw_i3c_master_of_match[] = { 1223 { .compatible = "snps,dw-i3c-master-1.00a", }, 1224 {}, 1225 }; 1226 MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); 1227 1228 static struct platform_driver dw_i3c_driver = { 1229 .probe = dw_i3c_probe, 1230 .remove_new = dw_i3c_remove, 1231 .driver = { 1232 .name = "dw-i3c-master", 1233 .of_match_table = dw_i3c_master_of_match, 1234 }, 1235 }; 1236 module_platform_driver(dw_i3c_driver); 1237 1238 MODULE_AUTHOR("Vitor Soares <vitor.soares@synopsys.com>"); 1239 MODULE_DESCRIPTION("DesignWare MIPI I3C driver"); 1240 MODULE_LICENSE("GPL v2"); 1241