1*3e0a4e85SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
27a0786c1SMauro Carvalho Chehab /*
37a0786c1SMauro Carvalho Chehab  * gp8psk_fe driver
47a0786c1SMauro Carvalho Chehab  */
57a0786c1SMauro Carvalho Chehab 
67a0786c1SMauro Carvalho Chehab #ifndef GP8PSK_FE_H
77a0786c1SMauro Carvalho Chehab #define GP8PSK_FE_H
87a0786c1SMauro Carvalho Chehab 
97a0786c1SMauro Carvalho Chehab #include <linux/types.h>
107a0786c1SMauro Carvalho Chehab 
117a0786c1SMauro Carvalho Chehab /* gp8psk commands */
127a0786c1SMauro Carvalho Chehab 
137a0786c1SMauro Carvalho Chehab #define GET_8PSK_CONFIG                 0x80    /* in */
147a0786c1SMauro Carvalho Chehab #define SET_8PSK_CONFIG                 0x81
157a0786c1SMauro Carvalho Chehab #define I2C_WRITE			0x83
167a0786c1SMauro Carvalho Chehab #define I2C_READ			0x84
177a0786c1SMauro Carvalho Chehab #define ARM_TRANSFER                    0x85
187a0786c1SMauro Carvalho Chehab #define TUNE_8PSK                       0x86
197a0786c1SMauro Carvalho Chehab #define GET_SIGNAL_STRENGTH             0x87    /* in */
207a0786c1SMauro Carvalho Chehab #define LOAD_BCM4500                    0x88
217a0786c1SMauro Carvalho Chehab #define BOOT_8PSK                       0x89    /* in */
227a0786c1SMauro Carvalho Chehab #define START_INTERSIL                  0x8A    /* in */
237a0786c1SMauro Carvalho Chehab #define SET_LNB_VOLTAGE                 0x8B
247a0786c1SMauro Carvalho Chehab #define SET_22KHZ_TONE                  0x8C
257a0786c1SMauro Carvalho Chehab #define SEND_DISEQC_COMMAND             0x8D
267a0786c1SMauro Carvalho Chehab #define SET_DVB_MODE                    0x8E
277a0786c1SMauro Carvalho Chehab #define SET_DN_SWITCH                   0x8F
287a0786c1SMauro Carvalho Chehab #define GET_SIGNAL_LOCK                 0x90    /* in */
297a0786c1SMauro Carvalho Chehab #define GET_FW_VERS			0x92
307a0786c1SMauro Carvalho Chehab #define GET_SERIAL_NUMBER               0x93    /* in */
317a0786c1SMauro Carvalho Chehab #define USE_EXTRA_VOLT                  0x94
327a0786c1SMauro Carvalho Chehab #define GET_FPGA_VERS			0x95
337a0786c1SMauro Carvalho Chehab #define CW3K_INIT			0x9d
347a0786c1SMauro Carvalho Chehab 
357a0786c1SMauro Carvalho Chehab /* PSK_configuration bits */
367a0786c1SMauro Carvalho Chehab #define bm8pskStarted                   0x01
377a0786c1SMauro Carvalho Chehab #define bm8pskFW_Loaded                 0x02
387a0786c1SMauro Carvalho Chehab #define bmIntersilOn                    0x04
397a0786c1SMauro Carvalho Chehab #define bmDVBmode                       0x08
407a0786c1SMauro Carvalho Chehab #define bm22kHz                         0x10
417a0786c1SMauro Carvalho Chehab #define bmSEL18V                        0x20
427a0786c1SMauro Carvalho Chehab #define bmDCtuned                       0x40
437a0786c1SMauro Carvalho Chehab #define bmArmed                         0x80
447a0786c1SMauro Carvalho Chehab 
457a0786c1SMauro Carvalho Chehab /* Satellite modulation modes */
467a0786c1SMauro Carvalho Chehab #define ADV_MOD_DVB_QPSK 0     /* DVB-S QPSK */
477a0786c1SMauro Carvalho Chehab #define ADV_MOD_TURBO_QPSK 1   /* Turbo QPSK */
487a0786c1SMauro Carvalho Chehab #define ADV_MOD_TURBO_8PSK 2   /* Turbo 8PSK (also used for Trellis 8PSK) */
497a0786c1SMauro Carvalho Chehab #define ADV_MOD_TURBO_16QAM 3  /* Turbo 16QAM (also used for Trellis 8PSK) */
507a0786c1SMauro Carvalho Chehab 
517a0786c1SMauro Carvalho Chehab #define ADV_MOD_DCII_C_QPSK 4  /* Digicipher II Combo */
527a0786c1SMauro Carvalho Chehab #define ADV_MOD_DCII_I_QPSK 5  /* Digicipher II I-stream */
537a0786c1SMauro Carvalho Chehab #define ADV_MOD_DCII_Q_QPSK 6  /* Digicipher II Q-stream */
547a0786c1SMauro Carvalho Chehab #define ADV_MOD_DCII_C_OQPSK 7 /* Digicipher II offset QPSK */
557a0786c1SMauro Carvalho Chehab #define ADV_MOD_DSS_QPSK 8     /* DSS (DIRECTV) QPSK */
567a0786c1SMauro Carvalho Chehab #define ADV_MOD_DVB_BPSK 9     /* DVB-S BPSK */
577a0786c1SMauro Carvalho Chehab 
587a0786c1SMauro Carvalho Chehab /* firmware revision id's */
597a0786c1SMauro Carvalho Chehab #define GP8PSK_FW_REV1			0x020604
607a0786c1SMauro Carvalho Chehab #define GP8PSK_FW_REV2			0x020704
617a0786c1SMauro Carvalho Chehab #define GP8PSK_FW_VERS(_fw_vers) \
627a0786c1SMauro Carvalho Chehab 	((_fw_vers)[2]<<0x10 | (_fw_vers)[1]<<0x08 | (_fw_vers)[0])
637a0786c1SMauro Carvalho Chehab 
647a0786c1SMauro Carvalho Chehab struct gp8psk_fe_ops {
657a0786c1SMauro Carvalho Chehab 	int (*in)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
667a0786c1SMauro Carvalho Chehab 	int (*out)(void *priv, u8 req, u16 value, u16 index, u8 *b, int blen);
677a0786c1SMauro Carvalho Chehab 	int (*reload)(void *priv);
687a0786c1SMauro Carvalho Chehab };
697a0786c1SMauro Carvalho Chehab 
707a0786c1SMauro Carvalho Chehab struct dvb_frontend *gp8psk_fe_attach(const struct gp8psk_fe_ops *ops,
717a0786c1SMauro Carvalho Chehab 				      void *priv, bool is_rev1);
727a0786c1SMauro Carvalho Chehab 
737a0786c1SMauro Carvalho Chehab #endif
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