19c92ab61SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2f7e7b48eSJacob Chen /* 3f7e7b48eSJacob Chen * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4f7e7b48eSJacob Chen * Author: Jacob Chen <jacob-chen@iotwrt.com> 5f7e7b48eSJacob Chen */ 6f7e7b48eSJacob Chen #ifndef __RGA_HW_H__ 7f7e7b48eSJacob Chen #define __RGA_HW_H__ 8f7e7b48eSJacob Chen 9f7e7b48eSJacob Chen #define RGA_CMDBUF_SIZE 0x20 10f7e7b48eSJacob Chen 11f7e7b48eSJacob Chen /* Hardware limits */ 12f7e7b48eSJacob Chen #define MAX_WIDTH 8192 13f7e7b48eSJacob Chen #define MAX_HEIGHT 8192 14f7e7b48eSJacob Chen 15f7e7b48eSJacob Chen #define MIN_WIDTH 34 16f7e7b48eSJacob Chen #define MIN_HEIGHT 34 17f7e7b48eSJacob Chen 18f7e7b48eSJacob Chen #define DEFAULT_WIDTH 100 19f7e7b48eSJacob Chen #define DEFAULT_HEIGHT 100 20f7e7b48eSJacob Chen 21f7e7b48eSJacob Chen #define RGA_TIMEOUT 500 22f7e7b48eSJacob Chen 23f7e7b48eSJacob Chen /* Registers address */ 24f7e7b48eSJacob Chen #define RGA_SYS_CTRL 0x0000 25f7e7b48eSJacob Chen #define RGA_CMD_CTRL 0x0004 26f7e7b48eSJacob Chen #define RGA_CMD_BASE 0x0008 27f7e7b48eSJacob Chen #define RGA_INT 0x0010 28f7e7b48eSJacob Chen #define RGA_MMU_CTRL0 0x0014 29f7e7b48eSJacob Chen #define RGA_VERSION_INFO 0x0028 30f7e7b48eSJacob Chen 31f7e7b48eSJacob Chen #define RGA_MODE_BASE_REG 0x0100 32f7e7b48eSJacob Chen #define RGA_MODE_MAX_REG 0x017C 33f7e7b48eSJacob Chen 34f7e7b48eSJacob Chen #define RGA_MODE_CTRL 0x0100 35f7e7b48eSJacob Chen #define RGA_SRC_INFO 0x0104 36f7e7b48eSJacob Chen #define RGA_SRC_Y_RGB_BASE_ADDR 0x0108 37f7e7b48eSJacob Chen #define RGA_SRC_CB_BASE_ADDR 0x010c 38f7e7b48eSJacob Chen #define RGA_SRC_CR_BASE_ADDR 0x0110 39f7e7b48eSJacob Chen #define RGA_SRC1_RGB_BASE_ADDR 0x0114 40f7e7b48eSJacob Chen #define RGA_SRC_VIR_INFO 0x0118 41f7e7b48eSJacob Chen #define RGA_SRC_ACT_INFO 0x011c 42f7e7b48eSJacob Chen #define RGA_SRC_X_FACTOR 0x0120 43f7e7b48eSJacob Chen #define RGA_SRC_Y_FACTOR 0x0124 44f7e7b48eSJacob Chen #define RGA_SRC_BG_COLOR 0x0128 45f7e7b48eSJacob Chen #define RGA_SRC_FG_COLOR 0x012c 46f7e7b48eSJacob Chen #define RGA_SRC_TR_COLOR0 0x0130 47f7e7b48eSJacob Chen #define RGA_SRC_TR_COLOR1 0x0134 48f7e7b48eSJacob Chen 49f7e7b48eSJacob Chen #define RGA_DST_INFO 0x0138 50f7e7b48eSJacob Chen #define RGA_DST_Y_RGB_BASE_ADDR 0x013c 51f7e7b48eSJacob Chen #define RGA_DST_CB_BASE_ADDR 0x0140 52f7e7b48eSJacob Chen #define RGA_DST_CR_BASE_ADDR 0x0144 53f7e7b48eSJacob Chen #define RGA_DST_VIR_INFO 0x0148 54f7e7b48eSJacob Chen #define RGA_DST_ACT_INFO 0x014c 55f7e7b48eSJacob Chen 56f7e7b48eSJacob Chen #define RGA_ALPHA_CTRL0 0x0150 57f7e7b48eSJacob Chen #define RGA_ALPHA_CTRL1 0x0154 58f7e7b48eSJacob Chen #define RGA_FADING_CTRL 0x0158 59f7e7b48eSJacob Chen #define RGA_PAT_CON 0x015c 60f7e7b48eSJacob Chen #define RGA_ROP_CON0 0x0160 61f7e7b48eSJacob Chen #define RGA_ROP_CON1 0x0164 62f7e7b48eSJacob Chen #define RGA_MASK_BASE 0x0168 63f7e7b48eSJacob Chen 64f7e7b48eSJacob Chen #define RGA_MMU_CTRL1 0x016C 65f7e7b48eSJacob Chen #define RGA_MMU_SRC_BASE 0x0170 66f7e7b48eSJacob Chen #define RGA_MMU_SRC1_BASE 0x0174 67f7e7b48eSJacob Chen #define RGA_MMU_DST_BASE 0x0178 68f7e7b48eSJacob Chen 69f7e7b48eSJacob Chen /* Registers value */ 70f7e7b48eSJacob Chen #define RGA_MODE_RENDER_BITBLT 0 71f7e7b48eSJacob Chen #define RGA_MODE_RENDER_COLOR_PALETTE 1 72f7e7b48eSJacob Chen #define RGA_MODE_RENDER_RECTANGLE_FILL 2 73f7e7b48eSJacob Chen #define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3 74f7e7b48eSJacob Chen 75f7e7b48eSJacob Chen #define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0 76f7e7b48eSJacob Chen #define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1 77f7e7b48eSJacob Chen 78f7e7b48eSJacob Chen #define RGA_MODE_CF_ROP4_SOLID 0 79f7e7b48eSJacob Chen #define RGA_MODE_CF_ROP4_PATTERN 1 80f7e7b48eSJacob Chen 81f7e7b48eSJacob Chen #define RGA_COLOR_FMT_ABGR8888 0 82f7e7b48eSJacob Chen #define RGA_COLOR_FMT_XBGR8888 1 83f7e7b48eSJacob Chen #define RGA_COLOR_FMT_RGB888 2 84f7e7b48eSJacob Chen #define RGA_COLOR_FMT_BGR565 4 85f7e7b48eSJacob Chen #define RGA_COLOR_FMT_ABGR1555 5 86f7e7b48eSJacob Chen #define RGA_COLOR_FMT_ABGR4444 6 87f7e7b48eSJacob Chen #define RGA_COLOR_FMT_YUV422SP 8 88f7e7b48eSJacob Chen #define RGA_COLOR_FMT_YUV422P 9 89f7e7b48eSJacob Chen #define RGA_COLOR_FMT_YUV420SP 10 90f7e7b48eSJacob Chen #define RGA_COLOR_FMT_YUV420P 11 91f7e7b48eSJacob Chen /* SRC_COLOR Palette */ 92f7e7b48eSJacob Chen #define RGA_COLOR_FMT_CP_1BPP 12 93f7e7b48eSJacob Chen #define RGA_COLOR_FMT_CP_2BPP 13 94f7e7b48eSJacob Chen #define RGA_COLOR_FMT_CP_4BPP 14 95f7e7b48eSJacob Chen #define RGA_COLOR_FMT_CP_8BPP 15 96f7e7b48eSJacob Chen #define RGA_COLOR_FMT_MASK 15 97f7e7b48eSJacob Chen 98*ded874ecSPaul Kocialkowski #define RGA_COLOR_FMT_IS_YUV(fmt) \ 99*ded874ecSPaul Kocialkowski (((fmt) >= RGA_COLOR_FMT_YUV422SP) && ((fmt) < RGA_COLOR_FMT_CP_1BPP)) 100*ded874ecSPaul Kocialkowski #define RGA_COLOR_FMT_IS_RGB(fmt) \ 101*ded874ecSPaul Kocialkowski ((fmt) < RGA_COLOR_FMT_YUV422SP) 102*ded874ecSPaul Kocialkowski 103f7e7b48eSJacob Chen #define RGA_COLOR_NONE_SWAP 0 104f7e7b48eSJacob Chen #define RGA_COLOR_RB_SWAP 1 105f7e7b48eSJacob Chen #define RGA_COLOR_ALPHA_SWAP 2 106f7e7b48eSJacob Chen #define RGA_COLOR_UV_SWAP 4 107f7e7b48eSJacob Chen 108f7e7b48eSJacob Chen #define RGA_SRC_CSC_MODE_BYPASS 0 109f7e7b48eSJacob Chen #define RGA_SRC_CSC_MODE_BT601_R0 1 110f7e7b48eSJacob Chen #define RGA_SRC_CSC_MODE_BT601_R1 2 111f7e7b48eSJacob Chen #define RGA_SRC_CSC_MODE_BT709_R0 3 112f7e7b48eSJacob Chen #define RGA_SRC_CSC_MODE_BT709_R1 4 113f7e7b48eSJacob Chen 114f7e7b48eSJacob Chen #define RGA_SRC_ROT_MODE_0_DEGREE 0 115f7e7b48eSJacob Chen #define RGA_SRC_ROT_MODE_90_DEGREE 1 116f7e7b48eSJacob Chen #define RGA_SRC_ROT_MODE_180_DEGREE 2 117f7e7b48eSJacob Chen #define RGA_SRC_ROT_MODE_270_DEGREE 3 118f7e7b48eSJacob Chen 119f7e7b48eSJacob Chen #define RGA_SRC_MIRR_MODE_NO 0 120f7e7b48eSJacob Chen #define RGA_SRC_MIRR_MODE_X 1 121f7e7b48eSJacob Chen #define RGA_SRC_MIRR_MODE_Y 2 122f7e7b48eSJacob Chen #define RGA_SRC_MIRR_MODE_X_Y 3 123f7e7b48eSJacob Chen 124f7e7b48eSJacob Chen #define RGA_SRC_HSCL_MODE_NO 0 125f7e7b48eSJacob Chen #define RGA_SRC_HSCL_MODE_DOWN 1 126f7e7b48eSJacob Chen #define RGA_SRC_HSCL_MODE_UP 2 127f7e7b48eSJacob Chen 128f7e7b48eSJacob Chen #define RGA_SRC_VSCL_MODE_NO 0 129f7e7b48eSJacob Chen #define RGA_SRC_VSCL_MODE_DOWN 1 130f7e7b48eSJacob Chen #define RGA_SRC_VSCL_MODE_UP 2 131f7e7b48eSJacob Chen 132f7e7b48eSJacob Chen #define RGA_SRC_TRANS_ENABLE_R 1 133f7e7b48eSJacob Chen #define RGA_SRC_TRANS_ENABLE_G 2 134f7e7b48eSJacob Chen #define RGA_SRC_TRANS_ENABLE_B 4 135f7e7b48eSJacob Chen #define RGA_SRC_TRANS_ENABLE_A 8 136f7e7b48eSJacob Chen 137f7e7b48eSJacob Chen #define RGA_SRC_BIC_COE_SELEC_CATROM 0 138f7e7b48eSJacob Chen #define RGA_SRC_BIC_COE_SELEC_MITCHELL 1 139f7e7b48eSJacob Chen #define RGA_SRC_BIC_COE_SELEC_HERMITE 2 140f7e7b48eSJacob Chen #define RGA_SRC_BIC_COE_SELEC_BSPLINE 3 141f7e7b48eSJacob Chen 142f7e7b48eSJacob Chen #define RGA_DST_DITHER_MODE_888_TO_666 0 143f7e7b48eSJacob Chen #define RGA_DST_DITHER_MODE_888_TO_565 1 144f7e7b48eSJacob Chen #define RGA_DST_DITHER_MODE_888_TO_555 2 145f7e7b48eSJacob Chen #define RGA_DST_DITHER_MODE_888_TO_444 3 146f7e7b48eSJacob Chen 147f7e7b48eSJacob Chen #define RGA_DST_CSC_MODE_BYPASS 0 148f7e7b48eSJacob Chen #define RGA_DST_CSC_MODE_BT601_R0 1 149f7e7b48eSJacob Chen #define RGA_DST_CSC_MODE_BT601_R1 2 150f7e7b48eSJacob Chen #define RGA_DST_CSC_MODE_BT709_R0 3 151f7e7b48eSJacob Chen 152f7e7b48eSJacob Chen #define RGA_ALPHA_ROP_MODE_2 0 153f7e7b48eSJacob Chen #define RGA_ALPHA_ROP_MODE_3 1 154f7e7b48eSJacob Chen #define RGA_ALPHA_ROP_MODE_4 2 155f7e7b48eSJacob Chen 156f7e7b48eSJacob Chen #define RGA_ALPHA_SELECT_ALPHA 0 157f7e7b48eSJacob Chen #define RGA_ALPHA_SELECT_ROP 1 158f7e7b48eSJacob Chen 159f7e7b48eSJacob Chen #define RGA_ALPHA_MASK_BIG_ENDIAN 0 160f7e7b48eSJacob Chen #define RGA_ALPHA_MASK_LITTLE_ENDIAN 1 161f7e7b48eSJacob Chen 162f7e7b48eSJacob Chen #define RGA_ALPHA_NORMAL 0 163f7e7b48eSJacob Chen #define RGA_ALPHA_REVERSE 1 164f7e7b48eSJacob Chen 165f7e7b48eSJacob Chen #define RGA_ALPHA_BLEND_GLOBAL 0 166f7e7b48eSJacob Chen #define RGA_ALPHA_BLEND_NORMAL 1 167f7e7b48eSJacob Chen #define RGA_ALPHA_BLEND_MULTIPLY 2 168f7e7b48eSJacob Chen 169f7e7b48eSJacob Chen #define RGA_ALPHA_CAL_CUT 0 170f7e7b48eSJacob Chen #define RGA_ALPHA_CAL_NORMAL 1 171f7e7b48eSJacob Chen 172f7e7b48eSJacob Chen #define RGA_ALPHA_FACTOR_ZERO 0 173f7e7b48eSJacob Chen #define RGA_ALPHA_FACTOR_ONE 1 174f7e7b48eSJacob Chen #define RGA_ALPHA_FACTOR_OTHER 2 175f7e7b48eSJacob Chen #define RGA_ALPHA_FACTOR_OTHER_REVERSE 3 176f7e7b48eSJacob Chen #define RGA_ALPHA_FACTOR_SELF 4 177f7e7b48eSJacob Chen 178f7e7b48eSJacob Chen #define RGA_ALPHA_COLOR_NORMAL 0 179f7e7b48eSJacob Chen #define RGA_ALPHA_COLOR_MULTIPLY_CAL 1 180f7e7b48eSJacob Chen 181f7e7b48eSJacob Chen /* Registers union */ 182f7e7b48eSJacob Chen union rga_mode_ctrl { 183f7e7b48eSJacob Chen unsigned int val; 184f7e7b48eSJacob Chen struct { 185f7e7b48eSJacob Chen /* [0:2] */ 186f7e7b48eSJacob Chen unsigned int render:3; 187f7e7b48eSJacob Chen /* [3:6] */ 188f7e7b48eSJacob Chen unsigned int bitblt:1; 189f7e7b48eSJacob Chen unsigned int cf_rop4_pat:1; 190f7e7b48eSJacob Chen unsigned int alpha_zero_key:1; 191f7e7b48eSJacob Chen unsigned int gradient_sat:1; 192f7e7b48eSJacob Chen /* [7:31] */ 193f7e7b48eSJacob Chen unsigned int reserved:25; 194f7e7b48eSJacob Chen } data; 195f7e7b48eSJacob Chen }; 196f7e7b48eSJacob Chen 197f7e7b48eSJacob Chen union rga_src_info { 198f7e7b48eSJacob Chen unsigned int val; 199f7e7b48eSJacob Chen struct { 200f7e7b48eSJacob Chen /* [0:3] */ 201f7e7b48eSJacob Chen unsigned int format:4; 202f7e7b48eSJacob Chen /* [4:7] */ 203f7e7b48eSJacob Chen unsigned int swap:3; 204f7e7b48eSJacob Chen unsigned int cp_endian:1; 205f7e7b48eSJacob Chen /* [8:17] */ 206f7e7b48eSJacob Chen unsigned int csc_mode:2; 207f7e7b48eSJacob Chen unsigned int rot_mode:2; 208f7e7b48eSJacob Chen unsigned int mir_mode:2; 209f7e7b48eSJacob Chen unsigned int hscl_mode:2; 210f7e7b48eSJacob Chen unsigned int vscl_mode:2; 211f7e7b48eSJacob Chen /* [18:22] */ 212f7e7b48eSJacob Chen unsigned int trans_mode:1; 213f7e7b48eSJacob Chen unsigned int trans_enable:4; 214f7e7b48eSJacob Chen /* [23:25] */ 215f7e7b48eSJacob Chen unsigned int dither_up_en:1; 216f7e7b48eSJacob Chen unsigned int bic_coe_sel:2; 217f7e7b48eSJacob Chen /* [26:31] */ 218f7e7b48eSJacob Chen unsigned int reserved:6; 219f7e7b48eSJacob Chen } data; 220f7e7b48eSJacob Chen }; 221f7e7b48eSJacob Chen 222f7e7b48eSJacob Chen union rga_src_vir_info { 223f7e7b48eSJacob Chen unsigned int val; 224f7e7b48eSJacob Chen struct { 225f7e7b48eSJacob Chen /* [0:15] */ 226f7e7b48eSJacob Chen unsigned int vir_width:15; 227f7e7b48eSJacob Chen unsigned int reserved:1; 228f7e7b48eSJacob Chen /* [16:25] */ 229f7e7b48eSJacob Chen unsigned int vir_stride:10; 230f7e7b48eSJacob Chen /* [26:31] */ 231f7e7b48eSJacob Chen unsigned int reserved1:6; 232f7e7b48eSJacob Chen } data; 233f7e7b48eSJacob Chen }; 234f7e7b48eSJacob Chen 235f7e7b48eSJacob Chen union rga_src_act_info { 236f7e7b48eSJacob Chen unsigned int val; 237f7e7b48eSJacob Chen struct { 238f7e7b48eSJacob Chen /* [0:15] */ 239f7e7b48eSJacob Chen unsigned int act_width:13; 240f7e7b48eSJacob Chen unsigned int reserved:3; 241f7e7b48eSJacob Chen /* [16:31] */ 242f7e7b48eSJacob Chen unsigned int act_height:13; 243f7e7b48eSJacob Chen unsigned int reserved1:3; 244f7e7b48eSJacob Chen } data; 245f7e7b48eSJacob Chen }; 246f7e7b48eSJacob Chen 247f7e7b48eSJacob Chen union rga_src_x_factor { 248f7e7b48eSJacob Chen unsigned int val; 249f7e7b48eSJacob Chen struct { 250f7e7b48eSJacob Chen /* [0:15] */ 251f7e7b48eSJacob Chen unsigned int down_scale_factor:16; 252f7e7b48eSJacob Chen /* [16:31] */ 253f7e7b48eSJacob Chen unsigned int up_scale_factor:16; 254f7e7b48eSJacob Chen } data; 255f7e7b48eSJacob Chen }; 256f7e7b48eSJacob Chen 257f7e7b48eSJacob Chen union rga_src_y_factor { 258f7e7b48eSJacob Chen unsigned int val; 259f7e7b48eSJacob Chen struct { 260f7e7b48eSJacob Chen /* [0:15] */ 261f7e7b48eSJacob Chen unsigned int down_scale_factor:16; 262f7e7b48eSJacob Chen /* [16:31] */ 263f7e7b48eSJacob Chen unsigned int up_scale_factor:16; 264f7e7b48eSJacob Chen } data; 265f7e7b48eSJacob Chen }; 266f7e7b48eSJacob Chen 267f7e7b48eSJacob Chen /* Alpha / Red / Green / Blue */ 268f7e7b48eSJacob Chen union rga_src_cp_gr_color { 269f7e7b48eSJacob Chen unsigned int val; 270f7e7b48eSJacob Chen struct { 271f7e7b48eSJacob Chen /* [0:15] */ 272f7e7b48eSJacob Chen unsigned int gradient_x:16; 273f7e7b48eSJacob Chen /* [16:31] */ 274f7e7b48eSJacob Chen unsigned int gradient_y:16; 275f7e7b48eSJacob Chen } data; 276f7e7b48eSJacob Chen }; 277f7e7b48eSJacob Chen 278f7e7b48eSJacob Chen union rga_src_transparency_color0 { 279f7e7b48eSJacob Chen unsigned int val; 280f7e7b48eSJacob Chen struct { 281f7e7b48eSJacob Chen /* [0:7] */ 282f7e7b48eSJacob Chen unsigned int trans_rmin:8; 283f7e7b48eSJacob Chen /* [8:15] */ 284f7e7b48eSJacob Chen unsigned int trans_gmin:8; 285f7e7b48eSJacob Chen /* [16:23] */ 286f7e7b48eSJacob Chen unsigned int trans_bmin:8; 287f7e7b48eSJacob Chen /* [24:31] */ 288f7e7b48eSJacob Chen unsigned int trans_amin:8; 289f7e7b48eSJacob Chen } data; 290f7e7b48eSJacob Chen }; 291f7e7b48eSJacob Chen 292f7e7b48eSJacob Chen union rga_src_transparency_color1 { 293f7e7b48eSJacob Chen unsigned int val; 294f7e7b48eSJacob Chen struct { 295f7e7b48eSJacob Chen /* [0:7] */ 296f7e7b48eSJacob Chen unsigned int trans_rmax:8; 297f7e7b48eSJacob Chen /* [8:15] */ 298f7e7b48eSJacob Chen unsigned int trans_gmax:8; 299f7e7b48eSJacob Chen /* [16:23] */ 300f7e7b48eSJacob Chen unsigned int trans_bmax:8; 301f7e7b48eSJacob Chen /* [24:31] */ 302f7e7b48eSJacob Chen unsigned int trans_amax:8; 303f7e7b48eSJacob Chen } data; 304f7e7b48eSJacob Chen }; 305f7e7b48eSJacob Chen 306f7e7b48eSJacob Chen union rga_dst_info { 307f7e7b48eSJacob Chen unsigned int val; 308f7e7b48eSJacob Chen struct { 309f7e7b48eSJacob Chen /* [0:3] */ 310f7e7b48eSJacob Chen unsigned int format:4; 311f7e7b48eSJacob Chen /* [4:6] */ 312f7e7b48eSJacob Chen unsigned int swap:3; 313f7e7b48eSJacob Chen /* [7:9] */ 314f7e7b48eSJacob Chen unsigned int src1_format:3; 315f7e7b48eSJacob Chen /* [10:11] */ 316f7e7b48eSJacob Chen unsigned int src1_swap:2; 317f7e7b48eSJacob Chen /* [12:15] */ 318f7e7b48eSJacob Chen unsigned int dither_up_en:1; 319f7e7b48eSJacob Chen unsigned int dither_down_en:1; 320f7e7b48eSJacob Chen unsigned int dither_down_mode:2; 321f7e7b48eSJacob Chen /* [16:18] */ 322f7e7b48eSJacob Chen unsigned int csc_mode:2; 323f7e7b48eSJacob Chen unsigned int csc_clip:1; 324f7e7b48eSJacob Chen /* [19:31] */ 325f7e7b48eSJacob Chen unsigned int reserved:13; 326f7e7b48eSJacob Chen } data; 327f7e7b48eSJacob Chen }; 328f7e7b48eSJacob Chen 329f7e7b48eSJacob Chen union rga_dst_vir_info { 330f7e7b48eSJacob Chen unsigned int val; 331f7e7b48eSJacob Chen struct { 332f7e7b48eSJacob Chen /* [0:15] */ 333f7e7b48eSJacob Chen unsigned int vir_stride:15; 334f7e7b48eSJacob Chen unsigned int reserved:1; 335f7e7b48eSJacob Chen /* [16:31] */ 336f7e7b48eSJacob Chen unsigned int src1_vir_stride:15; 337f7e7b48eSJacob Chen unsigned int reserved1:1; 338f7e7b48eSJacob Chen } data; 339f7e7b48eSJacob Chen }; 340f7e7b48eSJacob Chen 341f7e7b48eSJacob Chen union rga_dst_act_info { 342f7e7b48eSJacob Chen unsigned int val; 343f7e7b48eSJacob Chen struct { 344f7e7b48eSJacob Chen /* [0:15] */ 345f7e7b48eSJacob Chen unsigned int act_width:12; 346f7e7b48eSJacob Chen unsigned int reserved:4; 347f7e7b48eSJacob Chen /* [16:31] */ 348f7e7b48eSJacob Chen unsigned int act_height:12; 349f7e7b48eSJacob Chen unsigned int reserved1:4; 350f7e7b48eSJacob Chen } data; 351f7e7b48eSJacob Chen }; 352f7e7b48eSJacob Chen 353f7e7b48eSJacob Chen union rga_alpha_ctrl0 { 354f7e7b48eSJacob Chen unsigned int val; 355f7e7b48eSJacob Chen struct { 356f7e7b48eSJacob Chen /* [0:3] */ 357f7e7b48eSJacob Chen unsigned int rop_en:1; 358f7e7b48eSJacob Chen unsigned int rop_select:1; 359f7e7b48eSJacob Chen unsigned int rop_mode:2; 360f7e7b48eSJacob Chen /* [4:11] */ 361f7e7b48eSJacob Chen unsigned int src_fading_val:8; 362f7e7b48eSJacob Chen /* [12:20] */ 363f7e7b48eSJacob Chen unsigned int dst_fading_val:8; 364f7e7b48eSJacob Chen unsigned int mask_endian:1; 365f7e7b48eSJacob Chen /* [21:31] */ 366f7e7b48eSJacob Chen unsigned int reserved:11; 367f7e7b48eSJacob Chen } data; 368f7e7b48eSJacob Chen }; 369f7e7b48eSJacob Chen 370f7e7b48eSJacob Chen union rga_alpha_ctrl1 { 371f7e7b48eSJacob Chen unsigned int val; 372f7e7b48eSJacob Chen struct { 373f7e7b48eSJacob Chen /* [0:1] */ 374f7e7b48eSJacob Chen unsigned int dst_color_m0:1; 375f7e7b48eSJacob Chen unsigned int src_color_m0:1; 376f7e7b48eSJacob Chen /* [2:7] */ 377f7e7b48eSJacob Chen unsigned int dst_factor_m0:3; 378f7e7b48eSJacob Chen unsigned int src_factor_m0:3; 379f7e7b48eSJacob Chen /* [8:9] */ 380f7e7b48eSJacob Chen unsigned int dst_alpha_cal_m0:1; 381f7e7b48eSJacob Chen unsigned int src_alpha_cal_m0:1; 382f7e7b48eSJacob Chen /* [10:13] */ 383f7e7b48eSJacob Chen unsigned int dst_blend_m0:2; 384f7e7b48eSJacob Chen unsigned int src_blend_m0:2; 385f7e7b48eSJacob Chen /* [14:15] */ 386f7e7b48eSJacob Chen unsigned int dst_alpha_m0:1; 387f7e7b48eSJacob Chen unsigned int src_alpha_m0:1; 388f7e7b48eSJacob Chen /* [16:21] */ 389f7e7b48eSJacob Chen unsigned int dst_factor_m1:3; 390f7e7b48eSJacob Chen unsigned int src_factor_m1:3; 391f7e7b48eSJacob Chen /* [22:23] */ 392f7e7b48eSJacob Chen unsigned int dst_alpha_cal_m1:1; 393f7e7b48eSJacob Chen unsigned int src_alpha_cal_m1:1; 394f7e7b48eSJacob Chen /* [24:27] */ 395f7e7b48eSJacob Chen unsigned int dst_blend_m1:2; 396f7e7b48eSJacob Chen unsigned int src_blend_m1:2; 397f7e7b48eSJacob Chen /* [28:29] */ 398f7e7b48eSJacob Chen unsigned int dst_alpha_m1:1; 399f7e7b48eSJacob Chen unsigned int src_alpha_m1:1; 400f7e7b48eSJacob Chen /* [30:31] */ 401f7e7b48eSJacob Chen unsigned int reserved:2; 402f7e7b48eSJacob Chen } data; 403f7e7b48eSJacob Chen }; 404f7e7b48eSJacob Chen 405f7e7b48eSJacob Chen union rga_fading_ctrl { 406f7e7b48eSJacob Chen unsigned int val; 407f7e7b48eSJacob Chen struct { 408f7e7b48eSJacob Chen /* [0:7] */ 409f7e7b48eSJacob Chen unsigned int fading_offset_r:8; 410f7e7b48eSJacob Chen /* [8:15] */ 411f7e7b48eSJacob Chen unsigned int fading_offset_g:8; 412f7e7b48eSJacob Chen /* [16:23] */ 413f7e7b48eSJacob Chen unsigned int fading_offset_b:8; 414f7e7b48eSJacob Chen /* [24:31] */ 415f7e7b48eSJacob Chen unsigned int fading_en:1; 416f7e7b48eSJacob Chen unsigned int reserved:7; 417f7e7b48eSJacob Chen } data; 418f7e7b48eSJacob Chen }; 419f7e7b48eSJacob Chen 420f7e7b48eSJacob Chen union rga_pat_con { 421f7e7b48eSJacob Chen unsigned int val; 422f7e7b48eSJacob Chen struct { 423f7e7b48eSJacob Chen /* [0:7] */ 424f7e7b48eSJacob Chen unsigned int width:8; 425f7e7b48eSJacob Chen /* [8:15] */ 426f7e7b48eSJacob Chen unsigned int height:8; 427f7e7b48eSJacob Chen /* [16:23] */ 428f7e7b48eSJacob Chen unsigned int offset_x:8; 429f7e7b48eSJacob Chen /* [24:31] */ 430f7e7b48eSJacob Chen unsigned int offset_y:8; 431f7e7b48eSJacob Chen } data; 432f7e7b48eSJacob Chen }; 433f7e7b48eSJacob Chen 434f7e7b48eSJacob Chen #endif 435