152d15dd2SThierry Reding // SPDX-License-Identifier: GPL-2.0-only
252d15dd2SThierry Reding /*
352d15dd2SThierry Reding * Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
452d15dd2SThierry Reding */
552d15dd2SThierry Reding
652d15dd2SThierry Reding #include <linux/clk.h>
752d15dd2SThierry Reding #include <linux/debugfs.h>
852d15dd2SThierry Reding #include <linux/module.h>
952d15dd2SThierry Reding #include <linux/mod_devicetable.h>
109a38cb27SSumit Gupta #include <linux/of_platform.h>
1152d15dd2SThierry Reding #include <linux/platform_device.h>
1252d15dd2SThierry Reding
1352d15dd2SThierry Reding #include <soc/tegra/bpmp.h>
149a38cb27SSumit Gupta #include "mc.h"
1552d15dd2SThierry Reding
1652d15dd2SThierry Reding struct tegra186_emc_dvfs {
1752d15dd2SThierry Reding unsigned long latency;
1852d15dd2SThierry Reding unsigned long rate;
1952d15dd2SThierry Reding };
2052d15dd2SThierry Reding
2152d15dd2SThierry Reding struct tegra186_emc {
2252d15dd2SThierry Reding struct tegra_bpmp *bpmp;
2352d15dd2SThierry Reding struct device *dev;
2452d15dd2SThierry Reding struct clk *clk;
2552d15dd2SThierry Reding
2652d15dd2SThierry Reding struct tegra186_emc_dvfs *dvfs;
2752d15dd2SThierry Reding unsigned int num_dvfs;
2852d15dd2SThierry Reding
2952d15dd2SThierry Reding struct {
3052d15dd2SThierry Reding struct dentry *root;
3152d15dd2SThierry Reding unsigned long min_rate;
3252d15dd2SThierry Reding unsigned long max_rate;
3352d15dd2SThierry Reding } debugfs;
349a38cb27SSumit Gupta
359a38cb27SSumit Gupta struct icc_provider provider;
3652d15dd2SThierry Reding };
3752d15dd2SThierry Reding
3852d15dd2SThierry Reding /*
3952d15dd2SThierry Reding * debugfs interface
4052d15dd2SThierry Reding *
4152d15dd2SThierry Reding * The memory controller driver exposes some files in debugfs that can be used
4252d15dd2SThierry Reding * to control the EMC frequency. The top-level directory can be found here:
4352d15dd2SThierry Reding *
4452d15dd2SThierry Reding * /sys/kernel/debug/emc
4552d15dd2SThierry Reding *
4652d15dd2SThierry Reding * It contains the following files:
4752d15dd2SThierry Reding *
4852d15dd2SThierry Reding * - available_rates: This file contains a list of valid, space-separated
4952d15dd2SThierry Reding * EMC frequencies.
5052d15dd2SThierry Reding *
5152d15dd2SThierry Reding * - min_rate: Writing a value to this file sets the given frequency as the
5252d15dd2SThierry Reding * floor of the permitted range. If this is higher than the currently
5352d15dd2SThierry Reding * configured EMC frequency, this will cause the frequency to be
5452d15dd2SThierry Reding * increased so that it stays within the valid range.
5552d15dd2SThierry Reding *
5652d15dd2SThierry Reding * - max_rate: Similarily to the min_rate file, writing a value to this file
5752d15dd2SThierry Reding * sets the given frequency as the ceiling of the permitted range. If
5852d15dd2SThierry Reding * the value is lower than the currently configured EMC frequency, this
5952d15dd2SThierry Reding * will cause the frequency to be decreased so that it stays within the
6052d15dd2SThierry Reding * valid range.
6152d15dd2SThierry Reding */
6252d15dd2SThierry Reding
tegra186_emc_validate_rate(struct tegra186_emc * emc,unsigned long rate)6352d15dd2SThierry Reding static bool tegra186_emc_validate_rate(struct tegra186_emc *emc,
6452d15dd2SThierry Reding unsigned long rate)
6552d15dd2SThierry Reding {
6652d15dd2SThierry Reding unsigned int i;
6752d15dd2SThierry Reding
6852d15dd2SThierry Reding for (i = 0; i < emc->num_dvfs; i++)
6952d15dd2SThierry Reding if (rate == emc->dvfs[i].rate)
7052d15dd2SThierry Reding return true;
7152d15dd2SThierry Reding
7252d15dd2SThierry Reding return false;
7352d15dd2SThierry Reding }
7452d15dd2SThierry Reding
tegra186_emc_debug_available_rates_show(struct seq_file * s,void * data)7552d15dd2SThierry Reding static int tegra186_emc_debug_available_rates_show(struct seq_file *s,
7652d15dd2SThierry Reding void *data)
7752d15dd2SThierry Reding {
7852d15dd2SThierry Reding struct tegra186_emc *emc = s->private;
7952d15dd2SThierry Reding const char *prefix = "";
8052d15dd2SThierry Reding unsigned int i;
8152d15dd2SThierry Reding
8252d15dd2SThierry Reding for (i = 0; i < emc->num_dvfs; i++) {
8352d15dd2SThierry Reding seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate);
8452d15dd2SThierry Reding prefix = " ";
8552d15dd2SThierry Reding }
8652d15dd2SThierry Reding
8752d15dd2SThierry Reding seq_puts(s, "\n");
8852d15dd2SThierry Reding
8952d15dd2SThierry Reding return 0;
9052d15dd2SThierry Reding }
9158504acdSLiu Shixin DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates);
9252d15dd2SThierry Reding
tegra186_emc_debug_min_rate_get(void * data,u64 * rate)9352d15dd2SThierry Reding static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate)
9452d15dd2SThierry Reding {
9552d15dd2SThierry Reding struct tegra186_emc *emc = data;
9652d15dd2SThierry Reding
9752d15dd2SThierry Reding *rate = emc->debugfs.min_rate;
9852d15dd2SThierry Reding
9952d15dd2SThierry Reding return 0;
10052d15dd2SThierry Reding }
10152d15dd2SThierry Reding
tegra186_emc_debug_min_rate_set(void * data,u64 rate)10252d15dd2SThierry Reding static int tegra186_emc_debug_min_rate_set(void *data, u64 rate)
10352d15dd2SThierry Reding {
10452d15dd2SThierry Reding struct tegra186_emc *emc = data;
10552d15dd2SThierry Reding int err;
10652d15dd2SThierry Reding
10752d15dd2SThierry Reding if (!tegra186_emc_validate_rate(emc, rate))
10852d15dd2SThierry Reding return -EINVAL;
10952d15dd2SThierry Reding
11052d15dd2SThierry Reding err = clk_set_min_rate(emc->clk, rate);
11152d15dd2SThierry Reding if (err < 0)
11252d15dd2SThierry Reding return err;
11352d15dd2SThierry Reding
11452d15dd2SThierry Reding emc->debugfs.min_rate = rate;
11552d15dd2SThierry Reding
11652d15dd2SThierry Reding return 0;
11752d15dd2SThierry Reding }
11852d15dd2SThierry Reding
119321b36c7SJiapeng Chong DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops,
12052d15dd2SThierry Reding tegra186_emc_debug_min_rate_get,
12152d15dd2SThierry Reding tegra186_emc_debug_min_rate_set, "%llu\n");
12252d15dd2SThierry Reding
tegra186_emc_debug_max_rate_get(void * data,u64 * rate)12352d15dd2SThierry Reding static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate)
12452d15dd2SThierry Reding {
12552d15dd2SThierry Reding struct tegra186_emc *emc = data;
12652d15dd2SThierry Reding
12752d15dd2SThierry Reding *rate = emc->debugfs.max_rate;
12852d15dd2SThierry Reding
12952d15dd2SThierry Reding return 0;
13052d15dd2SThierry Reding }
13152d15dd2SThierry Reding
tegra186_emc_debug_max_rate_set(void * data,u64 rate)13252d15dd2SThierry Reding static int tegra186_emc_debug_max_rate_set(void *data, u64 rate)
13352d15dd2SThierry Reding {
13452d15dd2SThierry Reding struct tegra186_emc *emc = data;
13552d15dd2SThierry Reding int err;
13652d15dd2SThierry Reding
13752d15dd2SThierry Reding if (!tegra186_emc_validate_rate(emc, rate))
13852d15dd2SThierry Reding return -EINVAL;
13952d15dd2SThierry Reding
14052d15dd2SThierry Reding err = clk_set_max_rate(emc->clk, rate);
14152d15dd2SThierry Reding if (err < 0)
14252d15dd2SThierry Reding return err;
14352d15dd2SThierry Reding
14452d15dd2SThierry Reding emc->debugfs.max_rate = rate;
14552d15dd2SThierry Reding
14652d15dd2SThierry Reding return 0;
14752d15dd2SThierry Reding }
14852d15dd2SThierry Reding
149321b36c7SJiapeng Chong DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops,
15052d15dd2SThierry Reding tegra186_emc_debug_max_rate_get,
15152d15dd2SThierry Reding tegra186_emc_debug_max_rate_set, "%llu\n");
15252d15dd2SThierry Reding
tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc * emc)1530a7e4578SSumit Gupta static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
1540a7e4578SSumit Gupta {
1550a7e4578SSumit Gupta struct mrq_emc_dvfs_latency_response response;
1560a7e4578SSumit Gupta struct tegra_bpmp_message msg;
1570a7e4578SSumit Gupta unsigned int i;
1580a7e4578SSumit Gupta int err;
1590a7e4578SSumit Gupta
1600a7e4578SSumit Gupta memset(&msg, 0, sizeof(msg));
1610a7e4578SSumit Gupta msg.mrq = MRQ_EMC_DVFS_LATENCY;
1620a7e4578SSumit Gupta msg.tx.data = NULL;
1630a7e4578SSumit Gupta msg.tx.size = 0;
1640a7e4578SSumit Gupta msg.rx.data = &response;
1650a7e4578SSumit Gupta msg.rx.size = sizeof(response);
1660a7e4578SSumit Gupta
1670a7e4578SSumit Gupta err = tegra_bpmp_transfer(emc->bpmp, &msg);
1680a7e4578SSumit Gupta if (err < 0) {
1690a7e4578SSumit Gupta dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
1700a7e4578SSumit Gupta return err;
1710a7e4578SSumit Gupta }
1720a7e4578SSumit Gupta if (msg.rx.ret < 0) {
1730a7e4578SSumit Gupta dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
1740a7e4578SSumit Gupta return -EINVAL;
1750a7e4578SSumit Gupta }
1760a7e4578SSumit Gupta
1770a7e4578SSumit Gupta emc->debugfs.min_rate = ULONG_MAX;
1780a7e4578SSumit Gupta emc->debugfs.max_rate = 0;
1790a7e4578SSumit Gupta
1800a7e4578SSumit Gupta emc->num_dvfs = response.num_pairs;
1810a7e4578SSumit Gupta
1820a7e4578SSumit Gupta emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
1830a7e4578SSumit Gupta if (!emc->dvfs)
1840a7e4578SSumit Gupta return -ENOMEM;
1850a7e4578SSumit Gupta
1860a7e4578SSumit Gupta dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
1870a7e4578SSumit Gupta
1880a7e4578SSumit Gupta for (i = 0; i < emc->num_dvfs; i++) {
1890a7e4578SSumit Gupta emc->dvfs[i].rate = response.pairs[i].freq * 1000;
1900a7e4578SSumit Gupta emc->dvfs[i].latency = response.pairs[i].latency;
1910a7e4578SSumit Gupta
1920a7e4578SSumit Gupta if (emc->dvfs[i].rate < emc->debugfs.min_rate)
1930a7e4578SSumit Gupta emc->debugfs.min_rate = emc->dvfs[i].rate;
1940a7e4578SSumit Gupta
1950a7e4578SSumit Gupta if (emc->dvfs[i].rate > emc->debugfs.max_rate)
1960a7e4578SSumit Gupta emc->debugfs.max_rate = emc->dvfs[i].rate;
1970a7e4578SSumit Gupta
1980a7e4578SSumit Gupta dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
1990a7e4578SSumit Gupta emc->dvfs[i].rate, emc->dvfs[i].latency);
2000a7e4578SSumit Gupta }
2010a7e4578SSumit Gupta
2020a7e4578SSumit Gupta err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
2030a7e4578SSumit Gupta if (err < 0) {
2040a7e4578SSumit Gupta dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
2050a7e4578SSumit Gupta emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
2060a7e4578SSumit Gupta return err;
2070a7e4578SSumit Gupta }
2080a7e4578SSumit Gupta
2090a7e4578SSumit Gupta emc->debugfs.root = debugfs_create_dir("emc", NULL);
2106e1547f9SThierry Reding debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
2116e1547f9SThierry Reding &tegra186_emc_debug_available_rates_fops);
2126e1547f9SThierry Reding debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
2136e1547f9SThierry Reding &tegra186_emc_debug_min_rate_fops);
2146e1547f9SThierry Reding debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
2156e1547f9SThierry Reding &tegra186_emc_debug_max_rate_fops);
2160a7e4578SSumit Gupta
2170a7e4578SSumit Gupta return 0;
2180a7e4578SSumit Gupta }
2190a7e4578SSumit Gupta
2209a38cb27SSumit Gupta /*
2219a38cb27SSumit Gupta * tegra_emc_icc_set_bw() - Set BW api for EMC provider
2229a38cb27SSumit Gupta * @src: ICC node for External Memory Controller (EMC)
2239a38cb27SSumit Gupta * @dst: ICC node for External Memory (DRAM)
2249a38cb27SSumit Gupta *
2259a38cb27SSumit Gupta * Do nothing here as info to BPMP-FW is now passed in the BW set function
2269a38cb27SSumit Gupta * of the MC driver. BPMP-FW sets the final Freq based on the passed values.
2279a38cb27SSumit Gupta */
tegra_emc_icc_set_bw(struct icc_node * src,struct icc_node * dst)2289a38cb27SSumit Gupta static int tegra_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst)
2299a38cb27SSumit Gupta {
2309a38cb27SSumit Gupta return 0;
2319a38cb27SSumit Gupta }
2329a38cb27SSumit Gupta
2339a38cb27SSumit Gupta static struct icc_node *
tegra_emc_of_icc_xlate(const struct of_phandle_args * spec,void * data)234*0dc5b8abSKrzysztof Kozlowski tegra_emc_of_icc_xlate(const struct of_phandle_args *spec, void *data)
2359a38cb27SSumit Gupta {
2369a38cb27SSumit Gupta struct icc_provider *provider = data;
2379a38cb27SSumit Gupta struct icc_node *node;
2389a38cb27SSumit Gupta
2399a38cb27SSumit Gupta /* External Memory is the only possible ICC route */
2409a38cb27SSumit Gupta list_for_each_entry(node, &provider->nodes, node_list) {
2419a38cb27SSumit Gupta if (node->id != TEGRA_ICC_EMEM)
2429a38cb27SSumit Gupta continue;
2439a38cb27SSumit Gupta
2449a38cb27SSumit Gupta return node;
2459a38cb27SSumit Gupta }
2469a38cb27SSumit Gupta
2479a38cb27SSumit Gupta return ERR_PTR(-EPROBE_DEFER);
2489a38cb27SSumit Gupta }
2499a38cb27SSumit Gupta
tegra_emc_icc_get_init_bw(struct icc_node * node,u32 * avg,u32 * peak)2509a38cb27SSumit Gupta static int tegra_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
2519a38cb27SSumit Gupta {
2529a38cb27SSumit Gupta *avg = 0;
2539a38cb27SSumit Gupta *peak = 0;
2549a38cb27SSumit Gupta
2559a38cb27SSumit Gupta return 0;
2569a38cb27SSumit Gupta }
2579a38cb27SSumit Gupta
tegra_emc_interconnect_init(struct tegra186_emc * emc)2589a38cb27SSumit Gupta static int tegra_emc_interconnect_init(struct tegra186_emc *emc)
2599a38cb27SSumit Gupta {
2609a38cb27SSumit Gupta struct tegra_mc *mc = dev_get_drvdata(emc->dev->parent);
2619a38cb27SSumit Gupta const struct tegra_mc_soc *soc = mc->soc;
2629a38cb27SSumit Gupta struct icc_node *node;
2639a38cb27SSumit Gupta int err;
2649a38cb27SSumit Gupta
2659a38cb27SSumit Gupta emc->provider.dev = emc->dev;
2669a38cb27SSumit Gupta emc->provider.set = tegra_emc_icc_set_bw;
2679a38cb27SSumit Gupta emc->provider.data = &emc->provider;
2689a38cb27SSumit Gupta emc->provider.aggregate = soc->icc_ops->aggregate;
2699a38cb27SSumit Gupta emc->provider.xlate = tegra_emc_of_icc_xlate;
2709a38cb27SSumit Gupta emc->provider.get_bw = tegra_emc_icc_get_init_bw;
2719a38cb27SSumit Gupta
2729a38cb27SSumit Gupta icc_provider_init(&emc->provider);
2739a38cb27SSumit Gupta
2749a38cb27SSumit Gupta /* create External Memory Controller node */
2759a38cb27SSumit Gupta node = icc_node_create(TEGRA_ICC_EMC);
2769a38cb27SSumit Gupta if (IS_ERR(node)) {
2779a38cb27SSumit Gupta err = PTR_ERR(node);
2789a38cb27SSumit Gupta goto err_msg;
2799a38cb27SSumit Gupta }
2809a38cb27SSumit Gupta
2819a38cb27SSumit Gupta node->name = "External Memory Controller";
2829a38cb27SSumit Gupta icc_node_add(node, &emc->provider);
2839a38cb27SSumit Gupta
2849a38cb27SSumit Gupta /* link External Memory Controller to External Memory (DRAM) */
2859a38cb27SSumit Gupta err = icc_link_create(node, TEGRA_ICC_EMEM);
2869a38cb27SSumit Gupta if (err)
2879a38cb27SSumit Gupta goto remove_nodes;
2889a38cb27SSumit Gupta
2899a38cb27SSumit Gupta /* create External Memory node */
2909a38cb27SSumit Gupta node = icc_node_create(TEGRA_ICC_EMEM);
2919a38cb27SSumit Gupta if (IS_ERR(node)) {
2929a38cb27SSumit Gupta err = PTR_ERR(node);
2939a38cb27SSumit Gupta goto remove_nodes;
2949a38cb27SSumit Gupta }
2959a38cb27SSumit Gupta
2969a38cb27SSumit Gupta node->name = "External Memory (DRAM)";
2979a38cb27SSumit Gupta icc_node_add(node, &emc->provider);
2989a38cb27SSumit Gupta
2999a38cb27SSumit Gupta err = icc_provider_register(&emc->provider);
3009a38cb27SSumit Gupta if (err)
3019a38cb27SSumit Gupta goto remove_nodes;
3029a38cb27SSumit Gupta
3039a38cb27SSumit Gupta return 0;
3049a38cb27SSumit Gupta
3059a38cb27SSumit Gupta remove_nodes:
3069a38cb27SSumit Gupta icc_nodes_remove(&emc->provider);
3079a38cb27SSumit Gupta err_msg:
3089a38cb27SSumit Gupta dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
3099a38cb27SSumit Gupta
3109a38cb27SSumit Gupta return err;
3119a38cb27SSumit Gupta }
3129a38cb27SSumit Gupta
tegra186_emc_probe(struct platform_device * pdev)31352d15dd2SThierry Reding static int tegra186_emc_probe(struct platform_device *pdev)
31452d15dd2SThierry Reding {
3159a38cb27SSumit Gupta struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
31652d15dd2SThierry Reding struct tegra186_emc *emc;
31752d15dd2SThierry Reding int err;
31852d15dd2SThierry Reding
31952d15dd2SThierry Reding emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
32052d15dd2SThierry Reding if (!emc)
32152d15dd2SThierry Reding return -ENOMEM;
32252d15dd2SThierry Reding
32352d15dd2SThierry Reding emc->bpmp = tegra_bpmp_get(&pdev->dev);
32425f2f5e5SKrzysztof Kozlowski if (IS_ERR(emc->bpmp))
32525f2f5e5SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), "failed to get BPMP\n");
32652d15dd2SThierry Reding
32752d15dd2SThierry Reding emc->clk = devm_clk_get(&pdev->dev, "emc");
32852d15dd2SThierry Reding if (IS_ERR(emc->clk)) {
32952d15dd2SThierry Reding err = PTR_ERR(emc->clk);
33052d15dd2SThierry Reding dev_err(&pdev->dev, "failed to get EMC clock: %d\n", err);
331c3d4eb3bSChristophe JAILLET goto put_bpmp;
33252d15dd2SThierry Reding }
33352d15dd2SThierry Reding
33452d15dd2SThierry Reding platform_set_drvdata(pdev, emc);
33552d15dd2SThierry Reding emc->dev = &pdev->dev;
33652d15dd2SThierry Reding
3370a7e4578SSumit Gupta if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
3380a7e4578SSumit Gupta err = tegra186_emc_get_emc_dvfs_latency(emc);
3390a7e4578SSumit Gupta if (err)
340c3d4eb3bSChristophe JAILLET goto put_bpmp;
34152d15dd2SThierry Reding }
34252d15dd2SThierry Reding
3439a38cb27SSumit Gupta if (mc && mc->soc->icc_ops) {
3449a38cb27SSumit Gupta if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {
3459a38cb27SSumit Gupta mc->bwmgr_mrq_supported = true;
3469a38cb27SSumit Gupta
3479a38cb27SSumit Gupta /*
3489a38cb27SSumit Gupta * MC driver probe can't get BPMP reference as it gets probed
3499a38cb27SSumit Gupta * earlier than BPMP. So, save the BPMP ref got from the EMC
3509a38cb27SSumit Gupta * DT node in the mc->bpmp and use it in MC's icc_set hook.
3519a38cb27SSumit Gupta */
3529a38cb27SSumit Gupta mc->bpmp = emc->bpmp;
3539a38cb27SSumit Gupta barrier();
3549a38cb27SSumit Gupta }
3559a38cb27SSumit Gupta
3569a38cb27SSumit Gupta /*
3579a38cb27SSumit Gupta * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'.
3589a38cb27SSumit Gupta * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return
3599a38cb27SSumit Gupta * EINVAL instead of passing the request to BPMP-FW later when the BW
3609a38cb27SSumit Gupta * request is made by client with 'icc_set_bw()' call.
3619a38cb27SSumit Gupta */
3629a38cb27SSumit Gupta err = tegra_emc_interconnect_init(emc);
3639a38cb27SSumit Gupta if (err) {
3649a38cb27SSumit Gupta mc->bpmp = NULL;
3659a38cb27SSumit Gupta goto put_bpmp;
3669a38cb27SSumit Gupta }
3679a38cb27SSumit Gupta }
3689a38cb27SSumit Gupta
36952d15dd2SThierry Reding return 0;
370c3d4eb3bSChristophe JAILLET
371c3d4eb3bSChristophe JAILLET put_bpmp:
372c3d4eb3bSChristophe JAILLET tegra_bpmp_put(emc->bpmp);
373c3d4eb3bSChristophe JAILLET return err;
37452d15dd2SThierry Reding }
37552d15dd2SThierry Reding
tegra186_emc_remove(struct platform_device * pdev)376dcefa036SUwe Kleine-König static void tegra186_emc_remove(struct platform_device *pdev)
37752d15dd2SThierry Reding {
3789a38cb27SSumit Gupta struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
37952d15dd2SThierry Reding struct tegra186_emc *emc = platform_get_drvdata(pdev);
38052d15dd2SThierry Reding
38152d15dd2SThierry Reding debugfs_remove_recursive(emc->debugfs.root);
3829a38cb27SSumit Gupta
3839a38cb27SSumit Gupta mc->bpmp = NULL;
38452d15dd2SThierry Reding tegra_bpmp_put(emc->bpmp);
38552d15dd2SThierry Reding }
38652d15dd2SThierry Reding
38752d15dd2SThierry Reding static const struct of_device_id tegra186_emc_of_match[] = {
3880454efbcSJon Hunter #if defined(CONFIG_ARCH_TEGRA_186_SOC)
38952d15dd2SThierry Reding { .compatible = "nvidia,tegra186-emc" },
3904e04b886SThierry Reding #endif
3910454efbcSJon Hunter #if defined(CONFIG_ARCH_TEGRA_194_SOC)
392a127e690SThierry Reding { .compatible = "nvidia,tegra194-emc" },
393a127e690SThierry Reding #endif
39472c81bb6SThierry Reding #if defined(CONFIG_ARCH_TEGRA_234_SOC)
39572c81bb6SThierry Reding { .compatible = "nvidia,tegra234-emc" },
39672c81bb6SThierry Reding #endif
39752d15dd2SThierry Reding { /* sentinel */ }
39852d15dd2SThierry Reding };
39952d15dd2SThierry Reding MODULE_DEVICE_TABLE(of, tegra186_emc_of_match);
40052d15dd2SThierry Reding
40152d15dd2SThierry Reding static struct platform_driver tegra186_emc_driver = {
40252d15dd2SThierry Reding .driver = {
40352d15dd2SThierry Reding .name = "tegra186-emc",
40452d15dd2SThierry Reding .of_match_table = tegra186_emc_of_match,
40552d15dd2SThierry Reding .suppress_bind_attrs = true,
4069a38cb27SSumit Gupta .sync_state = icc_sync_state,
40752d15dd2SThierry Reding },
40852d15dd2SThierry Reding .probe = tegra186_emc_probe,
409dcefa036SUwe Kleine-König .remove_new = tegra186_emc_remove,
41052d15dd2SThierry Reding };
41152d15dd2SThierry Reding module_platform_driver(tegra186_emc_driver);
41252d15dd2SThierry Reding
41352d15dd2SThierry Reding MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
41452d15dd2SThierry Reding MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver");
415