1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
293db446aSBoris Brezillon /*
393db446aSBoris Brezillon * Driver for NAND MLC Controller in LPC32xx
493db446aSBoris Brezillon *
593db446aSBoris Brezillon * Author: Roland Stigge <stigge@antcom.de>
693db446aSBoris Brezillon *
793db446aSBoris Brezillon * Copyright © 2011 WORK Microwave GmbH
893db446aSBoris Brezillon * Copyright © 2011, 2012 Roland Stigge
993db446aSBoris Brezillon *
1093db446aSBoris Brezillon * NAND Flash Controller Operation:
1193db446aSBoris Brezillon * - Read: Auto Decode
1293db446aSBoris Brezillon * - Write: Auto Encode
1393db446aSBoris Brezillon * - Tested Page Sizes: 2048, 4096
1493db446aSBoris Brezillon */
1593db446aSBoris Brezillon
1693db446aSBoris Brezillon #include <linux/slab.h>
1793db446aSBoris Brezillon #include <linux/module.h>
1893db446aSBoris Brezillon #include <linux/platform_device.h>
1993db446aSBoris Brezillon #include <linux/mtd/mtd.h>
2093db446aSBoris Brezillon #include <linux/mtd/rawnand.h>
2193db446aSBoris Brezillon #include <linux/mtd/partitions.h>
2293db446aSBoris Brezillon #include <linux/clk.h>
2393db446aSBoris Brezillon #include <linux/err.h>
2493db446aSBoris Brezillon #include <linux/delay.h>
2593db446aSBoris Brezillon #include <linux/completion.h>
2693db446aSBoris Brezillon #include <linux/interrupt.h>
2793db446aSBoris Brezillon #include <linux/of.h>
28782e32a9SDmitry Torokhov #include <linux/gpio/consumer.h>
2993db446aSBoris Brezillon #include <linux/mtd/lpc32xx_mlc.h>
3093db446aSBoris Brezillon #include <linux/io.h>
3193db446aSBoris Brezillon #include <linux/mm.h>
3293db446aSBoris Brezillon #include <linux/dma-mapping.h>
3393db446aSBoris Brezillon #include <linux/dmaengine.h>
3493db446aSBoris Brezillon
3593db446aSBoris Brezillon #define DRV_NAME "lpc32xx_mlc"
3693db446aSBoris Brezillon
3793db446aSBoris Brezillon /**********************************************************************
3893db446aSBoris Brezillon * MLC NAND controller register offsets
3993db446aSBoris Brezillon **********************************************************************/
4093db446aSBoris Brezillon
4193db446aSBoris Brezillon #define MLC_BUFF(x) (x + 0x00000)
4293db446aSBoris Brezillon #define MLC_DATA(x) (x + 0x08000)
4393db446aSBoris Brezillon #define MLC_CMD(x) (x + 0x10000)
4493db446aSBoris Brezillon #define MLC_ADDR(x) (x + 0x10004)
4593db446aSBoris Brezillon #define MLC_ECC_ENC_REG(x) (x + 0x10008)
4693db446aSBoris Brezillon #define MLC_ECC_DEC_REG(x) (x + 0x1000C)
4793db446aSBoris Brezillon #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010)
4893db446aSBoris Brezillon #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014)
4993db446aSBoris Brezillon #define MLC_RPR(x) (x + 0x10018)
5093db446aSBoris Brezillon #define MLC_WPR(x) (x + 0x1001C)
5193db446aSBoris Brezillon #define MLC_RUBP(x) (x + 0x10020)
5293db446aSBoris Brezillon #define MLC_ROBP(x) (x + 0x10024)
5393db446aSBoris Brezillon #define MLC_SW_WP_ADD_LOW(x) (x + 0x10028)
5493db446aSBoris Brezillon #define MLC_SW_WP_ADD_HIG(x) (x + 0x1002C)
5593db446aSBoris Brezillon #define MLC_ICR(x) (x + 0x10030)
5693db446aSBoris Brezillon #define MLC_TIME_REG(x) (x + 0x10034)
5793db446aSBoris Brezillon #define MLC_IRQ_MR(x) (x + 0x10038)
5893db446aSBoris Brezillon #define MLC_IRQ_SR(x) (x + 0x1003C)
5993db446aSBoris Brezillon #define MLC_LOCK_PR(x) (x + 0x10044)
6093db446aSBoris Brezillon #define MLC_ISR(x) (x + 0x10048)
6193db446aSBoris Brezillon #define MLC_CEH(x) (x + 0x1004C)
6293db446aSBoris Brezillon
6393db446aSBoris Brezillon /**********************************************************************
6493db446aSBoris Brezillon * MLC_CMD bit definitions
6593db446aSBoris Brezillon **********************************************************************/
6693db446aSBoris Brezillon #define MLCCMD_RESET 0xFF
6793db446aSBoris Brezillon
6893db446aSBoris Brezillon /**********************************************************************
6993db446aSBoris Brezillon * MLC_ICR bit definitions
7093db446aSBoris Brezillon **********************************************************************/
7193db446aSBoris Brezillon #define MLCICR_WPROT (1 << 3)
7293db446aSBoris Brezillon #define MLCICR_LARGEBLOCK (1 << 2)
7393db446aSBoris Brezillon #define MLCICR_LONGADDR (1 << 1)
7493db446aSBoris Brezillon #define MLCICR_16BIT (1 << 0) /* unsupported by LPC32x0! */
7593db446aSBoris Brezillon
7693db446aSBoris Brezillon /**********************************************************************
7793db446aSBoris Brezillon * MLC_TIME_REG bit definitions
7893db446aSBoris Brezillon **********************************************************************/
7993db446aSBoris Brezillon #define MLCTIMEREG_TCEA_DELAY(n) (((n) & 0x03) << 24)
8093db446aSBoris Brezillon #define MLCTIMEREG_BUSY_DELAY(n) (((n) & 0x1F) << 19)
8193db446aSBoris Brezillon #define MLCTIMEREG_NAND_TA(n) (((n) & 0x07) << 16)
8293db446aSBoris Brezillon #define MLCTIMEREG_RD_HIGH(n) (((n) & 0x0F) << 12)
8393db446aSBoris Brezillon #define MLCTIMEREG_RD_LOW(n) (((n) & 0x0F) << 8)
8493db446aSBoris Brezillon #define MLCTIMEREG_WR_HIGH(n) (((n) & 0x0F) << 4)
8593db446aSBoris Brezillon #define MLCTIMEREG_WR_LOW(n) (((n) & 0x0F) << 0)
8693db446aSBoris Brezillon
8793db446aSBoris Brezillon /**********************************************************************
8893db446aSBoris Brezillon * MLC_IRQ_MR and MLC_IRQ_SR bit definitions
8993db446aSBoris Brezillon **********************************************************************/
9093db446aSBoris Brezillon #define MLCIRQ_NAND_READY (1 << 5)
9193db446aSBoris Brezillon #define MLCIRQ_CONTROLLER_READY (1 << 4)
9293db446aSBoris Brezillon #define MLCIRQ_DECODE_FAILURE (1 << 3)
9393db446aSBoris Brezillon #define MLCIRQ_DECODE_ERROR (1 << 2)
9493db446aSBoris Brezillon #define MLCIRQ_ECC_READY (1 << 1)
9593db446aSBoris Brezillon #define MLCIRQ_WRPROT_FAULT (1 << 0)
9693db446aSBoris Brezillon
9793db446aSBoris Brezillon /**********************************************************************
9893db446aSBoris Brezillon * MLC_LOCK_PR bit definitions
9993db446aSBoris Brezillon **********************************************************************/
10093db446aSBoris Brezillon #define MLCLOCKPR_MAGIC 0xA25E
10193db446aSBoris Brezillon
10293db446aSBoris Brezillon /**********************************************************************
10393db446aSBoris Brezillon * MLC_ISR bit definitions
10493db446aSBoris Brezillon **********************************************************************/
10593db446aSBoris Brezillon #define MLCISR_DECODER_FAILURE (1 << 6)
10693db446aSBoris Brezillon #define MLCISR_ERRORS ((1 << 4) | (1 << 5))
10793db446aSBoris Brezillon #define MLCISR_ERRORS_DETECTED (1 << 3)
10893db446aSBoris Brezillon #define MLCISR_ECC_READY (1 << 2)
10993db446aSBoris Brezillon #define MLCISR_CONTROLLER_READY (1 << 1)
11093db446aSBoris Brezillon #define MLCISR_NAND_READY (1 << 0)
11193db446aSBoris Brezillon
11293db446aSBoris Brezillon /**********************************************************************
11393db446aSBoris Brezillon * MLC_CEH bit definitions
11493db446aSBoris Brezillon **********************************************************************/
11593db446aSBoris Brezillon #define MLCCEH_NORMAL (1 << 0)
11693db446aSBoris Brezillon
11793db446aSBoris Brezillon struct lpc32xx_nand_cfg_mlc {
11893db446aSBoris Brezillon uint32_t tcea_delay;
11993db446aSBoris Brezillon uint32_t busy_delay;
12093db446aSBoris Brezillon uint32_t nand_ta;
12193db446aSBoris Brezillon uint32_t rd_high;
12293db446aSBoris Brezillon uint32_t rd_low;
12393db446aSBoris Brezillon uint32_t wr_high;
12493db446aSBoris Brezillon uint32_t wr_low;
12593db446aSBoris Brezillon struct mtd_partition *parts;
12693db446aSBoris Brezillon unsigned num_parts;
12793db446aSBoris Brezillon };
12893db446aSBoris Brezillon
lpc32xx_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)12993db446aSBoris Brezillon static int lpc32xx_ooblayout_ecc(struct mtd_info *mtd, int section,
13093db446aSBoris Brezillon struct mtd_oob_region *oobregion)
13193db446aSBoris Brezillon {
13293db446aSBoris Brezillon struct nand_chip *nand_chip = mtd_to_nand(mtd);
13393db446aSBoris Brezillon
13493db446aSBoris Brezillon if (section >= nand_chip->ecc.steps)
13593db446aSBoris Brezillon return -ERANGE;
13693db446aSBoris Brezillon
13793db446aSBoris Brezillon oobregion->offset = ((section + 1) * 16) - nand_chip->ecc.bytes;
13893db446aSBoris Brezillon oobregion->length = nand_chip->ecc.bytes;
13993db446aSBoris Brezillon
14093db446aSBoris Brezillon return 0;
14193db446aSBoris Brezillon }
14293db446aSBoris Brezillon
lpc32xx_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)14393db446aSBoris Brezillon static int lpc32xx_ooblayout_free(struct mtd_info *mtd, int section,
14493db446aSBoris Brezillon struct mtd_oob_region *oobregion)
14593db446aSBoris Brezillon {
14693db446aSBoris Brezillon struct nand_chip *nand_chip = mtd_to_nand(mtd);
14793db446aSBoris Brezillon
14893db446aSBoris Brezillon if (section >= nand_chip->ecc.steps)
14993db446aSBoris Brezillon return -ERANGE;
15093db446aSBoris Brezillon
15193db446aSBoris Brezillon oobregion->offset = 16 * section;
15293db446aSBoris Brezillon oobregion->length = 16 - nand_chip->ecc.bytes;
15393db446aSBoris Brezillon
15493db446aSBoris Brezillon return 0;
15593db446aSBoris Brezillon }
15693db446aSBoris Brezillon
15793db446aSBoris Brezillon static const struct mtd_ooblayout_ops lpc32xx_ooblayout_ops = {
15893db446aSBoris Brezillon .ecc = lpc32xx_ooblayout_ecc,
15993db446aSBoris Brezillon .free = lpc32xx_ooblayout_free,
16093db446aSBoris Brezillon };
16193db446aSBoris Brezillon
16293db446aSBoris Brezillon static struct nand_bbt_descr lpc32xx_nand_bbt = {
16393db446aSBoris Brezillon .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
16493db446aSBoris Brezillon NAND_BBT_WRITE,
16593db446aSBoris Brezillon .pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
16693db446aSBoris Brezillon };
16793db446aSBoris Brezillon
16893db446aSBoris Brezillon static struct nand_bbt_descr lpc32xx_nand_bbt_mirror = {
16993db446aSBoris Brezillon .options = NAND_BBT_ABSPAGE | NAND_BBT_2BIT | NAND_BBT_NO_OOB |
17093db446aSBoris Brezillon NAND_BBT_WRITE,
17193db446aSBoris Brezillon .pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
17293db446aSBoris Brezillon };
17393db446aSBoris Brezillon
17493db446aSBoris Brezillon struct lpc32xx_nand_host {
175c49f3beeSMiquel Raynal struct platform_device *pdev;
17693db446aSBoris Brezillon struct nand_chip nand_chip;
17793db446aSBoris Brezillon struct lpc32xx_mlc_platform_data *pdata;
17893db446aSBoris Brezillon struct clk *clk;
179782e32a9SDmitry Torokhov struct gpio_desc *wp_gpio;
18093db446aSBoris Brezillon void __iomem *io_base;
18193db446aSBoris Brezillon int irq;
18293db446aSBoris Brezillon struct lpc32xx_nand_cfg_mlc *ncfg;
18393db446aSBoris Brezillon struct completion comp_nand;
18493db446aSBoris Brezillon struct completion comp_controller;
18593db446aSBoris Brezillon uint32_t llptr;
18693db446aSBoris Brezillon /*
18793db446aSBoris Brezillon * Physical addresses of ECC buffer, DMA data buffers, OOB data buffer
18893db446aSBoris Brezillon */
18993db446aSBoris Brezillon dma_addr_t oob_buf_phy;
19093db446aSBoris Brezillon /*
19193db446aSBoris Brezillon * Virtual addresses of ECC buffer, DMA data buffers, OOB data buffer
19293db446aSBoris Brezillon */
19393db446aSBoris Brezillon uint8_t *oob_buf;
19493db446aSBoris Brezillon /* Physical address of DMA base address */
19593db446aSBoris Brezillon dma_addr_t io_base_phy;
19693db446aSBoris Brezillon
19793db446aSBoris Brezillon struct completion comp_dma;
19893db446aSBoris Brezillon struct dma_chan *dma_chan;
19993db446aSBoris Brezillon struct dma_slave_config dma_slave_config;
20093db446aSBoris Brezillon struct scatterlist sgl;
20193db446aSBoris Brezillon uint8_t *dma_buf;
20293db446aSBoris Brezillon uint8_t *dummy_buf;
20393db446aSBoris Brezillon int mlcsubpages; /* number of 512bytes-subpages */
20493db446aSBoris Brezillon };
20593db446aSBoris Brezillon
20693db446aSBoris Brezillon /*
20793db446aSBoris Brezillon * Activate/Deactivate DMA Operation:
20893db446aSBoris Brezillon *
20993db446aSBoris Brezillon * Using the PL080 DMA Controller for transferring the 512 byte subpages
21093db446aSBoris Brezillon * instead of doing readl() / writel() in a loop slows it down significantly.
21193db446aSBoris Brezillon * Measurements via getnstimeofday() upon 512 byte subpage reads reveal:
21293db446aSBoris Brezillon *
21393db446aSBoris Brezillon * - readl() of 128 x 32 bits in a loop: ~20us
21493db446aSBoris Brezillon * - DMA read of 512 bytes (32 bit, 4...128 words bursts): ~60us
21593db446aSBoris Brezillon * - DMA read of 512 bytes (32 bit, no bursts): ~100us
21693db446aSBoris Brezillon *
21793db446aSBoris Brezillon * This applies to the transfer itself. In the DMA case: only the
21893db446aSBoris Brezillon * wait_for_completion() (DMA setup _not_ included).
21993db446aSBoris Brezillon *
22093db446aSBoris Brezillon * Note that the 512 bytes subpage transfer is done directly from/to a
22193db446aSBoris Brezillon * FIFO/buffer inside the NAND controller. Most of the time (~400-800us for a
22293db446aSBoris Brezillon * 2048 bytes page) is spent waiting for the NAND IRQ, anyway. (The NAND
22393db446aSBoris Brezillon * controller transferring data between its internal buffer to/from the NAND
22493db446aSBoris Brezillon * chip.)
22593db446aSBoris Brezillon *
22693db446aSBoris Brezillon * Therefore, using the PL080 DMA is disabled by default, for now.
22793db446aSBoris Brezillon *
22893db446aSBoris Brezillon */
22993db446aSBoris Brezillon static int use_dma;
23093db446aSBoris Brezillon
lpc32xx_nand_setup(struct lpc32xx_nand_host * host)23193db446aSBoris Brezillon static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
23293db446aSBoris Brezillon {
23393db446aSBoris Brezillon uint32_t clkrate, tmp;
23493db446aSBoris Brezillon
23593db446aSBoris Brezillon /* Reset MLC controller */
23693db446aSBoris Brezillon writel(MLCCMD_RESET, MLC_CMD(host->io_base));
23793db446aSBoris Brezillon udelay(1000);
23893db446aSBoris Brezillon
23993db446aSBoris Brezillon /* Get base clock for MLC block */
24093db446aSBoris Brezillon clkrate = clk_get_rate(host->clk);
24193db446aSBoris Brezillon if (clkrate == 0)
24293db446aSBoris Brezillon clkrate = 104000000;
24393db446aSBoris Brezillon
24493db446aSBoris Brezillon /* Unlock MLC_ICR
24593db446aSBoris Brezillon * (among others, will be locked again automatically) */
24693db446aSBoris Brezillon writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
24793db446aSBoris Brezillon
24893db446aSBoris Brezillon /* Configure MLC Controller: Large Block, 5 Byte Address */
24993db446aSBoris Brezillon tmp = MLCICR_LARGEBLOCK | MLCICR_LONGADDR;
25093db446aSBoris Brezillon writel(tmp, MLC_ICR(host->io_base));
25193db446aSBoris Brezillon
25293db446aSBoris Brezillon /* Unlock MLC_TIME_REG
25393db446aSBoris Brezillon * (among others, will be locked again automatically) */
25493db446aSBoris Brezillon writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
25593db446aSBoris Brezillon
25693db446aSBoris Brezillon /* Compute clock setup values, see LPC and NAND manual */
25793db446aSBoris Brezillon tmp = 0;
25893db446aSBoris Brezillon tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
25993db446aSBoris Brezillon tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
26093db446aSBoris Brezillon tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
26193db446aSBoris Brezillon tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
26293db446aSBoris Brezillon tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
26393db446aSBoris Brezillon tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
26493db446aSBoris Brezillon tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
26593db446aSBoris Brezillon writel(tmp, MLC_TIME_REG(host->io_base));
26693db446aSBoris Brezillon
26793db446aSBoris Brezillon /* Enable IRQ for CONTROLLER_READY and NAND_READY */
26893db446aSBoris Brezillon writeb(MLCIRQ_CONTROLLER_READY | MLCIRQ_NAND_READY,
26993db446aSBoris Brezillon MLC_IRQ_MR(host->io_base));
27093db446aSBoris Brezillon
27193db446aSBoris Brezillon /* Normal nCE operation: nCE controlled by controller */
27293db446aSBoris Brezillon writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
27393db446aSBoris Brezillon }
27493db446aSBoris Brezillon
27593db446aSBoris Brezillon /*
27693db446aSBoris Brezillon * Hardware specific access to control lines
27793db446aSBoris Brezillon */
lpc32xx_nand_cmd_ctrl(struct nand_chip * nand_chip,int cmd,unsigned int ctrl)2780f808c16SBoris Brezillon static void lpc32xx_nand_cmd_ctrl(struct nand_chip *nand_chip, int cmd,
27993db446aSBoris Brezillon unsigned int ctrl)
28093db446aSBoris Brezillon {
28193db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
28293db446aSBoris Brezillon
28393db446aSBoris Brezillon if (cmd != NAND_CMD_NONE) {
28493db446aSBoris Brezillon if (ctrl & NAND_CLE)
28593db446aSBoris Brezillon writel(cmd, MLC_CMD(host->io_base));
28693db446aSBoris Brezillon else
28793db446aSBoris Brezillon writel(cmd, MLC_ADDR(host->io_base));
28893db446aSBoris Brezillon }
28993db446aSBoris Brezillon }
29093db446aSBoris Brezillon
29193db446aSBoris Brezillon /*
29293db446aSBoris Brezillon * Read Device Ready (NAND device _and_ controller ready)
29393db446aSBoris Brezillon */
lpc32xx_nand_device_ready(struct nand_chip * nand_chip)29450a487e7SBoris Brezillon static int lpc32xx_nand_device_ready(struct nand_chip *nand_chip)
29593db446aSBoris Brezillon {
29693db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
29793db446aSBoris Brezillon
29893db446aSBoris Brezillon if ((readb(MLC_ISR(host->io_base)) &
29993db446aSBoris Brezillon (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY)) ==
30093db446aSBoris Brezillon (MLCISR_CONTROLLER_READY | MLCISR_NAND_READY))
30193db446aSBoris Brezillon return 1;
30293db446aSBoris Brezillon
30393db446aSBoris Brezillon return 0;
30493db446aSBoris Brezillon }
30593db446aSBoris Brezillon
lpc3xxx_nand_irq(int irq,void * data)306347b8288SArnd Bergmann static irqreturn_t lpc3xxx_nand_irq(int irq, void *data)
30793db446aSBoris Brezillon {
308347b8288SArnd Bergmann struct lpc32xx_nand_host *host = data;
30993db446aSBoris Brezillon uint8_t sr;
31093db446aSBoris Brezillon
31193db446aSBoris Brezillon /* Clear interrupt flag by reading status */
31293db446aSBoris Brezillon sr = readb(MLC_IRQ_SR(host->io_base));
31393db446aSBoris Brezillon if (sr & MLCIRQ_NAND_READY)
31493db446aSBoris Brezillon complete(&host->comp_nand);
31593db446aSBoris Brezillon if (sr & MLCIRQ_CONTROLLER_READY)
31693db446aSBoris Brezillon complete(&host->comp_controller);
31793db446aSBoris Brezillon
31893db446aSBoris Brezillon return IRQ_HANDLED;
31993db446aSBoris Brezillon }
32093db446aSBoris Brezillon
lpc32xx_waitfunc_nand(struct nand_chip * chip)321f1d46942SBoris Brezillon static int lpc32xx_waitfunc_nand(struct nand_chip *chip)
32293db446aSBoris Brezillon {
323f1d46942SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
32493db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
32593db446aSBoris Brezillon
32693db446aSBoris Brezillon if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
32793db446aSBoris Brezillon goto exit;
32893db446aSBoris Brezillon
32993db446aSBoris Brezillon wait_for_completion(&host->comp_nand);
33093db446aSBoris Brezillon
33193db446aSBoris Brezillon while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
33293db446aSBoris Brezillon /* Seems to be delayed sometimes by controller */
33393db446aSBoris Brezillon dev_dbg(&mtd->dev, "Warning: NAND not ready.\n");
33493db446aSBoris Brezillon cpu_relax();
33593db446aSBoris Brezillon }
33693db446aSBoris Brezillon
33793db446aSBoris Brezillon exit:
33893db446aSBoris Brezillon return NAND_STATUS_READY;
33993db446aSBoris Brezillon }
34093db446aSBoris Brezillon
lpc32xx_waitfunc_controller(struct nand_chip * chip)341f1d46942SBoris Brezillon static int lpc32xx_waitfunc_controller(struct nand_chip *chip)
34293db446aSBoris Brezillon {
343f1d46942SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
34493db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
34593db446aSBoris Brezillon
34693db446aSBoris Brezillon if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
34793db446aSBoris Brezillon goto exit;
34893db446aSBoris Brezillon
34993db446aSBoris Brezillon wait_for_completion(&host->comp_controller);
35093db446aSBoris Brezillon
35193db446aSBoris Brezillon while (!(readb(MLC_ISR(host->io_base)) &
35293db446aSBoris Brezillon MLCISR_CONTROLLER_READY)) {
35393db446aSBoris Brezillon dev_dbg(&mtd->dev, "Warning: Controller not ready.\n");
35493db446aSBoris Brezillon cpu_relax();
35593db446aSBoris Brezillon }
35693db446aSBoris Brezillon
35793db446aSBoris Brezillon exit:
35893db446aSBoris Brezillon return NAND_STATUS_READY;
35993db446aSBoris Brezillon }
36093db446aSBoris Brezillon
lpc32xx_waitfunc(struct nand_chip * chip)361f1d46942SBoris Brezillon static int lpc32xx_waitfunc(struct nand_chip *chip)
36293db446aSBoris Brezillon {
363f1d46942SBoris Brezillon lpc32xx_waitfunc_nand(chip);
364f1d46942SBoris Brezillon lpc32xx_waitfunc_controller(chip);
36593db446aSBoris Brezillon
36693db446aSBoris Brezillon return NAND_STATUS_READY;
36793db446aSBoris Brezillon }
36893db446aSBoris Brezillon
36993db446aSBoris Brezillon /*
37093db446aSBoris Brezillon * Enable NAND write protect
37193db446aSBoris Brezillon */
lpc32xx_wp_enable(struct lpc32xx_nand_host * host)37293db446aSBoris Brezillon static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
37393db446aSBoris Brezillon {
374782e32a9SDmitry Torokhov if (host->wp_gpio)
375782e32a9SDmitry Torokhov gpiod_set_value_cansleep(host->wp_gpio, 1);
37693db446aSBoris Brezillon }
37793db446aSBoris Brezillon
37893db446aSBoris Brezillon /*
37993db446aSBoris Brezillon * Disable NAND write protect
38093db446aSBoris Brezillon */
lpc32xx_wp_disable(struct lpc32xx_nand_host * host)38193db446aSBoris Brezillon static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
38293db446aSBoris Brezillon {
383782e32a9SDmitry Torokhov if (host->wp_gpio)
384782e32a9SDmitry Torokhov gpiod_set_value_cansleep(host->wp_gpio, 0);
38593db446aSBoris Brezillon }
38693db446aSBoris Brezillon
lpc32xx_dma_complete_func(void * completion)38793db446aSBoris Brezillon static void lpc32xx_dma_complete_func(void *completion)
38893db446aSBoris Brezillon {
38993db446aSBoris Brezillon complete(completion);
39093db446aSBoris Brezillon }
39193db446aSBoris Brezillon
lpc32xx_xmit_dma(struct mtd_info * mtd,void * mem,int len,enum dma_transfer_direction dir)39293db446aSBoris Brezillon static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
39393db446aSBoris Brezillon enum dma_transfer_direction dir)
39493db446aSBoris Brezillon {
39593db446aSBoris Brezillon struct nand_chip *chip = mtd_to_nand(mtd);
39693db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
39793db446aSBoris Brezillon struct dma_async_tx_descriptor *desc;
39893db446aSBoris Brezillon int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
39993db446aSBoris Brezillon int res;
40093db446aSBoris Brezillon
40193db446aSBoris Brezillon sg_init_one(&host->sgl, mem, len);
40293db446aSBoris Brezillon
40393db446aSBoris Brezillon res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
40493db446aSBoris Brezillon DMA_BIDIRECTIONAL);
40593db446aSBoris Brezillon if (res != 1) {
40693db446aSBoris Brezillon dev_err(mtd->dev.parent, "Failed to map sg list\n");
40793db446aSBoris Brezillon return -ENXIO;
40893db446aSBoris Brezillon }
40993db446aSBoris Brezillon desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
41093db446aSBoris Brezillon flags);
41193db446aSBoris Brezillon if (!desc) {
41293db446aSBoris Brezillon dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
41393db446aSBoris Brezillon goto out1;
41493db446aSBoris Brezillon }
41593db446aSBoris Brezillon
41693db446aSBoris Brezillon init_completion(&host->comp_dma);
41793db446aSBoris Brezillon desc->callback = lpc32xx_dma_complete_func;
41893db446aSBoris Brezillon desc->callback_param = &host->comp_dma;
41993db446aSBoris Brezillon
42093db446aSBoris Brezillon dmaengine_submit(desc);
42193db446aSBoris Brezillon dma_async_issue_pending(host->dma_chan);
42293db446aSBoris Brezillon
42393db446aSBoris Brezillon wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
42493db446aSBoris Brezillon
42593db446aSBoris Brezillon dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
42693db446aSBoris Brezillon DMA_BIDIRECTIONAL);
42793db446aSBoris Brezillon return 0;
42893db446aSBoris Brezillon out1:
42993db446aSBoris Brezillon dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
43093db446aSBoris Brezillon DMA_BIDIRECTIONAL);
43193db446aSBoris Brezillon return -ENXIO;
43293db446aSBoris Brezillon }
43393db446aSBoris Brezillon
lpc32xx_read_page(struct nand_chip * chip,uint8_t * buf,int oob_required,int page)434b9761687SBoris Brezillon static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
435b9761687SBoris Brezillon int oob_required, int page)
43693db446aSBoris Brezillon {
437b9761687SBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
43893db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
43993db446aSBoris Brezillon int i, j;
44093db446aSBoris Brezillon uint8_t *oobbuf = chip->oob_poi;
44193db446aSBoris Brezillon uint32_t mlc_isr;
44293db446aSBoris Brezillon int res;
44393db446aSBoris Brezillon uint8_t *dma_buf;
44493db446aSBoris Brezillon bool dma_mapped;
44593db446aSBoris Brezillon
44693db446aSBoris Brezillon if ((void *)buf <= high_memory) {
44793db446aSBoris Brezillon dma_buf = buf;
44893db446aSBoris Brezillon dma_mapped = true;
44993db446aSBoris Brezillon } else {
45093db446aSBoris Brezillon dma_buf = host->dma_buf;
45193db446aSBoris Brezillon dma_mapped = false;
45293db446aSBoris Brezillon }
45393db446aSBoris Brezillon
45493db446aSBoris Brezillon /* Writing Command and Address */
45593db446aSBoris Brezillon nand_read_page_op(chip, page, 0, NULL, 0);
45693db446aSBoris Brezillon
45793db446aSBoris Brezillon /* For all sub-pages */
45893db446aSBoris Brezillon for (i = 0; i < host->mlcsubpages; i++) {
45993db446aSBoris Brezillon /* Start Auto Decode Command */
46093db446aSBoris Brezillon writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
46193db446aSBoris Brezillon
46293db446aSBoris Brezillon /* Wait for Controller Ready */
463f1d46942SBoris Brezillon lpc32xx_waitfunc_controller(chip);
46493db446aSBoris Brezillon
46593db446aSBoris Brezillon /* Check ECC Error status */
46693db446aSBoris Brezillon mlc_isr = readl(MLC_ISR(host->io_base));
46793db446aSBoris Brezillon if (mlc_isr & MLCISR_DECODER_FAILURE) {
46893db446aSBoris Brezillon mtd->ecc_stats.failed++;
46993db446aSBoris Brezillon dev_warn(&mtd->dev, "%s: DECODER_FAILURE\n", __func__);
47093db446aSBoris Brezillon } else if (mlc_isr & MLCISR_ERRORS_DETECTED) {
47193db446aSBoris Brezillon mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;
47293db446aSBoris Brezillon }
47393db446aSBoris Brezillon
47493db446aSBoris Brezillon /* Read 512 + 16 Bytes */
47593db446aSBoris Brezillon if (use_dma) {
47693db446aSBoris Brezillon res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
47793db446aSBoris Brezillon DMA_DEV_TO_MEM);
47893db446aSBoris Brezillon if (res)
47993db446aSBoris Brezillon return res;
48093db446aSBoris Brezillon } else {
48193db446aSBoris Brezillon for (j = 0; j < (512 >> 2); j++) {
48293db446aSBoris Brezillon *((uint32_t *)(buf)) =
48393db446aSBoris Brezillon readl(MLC_BUFF(host->io_base));
48493db446aSBoris Brezillon buf += 4;
48593db446aSBoris Brezillon }
48693db446aSBoris Brezillon }
48793db446aSBoris Brezillon for (j = 0; j < (16 >> 2); j++) {
48893db446aSBoris Brezillon *((uint32_t *)(oobbuf)) =
48993db446aSBoris Brezillon readl(MLC_BUFF(host->io_base));
49093db446aSBoris Brezillon oobbuf += 4;
49193db446aSBoris Brezillon }
49293db446aSBoris Brezillon }
49393db446aSBoris Brezillon
49493db446aSBoris Brezillon if (use_dma && !dma_mapped)
49593db446aSBoris Brezillon memcpy(buf, dma_buf, mtd->writesize);
49693db446aSBoris Brezillon
49793db446aSBoris Brezillon return 0;
49893db446aSBoris Brezillon }
49993db446aSBoris Brezillon
lpc32xx_write_page_lowlevel(struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)500767eb6fbSBoris Brezillon static int lpc32xx_write_page_lowlevel(struct nand_chip *chip,
50193db446aSBoris Brezillon const uint8_t *buf, int oob_required,
50293db446aSBoris Brezillon int page)
50393db446aSBoris Brezillon {
504767eb6fbSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(chip);
50593db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
50693db446aSBoris Brezillon const uint8_t *oobbuf = chip->oob_poi;
50793db446aSBoris Brezillon uint8_t *dma_buf = (uint8_t *)buf;
50893db446aSBoris Brezillon int res;
50993db446aSBoris Brezillon int i, j;
51093db446aSBoris Brezillon
51193db446aSBoris Brezillon if (use_dma && (void *)buf >= high_memory) {
51293db446aSBoris Brezillon dma_buf = host->dma_buf;
51393db446aSBoris Brezillon memcpy(dma_buf, buf, mtd->writesize);
51493db446aSBoris Brezillon }
51593db446aSBoris Brezillon
51693db446aSBoris Brezillon nand_prog_page_begin_op(chip, page, 0, NULL, 0);
51793db446aSBoris Brezillon
51893db446aSBoris Brezillon for (i = 0; i < host->mlcsubpages; i++) {
51993db446aSBoris Brezillon /* Start Encode */
52093db446aSBoris Brezillon writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
52193db446aSBoris Brezillon
52293db446aSBoris Brezillon /* Write 512 + 6 Bytes to Buffer */
52393db446aSBoris Brezillon if (use_dma) {
52493db446aSBoris Brezillon res = lpc32xx_xmit_dma(mtd, dma_buf + i * 512, 512,
52593db446aSBoris Brezillon DMA_MEM_TO_DEV);
52693db446aSBoris Brezillon if (res)
52793db446aSBoris Brezillon return res;
52893db446aSBoris Brezillon } else {
52993db446aSBoris Brezillon for (j = 0; j < (512 >> 2); j++) {
53093db446aSBoris Brezillon writel(*((uint32_t *)(buf)),
53193db446aSBoris Brezillon MLC_BUFF(host->io_base));
53293db446aSBoris Brezillon buf += 4;
53393db446aSBoris Brezillon }
53493db446aSBoris Brezillon }
53593db446aSBoris Brezillon writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
53693db446aSBoris Brezillon oobbuf += 4;
53793db446aSBoris Brezillon writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
53893db446aSBoris Brezillon oobbuf += 12;
53993db446aSBoris Brezillon
54093db446aSBoris Brezillon /* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */
54193db446aSBoris Brezillon writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
54293db446aSBoris Brezillon
54393db446aSBoris Brezillon /* Wait for Controller Ready */
544f1d46942SBoris Brezillon lpc32xx_waitfunc_controller(chip);
54593db446aSBoris Brezillon }
54693db446aSBoris Brezillon
54793db446aSBoris Brezillon return nand_prog_page_end_op(chip);
54893db446aSBoris Brezillon }
54993db446aSBoris Brezillon
lpc32xx_read_oob(struct nand_chip * chip,int page)550b9761687SBoris Brezillon static int lpc32xx_read_oob(struct nand_chip *chip, int page)
55193db446aSBoris Brezillon {
55293db446aSBoris Brezillon struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
55393db446aSBoris Brezillon
55493db446aSBoris Brezillon /* Read whole page - necessary with MLC controller! */
555b9761687SBoris Brezillon lpc32xx_read_page(chip, host->dummy_buf, 1, page);
55693db446aSBoris Brezillon
55793db446aSBoris Brezillon return 0;
55893db446aSBoris Brezillon }
55993db446aSBoris Brezillon
lpc32xx_write_oob(struct nand_chip * chip,int page)560767eb6fbSBoris Brezillon static int lpc32xx_write_oob(struct nand_chip *chip, int page)
56193db446aSBoris Brezillon {
56293db446aSBoris Brezillon /* None, write_oob conflicts with the automatic LPC MLC ECC decoder! */
56393db446aSBoris Brezillon return 0;
56493db446aSBoris Brezillon }
56593db446aSBoris Brezillon
56693db446aSBoris Brezillon /* Prepares MLC for transfers with H/W ECC enabled: always enabled anyway */
lpc32xx_ecc_enable(struct nand_chip * chip,int mode)567ec47636cSBoris Brezillon static void lpc32xx_ecc_enable(struct nand_chip *chip, int mode)
56893db446aSBoris Brezillon {
56993db446aSBoris Brezillon /* Always enabled! */
57093db446aSBoris Brezillon }
57193db446aSBoris Brezillon
lpc32xx_dma_setup(struct lpc32xx_nand_host * host)57293db446aSBoris Brezillon static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
57393db446aSBoris Brezillon {
57493db446aSBoris Brezillon struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
57593db446aSBoris Brezillon dma_cap_mask_t mask;
57693db446aSBoris Brezillon
57747821186SPiotr Wojtaszczyk host->dma_chan = dma_request_chan(mtd->dev.parent, "rx-tx");
578*a503f91aSPiotr Wojtaszczyk if (IS_ERR(host->dma_chan)) {
57947821186SPiotr Wojtaszczyk /* fallback to request using platform data */
58093db446aSBoris Brezillon if (!host->pdata || !host->pdata->dma_filter) {
58193db446aSBoris Brezillon dev_err(mtd->dev.parent, "no DMA platform data\n");
58293db446aSBoris Brezillon return -ENOENT;
58393db446aSBoris Brezillon }
58493db446aSBoris Brezillon
58593db446aSBoris Brezillon dma_cap_zero(mask);
58693db446aSBoris Brezillon dma_cap_set(DMA_SLAVE, mask);
58747821186SPiotr Wojtaszczyk host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter, "nand-mlc");
58847821186SPiotr Wojtaszczyk
58993db446aSBoris Brezillon if (!host->dma_chan) {
59093db446aSBoris Brezillon dev_err(mtd->dev.parent, "Failed to request DMA channel\n");
59193db446aSBoris Brezillon return -EBUSY;
59293db446aSBoris Brezillon }
59347821186SPiotr Wojtaszczyk }
59493db446aSBoris Brezillon
59593db446aSBoris Brezillon /*
59693db446aSBoris Brezillon * Set direction to a sensible value even if the dmaengine driver
59793db446aSBoris Brezillon * should ignore it. With the default (DMA_MEM_TO_MEM), the amba-pl08x
59893db446aSBoris Brezillon * driver criticizes it as "alien transfer direction".
59993db446aSBoris Brezillon */
60093db446aSBoris Brezillon host->dma_slave_config.direction = DMA_DEV_TO_MEM;
60193db446aSBoris Brezillon host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
60293db446aSBoris Brezillon host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
60393db446aSBoris Brezillon host->dma_slave_config.src_maxburst = 128;
60493db446aSBoris Brezillon host->dma_slave_config.dst_maxburst = 128;
60593db446aSBoris Brezillon /* DMA controller does flow control: */
60693db446aSBoris Brezillon host->dma_slave_config.device_fc = false;
60793db446aSBoris Brezillon host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
60893db446aSBoris Brezillon host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
60993db446aSBoris Brezillon if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
61093db446aSBoris Brezillon dev_err(mtd->dev.parent, "Failed to setup DMA slave\n");
61193db446aSBoris Brezillon goto out1;
61293db446aSBoris Brezillon }
61393db446aSBoris Brezillon
61493db446aSBoris Brezillon return 0;
61593db446aSBoris Brezillon out1:
61693db446aSBoris Brezillon dma_release_channel(host->dma_chan);
61793db446aSBoris Brezillon return -ENXIO;
61893db446aSBoris Brezillon }
61993db446aSBoris Brezillon
lpc32xx_parse_dt(struct device * dev)62093db446aSBoris Brezillon static struct lpc32xx_nand_cfg_mlc *lpc32xx_parse_dt(struct device *dev)
62193db446aSBoris Brezillon {
62293db446aSBoris Brezillon struct lpc32xx_nand_cfg_mlc *ncfg;
62393db446aSBoris Brezillon struct device_node *np = dev->of_node;
62493db446aSBoris Brezillon
62593db446aSBoris Brezillon ncfg = devm_kzalloc(dev, sizeof(*ncfg), GFP_KERNEL);
62693db446aSBoris Brezillon if (!ncfg)
62793db446aSBoris Brezillon return NULL;
62893db446aSBoris Brezillon
62993db446aSBoris Brezillon of_property_read_u32(np, "nxp,tcea-delay", &ncfg->tcea_delay);
63093db446aSBoris Brezillon of_property_read_u32(np, "nxp,busy-delay", &ncfg->busy_delay);
63193db446aSBoris Brezillon of_property_read_u32(np, "nxp,nand-ta", &ncfg->nand_ta);
63293db446aSBoris Brezillon of_property_read_u32(np, "nxp,rd-high", &ncfg->rd_high);
63393db446aSBoris Brezillon of_property_read_u32(np, "nxp,rd-low", &ncfg->rd_low);
63493db446aSBoris Brezillon of_property_read_u32(np, "nxp,wr-high", &ncfg->wr_high);
63593db446aSBoris Brezillon of_property_read_u32(np, "nxp,wr-low", &ncfg->wr_low);
63693db446aSBoris Brezillon
63793db446aSBoris Brezillon if (!ncfg->tcea_delay || !ncfg->busy_delay || !ncfg->nand_ta ||
63893db446aSBoris Brezillon !ncfg->rd_high || !ncfg->rd_low || !ncfg->wr_high ||
63993db446aSBoris Brezillon !ncfg->wr_low) {
64093db446aSBoris Brezillon dev_err(dev, "chip parameters not specified correctly\n");
64193db446aSBoris Brezillon return NULL;
64293db446aSBoris Brezillon }
64393db446aSBoris Brezillon
64493db446aSBoris Brezillon return ncfg;
64593db446aSBoris Brezillon }
64693db446aSBoris Brezillon
lpc32xx_nand_attach_chip(struct nand_chip * chip)647c49f3beeSMiquel Raynal static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
648c49f3beeSMiquel Raynal {
649c49f3beeSMiquel Raynal struct mtd_info *mtd = nand_to_mtd(chip);
650c49f3beeSMiquel Raynal struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
651c49f3beeSMiquel Raynal struct device *dev = &host->pdev->dev;
652c49f3beeSMiquel Raynal
6532dbd8382SMiquel Raynal if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
6542dbd8382SMiquel Raynal return 0;
6552dbd8382SMiquel Raynal
656c49f3beeSMiquel Raynal host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
657c49f3beeSMiquel Raynal if (!host->dma_buf)
658c49f3beeSMiquel Raynal return -ENOMEM;
659c49f3beeSMiquel Raynal
660c49f3beeSMiquel Raynal host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
661c49f3beeSMiquel Raynal if (!host->dummy_buf)
662c49f3beeSMiquel Raynal return -ENOMEM;
663c49f3beeSMiquel Raynal
664c49f3beeSMiquel Raynal chip->ecc.size = 512;
6652dbd8382SMiquel Raynal chip->ecc.hwctl = lpc32xx_ecc_enable;
6662dbd8382SMiquel Raynal chip->ecc.read_page_raw = lpc32xx_read_page;
6672dbd8382SMiquel Raynal chip->ecc.read_page = lpc32xx_read_page;
6682dbd8382SMiquel Raynal chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
6692dbd8382SMiquel Raynal chip->ecc.write_page = lpc32xx_write_page_lowlevel;
6702dbd8382SMiquel Raynal chip->ecc.write_oob = lpc32xx_write_oob;
6712dbd8382SMiquel Raynal chip->ecc.read_oob = lpc32xx_read_oob;
6722dbd8382SMiquel Raynal chip->ecc.strength = 4;
6732dbd8382SMiquel Raynal chip->ecc.bytes = 10;
6742dbd8382SMiquel Raynal
675c49f3beeSMiquel Raynal mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops);
676c49f3beeSMiquel Raynal host->mlcsubpages = mtd->writesize / 512;
677c49f3beeSMiquel Raynal
678c49f3beeSMiquel Raynal return 0;
679c49f3beeSMiquel Raynal }
680c49f3beeSMiquel Raynal
681c49f3beeSMiquel Raynal static const struct nand_controller_ops lpc32xx_nand_controller_ops = {
682c49f3beeSMiquel Raynal .attach_chip = lpc32xx_nand_attach_chip,
683c49f3beeSMiquel Raynal };
684c49f3beeSMiquel Raynal
68593db446aSBoris Brezillon /*
68693db446aSBoris Brezillon * Probe for NAND controller
68793db446aSBoris Brezillon */
lpc32xx_nand_probe(struct platform_device * pdev)68893db446aSBoris Brezillon static int lpc32xx_nand_probe(struct platform_device *pdev)
68993db446aSBoris Brezillon {
69093db446aSBoris Brezillon struct lpc32xx_nand_host *host;
69193db446aSBoris Brezillon struct mtd_info *mtd;
69293db446aSBoris Brezillon struct nand_chip *nand_chip;
69393db446aSBoris Brezillon struct resource *rc;
69493db446aSBoris Brezillon int res;
69593db446aSBoris Brezillon
69693db446aSBoris Brezillon /* Allocate memory for the device structure (and zero it) */
69793db446aSBoris Brezillon host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
69893db446aSBoris Brezillon if (!host)
69993db446aSBoris Brezillon return -ENOMEM;
70093db446aSBoris Brezillon
701c49f3beeSMiquel Raynal host->pdev = pdev;
702c49f3beeSMiquel Raynal
7039cd9dda8SYangtao Li host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
70493db446aSBoris Brezillon if (IS_ERR(host->io_base))
70593db446aSBoris Brezillon return PTR_ERR(host->io_base);
70693db446aSBoris Brezillon
70793db446aSBoris Brezillon host->io_base_phy = rc->start;
70893db446aSBoris Brezillon
70993db446aSBoris Brezillon nand_chip = &host->nand_chip;
71093db446aSBoris Brezillon mtd = nand_to_mtd(nand_chip);
71193db446aSBoris Brezillon if (pdev->dev.of_node)
71293db446aSBoris Brezillon host->ncfg = lpc32xx_parse_dt(&pdev->dev);
71393db446aSBoris Brezillon if (!host->ncfg) {
71493db446aSBoris Brezillon dev_err(&pdev->dev,
71593db446aSBoris Brezillon "Missing or bad NAND config from device tree\n");
71693db446aSBoris Brezillon return -ENOENT;
71793db446aSBoris Brezillon }
718782e32a9SDmitry Torokhov
719782e32a9SDmitry Torokhov /* Start with WP disabled, if available */
720782e32a9SDmitry Torokhov host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
721782e32a9SDmitry Torokhov res = PTR_ERR_OR_ZERO(host->wp_gpio);
722782e32a9SDmitry Torokhov if (res) {
723782e32a9SDmitry Torokhov if (res != -EPROBE_DEFER)
724782e32a9SDmitry Torokhov dev_err(&pdev->dev, "WP GPIO is not available: %d\n",
725782e32a9SDmitry Torokhov res);
726782e32a9SDmitry Torokhov return res;
72793db446aSBoris Brezillon }
728782e32a9SDmitry Torokhov
729782e32a9SDmitry Torokhov gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
73093db446aSBoris Brezillon
73193db446aSBoris Brezillon host->pdata = dev_get_platdata(&pdev->dev);
73293db446aSBoris Brezillon
73393db446aSBoris Brezillon /* link the private data structures */
73493db446aSBoris Brezillon nand_set_controller_data(nand_chip, host);
73593db446aSBoris Brezillon nand_set_flash_node(nand_chip, pdev->dev.of_node);
73693db446aSBoris Brezillon mtd->dev.parent = &pdev->dev;
73793db446aSBoris Brezillon
73893db446aSBoris Brezillon /* Get NAND clock */
73993db446aSBoris Brezillon host->clk = clk_get(&pdev->dev, NULL);
74093db446aSBoris Brezillon if (IS_ERR(host->clk)) {
74193db446aSBoris Brezillon dev_err(&pdev->dev, "Clock initialization failure\n");
74293db446aSBoris Brezillon res = -ENOENT;
743ed64cb1dSMiquel Raynal goto free_gpio;
74493db446aSBoris Brezillon }
74593db446aSBoris Brezillon res = clk_prepare_enable(host->clk);
74693db446aSBoris Brezillon if (res)
747ed64cb1dSMiquel Raynal goto put_clk;
74893db446aSBoris Brezillon
749bf6065c6SBoris Brezillon nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
7508395b753SBoris Brezillon nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
7513cece3abSBoris Brezillon nand_chip->legacy.chip_delay = 25; /* us */
75282fc5099SBoris Brezillon nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
75382fc5099SBoris Brezillon nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
75493db446aSBoris Brezillon
75593db446aSBoris Brezillon /* Init NAND controller */
75693db446aSBoris Brezillon lpc32xx_nand_setup(host);
75793db446aSBoris Brezillon
75893db446aSBoris Brezillon platform_set_drvdata(pdev, host);
75993db446aSBoris Brezillon
76093db446aSBoris Brezillon /* Initialize function pointers */
7618395b753SBoris Brezillon nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
76293db446aSBoris Brezillon
76393db446aSBoris Brezillon nand_chip->options = NAND_NO_SUBPAGE_WRITE;
76493db446aSBoris Brezillon nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
76593db446aSBoris Brezillon nand_chip->bbt_td = &lpc32xx_nand_bbt;
76693db446aSBoris Brezillon nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
76793db446aSBoris Brezillon
76893db446aSBoris Brezillon if (use_dma) {
76993db446aSBoris Brezillon res = lpc32xx_dma_setup(host);
77093db446aSBoris Brezillon if (res) {
77193db446aSBoris Brezillon res = -EIO;
772ed64cb1dSMiquel Raynal goto unprepare_clk;
77393db446aSBoris Brezillon }
77493db446aSBoris Brezillon }
77593db446aSBoris Brezillon
77693db446aSBoris Brezillon /* initially clear interrupt status */
77793db446aSBoris Brezillon readb(MLC_IRQ_SR(host->io_base));
77893db446aSBoris Brezillon
77993db446aSBoris Brezillon init_completion(&host->comp_nand);
78093db446aSBoris Brezillon init_completion(&host->comp_controller);
78193db446aSBoris Brezillon
78293db446aSBoris Brezillon host->irq = platform_get_irq(pdev, 0);
78393db446aSBoris Brezillon if (host->irq < 0) {
78493db446aSBoris Brezillon res = -EINVAL;
785ed64cb1dSMiquel Raynal goto release_dma_chan;
78693db446aSBoris Brezillon }
78793db446aSBoris Brezillon
788347b8288SArnd Bergmann if (request_irq(host->irq, &lpc3xxx_nand_irq,
78993db446aSBoris Brezillon IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
79093db446aSBoris Brezillon dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
79193db446aSBoris Brezillon res = -ENXIO;
792ed64cb1dSMiquel Raynal goto release_dma_chan;
79393db446aSBoris Brezillon }
79493db446aSBoris Brezillon
79593db446aSBoris Brezillon /*
796c49f3beeSMiquel Raynal * Scan to find existence of the device and get the type of NAND device:
797c49f3beeSMiquel Raynal * SMALL block or LARGE block.
79893db446aSBoris Brezillon */
7997b6a9b28SBoris Brezillon nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
80000ad378fSBoris Brezillon res = nand_scan(nand_chip, 1);
80193db446aSBoris Brezillon if (res)
802ed64cb1dSMiquel Raynal goto free_irq;
80393db446aSBoris Brezillon
80493db446aSBoris Brezillon mtd->name = DRV_NAME;
80593db446aSBoris Brezillon
80693db446aSBoris Brezillon res = mtd_device_register(mtd, host->ncfg->parts,
80793db446aSBoris Brezillon host->ncfg->num_parts);
808ed64cb1dSMiquel Raynal if (res)
809838c07b0SMiquel Raynal goto cleanup_nand;
81093db446aSBoris Brezillon
811ed64cb1dSMiquel Raynal return 0;
812ed64cb1dSMiquel Raynal
813838c07b0SMiquel Raynal cleanup_nand:
814838c07b0SMiquel Raynal nand_cleanup(nand_chip);
815ed64cb1dSMiquel Raynal free_irq:
81693db446aSBoris Brezillon free_irq(host->irq, host);
817ed64cb1dSMiquel Raynal release_dma_chan:
81893db446aSBoris Brezillon if (use_dma)
81993db446aSBoris Brezillon dma_release_channel(host->dma_chan);
820ed64cb1dSMiquel Raynal unprepare_clk:
82193db446aSBoris Brezillon clk_disable_unprepare(host->clk);
822ed64cb1dSMiquel Raynal put_clk:
82393db446aSBoris Brezillon clk_put(host->clk);
824ed64cb1dSMiquel Raynal free_gpio:
82593db446aSBoris Brezillon lpc32xx_wp_enable(host);
826782e32a9SDmitry Torokhov gpiod_put(host->wp_gpio);
82793db446aSBoris Brezillon
82893db446aSBoris Brezillon return res;
82993db446aSBoris Brezillon }
83093db446aSBoris Brezillon
83193db446aSBoris Brezillon /*
83293db446aSBoris Brezillon * Remove NAND device
83393db446aSBoris Brezillon */
lpc32xx_nand_remove(struct platform_device * pdev)834ec185b18SUwe Kleine-König static void lpc32xx_nand_remove(struct platform_device *pdev)
83593db446aSBoris Brezillon {
83693db446aSBoris Brezillon struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
8375f3bce3aSMiquel Raynal struct nand_chip *chip = &host->nand_chip;
8385f3bce3aSMiquel Raynal int ret;
83993db446aSBoris Brezillon
8405f3bce3aSMiquel Raynal ret = mtd_device_unregister(nand_to_mtd(chip));
8415f3bce3aSMiquel Raynal WARN_ON(ret);
8425f3bce3aSMiquel Raynal nand_cleanup(chip);
8435f3bce3aSMiquel Raynal
84493db446aSBoris Brezillon free_irq(host->irq, host);
84593db446aSBoris Brezillon if (use_dma)
84693db446aSBoris Brezillon dma_release_channel(host->dma_chan);
84793db446aSBoris Brezillon
84893db446aSBoris Brezillon clk_disable_unprepare(host->clk);
84993db446aSBoris Brezillon clk_put(host->clk);
85093db446aSBoris Brezillon
85193db446aSBoris Brezillon lpc32xx_wp_enable(host);
852782e32a9SDmitry Torokhov gpiod_put(host->wp_gpio);
85393db446aSBoris Brezillon }
85493db446aSBoris Brezillon
lpc32xx_nand_resume(struct platform_device * pdev)85593db446aSBoris Brezillon static int lpc32xx_nand_resume(struct platform_device *pdev)
85693db446aSBoris Brezillon {
85793db446aSBoris Brezillon struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
85893db446aSBoris Brezillon int ret;
85993db446aSBoris Brezillon
86093db446aSBoris Brezillon /* Re-enable NAND clock */
86193db446aSBoris Brezillon ret = clk_prepare_enable(host->clk);
86293db446aSBoris Brezillon if (ret)
86393db446aSBoris Brezillon return ret;
86493db446aSBoris Brezillon
86593db446aSBoris Brezillon /* Fresh init of NAND controller */
86693db446aSBoris Brezillon lpc32xx_nand_setup(host);
86793db446aSBoris Brezillon
86893db446aSBoris Brezillon /* Disable write protect */
86993db446aSBoris Brezillon lpc32xx_wp_disable(host);
87093db446aSBoris Brezillon
87193db446aSBoris Brezillon return 0;
87293db446aSBoris Brezillon }
87393db446aSBoris Brezillon
lpc32xx_nand_suspend(struct platform_device * pdev,pm_message_t pm)87493db446aSBoris Brezillon static int lpc32xx_nand_suspend(struct platform_device *pdev, pm_message_t pm)
87593db446aSBoris Brezillon {
87693db446aSBoris Brezillon struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
87793db446aSBoris Brezillon
87893db446aSBoris Brezillon /* Enable write protect for safety */
87993db446aSBoris Brezillon lpc32xx_wp_enable(host);
88093db446aSBoris Brezillon
88193db446aSBoris Brezillon /* Disable clock */
88293db446aSBoris Brezillon clk_disable_unprepare(host->clk);
88393db446aSBoris Brezillon return 0;
88493db446aSBoris Brezillon }
88593db446aSBoris Brezillon
88693db446aSBoris Brezillon static const struct of_device_id lpc32xx_nand_match[] = {
88793db446aSBoris Brezillon { .compatible = "nxp,lpc3220-mlc" },
88893db446aSBoris Brezillon { /* sentinel */ },
88993db446aSBoris Brezillon };
89093db446aSBoris Brezillon MODULE_DEVICE_TABLE(of, lpc32xx_nand_match);
89193db446aSBoris Brezillon
89293db446aSBoris Brezillon static struct platform_driver lpc32xx_nand_driver = {
89393db446aSBoris Brezillon .probe = lpc32xx_nand_probe,
894ec185b18SUwe Kleine-König .remove_new = lpc32xx_nand_remove,
895991cc42aSGeert Uytterhoeven .resume = pm_ptr(lpc32xx_nand_resume),
896991cc42aSGeert Uytterhoeven .suspend = pm_ptr(lpc32xx_nand_suspend),
89793db446aSBoris Brezillon .driver = {
89893db446aSBoris Brezillon .name = DRV_NAME,
89993db446aSBoris Brezillon .of_match_table = lpc32xx_nand_match,
90093db446aSBoris Brezillon },
90193db446aSBoris Brezillon };
90293db446aSBoris Brezillon
90393db446aSBoris Brezillon module_platform_driver(lpc32xx_nand_driver);
90493db446aSBoris Brezillon
90593db446aSBoris Brezillon MODULE_LICENSE("GPL");
90693db446aSBoris Brezillon MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
90793db446aSBoris Brezillon MODULE_DESCRIPTION("NAND driver for the NXP LPC32XX MLC controller");
908