1f7917c00SJeff Kirsher /* 2f7917c00SJeff Kirsher * This file is part of the Chelsio T4 Ethernet driver for Linux. 3f7917c00SJeff Kirsher * 4b72a32daSRahul Lakkireddy * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. 5f7917c00SJeff Kirsher * 6f7917c00SJeff Kirsher * This software is available to you under a choice of one of two 7f7917c00SJeff Kirsher * licenses. You may choose to be licensed under the terms of the GNU 8f7917c00SJeff Kirsher * General Public License (GPL) Version 2, available from the file 9f7917c00SJeff Kirsher * COPYING in the main directory of this source tree, or the 10f7917c00SJeff Kirsher * OpenIB.org BSD license below: 11f7917c00SJeff Kirsher * 12f7917c00SJeff Kirsher * Redistribution and use in source and binary forms, with or 13f7917c00SJeff Kirsher * without modification, are permitted provided that the following 14f7917c00SJeff Kirsher * conditions are met: 15f7917c00SJeff Kirsher * 16f7917c00SJeff Kirsher * - Redistributions of source code must retain the above 17f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 18f7917c00SJeff Kirsher * disclaimer. 19f7917c00SJeff Kirsher * 20f7917c00SJeff Kirsher * - Redistributions in binary form must reproduce the above 21f7917c00SJeff Kirsher * copyright notice, this list of conditions and the following 22f7917c00SJeff Kirsher * disclaimer in the documentation and/or other materials 23f7917c00SJeff Kirsher * provided with the distribution. 24f7917c00SJeff Kirsher * 25f7917c00SJeff Kirsher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26f7917c00SJeff Kirsher * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27f7917c00SJeff Kirsher * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28f7917c00SJeff Kirsher * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29f7917c00SJeff Kirsher * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30f7917c00SJeff Kirsher * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31f7917c00SJeff Kirsher * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32f7917c00SJeff Kirsher * SOFTWARE. 33f7917c00SJeff Kirsher */ 34f7917c00SJeff Kirsher 35f7917c00SJeff Kirsher #ifndef _T4FW_INTERFACE_H_ 36f7917c00SJeff Kirsher #define _T4FW_INTERFACE_H_ 37f7917c00SJeff Kirsher 385be78ee9SVipul Pandya enum fw_retval { 39dbedd44eSJoe Perches FW_SUCCESS = 0, /* completed successfully */ 405be78ee9SVipul Pandya FW_EPERM = 1, /* operation not permitted */ 415be78ee9SVipul Pandya FW_ENOENT = 2, /* no such file or directory */ 425be78ee9SVipul Pandya FW_EIO = 5, /* input/output error; hw bad */ 435be78ee9SVipul Pandya FW_ENOEXEC = 8, /* exec format error; inv microcode */ 445be78ee9SVipul Pandya FW_EAGAIN = 11, /* try again */ 455be78ee9SVipul Pandya FW_ENOMEM = 12, /* out of memory */ 465be78ee9SVipul Pandya FW_EFAULT = 14, /* bad address; fw bad */ 475be78ee9SVipul Pandya FW_EBUSY = 16, /* resource busy */ 485be78ee9SVipul Pandya FW_EEXIST = 17, /* file exists */ 49989594e2SAnish Bhatt FW_ENODEV = 19, /* no such device */ 505be78ee9SVipul Pandya FW_EINVAL = 22, /* invalid argument */ 515be78ee9SVipul Pandya FW_ENOSPC = 28, /* no space left on device */ 525be78ee9SVipul Pandya FW_ENOSYS = 38, /* functionality not implemented */ 53989594e2SAnish Bhatt FW_ENODATA = 61, /* no data available */ 545be78ee9SVipul Pandya FW_EPROTO = 71, /* protocol error */ 555be78ee9SVipul Pandya FW_EADDRINUSE = 98, /* address already in use */ 565be78ee9SVipul Pandya FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 575be78ee9SVipul Pandya FW_ENETDOWN = 100, /* network is down */ 585be78ee9SVipul Pandya FW_ENETUNREACH = 101, /* network is unreachable */ 595be78ee9SVipul Pandya FW_ENOBUFS = 105, /* no buffer space available */ 605be78ee9SVipul Pandya FW_ETIMEDOUT = 110, /* timeout */ 615be78ee9SVipul Pandya FW_EINPROGRESS = 115, /* fw internal */ 625be78ee9SVipul Pandya FW_SCSI_ABORT_REQUESTED = 128, /* */ 635be78ee9SVipul Pandya FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 645be78ee9SVipul Pandya FW_SCSI_ABORTED = 130, /* */ 655be78ee9SVipul Pandya FW_SCSI_CLOSE_REQUESTED = 131, /* */ 665be78ee9SVipul Pandya FW_ERR_LINK_DOWN = 132, /* */ 675be78ee9SVipul Pandya FW_RDEV_NOT_READY = 133, /* */ 685be78ee9SVipul Pandya FW_ERR_RDEV_LOST = 134, /* */ 695be78ee9SVipul Pandya FW_ERR_RDEV_LOGO = 135, /* */ 705be78ee9SVipul Pandya FW_FCOE_NO_XCHG = 136, /* */ 715be78ee9SVipul Pandya FW_SCSI_RSP_ERR = 137, /* */ 725be78ee9SVipul Pandya FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 735be78ee9SVipul Pandya FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 745be78ee9SVipul Pandya FW_SCSI_OVER_FLOW_ERR = 140, /* */ 755be78ee9SVipul Pandya FW_SCSI_DDP_ERR = 141, /* DDP error*/ 765be78ee9SVipul Pandya FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 77f2b7e78dSVipul Pandya }; 78f2b7e78dSVipul Pandya 79f7917c00SJeff Kirsher #define FW_T4VF_SGE_BASE_ADDR 0x0000 80f7917c00SJeff Kirsher #define FW_T4VF_MPS_BASE_ADDR 0x0100 81f7917c00SJeff Kirsher #define FW_T4VF_PL_BASE_ADDR 0x0200 82f7917c00SJeff Kirsher #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 83f7917c00SJeff Kirsher #define FW_T4VF_CIM_BASE_ADDR 0x0300 84f7917c00SJeff Kirsher 85f7917c00SJeff Kirsher enum fw_wr_opcodes { 86f7917c00SJeff Kirsher FW_FILTER_WR = 0x02, 87f7917c00SJeff Kirsher FW_ULPTX_WR = 0x04, 88f7917c00SJeff Kirsher FW_TP_WR = 0x05, 89f7917c00SJeff Kirsher FW_ETH_TX_PKT_WR = 0x08, 905be78ee9SVipul Pandya FW_OFLD_CONNECTION_WR = 0x2f, 91f7917c00SJeff Kirsher FW_FLOWC_WR = 0x0a, 92f7917c00SJeff Kirsher FW_OFLD_TX_DATA_WR = 0x0b, 93f7917c00SJeff Kirsher FW_CMD_WR = 0x10, 94f7917c00SJeff Kirsher FW_ETH_TX_PKT_VM_WR = 0x11, 95f7917c00SJeff Kirsher FW_RI_RES_WR = 0x0c, 96f7917c00SJeff Kirsher FW_RI_INIT_WR = 0x0d, 97f7917c00SJeff Kirsher FW_RI_RDMA_WRITE_WR = 0x14, 98f7917c00SJeff Kirsher FW_RI_SEND_WR = 0x15, 99f7917c00SJeff Kirsher FW_RI_RDMA_READ_WR = 0x16, 100f7917c00SJeff Kirsher FW_RI_RECV_WR = 0x17, 101f7917c00SJeff Kirsher FW_RI_BIND_MW_WR = 0x18, 102f7917c00SJeff Kirsher FW_RI_FR_NSMR_WR = 0x19, 10349b53a93SSteve Wise FW_RI_FR_NSMR_TPTE_WR = 0x20, 104f7917c00SJeff Kirsher FW_RI_INV_LSTAG_WR = 0x1a, 105b96c5cbbSVarun Prakash FW_ISCSI_TX_DATA_WR = 0x45, 106a4569504SAtul Gupta FW_PTP_TX_PKT_WR = 0x46, 107d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR = 0X6d, 1080ff90994SKumar Sanghvi FW_LASTC2E_WR = 0x70, 1090ff90994SKumar Sanghvi FW_FILTER2_WR = 0x77 110f7917c00SJeff Kirsher }; 111f7917c00SJeff Kirsher 112f7917c00SJeff Kirsher struct fw_wr_hdr { 113f7917c00SJeff Kirsher __be32 hi; 114f7917c00SJeff Kirsher __be32 lo; 115f7917c00SJeff Kirsher }; 116f7917c00SJeff Kirsher 117e2ac9628SHariprasad Shenai /* work request opcode (hi) */ 118e2ac9628SHariprasad Shenai #define FW_WR_OP_S 24 119e2ac9628SHariprasad Shenai #define FW_WR_OP_M 0xff 120e2ac9628SHariprasad Shenai #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S) 121e2ac9628SHariprasad Shenai #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M) 122f7917c00SJeff Kirsher 123e2ac9628SHariprasad Shenai /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ 124e2ac9628SHariprasad Shenai #define FW_WR_ATOMIC_S 23 125e2ac9628SHariprasad Shenai #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S) 126e2ac9628SHariprasad Shenai 127e2ac9628SHariprasad Shenai /* flush flag (hi) - firmware flushes flushable work request buffered 128e2ac9628SHariprasad Shenai * in the flow context. 129e2ac9628SHariprasad Shenai */ 130e2ac9628SHariprasad Shenai #define FW_WR_FLUSH_S 22 131e2ac9628SHariprasad Shenai #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S) 132e2ac9628SHariprasad Shenai 133e2ac9628SHariprasad Shenai /* completion flag (hi) - firmware generates a cpl_fw6_ack */ 134e2ac9628SHariprasad Shenai #define FW_WR_COMPL_S 21 135e2ac9628SHariprasad Shenai #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S) 136e2ac9628SHariprasad Shenai #define FW_WR_COMPL_F FW_WR_COMPL_V(1U) 137e2ac9628SHariprasad Shenai 138e2ac9628SHariprasad Shenai /* work request immediate data length (hi) */ 139e2ac9628SHariprasad Shenai #define FW_WR_IMMDLEN_S 0 140e2ac9628SHariprasad Shenai #define FW_WR_IMMDLEN_M 0xff 141e2ac9628SHariprasad Shenai #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S) 142e2ac9628SHariprasad Shenai 143e2ac9628SHariprasad Shenai /* egress queue status update to associated ingress queue entry (lo) */ 144e2ac9628SHariprasad Shenai #define FW_WR_EQUIQ_S 31 145e2ac9628SHariprasad Shenai #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S) 146e2ac9628SHariprasad Shenai #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U) 147e2ac9628SHariprasad Shenai 148e2ac9628SHariprasad Shenai /* egress queue status update to egress queue status entry (lo) */ 149e2ac9628SHariprasad Shenai #define FW_WR_EQUEQ_S 30 150e2ac9628SHariprasad Shenai #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S) 151e2ac9628SHariprasad Shenai #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U) 152e2ac9628SHariprasad Shenai 153e2ac9628SHariprasad Shenai /* flow context identifier (lo) */ 154e2ac9628SHariprasad Shenai #define FW_WR_FLOWID_S 8 155e2ac9628SHariprasad Shenai #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S) 156e2ac9628SHariprasad Shenai 157e2ac9628SHariprasad Shenai /* length in units of 16-bytes (lo) */ 158e2ac9628SHariprasad Shenai #define FW_WR_LEN16_S 0 159e2ac9628SHariprasad Shenai #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S) 160f7917c00SJeff Kirsher 16113ee15d3SVipul Pandya #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 1625be78ee9SVipul Pandya #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 16313ee15d3SVipul Pandya 164f2b7e78dSVipul Pandya /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 165f2b7e78dSVipul Pandya enum fw_filter_wr_cookie { 166f2b7e78dSVipul Pandya FW_FILTER_WR_SUCCESS, 167f2b7e78dSVipul Pandya FW_FILTER_WR_FLT_ADDED, 168f2b7e78dSVipul Pandya FW_FILTER_WR_FLT_DELETED, 169f2b7e78dSVipul Pandya FW_FILTER_WR_SMT_TBL_FULL, 170f2b7e78dSVipul Pandya FW_FILTER_WR_EINVAL, 171f2b7e78dSVipul Pandya }; 172f2b7e78dSVipul Pandya 173f2b7e78dSVipul Pandya struct fw_filter_wr { 174f2b7e78dSVipul Pandya __be32 op_pkd; 175f2b7e78dSVipul Pandya __be32 len16_pkd; 176f2b7e78dSVipul Pandya __be64 r3; 177f2b7e78dSVipul Pandya __be32 tid_to_iq; 178f2b7e78dSVipul Pandya __be32 del_filter_to_l2tix; 179f2b7e78dSVipul Pandya __be16 ethtype; 180f2b7e78dSVipul Pandya __be16 ethtypem; 181f2b7e78dSVipul Pandya __u8 frag_to_ovlan_vldm; 182f2b7e78dSVipul Pandya __u8 smac_sel; 183f2b7e78dSVipul Pandya __be16 rx_chan_rx_rpl_iq; 184f2b7e78dSVipul Pandya __be32 maci_to_matchtypem; 185f2b7e78dSVipul Pandya __u8 ptcl; 186f2b7e78dSVipul Pandya __u8 ptclm; 187f2b7e78dSVipul Pandya __u8 ttyp; 188f2b7e78dSVipul Pandya __u8 ttypm; 189f2b7e78dSVipul Pandya __be16 ivlan; 190f2b7e78dSVipul Pandya __be16 ivlanm; 191f2b7e78dSVipul Pandya __be16 ovlan; 192f2b7e78dSVipul Pandya __be16 ovlanm; 193f2b7e78dSVipul Pandya __u8 lip[16]; 194f2b7e78dSVipul Pandya __u8 lipm[16]; 195f2b7e78dSVipul Pandya __u8 fip[16]; 196f2b7e78dSVipul Pandya __u8 fipm[16]; 197f2b7e78dSVipul Pandya __be16 lp; 198f2b7e78dSVipul Pandya __be16 lpm; 199f2b7e78dSVipul Pandya __be16 fp; 200f2b7e78dSVipul Pandya __be16 fpm; 201f2b7e78dSVipul Pandya __be16 r7; 202f2b7e78dSVipul Pandya __u8 sma[6]; 203f2b7e78dSVipul Pandya }; 204f2b7e78dSVipul Pandya 2050ff90994SKumar Sanghvi struct fw_filter2_wr { 2060ff90994SKumar Sanghvi __be32 op_pkd; 2070ff90994SKumar Sanghvi __be32 len16_pkd; 2080ff90994SKumar Sanghvi __be64 r3; 2090ff90994SKumar Sanghvi __be32 tid_to_iq; 2100ff90994SKumar Sanghvi __be32 del_filter_to_l2tix; 2110ff90994SKumar Sanghvi __be16 ethtype; 2120ff90994SKumar Sanghvi __be16 ethtypem; 2130ff90994SKumar Sanghvi __u8 frag_to_ovlan_vldm; 2140ff90994SKumar Sanghvi __u8 smac_sel; 2150ff90994SKumar Sanghvi __be16 rx_chan_rx_rpl_iq; 2160ff90994SKumar Sanghvi __be32 maci_to_matchtypem; 2170ff90994SKumar Sanghvi __u8 ptcl; 2180ff90994SKumar Sanghvi __u8 ptclm; 2190ff90994SKumar Sanghvi __u8 ttyp; 2200ff90994SKumar Sanghvi __u8 ttypm; 2210ff90994SKumar Sanghvi __be16 ivlan; 2220ff90994SKumar Sanghvi __be16 ivlanm; 2230ff90994SKumar Sanghvi __be16 ovlan; 2240ff90994SKumar Sanghvi __be16 ovlanm; 2250ff90994SKumar Sanghvi __u8 lip[16]; 2260ff90994SKumar Sanghvi __u8 lipm[16]; 2270ff90994SKumar Sanghvi __u8 fip[16]; 2280ff90994SKumar Sanghvi __u8 fipm[16]; 2290ff90994SKumar Sanghvi __be16 lp; 2300ff90994SKumar Sanghvi __be16 lpm; 2310ff90994SKumar Sanghvi __be16 fp; 2320ff90994SKumar Sanghvi __be16 fpm; 2330ff90994SKumar Sanghvi __be16 r7; 2340ff90994SKumar Sanghvi __u8 sma[6]; 2350ff90994SKumar Sanghvi __be16 r8; 2360ff90994SKumar Sanghvi __u8 filter_type_swapmac; 2370ff90994SKumar Sanghvi __u8 natmode_to_ulp_type; 2380ff90994SKumar Sanghvi __be16 newlport; 2390ff90994SKumar Sanghvi __be16 newfport; 2400ff90994SKumar Sanghvi __u8 newlip[16]; 2410ff90994SKumar Sanghvi __u8 newfip[16]; 2420ff90994SKumar Sanghvi __be32 natseqcheck; 2430ff90994SKumar Sanghvi __be32 r9; 2440ff90994SKumar Sanghvi __be64 r10; 2450ff90994SKumar Sanghvi __be64 r11; 2460ff90994SKumar Sanghvi __be64 r12; 2470ff90994SKumar Sanghvi __be64 r13; 2480ff90994SKumar Sanghvi }; 2490ff90994SKumar Sanghvi 25077a80e23SHariprasad Shenai #define FW_FILTER_WR_TID_S 12 25177a80e23SHariprasad Shenai #define FW_FILTER_WR_TID_M 0xfffff 25277a80e23SHariprasad Shenai #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S) 25377a80e23SHariprasad Shenai #define FW_FILTER_WR_TID_G(x) \ 25477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M) 255f2b7e78dSVipul Pandya 25677a80e23SHariprasad Shenai #define FW_FILTER_WR_RQTYPE_S 11 25777a80e23SHariprasad Shenai #define FW_FILTER_WR_RQTYPE_M 0x1 25877a80e23SHariprasad Shenai #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S) 25977a80e23SHariprasad Shenai #define FW_FILTER_WR_RQTYPE_G(x) \ 26077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M) 26177a80e23SHariprasad Shenai #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U) 262f2b7e78dSVipul Pandya 26377a80e23SHariprasad Shenai #define FW_FILTER_WR_NOREPLY_S 10 26477a80e23SHariprasad Shenai #define FW_FILTER_WR_NOREPLY_M 0x1 26577a80e23SHariprasad Shenai #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S) 26677a80e23SHariprasad Shenai #define FW_FILTER_WR_NOREPLY_G(x) \ 26777a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M) 26877a80e23SHariprasad Shenai #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U) 269f2b7e78dSVipul Pandya 27077a80e23SHariprasad Shenai #define FW_FILTER_WR_IQ_S 0 27177a80e23SHariprasad Shenai #define FW_FILTER_WR_IQ_M 0x3ff 27277a80e23SHariprasad Shenai #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S) 27377a80e23SHariprasad Shenai #define FW_FILTER_WR_IQ_G(x) \ 27477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M) 275f2b7e78dSVipul Pandya 27677a80e23SHariprasad Shenai #define FW_FILTER_WR_DEL_FILTER_S 31 27777a80e23SHariprasad Shenai #define FW_FILTER_WR_DEL_FILTER_M 0x1 27877a80e23SHariprasad Shenai #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S) 27977a80e23SHariprasad Shenai #define FW_FILTER_WR_DEL_FILTER_G(x) \ 28077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M) 28177a80e23SHariprasad Shenai #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U) 282f2b7e78dSVipul Pandya 28377a80e23SHariprasad Shenai #define FW_FILTER_WR_RPTTID_S 25 28477a80e23SHariprasad Shenai #define FW_FILTER_WR_RPTTID_M 0x1 28577a80e23SHariprasad Shenai #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S) 28677a80e23SHariprasad Shenai #define FW_FILTER_WR_RPTTID_G(x) \ 28777a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M) 28877a80e23SHariprasad Shenai #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U) 289f2b7e78dSVipul Pandya 29077a80e23SHariprasad Shenai #define FW_FILTER_WR_DROP_S 24 29177a80e23SHariprasad Shenai #define FW_FILTER_WR_DROP_M 0x1 29277a80e23SHariprasad Shenai #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S) 29377a80e23SHariprasad Shenai #define FW_FILTER_WR_DROP_G(x) \ 29477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M) 29577a80e23SHariprasad Shenai #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U) 296f2b7e78dSVipul Pandya 29777a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEER_S 23 29877a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEER_M 0x1 29977a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S) 30077a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEER_G(x) \ 30177a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M) 30277a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U) 303f2b7e78dSVipul Pandya 30477a80e23SHariprasad Shenai #define FW_FILTER_WR_MASKHASH_S 22 30577a80e23SHariprasad Shenai #define FW_FILTER_WR_MASKHASH_M 0x1 30677a80e23SHariprasad Shenai #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S) 30777a80e23SHariprasad Shenai #define FW_FILTER_WR_MASKHASH_G(x) \ 30877a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M) 30977a80e23SHariprasad Shenai #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U) 310f2b7e78dSVipul Pandya 31177a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEERHASH_S 21 31277a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEERHASH_M 0x1 31377a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S) 31477a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEERHASH_G(x) \ 31577a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M) 31677a80e23SHariprasad Shenai #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U) 317f2b7e78dSVipul Pandya 31877a80e23SHariprasad Shenai #define FW_FILTER_WR_LPBK_S 20 31977a80e23SHariprasad Shenai #define FW_FILTER_WR_LPBK_M 0x1 32077a80e23SHariprasad Shenai #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S) 32177a80e23SHariprasad Shenai #define FW_FILTER_WR_LPBK_G(x) \ 32277a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M) 32377a80e23SHariprasad Shenai #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U) 324f2b7e78dSVipul Pandya 32577a80e23SHariprasad Shenai #define FW_FILTER_WR_DMAC_S 19 32677a80e23SHariprasad Shenai #define FW_FILTER_WR_DMAC_M 0x1 32777a80e23SHariprasad Shenai #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S) 32877a80e23SHariprasad Shenai #define FW_FILTER_WR_DMAC_G(x) \ 32977a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M) 33077a80e23SHariprasad Shenai #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U) 331f2b7e78dSVipul Pandya 33277a80e23SHariprasad Shenai #define FW_FILTER_WR_SMAC_S 18 33377a80e23SHariprasad Shenai #define FW_FILTER_WR_SMAC_M 0x1 33477a80e23SHariprasad Shenai #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S) 33577a80e23SHariprasad Shenai #define FW_FILTER_WR_SMAC_G(x) \ 33677a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M) 33777a80e23SHariprasad Shenai #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U) 338f2b7e78dSVipul Pandya 33977a80e23SHariprasad Shenai #define FW_FILTER_WR_INSVLAN_S 17 34077a80e23SHariprasad Shenai #define FW_FILTER_WR_INSVLAN_M 0x1 34177a80e23SHariprasad Shenai #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S) 34277a80e23SHariprasad Shenai #define FW_FILTER_WR_INSVLAN_G(x) \ 34377a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M) 34477a80e23SHariprasad Shenai #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U) 345f2b7e78dSVipul Pandya 34677a80e23SHariprasad Shenai #define FW_FILTER_WR_RMVLAN_S 16 34777a80e23SHariprasad Shenai #define FW_FILTER_WR_RMVLAN_M 0x1 34877a80e23SHariprasad Shenai #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S) 34977a80e23SHariprasad Shenai #define FW_FILTER_WR_RMVLAN_G(x) \ 35077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M) 35177a80e23SHariprasad Shenai #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U) 352f2b7e78dSVipul Pandya 35377a80e23SHariprasad Shenai #define FW_FILTER_WR_HITCNTS_S 15 35477a80e23SHariprasad Shenai #define FW_FILTER_WR_HITCNTS_M 0x1 35577a80e23SHariprasad Shenai #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S) 35677a80e23SHariprasad Shenai #define FW_FILTER_WR_HITCNTS_G(x) \ 35777a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M) 35877a80e23SHariprasad Shenai #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U) 359f2b7e78dSVipul Pandya 36077a80e23SHariprasad Shenai #define FW_FILTER_WR_TXCHAN_S 13 36177a80e23SHariprasad Shenai #define FW_FILTER_WR_TXCHAN_M 0x3 36277a80e23SHariprasad Shenai #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S) 36377a80e23SHariprasad Shenai #define FW_FILTER_WR_TXCHAN_G(x) \ 36477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M) 365f2b7e78dSVipul Pandya 36677a80e23SHariprasad Shenai #define FW_FILTER_WR_PRIO_S 12 36777a80e23SHariprasad Shenai #define FW_FILTER_WR_PRIO_M 0x1 36877a80e23SHariprasad Shenai #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S) 36977a80e23SHariprasad Shenai #define FW_FILTER_WR_PRIO_G(x) \ 37077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M) 37177a80e23SHariprasad Shenai #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U) 372f2b7e78dSVipul Pandya 37377a80e23SHariprasad Shenai #define FW_FILTER_WR_L2TIX_S 0 37477a80e23SHariprasad Shenai #define FW_FILTER_WR_L2TIX_M 0xfff 37577a80e23SHariprasad Shenai #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S) 37677a80e23SHariprasad Shenai #define FW_FILTER_WR_L2TIX_G(x) \ 37777a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M) 378f2b7e78dSVipul Pandya 37977a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAG_S 7 38077a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAG_M 0x1 38177a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S) 38277a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAG_G(x) \ 38377a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M) 38477a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U) 385f2b7e78dSVipul Pandya 38677a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAGM_S 6 38777a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAGM_M 0x1 38877a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S) 38977a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAGM_G(x) \ 39077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M) 39177a80e23SHariprasad Shenai #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U) 392f2b7e78dSVipul Pandya 39377a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLD_S 5 39477a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLD_M 0x1 39577a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S) 39677a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLD_G(x) \ 39777a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M) 39877a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U) 399f2b7e78dSVipul Pandya 40077a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLD_S 4 40177a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLD_M 0x1 40277a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S) 40377a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLD_G(x) \ 40477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M) 40577a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U) 406f2b7e78dSVipul Pandya 40777a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLDM_S 3 40877a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLDM_M 0x1 40977a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S) 41077a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLDM_G(x) \ 41177a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M) 41277a80e23SHariprasad Shenai #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U) 413f2b7e78dSVipul Pandya 41477a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLDM_S 2 41577a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLDM_M 0x1 41677a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S) 41777a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLDM_G(x) \ 41877a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M) 41977a80e23SHariprasad Shenai #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U) 420f2b7e78dSVipul Pandya 42177a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_CHAN_S 15 42277a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_CHAN_M 0x1 42377a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S) 42477a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_CHAN_G(x) \ 42577a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M) 42677a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U) 427f2b7e78dSVipul Pandya 42877a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_RPL_IQ_S 0 42977a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff 43077a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S) 43177a80e23SHariprasad Shenai #define FW_FILTER_WR_RX_RPL_IQ_G(x) \ 43277a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M) 433f2b7e78dSVipul Pandya 4340ff90994SKumar Sanghvi #define FW_FILTER2_WR_FILTER_TYPE_S 1 4350ff90994SKumar Sanghvi #define FW_FILTER2_WR_FILTER_TYPE_M 0x1 4360ff90994SKumar Sanghvi #define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S) 4370ff90994SKumar Sanghvi #define FW_FILTER2_WR_FILTER_TYPE_G(x) \ 4380ff90994SKumar Sanghvi (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M) 4390ff90994SKumar Sanghvi #define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U) 4400ff90994SKumar Sanghvi 4410ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATMODE_S 5 4420ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATMODE_M 0x7 4430ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S) 4440ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATMODE_G(x) \ 4450ff90994SKumar Sanghvi (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M) 4460ff90994SKumar Sanghvi 4470ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATFLAGCHECK_S 4 4480ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATFLAGCHECK_M 0x1 4490ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S) 4500ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \ 4510ff90994SKumar Sanghvi (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M) 4520ff90994SKumar Sanghvi #define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U) 4530ff90994SKumar Sanghvi 4540ff90994SKumar Sanghvi #define FW_FILTER2_WR_ULP_TYPE_S 0 4550ff90994SKumar Sanghvi #define FW_FILTER2_WR_ULP_TYPE_M 0xf 4560ff90994SKumar Sanghvi #define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S) 4570ff90994SKumar Sanghvi #define FW_FILTER2_WR_ULP_TYPE_G(x) \ 4580ff90994SKumar Sanghvi (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M) 4590ff90994SKumar Sanghvi 46077a80e23SHariprasad Shenai #define FW_FILTER_WR_MACI_S 23 46177a80e23SHariprasad Shenai #define FW_FILTER_WR_MACI_M 0x1ff 46277a80e23SHariprasad Shenai #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S) 46377a80e23SHariprasad Shenai #define FW_FILTER_WR_MACI_G(x) \ 46477a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M) 465f2b7e78dSVipul Pandya 46677a80e23SHariprasad Shenai #define FW_FILTER_WR_MACIM_S 14 46777a80e23SHariprasad Shenai #define FW_FILTER_WR_MACIM_M 0x1ff 46877a80e23SHariprasad Shenai #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S) 46977a80e23SHariprasad Shenai #define FW_FILTER_WR_MACIM_G(x) \ 47077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M) 471f2b7e78dSVipul Pandya 47277a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOE_S 13 47377a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOE_M 0x1 47477a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S) 47577a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOE_G(x) \ 47677a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M) 47777a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U) 478f2b7e78dSVipul Pandya 47977a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOEM_S 12 48077a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOEM_M 0x1 48177a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S) 48277a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOEM_G(x) \ 48377a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M) 48477a80e23SHariprasad Shenai #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U) 485f2b7e78dSVipul Pandya 48677a80e23SHariprasad Shenai #define FW_FILTER_WR_PORT_S 9 48777a80e23SHariprasad Shenai #define FW_FILTER_WR_PORT_M 0x7 48877a80e23SHariprasad Shenai #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S) 48977a80e23SHariprasad Shenai #define FW_FILTER_WR_PORT_G(x) \ 49077a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M) 491f2b7e78dSVipul Pandya 49277a80e23SHariprasad Shenai #define FW_FILTER_WR_PORTM_S 6 49377a80e23SHariprasad Shenai #define FW_FILTER_WR_PORTM_M 0x7 49477a80e23SHariprasad Shenai #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S) 49577a80e23SHariprasad Shenai #define FW_FILTER_WR_PORTM_G(x) \ 49677a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M) 497f2b7e78dSVipul Pandya 49877a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPE_S 3 49977a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPE_M 0x7 50077a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S) 50177a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPE_G(x) \ 50277a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M) 503f2b7e78dSVipul Pandya 50477a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPEM_S 0 50577a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPEM_M 0x7 50677a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S) 50777a80e23SHariprasad Shenai #define FW_FILTER_WR_MATCHTYPEM_G(x) \ 50877a80e23SHariprasad Shenai (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M) 509f2b7e78dSVipul Pandya 510f7917c00SJeff Kirsher struct fw_ulptx_wr { 511f7917c00SJeff Kirsher __be32 op_to_compl; 512f7917c00SJeff Kirsher __be32 flowid_len16; 513f7917c00SJeff Kirsher u64 cookie; 514f7917c00SJeff Kirsher }; 515f7917c00SJeff Kirsher 516a6ec572bSAtul Gupta #define FW_ULPTX_WR_DATA_S 28 517a6ec572bSAtul Gupta #define FW_ULPTX_WR_DATA_M 0x1 518a6ec572bSAtul Gupta #define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S) 519a6ec572bSAtul Gupta #define FW_ULPTX_WR_DATA_G(x) \ 520a6ec572bSAtul Gupta (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M) 521a6ec572bSAtul Gupta #define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U) 522a6ec572bSAtul Gupta 523f7917c00SJeff Kirsher struct fw_tp_wr { 524f7917c00SJeff Kirsher __be32 op_to_immdlen; 525f7917c00SJeff Kirsher __be32 flowid_len16; 526f7917c00SJeff Kirsher u64 cookie; 527f7917c00SJeff Kirsher }; 528f7917c00SJeff Kirsher 529f7917c00SJeff Kirsher struct fw_eth_tx_pkt_wr { 530f7917c00SJeff Kirsher __be32 op_immdlen; 531f7917c00SJeff Kirsher __be32 equiq_to_len16; 532f7917c00SJeff Kirsher __be64 r3; 533f7917c00SJeff Kirsher }; 534f7917c00SJeff Kirsher 5355be78ee9SVipul Pandya struct fw_ofld_connection_wr { 5365be78ee9SVipul Pandya __be32 op_compl; 5375be78ee9SVipul Pandya __be32 len16_pkd; 5385be78ee9SVipul Pandya __u64 cookie; 5395be78ee9SVipul Pandya __be64 r2; 5405be78ee9SVipul Pandya __be64 r3; 5415be78ee9SVipul Pandya struct fw_ofld_connection_le { 5425be78ee9SVipul Pandya __be32 version_cpl; 5435be78ee9SVipul Pandya __be32 filter; 5445be78ee9SVipul Pandya __be32 r1; 5455be78ee9SVipul Pandya __be16 lport; 5465be78ee9SVipul Pandya __be16 pport; 5475be78ee9SVipul Pandya union fw_ofld_connection_leip { 5485be78ee9SVipul Pandya struct fw_ofld_connection_le_ipv4 { 5495be78ee9SVipul Pandya __be32 pip; 5505be78ee9SVipul Pandya __be32 lip; 5515be78ee9SVipul Pandya __be64 r0; 5525be78ee9SVipul Pandya __be64 r1; 5535be78ee9SVipul Pandya __be64 r2; 5545be78ee9SVipul Pandya } ipv4; 5555be78ee9SVipul Pandya struct fw_ofld_connection_le_ipv6 { 5565be78ee9SVipul Pandya __be64 pip_hi; 5575be78ee9SVipul Pandya __be64 pip_lo; 5585be78ee9SVipul Pandya __be64 lip_hi; 5595be78ee9SVipul Pandya __be64 lip_lo; 5605be78ee9SVipul Pandya } ipv6; 5615be78ee9SVipul Pandya } u; 5625be78ee9SVipul Pandya } le; 5635be78ee9SVipul Pandya struct fw_ofld_connection_tcb { 5645be78ee9SVipul Pandya __be32 t_state_to_astid; 5655be78ee9SVipul Pandya __be16 cplrxdataack_cplpassacceptrpl; 5665be78ee9SVipul Pandya __be16 rcv_adv; 5675be78ee9SVipul Pandya __be32 rcv_nxt; 5685be78ee9SVipul Pandya __be32 tx_max; 5695be78ee9SVipul Pandya __be64 opt0; 5705be78ee9SVipul Pandya __be32 opt2; 5715be78ee9SVipul Pandya __be32 r1; 5725be78ee9SVipul Pandya __be64 r2; 5735be78ee9SVipul Pandya __be64 r3; 5745be78ee9SVipul Pandya } tcb; 5755be78ee9SVipul Pandya }; 5765be78ee9SVipul Pandya 57777a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_VERSION_S 31 57877a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1 57977a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \ 58077a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_VERSION_S) 58177a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \ 58277a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \ 58377a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_VERSION_M) 58477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_VERSION_F \ 58577a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_VERSION_V(1U) 5865be78ee9SVipul Pandya 58777a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPL_S 30 58877a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPL_M 0x1 58977a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S) 59077a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPL_G(x) \ 59177a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M) 59277a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U) 5935be78ee9SVipul Pandya 59477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_T_STATE_S 28 59577a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf 59677a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \ 59777a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S) 59877a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \ 59977a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \ 60077a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_T_STATE_M) 6015be78ee9SVipul Pandya 60277a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24 60377a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf 60477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \ 60577a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S) 60677a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \ 60777a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \ 60877a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_RCV_SCALE_M) 6095be78ee9SVipul Pandya 61077a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_ASTID_S 0 61177a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff 61277a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \ 61377a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_ASTID_S) 61477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \ 61577a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M) 6165be78ee9SVipul Pandya 61777a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15 61877a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1 61977a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \ 62077a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) 62177a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \ 62277a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \ 62377a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M) 62477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \ 62577a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U) 6265be78ee9SVipul Pandya 62777a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14 62877a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1 62977a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \ 63077a80e23SHariprasad Shenai ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) 63177a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \ 63277a80e23SHariprasad Shenai (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \ 63377a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M) 63477a80e23SHariprasad Shenai #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \ 63577a80e23SHariprasad Shenai FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U) 6365be78ee9SVipul Pandya 637f7917c00SJeff Kirsher enum fw_flowc_mnem { 638f7917c00SJeff Kirsher FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 639f7917c00SJeff Kirsher FW_FLOWC_MNEM_CH, 640f7917c00SJeff Kirsher FW_FLOWC_MNEM_PORT, 641f7917c00SJeff Kirsher FW_FLOWC_MNEM_IQID, 642f7917c00SJeff Kirsher FW_FLOWC_MNEM_SNDNXT, 643f7917c00SJeff Kirsher FW_FLOWC_MNEM_RCVNXT, 644f7917c00SJeff Kirsher FW_FLOWC_MNEM_SNDBUF, 645f7917c00SJeff Kirsher FW_FLOWC_MNEM_MSS, 64664bfead8SKaren Xie FW_FLOWC_MNEM_TXDATAPLEN_MAX, 647b96c5cbbSVarun Prakash FW_FLOWC_MNEM_TCPSTATE, 648b96c5cbbSVarun Prakash FW_FLOWC_MNEM_EOSTATE, 649b96c5cbbSVarun Prakash FW_FLOWC_MNEM_SCHEDCLASS, 650b96c5cbbSVarun Prakash FW_FLOWC_MNEM_DCBPRIO, 651b96c5cbbSVarun Prakash FW_FLOWC_MNEM_SND_SCALE, 652b96c5cbbSVarun Prakash FW_FLOWC_MNEM_RCV_SCALE, 653f7917c00SJeff Kirsher }; 654f7917c00SJeff Kirsher 655f7917c00SJeff Kirsher struct fw_flowc_mnemval { 656f7917c00SJeff Kirsher u8 mnemonic; 657f7917c00SJeff Kirsher u8 r4[3]; 658f7917c00SJeff Kirsher __be32 val; 659f7917c00SJeff Kirsher }; 660f7917c00SJeff Kirsher 661f7917c00SJeff Kirsher struct fw_flowc_wr { 662f7917c00SJeff Kirsher __be32 op_to_nparams; 663f7917c00SJeff Kirsher __be32 flowid_len16; 664f7917c00SJeff Kirsher struct fw_flowc_mnemval mnemval[0]; 665f7917c00SJeff Kirsher }; 666f7917c00SJeff Kirsher 667e2ac9628SHariprasad Shenai #define FW_FLOWC_WR_NPARAMS_S 0 668e2ac9628SHariprasad Shenai #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S) 669e2ac9628SHariprasad Shenai 670f7917c00SJeff Kirsher struct fw_ofld_tx_data_wr { 671f7917c00SJeff Kirsher __be32 op_to_immdlen; 672f7917c00SJeff Kirsher __be32 flowid_len16; 673f7917c00SJeff Kirsher __be32 plen; 674f7917c00SJeff Kirsher __be32 tunnel_to_proxy; 675f7917c00SJeff Kirsher }; 676f7917c00SJeff Kirsher 677e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19 678e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S) 679e2ac9628SHariprasad Shenai 680e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_SAVE_S 18 681e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S) 682e2ac9628SHariprasad Shenai 683e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_FLUSH_S 17 684e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S) 685e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U) 686e2ac9628SHariprasad Shenai 687e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_URGENT_S 16 688e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S) 689e2ac9628SHariprasad Shenai 690e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_MORE_S 15 691e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S) 692e2ac9628SHariprasad Shenai 693e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_SHOVE_S 14 694e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S) 695e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U) 696e2ac9628SHariprasad Shenai 697e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10 698e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S) 699e2ac9628SHariprasad Shenai 700e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6 701e2ac9628SHariprasad Shenai #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \ 702e2ac9628SHariprasad Shenai ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S) 703e2ac9628SHariprasad Shenai 704f7917c00SJeff Kirsher struct fw_cmd_wr { 705f7917c00SJeff Kirsher __be32 op_dma; 706f7917c00SJeff Kirsher __be32 len16_pkd; 707f7917c00SJeff Kirsher __be64 cookie_daddr; 708f7917c00SJeff Kirsher }; 709f7917c00SJeff Kirsher 710e2ac9628SHariprasad Shenai #define FW_CMD_WR_DMA_S 17 711e2ac9628SHariprasad Shenai #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S) 712e2ac9628SHariprasad Shenai 713f7917c00SJeff Kirsher struct fw_eth_tx_pkt_vm_wr { 714f7917c00SJeff Kirsher __be32 op_immdlen; 715f7917c00SJeff Kirsher __be32 equiq_to_len16; 716f7917c00SJeff Kirsher __be32 r3[2]; 717f7917c00SJeff Kirsher u8 ethmacdst[6]; 718f7917c00SJeff Kirsher u8 ethmacsrc[6]; 719f7917c00SJeff Kirsher __be16 ethtype; 720f7917c00SJeff Kirsher __be16 vlantci; 721f7917c00SJeff Kirsher }; 722f7917c00SJeff Kirsher 7232422d9a3SSantosh Rastapur #define FW_CMD_MAX_TIMEOUT 10000 724f7917c00SJeff Kirsher 725636f9d37SVipul Pandya /* 726636f9d37SVipul Pandya * If a host driver does a HELLO and discovers that there's already a MASTER 727636f9d37SVipul Pandya * selected, we may have to wait for that MASTER to finish issuing RESET, 728636f9d37SVipul Pandya * configuration and INITIALIZE commands. Also, there's a possibility that 729636f9d37SVipul Pandya * our own HELLO may get lost if it happens right as the MASTER is issuign a 730636f9d37SVipul Pandya * RESET command, so we need to be willing to make a few retries of our HELLO. 731636f9d37SVipul Pandya */ 732636f9d37SVipul Pandya #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 733636f9d37SVipul Pandya #define FW_CMD_HELLO_RETRIES 3 734636f9d37SVipul Pandya 735636f9d37SVipul Pandya 736f7917c00SJeff Kirsher enum fw_cmd_opcodes { 737f7917c00SJeff Kirsher FW_LDST_CMD = 0x01, 738f7917c00SJeff Kirsher FW_RESET_CMD = 0x03, 739f7917c00SJeff Kirsher FW_HELLO_CMD = 0x04, 740f7917c00SJeff Kirsher FW_BYE_CMD = 0x05, 741f7917c00SJeff Kirsher FW_INITIALIZE_CMD = 0x06, 742f7917c00SJeff Kirsher FW_CAPS_CONFIG_CMD = 0x07, 743f7917c00SJeff Kirsher FW_PARAMS_CMD = 0x08, 744f7917c00SJeff Kirsher FW_PFVF_CMD = 0x09, 745f7917c00SJeff Kirsher FW_IQ_CMD = 0x10, 746f7917c00SJeff Kirsher FW_EQ_MNGT_CMD = 0x11, 747f7917c00SJeff Kirsher FW_EQ_ETH_CMD = 0x12, 748f7917c00SJeff Kirsher FW_EQ_CTRL_CMD = 0x13, 749f7917c00SJeff Kirsher FW_EQ_OFLD_CMD = 0x21, 750f7917c00SJeff Kirsher FW_VI_CMD = 0x14, 751f7917c00SJeff Kirsher FW_VI_MAC_CMD = 0x15, 752f7917c00SJeff Kirsher FW_VI_RXMODE_CMD = 0x16, 753f7917c00SJeff Kirsher FW_VI_ENABLE_CMD = 0x17, 754f7917c00SJeff Kirsher FW_ACL_MAC_CMD = 0x18, 755f7917c00SJeff Kirsher FW_ACL_VLAN_CMD = 0x19, 756f7917c00SJeff Kirsher FW_VI_STATS_CMD = 0x1a, 757f7917c00SJeff Kirsher FW_PORT_CMD = 0x1b, 758f7917c00SJeff Kirsher FW_PORT_STATS_CMD = 0x1c, 759f7917c00SJeff Kirsher FW_PORT_LB_STATS_CMD = 0x1d, 760f7917c00SJeff Kirsher FW_PORT_TRACE_CMD = 0x1e, 761f7917c00SJeff Kirsher FW_PORT_TRACE_MMAP_CMD = 0x1f, 762f7917c00SJeff Kirsher FW_RSS_IND_TBL_CMD = 0x20, 763f7917c00SJeff Kirsher FW_RSS_GLB_CONFIG_CMD = 0x22, 764f7917c00SJeff Kirsher FW_RSS_VI_CONFIG_CMD = 0x23, 765b72a32daSRahul Lakkireddy FW_SCHED_CMD = 0x24, 76649aa284fSHariprasad Shenai FW_DEVLOG_CMD = 0x25, 76701bcca68SVipul Pandya FW_CLIP_CMD = 0x28, 768a4569504SAtul Gupta FW_PTP_CMD = 0x3e, 7698b4e6b3cSArjun Vynipadath FW_HMA_CMD = 0x3f, 770f7917c00SJeff Kirsher FW_LASTC2E_CMD = 0x40, 771f7917c00SJeff Kirsher FW_ERROR_CMD = 0x80, 772f7917c00SJeff Kirsher FW_DEBUG_CMD = 0x81, 773f7917c00SJeff Kirsher }; 774f7917c00SJeff Kirsher 775f7917c00SJeff Kirsher enum fw_cmd_cap { 776f7917c00SJeff Kirsher FW_CMD_CAP_PF = 0x01, 777f7917c00SJeff Kirsher FW_CMD_CAP_DMAQ = 0x02, 778f7917c00SJeff Kirsher FW_CMD_CAP_PORT = 0x04, 779f7917c00SJeff Kirsher FW_CMD_CAP_PORTPROMISC = 0x08, 780f7917c00SJeff Kirsher FW_CMD_CAP_PORTSTATS = 0x10, 781f7917c00SJeff Kirsher FW_CMD_CAP_VF = 0x80, 782f7917c00SJeff Kirsher }; 783f7917c00SJeff Kirsher 784f7917c00SJeff Kirsher /* 785f7917c00SJeff Kirsher * Generic command header flit0 786f7917c00SJeff Kirsher */ 787f7917c00SJeff Kirsher struct fw_cmd_hdr { 788f7917c00SJeff Kirsher __be32 hi; 789f7917c00SJeff Kirsher __be32 lo; 790f7917c00SJeff Kirsher }; 791f7917c00SJeff Kirsher 792e2ac9628SHariprasad Shenai #define FW_CMD_OP_S 24 793e2ac9628SHariprasad Shenai #define FW_CMD_OP_M 0xff 794e2ac9628SHariprasad Shenai #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S) 795e2ac9628SHariprasad Shenai #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M) 796e2ac9628SHariprasad Shenai 797e2ac9628SHariprasad Shenai #define FW_CMD_REQUEST_S 23 798e2ac9628SHariprasad Shenai #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S) 799e2ac9628SHariprasad Shenai #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U) 800e2ac9628SHariprasad Shenai 801e2ac9628SHariprasad Shenai #define FW_CMD_READ_S 22 802e2ac9628SHariprasad Shenai #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S) 803e2ac9628SHariprasad Shenai #define FW_CMD_READ_F FW_CMD_READ_V(1U) 804e2ac9628SHariprasad Shenai 805e2ac9628SHariprasad Shenai #define FW_CMD_WRITE_S 21 806e2ac9628SHariprasad Shenai #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S) 807e2ac9628SHariprasad Shenai #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U) 808e2ac9628SHariprasad Shenai 809e2ac9628SHariprasad Shenai #define FW_CMD_EXEC_S 20 810e2ac9628SHariprasad Shenai #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S) 811e2ac9628SHariprasad Shenai #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U) 812e2ac9628SHariprasad Shenai 813e2ac9628SHariprasad Shenai #define FW_CMD_RAMASK_S 20 814e2ac9628SHariprasad Shenai #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S) 815e2ac9628SHariprasad Shenai 816e2ac9628SHariprasad Shenai #define FW_CMD_RETVAL_S 8 817e2ac9628SHariprasad Shenai #define FW_CMD_RETVAL_M 0xff 818e2ac9628SHariprasad Shenai #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S) 819e2ac9628SHariprasad Shenai #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M) 820e2ac9628SHariprasad Shenai 821e2ac9628SHariprasad Shenai #define FW_CMD_LEN16_S 0 822e2ac9628SHariprasad Shenai #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S) 823e2ac9628SHariprasad Shenai 824e2ac9628SHariprasad Shenai #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16) 825f7917c00SJeff Kirsher 826f7917c00SJeff Kirsher enum fw_ldst_addrspc { 827f7917c00SJeff Kirsher FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 828f7917c00SJeff Kirsher FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 829f7917c00SJeff Kirsher FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 830f7917c00SJeff Kirsher FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 831f7917c00SJeff Kirsher FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 832f7917c00SJeff Kirsher FW_LDST_ADDRSPC_TP_PIO = 0x0010, 833f7917c00SJeff Kirsher FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 834f7917c00SJeff Kirsher FW_LDST_ADDRSPC_TP_MIB = 0x0012, 835f7917c00SJeff Kirsher FW_LDST_ADDRSPC_MDIO = 0x0018, 836f7917c00SJeff Kirsher FW_LDST_ADDRSPC_MPS = 0x0020, 837ce91a923SNaresh Kumar Inna FW_LDST_ADDRSPC_FUNC = 0x0028, 838ce91a923SNaresh Kumar Inna FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 839f56ec676SArjun Vynipadath FW_LDST_ADDRSPC_I2C = 0x0038, 840f7917c00SJeff Kirsher }; 841f7917c00SJeff Kirsher 842f7917c00SJeff Kirsher enum fw_ldst_mps_fid { 843f7917c00SJeff Kirsher FW_LDST_MPS_ATRB, 844f7917c00SJeff Kirsher FW_LDST_MPS_RPLC 845f7917c00SJeff Kirsher }; 846f7917c00SJeff Kirsher 847f7917c00SJeff Kirsher enum fw_ldst_func_access_ctl { 848f7917c00SJeff Kirsher FW_LDST_FUNC_ACC_CTL_VIID, 849f7917c00SJeff Kirsher FW_LDST_FUNC_ACC_CTL_FID 850f7917c00SJeff Kirsher }; 851f7917c00SJeff Kirsher 852f7917c00SJeff Kirsher enum fw_ldst_func_mod_index { 853f7917c00SJeff Kirsher FW_LDST_FUNC_MPS 854f7917c00SJeff Kirsher }; 855f7917c00SJeff Kirsher 856f7917c00SJeff Kirsher struct fw_ldst_cmd { 857f7917c00SJeff Kirsher __be32 op_to_addrspace; 858f7917c00SJeff Kirsher __be32 cycles_to_len16; 859f7917c00SJeff Kirsher union fw_ldst { 860f7917c00SJeff Kirsher struct fw_ldst_addrval { 861f7917c00SJeff Kirsher __be32 addr; 862f7917c00SJeff Kirsher __be32 val; 863f7917c00SJeff Kirsher } addrval; 864f7917c00SJeff Kirsher struct fw_ldst_idctxt { 865f7917c00SJeff Kirsher __be32 physid; 8665d700ecbSHariprasad Shenai __be32 msg_ctxtflush; 867f7917c00SJeff Kirsher __be32 ctxt_data7; 868f7917c00SJeff Kirsher __be32 ctxt_data6; 869f7917c00SJeff Kirsher __be32 ctxt_data5; 870f7917c00SJeff Kirsher __be32 ctxt_data4; 871f7917c00SJeff Kirsher __be32 ctxt_data3; 872f7917c00SJeff Kirsher __be32 ctxt_data2; 873f7917c00SJeff Kirsher __be32 ctxt_data1; 874f7917c00SJeff Kirsher __be32 ctxt_data0; 875f7917c00SJeff Kirsher } idctxt; 876f7917c00SJeff Kirsher struct fw_ldst_mdio { 877f7917c00SJeff Kirsher __be16 paddr_mmd; 878f7917c00SJeff Kirsher __be16 raddr; 879f7917c00SJeff Kirsher __be16 vctl; 880f7917c00SJeff Kirsher __be16 rval; 881f7917c00SJeff Kirsher } mdio; 882f2be053cSHariprasad Shenai struct fw_ldst_cim_rq { 883f2be053cSHariprasad Shenai u8 req_first64[8]; 884f2be053cSHariprasad Shenai u8 req_second64[8]; 885f2be053cSHariprasad Shenai u8 resp_first64[8]; 886f2be053cSHariprasad Shenai u8 resp_second64[8]; 887f2be053cSHariprasad Shenai __be32 r3[2]; 888f2be053cSHariprasad Shenai } cim_rq; 8893ccc6cf7SHariprasad Shenai union fw_ldst_mps { 8903ccc6cf7SHariprasad Shenai struct fw_ldst_mps_rplc { 8913ccc6cf7SHariprasad Shenai __be16 fid_idx; 892f7917c00SJeff Kirsher __be16 rplcpf_pkd; 8933ccc6cf7SHariprasad Shenai __be32 rplc255_224; 8943ccc6cf7SHariprasad Shenai __be32 rplc223_192; 8953ccc6cf7SHariprasad Shenai __be32 rplc191_160; 8963ccc6cf7SHariprasad Shenai __be32 rplc159_128; 897f7917c00SJeff Kirsher __be32 rplc127_96; 898f7917c00SJeff Kirsher __be32 rplc95_64; 899f7917c00SJeff Kirsher __be32 rplc63_32; 900f7917c00SJeff Kirsher __be32 rplc31_0; 9013ccc6cf7SHariprasad Shenai } rplc; 9023ccc6cf7SHariprasad Shenai struct fw_ldst_mps_atrb { 9033ccc6cf7SHariprasad Shenai __be16 fid_mpsid; 9043ccc6cf7SHariprasad Shenai __be16 r2[3]; 9053ccc6cf7SHariprasad Shenai __be32 r3[2]; 9063ccc6cf7SHariprasad Shenai __be32 r4; 907f7917c00SJeff Kirsher __be32 atrb; 908f7917c00SJeff Kirsher __be16 vlan[16]; 9093ccc6cf7SHariprasad Shenai } atrb; 910f7917c00SJeff Kirsher } mps; 911f7917c00SJeff Kirsher struct fw_ldst_func { 912f7917c00SJeff Kirsher u8 access_ctl; 913f7917c00SJeff Kirsher u8 mod_index; 914f7917c00SJeff Kirsher __be16 ctl_id; 915f7917c00SJeff Kirsher __be32 offset; 916f7917c00SJeff Kirsher __be64 data0; 917f7917c00SJeff Kirsher __be64 data1; 918f7917c00SJeff Kirsher } func; 919ce91a923SNaresh Kumar Inna struct fw_ldst_pcie { 920ce91a923SNaresh Kumar Inna u8 ctrl_to_fn; 921ce91a923SNaresh Kumar Inna u8 bnum; 922ce91a923SNaresh Kumar Inna u8 r; 923ce91a923SNaresh Kumar Inna u8 ext_r; 924ce91a923SNaresh Kumar Inna u8 select_naccess; 925ce91a923SNaresh Kumar Inna u8 pcie_fn; 926ce91a923SNaresh Kumar Inna __be16 nset_pkd; 927ce91a923SNaresh Kumar Inna __be32 data[12]; 928ce91a923SNaresh Kumar Inna } pcie; 929f2be053cSHariprasad Shenai struct fw_ldst_i2c_deprecated { 930f2be053cSHariprasad Shenai u8 pid_pkd; 931f2be053cSHariprasad Shenai u8 base; 932f2be053cSHariprasad Shenai u8 boffset; 933f2be053cSHariprasad Shenai u8 data; 934f2be053cSHariprasad Shenai __be32 r9; 935f2be053cSHariprasad Shenai } i2c_deprecated; 936f2be053cSHariprasad Shenai struct fw_ldst_i2c { 937f2be053cSHariprasad Shenai u8 pid; 938f2be053cSHariprasad Shenai u8 did; 939f2be053cSHariprasad Shenai u8 boffset; 940f2be053cSHariprasad Shenai u8 blen; 941f2be053cSHariprasad Shenai __be32 r9; 942f2be053cSHariprasad Shenai __u8 data[48]; 943f2be053cSHariprasad Shenai } i2c; 944f2be053cSHariprasad Shenai struct fw_ldst_le { 945f2be053cSHariprasad Shenai __be32 index; 946f2be053cSHariprasad Shenai __be32 r9; 947f2be053cSHariprasad Shenai u8 val[33]; 948f2be053cSHariprasad Shenai u8 r11[7]; 949f2be053cSHariprasad Shenai } le; 950f7917c00SJeff Kirsher } u; 951f7917c00SJeff Kirsher }; 952f7917c00SJeff Kirsher 953f2be053cSHariprasad Shenai #define FW_LDST_CMD_ADDRSPACE_S 0 954f2be053cSHariprasad Shenai #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S) 955f2be053cSHariprasad Shenai 9565167865aSHariprasad Shenai #define FW_LDST_CMD_MSG_S 31 9575167865aSHariprasad Shenai #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S) 9585167865aSHariprasad Shenai 9595d700ecbSHariprasad Shenai #define FW_LDST_CMD_CTXTFLUSH_S 30 9605d700ecbSHariprasad Shenai #define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S) 9615d700ecbSHariprasad Shenai #define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U) 9625d700ecbSHariprasad Shenai 9635167865aSHariprasad Shenai #define FW_LDST_CMD_PADDR_S 8 9645167865aSHariprasad Shenai #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S) 9655167865aSHariprasad Shenai 9665167865aSHariprasad Shenai #define FW_LDST_CMD_MMD_S 0 9675167865aSHariprasad Shenai #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S) 9685167865aSHariprasad Shenai 9695167865aSHariprasad Shenai #define FW_LDST_CMD_FID_S 15 9705167865aSHariprasad Shenai #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S) 9715167865aSHariprasad Shenai 9723ccc6cf7SHariprasad Shenai #define FW_LDST_CMD_IDX_S 0 9733ccc6cf7SHariprasad Shenai #define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S) 9745167865aSHariprasad Shenai 9755167865aSHariprasad Shenai #define FW_LDST_CMD_RPLCPF_S 0 9765167865aSHariprasad Shenai #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S) 9775167865aSHariprasad Shenai 9785167865aSHariprasad Shenai #define FW_LDST_CMD_LC_S 4 9795167865aSHariprasad Shenai #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S) 9805167865aSHariprasad Shenai #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U) 9815167865aSHariprasad Shenai 9825167865aSHariprasad Shenai #define FW_LDST_CMD_FN_S 0 9835167865aSHariprasad Shenai #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S) 9845167865aSHariprasad Shenai 9855167865aSHariprasad Shenai #define FW_LDST_CMD_NACCESS_S 0 9865167865aSHariprasad Shenai #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S) 987f7917c00SJeff Kirsher 988f7917c00SJeff Kirsher struct fw_reset_cmd { 989f7917c00SJeff Kirsher __be32 op_to_write; 990f7917c00SJeff Kirsher __be32 retval_len16; 991f7917c00SJeff Kirsher __be32 val; 99226f7cbc0SVipul Pandya __be32 halt_pkd; 993f7917c00SJeff Kirsher }; 994f7917c00SJeff Kirsher 9955167865aSHariprasad Shenai #define FW_RESET_CMD_HALT_S 31 9965167865aSHariprasad Shenai #define FW_RESET_CMD_HALT_M 0x1 9975167865aSHariprasad Shenai #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S) 9985167865aSHariprasad Shenai #define FW_RESET_CMD_HALT_G(x) \ 9995167865aSHariprasad Shenai (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M) 10005167865aSHariprasad Shenai #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U) 100126f7cbc0SVipul Pandya 1002636f9d37SVipul Pandya enum fw_hellow_cmd { 1003636f9d37SVipul Pandya fw_hello_cmd_stage_os = 0x0 1004636f9d37SVipul Pandya }; 1005636f9d37SVipul Pandya 1006f7917c00SJeff Kirsher struct fw_hello_cmd { 1007f7917c00SJeff Kirsher __be32 op_to_write; 1008f7917c00SJeff Kirsher __be32 retval_len16; 1009ce91a923SNaresh Kumar Inna __be32 err_to_clearinit; 1010f7917c00SJeff Kirsher __be32 fwrev; 1011f7917c00SJeff Kirsher }; 1012f7917c00SJeff Kirsher 10135167865aSHariprasad Shenai #define FW_HELLO_CMD_ERR_S 31 10145167865aSHariprasad Shenai #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S) 10155167865aSHariprasad Shenai #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U) 10165167865aSHariprasad Shenai 10175167865aSHariprasad Shenai #define FW_HELLO_CMD_INIT_S 30 10185167865aSHariprasad Shenai #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S) 10195167865aSHariprasad Shenai #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U) 10205167865aSHariprasad Shenai 10215167865aSHariprasad Shenai #define FW_HELLO_CMD_MASTERDIS_S 29 10225167865aSHariprasad Shenai #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S) 10235167865aSHariprasad Shenai 10245167865aSHariprasad Shenai #define FW_HELLO_CMD_MASTERFORCE_S 28 10255167865aSHariprasad Shenai #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S) 10265167865aSHariprasad Shenai 10275167865aSHariprasad Shenai #define FW_HELLO_CMD_MBMASTER_S 24 10285167865aSHariprasad Shenai #define FW_HELLO_CMD_MBMASTER_M 0xfU 10295167865aSHariprasad Shenai #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S) 10305167865aSHariprasad Shenai #define FW_HELLO_CMD_MBMASTER_G(x) \ 10315167865aSHariprasad Shenai (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M) 10325167865aSHariprasad Shenai 10335167865aSHariprasad Shenai #define FW_HELLO_CMD_MBASYNCNOTINT_S 23 10345167865aSHariprasad Shenai #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S) 10355167865aSHariprasad Shenai 10365167865aSHariprasad Shenai #define FW_HELLO_CMD_MBASYNCNOT_S 20 10375167865aSHariprasad Shenai #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S) 10385167865aSHariprasad Shenai 10395167865aSHariprasad Shenai #define FW_HELLO_CMD_STAGE_S 17 10405167865aSHariprasad Shenai #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S) 10415167865aSHariprasad Shenai 10425167865aSHariprasad Shenai #define FW_HELLO_CMD_CLEARINIT_S 16 10435167865aSHariprasad Shenai #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S) 10445167865aSHariprasad Shenai #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U) 10455167865aSHariprasad Shenai 1046f7917c00SJeff Kirsher struct fw_bye_cmd { 1047f7917c00SJeff Kirsher __be32 op_to_write; 1048f7917c00SJeff Kirsher __be32 retval_len16; 1049f7917c00SJeff Kirsher __be64 r3; 1050f7917c00SJeff Kirsher }; 1051f7917c00SJeff Kirsher 1052f7917c00SJeff Kirsher struct fw_initialize_cmd { 1053f7917c00SJeff Kirsher __be32 op_to_write; 1054f7917c00SJeff Kirsher __be32 retval_len16; 1055f7917c00SJeff Kirsher __be64 r3; 1056f7917c00SJeff Kirsher }; 1057f7917c00SJeff Kirsher 1058f7917c00SJeff Kirsher enum fw_caps_config_hm { 1059f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 1060f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_PL = 0x00000002, 1061f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_SGE = 0x00000004, 1062f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_CIM = 0x00000008, 1063f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 1064f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_TP = 0x00000020, 1065f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 1066f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 1067f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 1068f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_MC = 0x00000200, 1069f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_LE = 0x00000400, 1070f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_MPS = 0x00000800, 1071f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 1072f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 1073f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 1074f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_MI = 0x00008000, 1075f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 1076f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 1077f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_SMB = 0x00040000, 1078f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_MA = 0x00080000, 1079f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 1080f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_PMU = 0x00200000, 1081f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_UART = 0x00400000, 1082f7917c00SJeff Kirsher FW_CAPS_CONFIG_HM_SF = 0x00800000, 1083f7917c00SJeff Kirsher }; 1084f7917c00SJeff Kirsher 1085f7917c00SJeff Kirsher enum fw_caps_config_nbm { 1086f7917c00SJeff Kirsher FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 1087f7917c00SJeff Kirsher FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 1088f7917c00SJeff Kirsher }; 1089f7917c00SJeff Kirsher 1090f7917c00SJeff Kirsher enum fw_caps_config_link { 1091f7917c00SJeff Kirsher FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 1092f7917c00SJeff Kirsher FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 1093f7917c00SJeff Kirsher FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 1094f7917c00SJeff Kirsher }; 1095f7917c00SJeff Kirsher 1096f7917c00SJeff Kirsher enum fw_caps_config_switch { 1097f7917c00SJeff Kirsher FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 1098f7917c00SJeff Kirsher FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 1099f7917c00SJeff Kirsher }; 1100f7917c00SJeff Kirsher 1101f7917c00SJeff Kirsher enum fw_caps_config_nic { 1102f7917c00SJeff Kirsher FW_CAPS_CONFIG_NIC = 0x00000001, 1103f7917c00SJeff Kirsher FW_CAPS_CONFIG_NIC_VM = 0x00000002, 11045c31254eSKumar Sanghvi FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 1105f7917c00SJeff Kirsher }; 1106f7917c00SJeff Kirsher 1107f7917c00SJeff Kirsher enum fw_caps_config_ofld { 1108f7917c00SJeff Kirsher FW_CAPS_CONFIG_OFLD = 0x00000001, 1109f7917c00SJeff Kirsher }; 1110f7917c00SJeff Kirsher 1111f7917c00SJeff Kirsher enum fw_caps_config_rdma { 1112f7917c00SJeff Kirsher FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 1113f7917c00SJeff Kirsher FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 1114f7917c00SJeff Kirsher }; 1115f7917c00SJeff Kirsher 1116f7917c00SJeff Kirsher enum fw_caps_config_iscsi { 1117f7917c00SJeff Kirsher FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 1118f7917c00SJeff Kirsher FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 1119f7917c00SJeff Kirsher FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 1120f7917c00SJeff Kirsher FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 1121f7917c00SJeff Kirsher }; 1122f7917c00SJeff Kirsher 1123f7917c00SJeff Kirsher enum fw_caps_config_fcoe { 1124f7917c00SJeff Kirsher FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 1125f7917c00SJeff Kirsher FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 1126ce91a923SNaresh Kumar Inna FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 1127f7917c00SJeff Kirsher }; 1128f7917c00SJeff Kirsher 112952367a76SVipul Pandya enum fw_memtype_cf { 113052367a76SVipul Pandya FW_MEMTYPE_CF_EDC0 = 0x0, 113152367a76SVipul Pandya FW_MEMTYPE_CF_EDC1 = 0x1, 113252367a76SVipul Pandya FW_MEMTYPE_CF_EXTMEM = 0x2, 113352367a76SVipul Pandya FW_MEMTYPE_CF_FLASH = 0x4, 113452367a76SVipul Pandya FW_MEMTYPE_CF_INTERNAL = 0x5, 11357ef65a42SHariprasad Shenai FW_MEMTYPE_CF_EXTMEM1 = 0x6, 11368b4e6b3cSArjun Vynipadath FW_MEMTYPE_CF_HMA = 0x7, 113752367a76SVipul Pandya }; 113852367a76SVipul Pandya 1139f7917c00SJeff Kirsher struct fw_caps_config_cmd { 1140f7917c00SJeff Kirsher __be32 op_to_write; 1141ce91a923SNaresh Kumar Inna __be32 cfvalid_to_len16; 1142f7917c00SJeff Kirsher __be32 r2; 1143f7917c00SJeff Kirsher __be32 hwmbitmap; 1144f7917c00SJeff Kirsher __be16 nbmcaps; 1145f7917c00SJeff Kirsher __be16 linkcaps; 1146f7917c00SJeff Kirsher __be16 switchcaps; 1147f7917c00SJeff Kirsher __be16 r3; 1148f7917c00SJeff Kirsher __be16 niccaps; 1149f7917c00SJeff Kirsher __be16 ofldcaps; 1150f7917c00SJeff Kirsher __be16 rdmacaps; 115194cdb8bbSHariprasad Shenai __be16 cryptocaps; 1152f7917c00SJeff Kirsher __be16 iscsicaps; 1153f7917c00SJeff Kirsher __be16 fcoecaps; 115452367a76SVipul Pandya __be32 cfcsum; 115552367a76SVipul Pandya __be32 finiver; 115652367a76SVipul Pandya __be32 finicsum; 1157f7917c00SJeff Kirsher }; 1158f7917c00SJeff Kirsher 11595167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_CFVALID_S 27 11605167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S) 11615167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U) 11625167865aSHariprasad Shenai 11635167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24 11645167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \ 11655167865aSHariprasad Shenai ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S) 11665167865aSHariprasad Shenai 11675167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16 11685167865aSHariprasad Shenai #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \ 11695167865aSHariprasad Shenai ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S) 117052367a76SVipul Pandya 1171f7917c00SJeff Kirsher /* 1172f7917c00SJeff Kirsher * params command mnemonics 1173f7917c00SJeff Kirsher */ 1174f7917c00SJeff Kirsher enum fw_params_mnem { 1175f7917c00SJeff Kirsher FW_PARAMS_MNEM_DEV = 1, /* device params */ 1176f7917c00SJeff Kirsher FW_PARAMS_MNEM_PFVF = 2, /* function params */ 1177f7917c00SJeff Kirsher FW_PARAMS_MNEM_REG = 3, /* limited register access */ 1178f7917c00SJeff Kirsher FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 11797ef65a42SHariprasad Shenai FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 1180f7917c00SJeff Kirsher FW_PARAMS_MNEM_LAST 1181f7917c00SJeff Kirsher }; 1182f7917c00SJeff Kirsher 1183f7917c00SJeff Kirsher /* 1184f7917c00SJeff Kirsher * device parameters 1185f7917c00SJeff Kirsher */ 1186f7917c00SJeff Kirsher enum fw_params_param_dev { 1187f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 1188f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 1189f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 1190f7917c00SJeff Kirsher * allocated by the device's 1191f7917c00SJeff Kirsher * Lookup Engine 1192f7917c00SJeff Kirsher */ 1193f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 1194f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04, 1195f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05, 1196f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06, 1197f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07, 1198f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08, 1199f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09, 1200f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A, 1201f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 1202f7917c00SJeff Kirsher FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 120352367a76SVipul Pandya FW_PARAMS_PARAM_DEV_CF = 0x0D, 120401b69614SHariprasad Shenai FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 120570a5f3bbSHariprasad Shenai FW_PARAMS_PARAM_DEV_DIAG = 0x11, 12064c2c5763SHariprasad Shenai FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */ 12074c2c5763SHariprasad Shenai FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */ 12081ac0f095SKumar Sanghvi FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 120949216c1cSHariprasad Shenai FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 1210760446f9SGanesh Goudar FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 1211760446f9SGanesh Goudar FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 1212086de575SSteve Wise FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 12130ff90994SKumar Sanghvi FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 12148f46d467SArjun Vynipadath FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 12158b4e6b3cSArjun Vynipadath FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 1216f7917c00SJeff Kirsher }; 1217f7917c00SJeff Kirsher 1218f7917c00SJeff Kirsher /* 1219f7917c00SJeff Kirsher * physical and virtual function parameters 1220f7917c00SJeff Kirsher */ 1221f7917c00SJeff Kirsher enum fw_params_param_pfvf { 1222f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 1223f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 1224f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 1225f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 1226f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 1227f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 1228f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 1229f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 1230f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 1231f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 1232f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 1233f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 1234f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 1235f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 1236f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 1237f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 1238f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 1239f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 1240f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 1241f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 1242f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 1243f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 1244f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 1245f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 1246f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 1247*a3cdaa69SRaju Rangoju FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 1248*a3cdaa69SRaju Rangoju FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 1249f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 1250f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_VIID = 0x24, 1251f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 1252f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 1253f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 1254f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 1255f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 1256f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 1257f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 1258f7917c00SJeff Kirsher FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 125952367a76SVipul Pandya FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 1260b407a4a9SVipul Pandya FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 12619030e498SRahul Lakkireddy FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 1262b407a4a9SVipul Pandya FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 126372a56ca9SHarsh Jain FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 12649030e498SRahul Lakkireddy FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 12659030e498SRahul Lakkireddy FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 12669030e498SRahul Lakkireddy FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 1267c3168cabSGanesh Goudar FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 1268f7917c00SJeff Kirsher }; 1269f7917c00SJeff Kirsher 1270f7917c00SJeff Kirsher /* 1271f7917c00SJeff Kirsher * dma queue parameters 1272f7917c00SJeff Kirsher */ 1273f7917c00SJeff Kirsher enum fw_params_param_dmaq { 1274f7917c00SJeff Kirsher FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 1275f7917c00SJeff Kirsher FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 1276f7917c00SJeff Kirsher FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 1277f7917c00SJeff Kirsher FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 1278f7917c00SJeff Kirsher FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 1279989594e2SAnish Bhatt FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 1280b8b1ae99SHariprasad Shenai FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 1281f7917c00SJeff Kirsher }; 1282f7917c00SJeff Kirsher 128301b69614SHariprasad Shenai enum fw_params_param_dev_phyfw { 128401b69614SHariprasad Shenai FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 128501b69614SHariprasad Shenai FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 128601b69614SHariprasad Shenai }; 128701b69614SHariprasad Shenai 128870a5f3bbSHariprasad Shenai enum fw_params_param_dev_diag { 128970a5f3bbSHariprasad Shenai FW_PARAM_DEV_DIAG_TMP = 0x00, 129070a5f3bbSHariprasad Shenai FW_PARAM_DEV_DIAG_VDD = 0x01, 129170a5f3bbSHariprasad Shenai }; 129270a5f3bbSHariprasad Shenai 129349216c1cSHariprasad Shenai enum fw_params_param_dev_fwcache { 129449216c1cSHariprasad Shenai FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 129549216c1cSHariprasad Shenai FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 129649216c1cSHariprasad Shenai }; 129749216c1cSHariprasad Shenai 12985167865aSHariprasad Shenai #define FW_PARAMS_MNEM_S 24 12995167865aSHariprasad Shenai #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S) 13005167865aSHariprasad Shenai 13015167865aSHariprasad Shenai #define FW_PARAMS_PARAM_X_S 16 13025167865aSHariprasad Shenai #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S) 13035167865aSHariprasad Shenai 13045167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Y_S 8 13055167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Y_M 0xffU 13065167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S) 13075167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\ 13085167865aSHariprasad Shenai FW_PARAMS_PARAM_Y_M) 13095167865aSHariprasad Shenai 13105167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Z_S 0 13115167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Z_M 0xffu 13125167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S) 13135167865aSHariprasad Shenai #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\ 13145167865aSHariprasad Shenai FW_PARAMS_PARAM_Z_M) 13155167865aSHariprasad Shenai 13165167865aSHariprasad Shenai #define FW_PARAMS_PARAM_XYZ_S 0 13175167865aSHariprasad Shenai #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S) 13185167865aSHariprasad Shenai 13195167865aSHariprasad Shenai #define FW_PARAMS_PARAM_YZ_S 0 13205167865aSHariprasad Shenai #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S) 1321f7917c00SJeff Kirsher 1322f7917c00SJeff Kirsher struct fw_params_cmd { 1323f7917c00SJeff Kirsher __be32 op_to_vfn; 1324f7917c00SJeff Kirsher __be32 retval_len16; 1325f7917c00SJeff Kirsher struct fw_params_param { 1326f7917c00SJeff Kirsher __be32 mnem; 1327f7917c00SJeff Kirsher __be32 val; 1328f7917c00SJeff Kirsher } param[7]; 1329f7917c00SJeff Kirsher }; 1330f7917c00SJeff Kirsher 13315167865aSHariprasad Shenai #define FW_PARAMS_CMD_PFN_S 8 13325167865aSHariprasad Shenai #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S) 13335167865aSHariprasad Shenai 13345167865aSHariprasad Shenai #define FW_PARAMS_CMD_VFN_S 0 13355167865aSHariprasad Shenai #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S) 1336f7917c00SJeff Kirsher 1337f7917c00SJeff Kirsher struct fw_pfvf_cmd { 1338f7917c00SJeff Kirsher __be32 op_to_vfn; 1339f7917c00SJeff Kirsher __be32 retval_len16; 1340f7917c00SJeff Kirsher __be32 niqflint_niq; 1341f7917c00SJeff Kirsher __be32 type_to_neq; 1342f7917c00SJeff Kirsher __be32 tc_to_nexactf; 1343f7917c00SJeff Kirsher __be32 r_caps_to_nethctrl; 1344f7917c00SJeff Kirsher __be16 nricq; 1345f7917c00SJeff Kirsher __be16 nriqp; 1346f7917c00SJeff Kirsher __be32 r4; 1347f7917c00SJeff Kirsher }; 1348f7917c00SJeff Kirsher 13495167865aSHariprasad Shenai #define FW_PFVF_CMD_PFN_S 8 13505167865aSHariprasad Shenai #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S) 1351f7917c00SJeff Kirsher 13525167865aSHariprasad Shenai #define FW_PFVF_CMD_VFN_S 0 13535167865aSHariprasad Shenai #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S) 1354f7917c00SJeff Kirsher 13555167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQFLINT_S 20 13565167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQFLINT_M 0xfff 13575167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S) 13585167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQFLINT_G(x) \ 13595167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M) 1360f7917c00SJeff Kirsher 13615167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQ_S 0 13625167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQ_M 0xfffff 13635167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S) 13645167865aSHariprasad Shenai #define FW_PFVF_CMD_NIQ_G(x) \ 13655167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M) 1366f7917c00SJeff Kirsher 13675167865aSHariprasad Shenai #define FW_PFVF_CMD_TYPE_S 31 13685167865aSHariprasad Shenai #define FW_PFVF_CMD_TYPE_M 0x1 13695167865aSHariprasad Shenai #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S) 13705167865aSHariprasad Shenai #define FW_PFVF_CMD_TYPE_G(x) \ 13715167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M) 13725167865aSHariprasad Shenai #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U) 1373f7917c00SJeff Kirsher 13745167865aSHariprasad Shenai #define FW_PFVF_CMD_CMASK_S 24 13755167865aSHariprasad Shenai #define FW_PFVF_CMD_CMASK_M 0xf 13765167865aSHariprasad Shenai #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S) 13775167865aSHariprasad Shenai #define FW_PFVF_CMD_CMASK_G(x) \ 13785167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M) 1379f7917c00SJeff Kirsher 13805167865aSHariprasad Shenai #define FW_PFVF_CMD_PMASK_S 20 13815167865aSHariprasad Shenai #define FW_PFVF_CMD_PMASK_M 0xf 13825167865aSHariprasad Shenai #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S) 13835167865aSHariprasad Shenai #define FW_PFVF_CMD_PMASK_G(x) \ 13845167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M) 1385f7917c00SJeff Kirsher 13865167865aSHariprasad Shenai #define FW_PFVF_CMD_NEQ_S 0 13875167865aSHariprasad Shenai #define FW_PFVF_CMD_NEQ_M 0xfffff 13885167865aSHariprasad Shenai #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S) 13895167865aSHariprasad Shenai #define FW_PFVF_CMD_NEQ_G(x) \ 13905167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M) 1391f7917c00SJeff Kirsher 13925167865aSHariprasad Shenai #define FW_PFVF_CMD_TC_S 24 13935167865aSHariprasad Shenai #define FW_PFVF_CMD_TC_M 0xff 13945167865aSHariprasad Shenai #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S) 13955167865aSHariprasad Shenai #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M) 1396f7917c00SJeff Kirsher 13975167865aSHariprasad Shenai #define FW_PFVF_CMD_NVI_S 16 13985167865aSHariprasad Shenai #define FW_PFVF_CMD_NVI_M 0xff 13995167865aSHariprasad Shenai #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S) 14005167865aSHariprasad Shenai #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M) 1401f7917c00SJeff Kirsher 14025167865aSHariprasad Shenai #define FW_PFVF_CMD_NEXACTF_S 0 14035167865aSHariprasad Shenai #define FW_PFVF_CMD_NEXACTF_M 0xffff 14045167865aSHariprasad Shenai #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S) 14055167865aSHariprasad Shenai #define FW_PFVF_CMD_NEXACTF_G(x) \ 14065167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M) 1407f7917c00SJeff Kirsher 14085167865aSHariprasad Shenai #define FW_PFVF_CMD_R_CAPS_S 24 14095167865aSHariprasad Shenai #define FW_PFVF_CMD_R_CAPS_M 0xff 14105167865aSHariprasad Shenai #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S) 14115167865aSHariprasad Shenai #define FW_PFVF_CMD_R_CAPS_G(x) \ 14125167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M) 1413f7917c00SJeff Kirsher 14145167865aSHariprasad Shenai #define FW_PFVF_CMD_WX_CAPS_S 16 14155167865aSHariprasad Shenai #define FW_PFVF_CMD_WX_CAPS_M 0xff 14165167865aSHariprasad Shenai #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S) 14175167865aSHariprasad Shenai #define FW_PFVF_CMD_WX_CAPS_G(x) \ 14185167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M) 14195167865aSHariprasad Shenai 14205167865aSHariprasad Shenai #define FW_PFVF_CMD_NETHCTRL_S 0 14215167865aSHariprasad Shenai #define FW_PFVF_CMD_NETHCTRL_M 0xffff 14225167865aSHariprasad Shenai #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S) 14235167865aSHariprasad Shenai #define FW_PFVF_CMD_NETHCTRL_G(x) \ 14245167865aSHariprasad Shenai (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M) 1425f7917c00SJeff Kirsher 1426f7917c00SJeff Kirsher enum fw_iq_type { 1427f7917c00SJeff Kirsher FW_IQ_TYPE_FL_INT_CAP, 1428f7917c00SJeff Kirsher FW_IQ_TYPE_NO_FL_INT_CAP 1429f7917c00SJeff Kirsher }; 1430f7917c00SJeff Kirsher 1431f7917c00SJeff Kirsher struct fw_iq_cmd { 1432f7917c00SJeff Kirsher __be32 op_to_vfn; 1433f7917c00SJeff Kirsher __be32 alloc_to_len16; 1434f7917c00SJeff Kirsher __be16 physiqid; 1435f7917c00SJeff Kirsher __be16 iqid; 1436f7917c00SJeff Kirsher __be16 fl0id; 1437f7917c00SJeff Kirsher __be16 fl1id; 1438f7917c00SJeff Kirsher __be32 type_to_iqandstindex; 1439f7917c00SJeff Kirsher __be16 iqdroprss_to_iqesize; 1440f7917c00SJeff Kirsher __be16 iqsize; 1441f7917c00SJeff Kirsher __be64 iqaddr; 1442f7917c00SJeff Kirsher __be32 iqns_to_fl0congen; 1443f7917c00SJeff Kirsher __be16 fl0dcaen_to_fl0cidxfthresh; 1444f7917c00SJeff Kirsher __be16 fl0size; 1445f7917c00SJeff Kirsher __be64 fl0addr; 1446f7917c00SJeff Kirsher __be32 fl1cngchmap_to_fl1congen; 1447f7917c00SJeff Kirsher __be16 fl1dcaen_to_fl1cidxfthresh; 1448f7917c00SJeff Kirsher __be16 fl1size; 1449f7917c00SJeff Kirsher __be64 fl1addr; 1450f7917c00SJeff Kirsher }; 1451f7917c00SJeff Kirsher 14526e4b51a6SHariprasad Shenai #define FW_IQ_CMD_PFN_S 8 14536e4b51a6SHariprasad Shenai #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S) 1454f7917c00SJeff Kirsher 14556e4b51a6SHariprasad Shenai #define FW_IQ_CMD_VFN_S 0 14566e4b51a6SHariprasad Shenai #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S) 1457f7917c00SJeff Kirsher 14586e4b51a6SHariprasad Shenai #define FW_IQ_CMD_ALLOC_S 31 14596e4b51a6SHariprasad Shenai #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S) 14606e4b51a6SHariprasad Shenai #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U) 1461f7917c00SJeff Kirsher 14626e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FREE_S 30 14636e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S) 14646e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U) 1465f7917c00SJeff Kirsher 14666e4b51a6SHariprasad Shenai #define FW_IQ_CMD_MODIFY_S 29 14676e4b51a6SHariprasad Shenai #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S) 14686e4b51a6SHariprasad Shenai #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U) 1469f7917c00SJeff Kirsher 14706e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTART_S 28 14716e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S) 14726e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U) 1473f7917c00SJeff Kirsher 14746e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTOP_S 27 14756e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S) 14766e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U) 1477f7917c00SJeff Kirsher 14786e4b51a6SHariprasad Shenai #define FW_IQ_CMD_TYPE_S 29 14796e4b51a6SHariprasad Shenai #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S) 14806e4b51a6SHariprasad Shenai 14816e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQASYNCH_S 28 14826e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S) 14836e4b51a6SHariprasad Shenai 14846e4b51a6SHariprasad Shenai #define FW_IQ_CMD_VIID_S 16 14856e4b51a6SHariprasad Shenai #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S) 14866e4b51a6SHariprasad Shenai 14876e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANDST_S 15 14886e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S) 14896e4b51a6SHariprasad Shenai 14906e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANUS_S 14 14916e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S) 14926e4b51a6SHariprasad Shenai 14936e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANUD_S 12 14946e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S) 14956e4b51a6SHariprasad Shenai 14966e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANDSTINDEX_S 0 14976e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S) 14986e4b51a6SHariprasad Shenai 14996e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDROPRSS_S 15 15006e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S) 15016e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U) 15026e4b51a6SHariprasad Shenai 15036e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQGTSMODE_S 14 15046e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S) 15056e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U) 15066e4b51a6SHariprasad Shenai 15076e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQPCIECH_S 12 15086e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S) 15096e4b51a6SHariprasad Shenai 15106e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDCAEN_S 11 15116e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S) 15126e4b51a6SHariprasad Shenai 15136e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDCACPU_S 6 15146e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S) 15156e4b51a6SHariprasad Shenai 15166e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQINTCNTTHRESH_S 4 15176e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S) 15186e4b51a6SHariprasad Shenai 15196e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQO_S 3 15206e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S) 15216e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U) 15226e4b51a6SHariprasad Shenai 15236e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQCPRIO_S 2 15246e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S) 15256e4b51a6SHariprasad Shenai 15266e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQESIZE_S 0 15276e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S) 15286e4b51a6SHariprasad Shenai 15296e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQNS_S 31 15306e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S) 15316e4b51a6SHariprasad Shenai 15326e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQRO_S 30 15336e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S) 15346e4b51a6SHariprasad Shenai 15356e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTIQHSEN_S 28 15366e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S) 15376e4b51a6SHariprasad Shenai 15386e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTCONGEN_S 27 15396e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S) 1540145ef8a5SHariprasad Shenai #define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U) 15416e4b51a6SHariprasad Shenai 15426e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTISCSIC_S 26 15436e4b51a6SHariprasad Shenai #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S) 15446e4b51a6SHariprasad Shenai 15456e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CNGCHMAP_S 20 15466e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S) 15476e4b51a6SHariprasad Shenai 15486e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CACHELOCK_S 15 15496e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S) 15506e4b51a6SHariprasad Shenai 15516e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DBP_S 14 15526e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S) 15536e4b51a6SHariprasad Shenai 15546e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DATANS_S 13 15556e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S) 15566e4b51a6SHariprasad Shenai 15576e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DATARO_S 12 15586e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S) 15596e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U) 15606e4b51a6SHariprasad Shenai 15616e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CONGCIF_S 11 15626e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S) 1563145ef8a5SHariprasad Shenai #define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U) 15646e4b51a6SHariprasad Shenai 15656e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0ONCHIP_S 10 15666e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S) 15676e4b51a6SHariprasad Shenai 15686e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0STATUSPGNS_S 9 15696e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S) 15706e4b51a6SHariprasad Shenai 15716e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0STATUSPGRO_S 8 15726e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S) 15736e4b51a6SHariprasad Shenai 15746e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FETCHNS_S 7 15756e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S) 15766e4b51a6SHariprasad Shenai 15776e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FETCHRO_S 6 15786e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S) 15796e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U) 15806e4b51a6SHariprasad Shenai 15816e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0HOSTFCMODE_S 4 15826e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S) 15836e4b51a6SHariprasad Shenai 15846e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CPRIO_S 3 15856e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S) 15866e4b51a6SHariprasad Shenai 15876e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PADEN_S 2 15886e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S) 15896e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U) 15906e4b51a6SHariprasad Shenai 15916e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PACKEN_S 1 15926e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S) 15936e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U) 15946e4b51a6SHariprasad Shenai 15956e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CONGEN_S 0 15966e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S) 15976e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U) 15986e4b51a6SHariprasad Shenai 15996e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DCAEN_S 15 16006e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S) 16016e4b51a6SHariprasad Shenai 16026e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DCACPU_S 10 16036e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S) 16046e4b51a6SHariprasad Shenai 16056e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FBMIN_S 7 16066e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S) 16076e4b51a6SHariprasad Shenai 16086e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FBMAX_S 4 16096e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S) 16106e4b51a6SHariprasad Shenai 16116e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3 16126e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S) 16136e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U) 16146e4b51a6SHariprasad Shenai 16156e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0 16166e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S) 16176e4b51a6SHariprasad Shenai 16186e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CNGCHMAP_S 20 16196e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S) 16206e4b51a6SHariprasad Shenai 16216e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CACHELOCK_S 15 16226e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S) 16236e4b51a6SHariprasad Shenai 16246e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DBP_S 14 16256e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S) 16266e4b51a6SHariprasad Shenai 16276e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DATANS_S 13 16286e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S) 16296e4b51a6SHariprasad Shenai 16306e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DATARO_S 12 16316e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S) 16326e4b51a6SHariprasad Shenai 16336e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CONGCIF_S 11 16346e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S) 16356e4b51a6SHariprasad Shenai 16366e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1ONCHIP_S 10 16376e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S) 16386e4b51a6SHariprasad Shenai 16396e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1STATUSPGNS_S 9 16406e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S) 16416e4b51a6SHariprasad Shenai 16426e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1STATUSPGRO_S 8 16436e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S) 16446e4b51a6SHariprasad Shenai 16456e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FETCHNS_S 7 16466e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S) 16476e4b51a6SHariprasad Shenai 16486e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FETCHRO_S 6 16496e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S) 16506e4b51a6SHariprasad Shenai 16516e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1HOSTFCMODE_S 4 16526e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S) 16536e4b51a6SHariprasad Shenai 16546e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CPRIO_S 3 16556e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S) 16566e4b51a6SHariprasad Shenai 16576e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PADEN_S 2 16586e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S) 16596e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U) 16606e4b51a6SHariprasad Shenai 16616e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PACKEN_S 1 16626e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S) 16636e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U) 16646e4b51a6SHariprasad Shenai 16656e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CONGEN_S 0 16666e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S) 16676e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U) 16686e4b51a6SHariprasad Shenai 16696e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DCAEN_S 15 16706e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S) 16716e4b51a6SHariprasad Shenai 16726e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DCACPU_S 10 16736e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S) 16746e4b51a6SHariprasad Shenai 16756e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FBMIN_S 7 16766e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S) 16776e4b51a6SHariprasad Shenai 16786e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FBMAX_S 4 16796e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S) 16806e4b51a6SHariprasad Shenai 16816e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3 16826e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S) 16836e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U) 16846e4b51a6SHariprasad Shenai 16856e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0 16866e4b51a6SHariprasad Shenai #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S) 1687f7917c00SJeff Kirsher 1688f7917c00SJeff Kirsher struct fw_eq_eth_cmd { 1689f7917c00SJeff Kirsher __be32 op_to_vfn; 1690f7917c00SJeff Kirsher __be32 alloc_to_len16; 1691f7917c00SJeff Kirsher __be32 eqid_pkd; 1692f7917c00SJeff Kirsher __be32 physeqid_pkd; 1693f7917c00SJeff Kirsher __be32 fetchszm_to_iqid; 1694f7917c00SJeff Kirsher __be32 dcaen_to_eqsize; 1695f7917c00SJeff Kirsher __be64 eqaddr; 1696f7917c00SJeff Kirsher __be32 viid_pkd; 1697f7917c00SJeff Kirsher __be32 r8_lo; 1698f7917c00SJeff Kirsher __be64 r9; 1699f7917c00SJeff Kirsher }; 1700f7917c00SJeff Kirsher 17016e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PFN_S 8 17026e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S) 1703f7917c00SJeff Kirsher 17046e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_VFN_S 0 17056e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S) 1706f7917c00SJeff Kirsher 17076e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_ALLOC_S 31 17086e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S) 17096e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U) 1710f7917c00SJeff Kirsher 17116e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FREE_S 30 17126e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S) 17136e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U) 1714f7917c00SJeff Kirsher 17156e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_MODIFY_S 29 17166e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S) 17176e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U) 17186e4b51a6SHariprasad Shenai 17196e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTART_S 28 17206e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S) 17216e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U) 17226e4b51a6SHariprasad Shenai 17236e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTOP_S 27 17246e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S) 17256e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U) 17266e4b51a6SHariprasad Shenai 17276e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQID_S 0 17286e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQID_M 0xfffff 17296e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S) 17306e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQID_G(x) \ 17316e4b51a6SHariprasad Shenai (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M) 17326e4b51a6SHariprasad Shenai 17336e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PHYSEQID_S 0 17346e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff 17356e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S) 17366e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \ 17376e4b51a6SHariprasad Shenai (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M) 17386e4b51a6SHariprasad Shenai 17396e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHSZM_S 26 17406e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S) 17416e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U) 17426e4b51a6SHariprasad Shenai 17436e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_STATUSPGNS_S 25 17446e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S) 17456e4b51a6SHariprasad Shenai 17466e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_STATUSPGRO_S 24 17476e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S) 17486e4b51a6SHariprasad Shenai 17496e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHNS_S 23 17506e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S) 17516e4b51a6SHariprasad Shenai 17526e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHRO_S 22 17536e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S) 17541ecc7b7aSHariprasad Shenai #define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U) 17556e4b51a6SHariprasad Shenai 17566e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20 17576e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S) 17586e4b51a6SHariprasad Shenai 17596e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CPRIO_S 19 17606e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S) 17616e4b51a6SHariprasad Shenai 17626e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_ONCHIP_S 18 17636e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S) 17646e4b51a6SHariprasad Shenai 17656e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PCIECHN_S 16 17666e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S) 17676e4b51a6SHariprasad Shenai 17686e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_IQID_S 0 17696e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S) 17706e4b51a6SHariprasad Shenai 17716e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_DCAEN_S 31 17726e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S) 17736e4b51a6SHariprasad Shenai 17746e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_DCACPU_S 26 17756e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S) 17766e4b51a6SHariprasad Shenai 17776e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FBMIN_S 23 17786e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S) 17796e4b51a6SHariprasad Shenai 17806e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FBMAX_S 20 17816e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S) 17826e4b51a6SHariprasad Shenai 17836e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19 17846e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S) 17856e4b51a6SHariprasad Shenai 17866e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16 17876e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S) 17886e4b51a6SHariprasad Shenai 17896e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSIZE_S 0 17906e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S) 17916e4b51a6SHariprasad Shenai 17926e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30 17936e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S) 17946e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U) 17956e4b51a6SHariprasad Shenai 17966e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_VIID_S 16 17976e4b51a6SHariprasad Shenai #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S) 1798f7917c00SJeff Kirsher 1799f7917c00SJeff Kirsher struct fw_eq_ctrl_cmd { 1800f7917c00SJeff Kirsher __be32 op_to_vfn; 1801f7917c00SJeff Kirsher __be32 alloc_to_len16; 1802f7917c00SJeff Kirsher __be32 cmpliqid_eqid; 1803f7917c00SJeff Kirsher __be32 physeqid_pkd; 1804f7917c00SJeff Kirsher __be32 fetchszm_to_iqid; 1805f7917c00SJeff Kirsher __be32 dcaen_to_eqsize; 1806f7917c00SJeff Kirsher __be64 eqaddr; 1807f7917c00SJeff Kirsher }; 1808f7917c00SJeff Kirsher 18096e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PFN_S 8 18106e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S) 1811f7917c00SJeff Kirsher 18126e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_VFN_S 0 18136e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S) 1814f7917c00SJeff Kirsher 18156e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_ALLOC_S 31 18166e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S) 18176e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U) 1818f7917c00SJeff Kirsher 18196e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FREE_S 30 18206e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S) 18216e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U) 1822f7917c00SJeff Kirsher 18236e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_MODIFY_S 29 18246e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S) 18256e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U) 18266e4b51a6SHariprasad Shenai 18276e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTART_S 28 18286e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S) 18296e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U) 18306e4b51a6SHariprasad Shenai 18316e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTOP_S 27 18326e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S) 18336e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U) 18346e4b51a6SHariprasad Shenai 18356e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CMPLIQID_S 20 18366e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S) 18376e4b51a6SHariprasad Shenai 18386e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQID_S 0 18396e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQID_M 0xfffff 18406e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S) 18416e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQID_G(x) \ 18426e4b51a6SHariprasad Shenai (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M) 18436e4b51a6SHariprasad Shenai 18446e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PHYSEQID_S 0 18456e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff 18466e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \ 18476e4b51a6SHariprasad Shenai (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M) 18486e4b51a6SHariprasad Shenai 18496e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHSZM_S 26 18506e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S) 18516e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U) 18526e4b51a6SHariprasad Shenai 18536e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25 18546e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S) 18556e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U) 18566e4b51a6SHariprasad Shenai 18576e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24 18586e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S) 18596e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U) 18606e4b51a6SHariprasad Shenai 18616e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHNS_S 23 18626e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S) 18636e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U) 18646e4b51a6SHariprasad Shenai 18656e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHRO_S 22 18666e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S) 18676e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U) 18686e4b51a6SHariprasad Shenai 18696e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20 18706e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S) 18716e4b51a6SHariprasad Shenai 18726e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CPRIO_S 19 18736e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S) 18746e4b51a6SHariprasad Shenai 18756e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_ONCHIP_S 18 18766e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S) 18776e4b51a6SHariprasad Shenai 18786e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PCIECHN_S 16 18796e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S) 18806e4b51a6SHariprasad Shenai 18816e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_IQID_S 0 18826e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S) 18836e4b51a6SHariprasad Shenai 18846e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_DCAEN_S 31 18856e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S) 18866e4b51a6SHariprasad Shenai 18876e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_DCACPU_S 26 18886e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S) 18896e4b51a6SHariprasad Shenai 18906e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FBMIN_S 23 18916e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S) 18926e4b51a6SHariprasad Shenai 18936e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FBMAX_S 20 18946e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S) 18956e4b51a6SHariprasad Shenai 18966e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19 18976e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \ 18986e4b51a6SHariprasad Shenai ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S) 18996e4b51a6SHariprasad Shenai 19006e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16 19016e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S) 19026e4b51a6SHariprasad Shenai 19036e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSIZE_S 0 19046e4b51a6SHariprasad Shenai #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S) 1905f7917c00SJeff Kirsher 1906f7917c00SJeff Kirsher struct fw_eq_ofld_cmd { 1907f7917c00SJeff Kirsher __be32 op_to_vfn; 1908f7917c00SJeff Kirsher __be32 alloc_to_len16; 1909f7917c00SJeff Kirsher __be32 eqid_pkd; 1910f7917c00SJeff Kirsher __be32 physeqid_pkd; 1911f7917c00SJeff Kirsher __be32 fetchszm_to_iqid; 1912f7917c00SJeff Kirsher __be32 dcaen_to_eqsize; 1913f7917c00SJeff Kirsher __be64 eqaddr; 1914f7917c00SJeff Kirsher }; 1915f7917c00SJeff Kirsher 19166e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PFN_S 8 19176e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S) 1918f7917c00SJeff Kirsher 19196e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_VFN_S 0 19206e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S) 1921f7917c00SJeff Kirsher 19226e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_ALLOC_S 31 19236e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S) 19246e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U) 1925f7917c00SJeff Kirsher 19266e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FREE_S 30 19276e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S) 19286e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U) 1929f7917c00SJeff Kirsher 19306e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_MODIFY_S 29 19316e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S) 19326e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U) 19336e4b51a6SHariprasad Shenai 19346e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTART_S 28 19356e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S) 19366e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U) 19376e4b51a6SHariprasad Shenai 19386e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTOP_S 27 19396e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S) 19406e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U) 19416e4b51a6SHariprasad Shenai 19426e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQID_S 0 19436e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQID_M 0xfffff 19446e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S) 19456e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQID_G(x) \ 19466e4b51a6SHariprasad Shenai (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M) 19476e4b51a6SHariprasad Shenai 19486e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PHYSEQID_S 0 19496e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff 19506e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \ 19516e4b51a6SHariprasad Shenai (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M) 19526e4b51a6SHariprasad Shenai 19536e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHSZM_S 26 19546e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S) 19556e4b51a6SHariprasad Shenai 19566e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25 19576e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S) 19586e4b51a6SHariprasad Shenai 19596e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24 19606e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S) 19616e4b51a6SHariprasad Shenai 19626e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHNS_S 23 19636e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S) 19646e4b51a6SHariprasad Shenai 19656e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHRO_S 22 19666e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S) 19676e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U) 19686e4b51a6SHariprasad Shenai 19696e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20 19706e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S) 19716e4b51a6SHariprasad Shenai 19726e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CPRIO_S 19 19736e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S) 19746e4b51a6SHariprasad Shenai 19756e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_ONCHIP_S 18 19766e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S) 19776e4b51a6SHariprasad Shenai 19786e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PCIECHN_S 16 19796e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S) 19806e4b51a6SHariprasad Shenai 19816e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_IQID_S 0 19826e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S) 19836e4b51a6SHariprasad Shenai 19846e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_DCAEN_S 31 19856e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S) 19866e4b51a6SHariprasad Shenai 19876e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_DCACPU_S 26 19886e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S) 19896e4b51a6SHariprasad Shenai 19906e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FBMIN_S 23 19916e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S) 19926e4b51a6SHariprasad Shenai 19936e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FBMAX_S 20 19946e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S) 19956e4b51a6SHariprasad Shenai 19966e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19 19976e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \ 19986e4b51a6SHariprasad Shenai ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S) 19996e4b51a6SHariprasad Shenai 20006e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16 20016e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S) 20026e4b51a6SHariprasad Shenai 20036e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSIZE_S 0 20046e4b51a6SHariprasad Shenai #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S) 2005f7917c00SJeff Kirsher 2006f7917c00SJeff Kirsher /* 2007f7917c00SJeff Kirsher * Macros for VIID parsing: 2008f7917c00SJeff Kirsher * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 2009f7917c00SJeff Kirsher */ 2010d7990b0cSAnish Bhatt 2011d7990b0cSAnish Bhatt #define FW_VIID_PFN_S 8 2012d7990b0cSAnish Bhatt #define FW_VIID_PFN_M 0x7 2013d7990b0cSAnish Bhatt #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M) 2014d7990b0cSAnish Bhatt 20152b5fb1f2SHariprasad Shenai #define FW_VIID_VIVLD_S 7 20162b5fb1f2SHariprasad Shenai #define FW_VIID_VIVLD_M 0x1 20172b5fb1f2SHariprasad Shenai #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M) 20182b5fb1f2SHariprasad Shenai 20192b5fb1f2SHariprasad Shenai #define FW_VIID_VIN_S 0 20202b5fb1f2SHariprasad Shenai #define FW_VIID_VIN_M 0x7F 20212b5fb1f2SHariprasad Shenai #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M) 2022f7917c00SJeff Kirsher 2023f7917c00SJeff Kirsher struct fw_vi_cmd { 2024f7917c00SJeff Kirsher __be32 op_to_vfn; 2025f7917c00SJeff Kirsher __be32 alloc_to_len16; 2026f7917c00SJeff Kirsher __be16 type_viid; 2027f7917c00SJeff Kirsher u8 mac[6]; 2028f7917c00SJeff Kirsher u8 portid_pkd; 2029f7917c00SJeff Kirsher u8 nmac; 2030f7917c00SJeff Kirsher u8 nmac0[6]; 2031f7917c00SJeff Kirsher __be16 rsssize_pkd; 2032f7917c00SJeff Kirsher u8 nmac1[6]; 2033f7917c00SJeff Kirsher __be16 idsiiq_pkd; 2034f7917c00SJeff Kirsher u8 nmac2[6]; 2035f7917c00SJeff Kirsher __be16 idseiq_pkd; 2036f7917c00SJeff Kirsher u8 nmac3[6]; 2037f7917c00SJeff Kirsher __be64 r9; 2038f7917c00SJeff Kirsher __be64 r10; 2039f7917c00SJeff Kirsher }; 2040f7917c00SJeff Kirsher 20412b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PFN_S 8 20422b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S) 20432b5fb1f2SHariprasad Shenai 20442b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VFN_S 0 20452b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S) 20462b5fb1f2SHariprasad Shenai 20472b5fb1f2SHariprasad Shenai #define FW_VI_CMD_ALLOC_S 31 20482b5fb1f2SHariprasad Shenai #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S) 20492b5fb1f2SHariprasad Shenai #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U) 20502b5fb1f2SHariprasad Shenai 20512b5fb1f2SHariprasad Shenai #define FW_VI_CMD_FREE_S 30 20522b5fb1f2SHariprasad Shenai #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S) 20532b5fb1f2SHariprasad Shenai #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U) 20542b5fb1f2SHariprasad Shenai 20552b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VIID_S 0 20562b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VIID_M 0xfff 20572b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S) 20582b5fb1f2SHariprasad Shenai #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M) 20592b5fb1f2SHariprasad Shenai 20602b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PORTID_S 4 20612b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PORTID_M 0xf 20622b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S) 20632b5fb1f2SHariprasad Shenai #define FW_VI_CMD_PORTID_G(x) \ 20642b5fb1f2SHariprasad Shenai (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M) 20652b5fb1f2SHariprasad Shenai 20662b5fb1f2SHariprasad Shenai #define FW_VI_CMD_RSSSIZE_S 0 20672b5fb1f2SHariprasad Shenai #define FW_VI_CMD_RSSSIZE_M 0x7ff 20682b5fb1f2SHariprasad Shenai #define FW_VI_CMD_RSSSIZE_G(x) \ 20692b5fb1f2SHariprasad Shenai (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M) 2070f7917c00SJeff Kirsher 2071f7917c00SJeff Kirsher /* Special VI_MAC command index ids */ 2072f7917c00SJeff Kirsher #define FW_VI_MAC_ADD_MAC 0x3FF 2073f7917c00SJeff Kirsher #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 2074f7917c00SJeff Kirsher #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 2075ef0fd85aSGanesh Goudar #define FW_VI_MAC_ID_BASED_FREE 0x3FC 2076f7917c00SJeff Kirsher #define FW_CLS_TCAM_NUM_ENTRIES 336 2077f7917c00SJeff Kirsher 2078f7917c00SJeff Kirsher enum fw_vi_mac_smac { 2079f7917c00SJeff Kirsher FW_VI_MAC_MPS_TCAM_ENTRY, 2080f7917c00SJeff Kirsher FW_VI_MAC_MPS_TCAM_ONLY, 2081f7917c00SJeff Kirsher FW_VI_MAC_SMT_ONLY, 2082f7917c00SJeff Kirsher FW_VI_MAC_SMT_AND_MPSTCAM 2083f7917c00SJeff Kirsher }; 2084f7917c00SJeff Kirsher 2085f7917c00SJeff Kirsher enum fw_vi_mac_result { 2086f7917c00SJeff Kirsher FW_VI_MAC_R_SUCCESS, 2087f7917c00SJeff Kirsher FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 2088f7917c00SJeff Kirsher FW_VI_MAC_R_SMAC_FAIL, 2089f7917c00SJeff Kirsher FW_VI_MAC_R_F_ACL_CHECK 2090f7917c00SJeff Kirsher }; 2091f7917c00SJeff Kirsher 2092ef0fd85aSGanesh Goudar enum fw_vi_mac_entry_types { 2093ef0fd85aSGanesh Goudar FW_VI_MAC_TYPE_EXACTMAC, 2094ef0fd85aSGanesh Goudar FW_VI_MAC_TYPE_HASHVEC, 2095ef0fd85aSGanesh Goudar FW_VI_MAC_TYPE_RAW, 2096ef0fd85aSGanesh Goudar FW_VI_MAC_TYPE_EXACTMAC_VNI, 2097ef0fd85aSGanesh Goudar }; 2098ef0fd85aSGanesh Goudar 2099f7917c00SJeff Kirsher struct fw_vi_mac_cmd { 2100f7917c00SJeff Kirsher __be32 op_to_viid; 2101f7917c00SJeff Kirsher __be32 freemacs_to_len16; 2102f7917c00SJeff Kirsher union fw_vi_mac { 2103f7917c00SJeff Kirsher struct fw_vi_mac_exact { 2104f7917c00SJeff Kirsher __be16 valid_to_idx; 2105f7917c00SJeff Kirsher u8 macaddr[6]; 2106f7917c00SJeff Kirsher } exact[7]; 2107f7917c00SJeff Kirsher struct fw_vi_mac_hash { 2108f7917c00SJeff Kirsher __be64 hashvec; 2109f7917c00SJeff Kirsher } hash; 2110ef0fd85aSGanesh Goudar struct fw_vi_mac_raw { 2111ef0fd85aSGanesh Goudar __be32 raw_idx_pkd; 2112ef0fd85aSGanesh Goudar __be32 data0_pkd; 2113ef0fd85aSGanesh Goudar __be32 data1[2]; 2114ef0fd85aSGanesh Goudar __be64 data0m_pkd; 2115ef0fd85aSGanesh Goudar __be32 data1m[2]; 2116ef0fd85aSGanesh Goudar } raw; 2117f7917c00SJeff Kirsher } u; 2118f7917c00SJeff Kirsher }; 2119f7917c00SJeff Kirsher 21202b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_VIID_S 0 21212b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S) 21222b5fb1f2SHariprasad Shenai 21232b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_FREEMACS_S 31 21242b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S) 21252b5fb1f2SHariprasad Shenai 2126ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_ENTRY_TYPE_S 23 2127ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_ENTRY_TYPE_M 0x7 2128ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x) ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S) 2129ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x) \ 2130ef0fd85aSGanesh Goudar (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M) 2131ef0fd85aSGanesh Goudar 21322b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_HASHVECEN_S 23 21332b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S) 21342b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U) 21352b5fb1f2SHariprasad Shenai 21362b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_HASHUNIEN_S 22 21372b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S) 21382b5fb1f2SHariprasad Shenai 21392b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_VALID_S 15 21402b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S) 21412b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U) 21422b5fb1f2SHariprasad Shenai 21432b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_PRIO_S 12 21442b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S) 21452b5fb1f2SHariprasad Shenai 21462b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_SMAC_RESULT_S 10 21472b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3 21482b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S) 21492b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \ 21502b5fb1f2SHariprasad Shenai (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M) 21512b5fb1f2SHariprasad Shenai 21522b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_IDX_S 0 21532b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_IDX_M 0x3ff 21542b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S) 21552b5fb1f2SHariprasad Shenai #define FW_VI_MAC_CMD_IDX_G(x) \ 21562b5fb1f2SHariprasad Shenai (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M) 2157f7917c00SJeff Kirsher 2158ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_RAW_IDX_S 16 2159ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_RAW_IDX_M 0xffff 2160ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_RAW_IDX_V(x) ((x) << FW_VI_MAC_CMD_RAW_IDX_S) 2161ef0fd85aSGanesh Goudar #define FW_VI_MAC_CMD_RAW_IDX_G(x) \ 2162ef0fd85aSGanesh Goudar (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M) 2163ef0fd85aSGanesh Goudar 2164f7917c00SJeff Kirsher #define FW_RXMODE_MTU_NO_CHG 65535 2165f7917c00SJeff Kirsher 2166f7917c00SJeff Kirsher struct fw_vi_rxmode_cmd { 2167f7917c00SJeff Kirsher __be32 op_to_viid; 2168f7917c00SJeff Kirsher __be32 retval_len16; 2169f7917c00SJeff Kirsher __be32 mtu_to_vlanexen; 2170f7917c00SJeff Kirsher __be32 r4_lo; 2171f7917c00SJeff Kirsher }; 2172f7917c00SJeff Kirsher 21732b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_VIID_S 0 21742b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S) 21752b5fb1f2SHariprasad Shenai 21762b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_MTU_S 16 21772b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_MTU_M 0xffff 21782b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S) 21792b5fb1f2SHariprasad Shenai 21802b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_PROMISCEN_S 14 21812b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3 21822b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S) 21832b5fb1f2SHariprasad Shenai 21842b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12 21852b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3 21862b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \ 21872b5fb1f2SHariprasad Shenai ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S) 21882b5fb1f2SHariprasad Shenai 21892b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10 21902b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3 21912b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \ 21922b5fb1f2SHariprasad Shenai ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S) 21932b5fb1f2SHariprasad Shenai 21942b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_VLANEXEN_S 8 21952b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3 21962b5fb1f2SHariprasad Shenai #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S) 2197f7917c00SJeff Kirsher 2198f7917c00SJeff Kirsher struct fw_vi_enable_cmd { 2199f7917c00SJeff Kirsher __be32 op_to_viid; 2200f7917c00SJeff Kirsher __be32 ien_to_len16; 2201f7917c00SJeff Kirsher __be16 blinkdur; 2202f7917c00SJeff Kirsher __be16 r3; 2203f7917c00SJeff Kirsher __be32 r4; 2204f7917c00SJeff Kirsher }; 2205f7917c00SJeff Kirsher 22062b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_VIID_S 0 22072b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S) 22082b5fb1f2SHariprasad Shenai 22092b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_IEN_S 31 22102b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S) 22112b5fb1f2SHariprasad Shenai 22122b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_EEN_S 30 22132b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S) 22142b5fb1f2SHariprasad Shenai 22152b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_LED_S 29 22162b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S) 22172b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U) 22182b5fb1f2SHariprasad Shenai 22192b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_DCB_INFO_S 28 22202b5fb1f2SHariprasad Shenai #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S) 2221f7917c00SJeff Kirsher 2222f7917c00SJeff Kirsher /* VI VF stats offset definitions */ 2223f7917c00SJeff Kirsher #define VI_VF_NUM_STATS 16 2224f7917c00SJeff Kirsher enum fw_vi_stats_vf_index { 2225f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 2226f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 2227f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 2228f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 2229f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 2230f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 2231f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 2232f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 2233f7917c00SJeff Kirsher FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 2234f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 2235f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 2236f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 2237f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 2238f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 2239f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 2240f7917c00SJeff Kirsher FW_VI_VF_STAT_RX_ERR_FRAMES_IX 2241f7917c00SJeff Kirsher }; 2242f7917c00SJeff Kirsher 2243f7917c00SJeff Kirsher /* VI PF stats offset definitions */ 2244f7917c00SJeff Kirsher #define VI_PF_NUM_STATS 17 2245f7917c00SJeff Kirsher enum fw_vi_stats_pf_index { 2246f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 2247f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 2248f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 2249f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 2250f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 2251f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 2252f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 2253f7917c00SJeff Kirsher FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 2254f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_BYTES_IX, 2255f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_FRAMES_IX, 2256f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 2257f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 2258f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 2259f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 2260f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 2261f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 2262f7917c00SJeff Kirsher FW_VI_PF_STAT_RX_ERR_FRAMES_IX 2263f7917c00SJeff Kirsher }; 2264f7917c00SJeff Kirsher 2265f7917c00SJeff Kirsher struct fw_vi_stats_cmd { 2266f7917c00SJeff Kirsher __be32 op_to_viid; 2267f7917c00SJeff Kirsher __be32 retval_len16; 2268f7917c00SJeff Kirsher union fw_vi_stats { 2269f7917c00SJeff Kirsher struct fw_vi_stats_ctl { 2270f7917c00SJeff Kirsher __be16 nstats_ix; 2271f7917c00SJeff Kirsher __be16 r6; 2272f7917c00SJeff Kirsher __be32 r7; 2273f7917c00SJeff Kirsher __be64 stat0; 2274f7917c00SJeff Kirsher __be64 stat1; 2275f7917c00SJeff Kirsher __be64 stat2; 2276f7917c00SJeff Kirsher __be64 stat3; 2277f7917c00SJeff Kirsher __be64 stat4; 2278f7917c00SJeff Kirsher __be64 stat5; 2279f7917c00SJeff Kirsher } ctl; 2280f7917c00SJeff Kirsher struct fw_vi_stats_pf { 2281f7917c00SJeff Kirsher __be64 tx_bcast_bytes; 2282f7917c00SJeff Kirsher __be64 tx_bcast_frames; 2283f7917c00SJeff Kirsher __be64 tx_mcast_bytes; 2284f7917c00SJeff Kirsher __be64 tx_mcast_frames; 2285f7917c00SJeff Kirsher __be64 tx_ucast_bytes; 2286f7917c00SJeff Kirsher __be64 tx_ucast_frames; 2287f7917c00SJeff Kirsher __be64 tx_offload_bytes; 2288f7917c00SJeff Kirsher __be64 tx_offload_frames; 2289f7917c00SJeff Kirsher __be64 rx_pf_bytes; 2290f7917c00SJeff Kirsher __be64 rx_pf_frames; 2291f7917c00SJeff Kirsher __be64 rx_bcast_bytes; 2292f7917c00SJeff Kirsher __be64 rx_bcast_frames; 2293f7917c00SJeff Kirsher __be64 rx_mcast_bytes; 2294f7917c00SJeff Kirsher __be64 rx_mcast_frames; 2295f7917c00SJeff Kirsher __be64 rx_ucast_bytes; 2296f7917c00SJeff Kirsher __be64 rx_ucast_frames; 2297f7917c00SJeff Kirsher __be64 rx_err_frames; 2298f7917c00SJeff Kirsher } pf; 2299f7917c00SJeff Kirsher struct fw_vi_stats_vf { 2300f7917c00SJeff Kirsher __be64 tx_bcast_bytes; 2301f7917c00SJeff Kirsher __be64 tx_bcast_frames; 2302f7917c00SJeff Kirsher __be64 tx_mcast_bytes; 2303f7917c00SJeff Kirsher __be64 tx_mcast_frames; 2304f7917c00SJeff Kirsher __be64 tx_ucast_bytes; 2305f7917c00SJeff Kirsher __be64 tx_ucast_frames; 2306f7917c00SJeff Kirsher __be64 tx_drop_frames; 2307f7917c00SJeff Kirsher __be64 tx_offload_bytes; 2308f7917c00SJeff Kirsher __be64 tx_offload_frames; 2309f7917c00SJeff Kirsher __be64 rx_bcast_bytes; 2310f7917c00SJeff Kirsher __be64 rx_bcast_frames; 2311f7917c00SJeff Kirsher __be64 rx_mcast_bytes; 2312f7917c00SJeff Kirsher __be64 rx_mcast_frames; 2313f7917c00SJeff Kirsher __be64 rx_ucast_bytes; 2314f7917c00SJeff Kirsher __be64 rx_ucast_frames; 2315f7917c00SJeff Kirsher __be64 rx_err_frames; 2316f7917c00SJeff Kirsher } vf; 2317f7917c00SJeff Kirsher } u; 2318f7917c00SJeff Kirsher }; 2319f7917c00SJeff Kirsher 23202b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_VIID_S 0 23212b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S) 23222b5fb1f2SHariprasad Shenai 23232b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_NSTATS_S 12 23242b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S) 23252b5fb1f2SHariprasad Shenai 23262b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_IX_S 0 23272b5fb1f2SHariprasad Shenai #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S) 2328f7917c00SJeff Kirsher 2329f7917c00SJeff Kirsher struct fw_acl_mac_cmd { 2330f7917c00SJeff Kirsher __be32 op_to_vfn; 2331f7917c00SJeff Kirsher __be32 en_to_len16; 2332f7917c00SJeff Kirsher u8 nmac; 2333f7917c00SJeff Kirsher u8 r3[7]; 2334f7917c00SJeff Kirsher __be16 r4; 2335f7917c00SJeff Kirsher u8 macaddr0[6]; 2336f7917c00SJeff Kirsher __be16 r5; 2337f7917c00SJeff Kirsher u8 macaddr1[6]; 2338f7917c00SJeff Kirsher __be16 r6; 2339f7917c00SJeff Kirsher u8 macaddr2[6]; 2340f7917c00SJeff Kirsher __be16 r7; 2341f7917c00SJeff Kirsher u8 macaddr3[6]; 2342f7917c00SJeff Kirsher }; 2343f7917c00SJeff Kirsher 23442b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_PFN_S 8 23452b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S) 23462b5fb1f2SHariprasad Shenai 23472b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_VFN_S 0 23482b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S) 23492b5fb1f2SHariprasad Shenai 23502b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_EN_S 31 23512b5fb1f2SHariprasad Shenai #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S) 2352f7917c00SJeff Kirsher 2353f7917c00SJeff Kirsher struct fw_acl_vlan_cmd { 2354f7917c00SJeff Kirsher __be32 op_to_vfn; 2355f7917c00SJeff Kirsher __be32 en_to_len16; 2356f7917c00SJeff Kirsher u8 nvlan; 2357f7917c00SJeff Kirsher u8 dropnovlan_fm; 2358f7917c00SJeff Kirsher u8 r3_lo[6]; 2359f7917c00SJeff Kirsher __be16 vlanid[16]; 2360f7917c00SJeff Kirsher }; 2361f7917c00SJeff Kirsher 23622b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_PFN_S 8 23632b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S) 23642b5fb1f2SHariprasad Shenai 23652b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_VFN_S 0 23662b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S) 23672b5fb1f2SHariprasad Shenai 23682b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_EN_S 31 23699d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_EN_M 0x1 23702b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S) 23719d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_EN_G(x) \ 23729d5fd927SGanesh Goudar (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M) 23739d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_EN_F FW_ACL_VLAN_CMD_EN_V(1U) 23742b5fb1f2SHariprasad Shenai 23752b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7 23762b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S) 23772b5fb1f2SHariprasad Shenai 23782b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_FM_S 6 23799d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_FM_M 0x1 23802b5fb1f2SHariprasad Shenai #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S) 23819d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_FM_G(x) \ 23829d5fd927SGanesh Goudar (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M) 23839d5fd927SGanesh Goudar #define FW_ACL_VLAN_CMD_FM_F FW_ACL_VLAN_CMD_FM_V(1U) 2384f7917c00SJeff Kirsher 2385c3168cabSGanesh Goudar /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 2386f7917c00SJeff Kirsher enum fw_port_cap { 2387f7917c00SJeff Kirsher FW_PORT_CAP_SPEED_100M = 0x0001, 2388f7917c00SJeff Kirsher FW_PORT_CAP_SPEED_1G = 0x0002, 2389eb97ad99SGanesh Goudar FW_PORT_CAP_SPEED_25G = 0x0004, 2390f7917c00SJeff Kirsher FW_PORT_CAP_SPEED_10G = 0x0008, 2391f7917c00SJeff Kirsher FW_PORT_CAP_SPEED_40G = 0x0010, 2392f7917c00SJeff Kirsher FW_PORT_CAP_SPEED_100G = 0x0020, 2393f7917c00SJeff Kirsher FW_PORT_CAP_FC_RX = 0x0040, 2394f7917c00SJeff Kirsher FW_PORT_CAP_FC_TX = 0x0080, 2395f7917c00SJeff Kirsher FW_PORT_CAP_ANEG = 0x0100, 2396eb97ad99SGanesh Goudar FW_PORT_CAP_MDIX = 0x0200, 2397eb97ad99SGanesh Goudar FW_PORT_CAP_MDIAUTO = 0x0400, 23983bb4858fSGanesh Goudar FW_PORT_CAP_FEC_RS = 0x0800, 23993bb4858fSGanesh Goudar FW_PORT_CAP_FEC_BASER_RS = 0x1000, 24003bb4858fSGanesh Goudar FW_PORT_CAP_FEC_RESERVED = 0x2000, 2401eb97ad99SGanesh Goudar FW_PORT_CAP_802_3_PAUSE = 0x4000, 2402eb97ad99SGanesh Goudar FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 2403f7917c00SJeff Kirsher }; 2404f7917c00SJeff Kirsher 24059b86a8d1SHariprasad Shenai #define FW_PORT_CAP_SPEED_S 0 24069b86a8d1SHariprasad Shenai #define FW_PORT_CAP_SPEED_M 0x3f 24079b86a8d1SHariprasad Shenai #define FW_PORT_CAP_SPEED_V(x) ((x) << FW_PORT_CAP_SPEED_S) 24089b86a8d1SHariprasad Shenai #define FW_PORT_CAP_SPEED_G(x) \ 24099b86a8d1SHariprasad Shenai (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M) 24109b86a8d1SHariprasad Shenai 2411f7917c00SJeff Kirsher enum fw_port_mdi { 24122b5fb1f2SHariprasad Shenai FW_PORT_CAP_MDI_UNCHANGED, 24132b5fb1f2SHariprasad Shenai FW_PORT_CAP_MDI_AUTO, 24142b5fb1f2SHariprasad Shenai FW_PORT_CAP_MDI_F_STRAIGHT, 24152b5fb1f2SHariprasad Shenai FW_PORT_CAP_MDI_F_CROSSOVER 2416f7917c00SJeff Kirsher }; 2417f7917c00SJeff Kirsher 24182b5fb1f2SHariprasad Shenai #define FW_PORT_CAP_MDI_S 9 24192b5fb1f2SHariprasad Shenai #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S) 2420f7917c00SJeff Kirsher 2421c3168cabSGanesh Goudar /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 2422c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 2423c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 2424c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 2425c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 2426c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 2427c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 2428c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 2429c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 2430c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 2431c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 2432c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 2433c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 2434c3168cabSGanesh Goudar #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 2435c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_RX 0x00010000UL 2436c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_TX 0x00020000UL 2437c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 2438c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 2439c3168cabSGanesh Goudar #define FW_PORT_CAP32_ANEG 0x00100000UL 2440c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDIX 0x00200000UL 2441c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 2442c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_RS 0x00800000UL 2443c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 2444c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL 2445c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 2446c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 2447c3168cabSGanesh Goudar #define FW_PORT_CAP32_RESERVED2 0xf0000000UL 2448c3168cabSGanesh Goudar 2449c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_S 0 2450c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_M 0xfff 2451c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_V(x) ((x) << FW_PORT_CAP32_SPEED_S) 2452c3168cabSGanesh Goudar #define FW_PORT_CAP32_SPEED_G(x) \ 2453c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M) 2454c3168cabSGanesh Goudar 2455c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_S 16 2456c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_M 0x3 2457c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_V(x) ((x) << FW_PORT_CAP32_FC_S) 2458c3168cabSGanesh Goudar #define FW_PORT_CAP32_FC_G(x) \ 2459c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M) 2460c3168cabSGanesh Goudar 2461c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_S 18 2462c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_M 0x3 2463c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_V(x) ((x) << FW_PORT_CAP32_802_3_S) 2464c3168cabSGanesh Goudar #define FW_PORT_CAP32_802_3_G(x) \ 2465c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M) 2466c3168cabSGanesh Goudar 2467c3168cabSGanesh Goudar #define FW_PORT_CAP32_ANEG_S 20 2468c3168cabSGanesh Goudar #define FW_PORT_CAP32_ANEG_M 0x1 2469c3168cabSGanesh Goudar #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S) 2470c3168cabSGanesh Goudar #define FW_PORT_CAP32_ANEG_G(x) \ 2471c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M) 2472c3168cabSGanesh Goudar 2473c3168cabSGanesh Goudar enum fw_port_mdi32 { 2474c3168cabSGanesh Goudar FW_PORT_CAP32_MDI_UNCHANGED, 2475c3168cabSGanesh Goudar FW_PORT_CAP32_MDI_AUTO, 2476c3168cabSGanesh Goudar FW_PORT_CAP32_MDI_F_STRAIGHT, 2477c3168cabSGanesh Goudar FW_PORT_CAP32_MDI_F_CROSSOVER 2478c3168cabSGanesh Goudar }; 2479c3168cabSGanesh Goudar 2480c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDI_S 21 2481c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDI_M 3 2482c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S) 2483c3168cabSGanesh Goudar #define FW_PORT_CAP32_MDI_G(x) \ 2484c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M) 2485c3168cabSGanesh Goudar 2486c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_S 23 2487c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_M 0x1f 2488c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_V(x) ((x) << FW_PORT_CAP32_FEC_S) 2489c3168cabSGanesh Goudar #define FW_PORT_CAP32_FEC_G(x) \ 2490c3168cabSGanesh Goudar (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M) 2491c3168cabSGanesh Goudar 2492c3168cabSGanesh Goudar /* macros to isolate various 32-bit Port Capabilities sub-fields */ 2493c3168cabSGanesh Goudar #define CAP32_SPEED(__cap32) \ 2494c3168cabSGanesh Goudar (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32) 2495c3168cabSGanesh Goudar 2496c3168cabSGanesh Goudar #define CAP32_FEC(__cap32) \ 2497c3168cabSGanesh Goudar (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32) 2498c3168cabSGanesh Goudar 2499f7917c00SJeff Kirsher enum fw_port_action { 2500f7917c00SJeff Kirsher FW_PORT_ACTION_L1_CFG = 0x0001, 2501f7917c00SJeff Kirsher FW_PORT_ACTION_L2_CFG = 0x0002, 2502f7917c00SJeff Kirsher FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 2503f7917c00SJeff Kirsher FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 2504f7917c00SJeff Kirsher FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 2505989594e2SAnish Bhatt FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 2506989594e2SAnish Bhatt FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 2507989594e2SAnish Bhatt FW_PORT_ACTION_DCB_READ_DET = 0x0008, 2508c3168cabSGanesh Goudar FW_PORT_ACTION_L1_CFG32 = 0x0009, 2509c3168cabSGanesh Goudar FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 2510f7917c00SJeff Kirsher FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 2511f7917c00SJeff Kirsher FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 2512f7917c00SJeff Kirsher FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 2513f7917c00SJeff Kirsher FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 2514f7917c00SJeff Kirsher FW_PORT_ACTION_L1_LPBK = 0x0021, 2515f7917c00SJeff Kirsher FW_PORT_ACTION_L1_PMA_LPBK = 0x0022, 2516f7917c00SJeff Kirsher FW_PORT_ACTION_L1_PCS_LPBK = 0x0023, 2517f7917c00SJeff Kirsher FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024, 2518f7917c00SJeff Kirsher FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025, 2519f7917c00SJeff Kirsher FW_PORT_ACTION_PHY_RESET = 0x0040, 2520f7917c00SJeff Kirsher FW_PORT_ACTION_PMA_RESET = 0x0041, 2521f7917c00SJeff Kirsher FW_PORT_ACTION_PCS_RESET = 0x0042, 2522f7917c00SJeff Kirsher FW_PORT_ACTION_PHYXS_RESET = 0x0043, 2523f7917c00SJeff Kirsher FW_PORT_ACTION_DTEXS_REEST = 0x0044, 2524f7917c00SJeff Kirsher FW_PORT_ACTION_AN_RESET = 0x0045 2525f7917c00SJeff Kirsher }; 2526f7917c00SJeff Kirsher 2527f7917c00SJeff Kirsher enum fw_port_l2cfg_ctlbf { 2528f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 2529f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 2530f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 2531f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 2532f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_IVLAN = 0x10, 2533f7917c00SJeff Kirsher FW_PORT_L2_CTLBF_TXIPG = 0x20 2534f7917c00SJeff Kirsher }; 2535f7917c00SJeff Kirsher 253610b00466SAnish Bhatt enum fw_port_dcb_versions { 253710b00466SAnish Bhatt FW_PORT_DCB_VER_UNKNOWN, 253810b00466SAnish Bhatt FW_PORT_DCB_VER_CEE1D0, 253910b00466SAnish Bhatt FW_PORT_DCB_VER_CEE1D01, 254010b00466SAnish Bhatt FW_PORT_DCB_VER_IEEE, 254110b00466SAnish Bhatt FW_PORT_DCB_VER_AUTO = 7 254210b00466SAnish Bhatt }; 254310b00466SAnish Bhatt 2544f7917c00SJeff Kirsher enum fw_port_dcb_cfg { 2545f7917c00SJeff Kirsher FW_PORT_DCB_CFG_PG = 0x01, 2546f7917c00SJeff Kirsher FW_PORT_DCB_CFG_PFC = 0x02, 2547f7917c00SJeff Kirsher FW_PORT_DCB_CFG_APPL = 0x04 2548f7917c00SJeff Kirsher }; 2549f7917c00SJeff Kirsher 2550f7917c00SJeff Kirsher enum fw_port_dcb_cfg_rc { 2551f7917c00SJeff Kirsher FW_PORT_DCB_CFG_SUCCESS = 0x0, 2552f7917c00SJeff Kirsher FW_PORT_DCB_CFG_ERROR = 0x1 2553f7917c00SJeff Kirsher }; 2554f7917c00SJeff Kirsher 2555ce91a923SNaresh Kumar Inna enum fw_port_dcb_type { 2556ce91a923SNaresh Kumar Inna FW_PORT_DCB_TYPE_PGID = 0x00, 2557ce91a923SNaresh Kumar Inna FW_PORT_DCB_TYPE_PGRATE = 0x01, 2558ce91a923SNaresh Kumar Inna FW_PORT_DCB_TYPE_PRIORATE = 0x02, 2559ce91a923SNaresh Kumar Inna FW_PORT_DCB_TYPE_PFC = 0x03, 2560ce91a923SNaresh Kumar Inna FW_PORT_DCB_TYPE_APP_ID = 0x04, 2561989594e2SAnish Bhatt FW_PORT_DCB_TYPE_CONTROL = 0x05, 2562989594e2SAnish Bhatt }; 2563989594e2SAnish Bhatt 2564989594e2SAnish Bhatt enum fw_port_dcb_feature_state { 2565989594e2SAnish Bhatt FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 2566989594e2SAnish Bhatt FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 2567989594e2SAnish Bhatt FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 2568989594e2SAnish Bhatt FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 2569ce91a923SNaresh Kumar Inna }; 2570ce91a923SNaresh Kumar Inna 2571f7917c00SJeff Kirsher struct fw_port_cmd { 2572f7917c00SJeff Kirsher __be32 op_to_portid; 2573f7917c00SJeff Kirsher __be32 action_to_len16; 2574f7917c00SJeff Kirsher union fw_port { 2575f7917c00SJeff Kirsher struct fw_port_l1cfg { 2576f7917c00SJeff Kirsher __be32 rcap; 2577f7917c00SJeff Kirsher __be32 r; 2578f7917c00SJeff Kirsher } l1cfg; 2579f7917c00SJeff Kirsher struct fw_port_l2cfg { 2580989594e2SAnish Bhatt __u8 ctlbf; 2581989594e2SAnish Bhatt __u8 ovlan3_to_ivlan0; 2582f7917c00SJeff Kirsher __be16 ivlantype; 2583989594e2SAnish Bhatt __be16 txipg_force_pinfo; 2584989594e2SAnish Bhatt __be16 mtu; 2585f7917c00SJeff Kirsher __be16 ovlan0mask; 2586f7917c00SJeff Kirsher __be16 ovlan0type; 2587f7917c00SJeff Kirsher __be16 ovlan1mask; 2588f7917c00SJeff Kirsher __be16 ovlan1type; 2589f7917c00SJeff Kirsher __be16 ovlan2mask; 2590f7917c00SJeff Kirsher __be16 ovlan2type; 2591f7917c00SJeff Kirsher __be16 ovlan3mask; 2592f7917c00SJeff Kirsher __be16 ovlan3type; 2593f7917c00SJeff Kirsher } l2cfg; 2594f7917c00SJeff Kirsher struct fw_port_info { 2595f7917c00SJeff Kirsher __be32 lstatus_to_modtype; 2596f7917c00SJeff Kirsher __be16 pcap; 2597f7917c00SJeff Kirsher __be16 acap; 2598f7917c00SJeff Kirsher __be16 mtu; 2599f7917c00SJeff Kirsher __u8 cbllen; 2600989594e2SAnish Bhatt __u8 auxlinfo; 2601989594e2SAnish Bhatt __u8 dcbxdis_pkd; 2602eb97ad99SGanesh Goudar __u8 r8_lo; 2603eb97ad99SGanesh Goudar __be16 lpacap; 2604989594e2SAnish Bhatt __be64 r9; 2605f7917c00SJeff Kirsher } info; 2606989594e2SAnish Bhatt struct fw_port_diags { 2607989594e2SAnish Bhatt __u8 diagop; 2608989594e2SAnish Bhatt __u8 r[3]; 2609989594e2SAnish Bhatt __be32 diagval; 2610989594e2SAnish Bhatt } diags; 2611989594e2SAnish Bhatt union fw_port_dcb { 2612989594e2SAnish Bhatt struct fw_port_dcb_pgid { 2613989594e2SAnish Bhatt __u8 type; 2614989594e2SAnish Bhatt __u8 apply_pkd; 2615989594e2SAnish Bhatt __u8 r10_lo[2]; 2616989594e2SAnish Bhatt __be32 pgid; 2617989594e2SAnish Bhatt __be64 r11; 2618989594e2SAnish Bhatt } pgid; 2619989594e2SAnish Bhatt struct fw_port_dcb_pgrate { 2620989594e2SAnish Bhatt __u8 type; 2621989594e2SAnish Bhatt __u8 apply_pkd; 2622989594e2SAnish Bhatt __u8 r10_lo[5]; 2623989594e2SAnish Bhatt __u8 num_tcs_supported; 2624989594e2SAnish Bhatt __u8 pgrate[8]; 262510b00466SAnish Bhatt __u8 tsa[8]; 2626989594e2SAnish Bhatt } pgrate; 2627989594e2SAnish Bhatt struct fw_port_dcb_priorate { 2628989594e2SAnish Bhatt __u8 type; 2629989594e2SAnish Bhatt __u8 apply_pkd; 2630989594e2SAnish Bhatt __u8 r10_lo[6]; 2631989594e2SAnish Bhatt __u8 strict_priorate[8]; 2632989594e2SAnish Bhatt } priorate; 2633989594e2SAnish Bhatt struct fw_port_dcb_pfc { 2634989594e2SAnish Bhatt __u8 type; 2635989594e2SAnish Bhatt __u8 pfcen; 2636989594e2SAnish Bhatt __u8 r10[5]; 2637989594e2SAnish Bhatt __u8 max_pfc_tcs; 2638989594e2SAnish Bhatt __be64 r11; 2639989594e2SAnish Bhatt } pfc; 2640989594e2SAnish Bhatt struct fw_port_app_priority { 2641989594e2SAnish Bhatt __u8 type; 2642989594e2SAnish Bhatt __u8 r10[2]; 2643989594e2SAnish Bhatt __u8 idx; 2644989594e2SAnish Bhatt __u8 user_prio_map; 2645989594e2SAnish Bhatt __u8 sel_field; 2646989594e2SAnish Bhatt __be16 protocolid; 2647989594e2SAnish Bhatt __be64 r12; 2648989594e2SAnish Bhatt } app_priority; 2649989594e2SAnish Bhatt struct fw_port_dcb_control { 2650989594e2SAnish Bhatt __u8 type; 2651989594e2SAnish Bhatt __u8 all_syncd_pkd; 265210b00466SAnish Bhatt __be16 dcb_version_to_app_state; 2653f7917c00SJeff Kirsher __be32 r11; 2654989594e2SAnish Bhatt __be64 r12; 2655989594e2SAnish Bhatt } control; 2656f7917c00SJeff Kirsher } dcb; 2657c3168cabSGanesh Goudar struct fw_port_l1cfg32 { 2658c3168cabSGanesh Goudar __be32 rcap32; 2659c3168cabSGanesh Goudar __be32 r; 2660c3168cabSGanesh Goudar } l1cfg32; 2661c3168cabSGanesh Goudar struct fw_port_info32 { 2662c3168cabSGanesh Goudar __be32 lstatus32_to_cbllen32; 2663c3168cabSGanesh Goudar __be32 auxlinfo32_mtu32; 2664c3168cabSGanesh Goudar __be32 linkattr32; 2665c3168cabSGanesh Goudar __be32 pcaps32; 2666c3168cabSGanesh Goudar __be32 acaps32; 2667c3168cabSGanesh Goudar __be32 lpacaps32; 2668c3168cabSGanesh Goudar } info32; 2669f7917c00SJeff Kirsher } u; 2670f7917c00SJeff Kirsher }; 2671f7917c00SJeff Kirsher 26722b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_READ_S 22 26732b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S) 26742b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U) 2675f7917c00SJeff Kirsher 26762b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PORTID_S 0 26772b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PORTID_M 0xf 26782b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S) 26792b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PORTID_G(x) \ 26802b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M) 2681f7917c00SJeff Kirsher 26822b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ACTION_S 16 26832b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ACTION_M 0xffff 26842b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S) 26852b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ACTION_G(x) \ 26862b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M) 2687f7917c00SJeff Kirsher 26882b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN3_S 7 26892b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S) 2690f7917c00SJeff Kirsher 26912b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN2_S 6 26922b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S) 2693f7917c00SJeff Kirsher 26942b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN1_S 5 26952b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S) 2696f7917c00SJeff Kirsher 26972b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN0_S 4 26982b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S) 2699989594e2SAnish Bhatt 27002b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_IVLAN0_S 3 27012b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S) 2702f7917c00SJeff Kirsher 27032b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_TXIPG_S 3 27042b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S) 27052b5fb1f2SHariprasad Shenai 27062b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSTATUS_S 31 27072b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSTATUS_M 0x1 27082b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S) 27092b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSTATUS_G(x) \ 27102b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M) 27112b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U) 27122b5fb1f2SHariprasad Shenai 27132b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSPEED_S 24 27142b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSPEED_M 0x3f 27152b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S) 27162b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LSPEED_G(x) \ 27172b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M) 27182b5fb1f2SHariprasad Shenai 27192b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_TXPAUSE_S 23 27202b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S) 27212b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U) 27222b5fb1f2SHariprasad Shenai 27232b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_RXPAUSE_S 22 27242b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S) 27252b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U) 27262b5fb1f2SHariprasad Shenai 27272b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOCAP_S 21 27282b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S) 27292b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U) 27302b5fb1f2SHariprasad Shenai 27312b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOADDR_S 16 27322b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOADDR_M 0x1f 27332b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MDIOADDR_G(x) \ 27342b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M) 27352b5fb1f2SHariprasad Shenai 27362b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPTXPAUSE_S 15 27372b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S) 27382b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U) 27392b5fb1f2SHariprasad Shenai 27402b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPRXPAUSE_S 14 27412b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S) 27422b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U) 27432b5fb1f2SHariprasad Shenai 27442b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PTYPE_S 8 27452b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PTYPE_M 0x1f 27462b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_PTYPE_G(x) \ 27472b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M) 27482b5fb1f2SHariprasad Shenai 2749ddc7740dSHariprasad Shenai #define FW_PORT_CMD_LINKDNRC_S 5 2750ddc7740dSHariprasad Shenai #define FW_PORT_CMD_LINKDNRC_M 0x7 2751ddc7740dSHariprasad Shenai #define FW_PORT_CMD_LINKDNRC_G(x) \ 2752ddc7740dSHariprasad Shenai (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M) 2753ddc7740dSHariprasad Shenai 27542b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MODTYPE_S 0 27552b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MODTYPE_M 0x1f 27562b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S) 27572b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_MODTYPE_G(x) \ 27582b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M) 27592b5fb1f2SHariprasad Shenai 27602b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCBXDIS_S 7 27612b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S) 27622b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U) 27632b5fb1f2SHariprasad Shenai 27642b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_APPLY_S 7 27652b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S) 27662b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U) 27672b5fb1f2SHariprasad Shenai 27682b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ALL_SYNCD_S 7 27692b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S) 27702b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U) 27712b5fb1f2SHariprasad Shenai 27722b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCB_VERSION_S 12 27732b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCB_VERSION_M 0x7 27742b5fb1f2SHariprasad Shenai #define FW_PORT_CMD_DCB_VERSION_G(x) \ 27752b5fb1f2SHariprasad Shenai (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M) 2776f7917c00SJeff Kirsher 2777c3168cabSGanesh Goudar #define FW_PORT_CMD_LSTATUS32_S 31 2778c3168cabSGanesh Goudar #define FW_PORT_CMD_LSTATUS32_M 0x1 2779c3168cabSGanesh Goudar #define FW_PORT_CMD_LSTATUS32_V(x) ((x) << FW_PORT_CMD_LSTATUS32_S) 2780c3168cabSGanesh Goudar #define FW_PORT_CMD_LSTATUS32_G(x) \ 2781c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M) 2782c3168cabSGanesh Goudar #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U) 2783c3168cabSGanesh Goudar 2784c3168cabSGanesh Goudar #define FW_PORT_CMD_LINKDNRC32_S 28 2785c3168cabSGanesh Goudar #define FW_PORT_CMD_LINKDNRC32_M 0x7 2786c3168cabSGanesh Goudar #define FW_PORT_CMD_LINKDNRC32_V(x) ((x) << FW_PORT_CMD_LINKDNRC32_S) 2787c3168cabSGanesh Goudar #define FW_PORT_CMD_LINKDNRC32_G(x) \ 2788c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M) 2789c3168cabSGanesh Goudar 2790c3168cabSGanesh Goudar #define FW_PORT_CMD_DCBXDIS32_S 27 2791c3168cabSGanesh Goudar #define FW_PORT_CMD_DCBXDIS32_M 0x1 2792c3168cabSGanesh Goudar #define FW_PORT_CMD_DCBXDIS32_V(x) ((x) << FW_PORT_CMD_DCBXDIS32_S) 2793c3168cabSGanesh Goudar #define FW_PORT_CMD_DCBXDIS32_G(x) \ 2794c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M) 2795c3168cabSGanesh Goudar #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U) 2796c3168cabSGanesh Goudar 2797c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOCAP32_S 26 2798c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOCAP32_M 0x1 2799c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOCAP32_V(x) ((x) << FW_PORT_CMD_MDIOCAP32_S) 2800c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOCAP32_G(x) \ 2801c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M) 2802c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U) 2803c3168cabSGanesh Goudar 2804c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOADDR32_S 21 2805c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOADDR32_M 0x1f 2806c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOADDR32_V(x) ((x) << FW_PORT_CMD_MDIOADDR32_S) 2807c3168cabSGanesh Goudar #define FW_PORT_CMD_MDIOADDR32_G(x) \ 2808c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M) 2809c3168cabSGanesh Goudar 2810c3168cabSGanesh Goudar #define FW_PORT_CMD_PORTTYPE32_S 13 2811c3168cabSGanesh Goudar #define FW_PORT_CMD_PORTTYPE32_M 0xff 2812c3168cabSGanesh Goudar #define FW_PORT_CMD_PORTTYPE32_V(x) ((x) << FW_PORT_CMD_PORTTYPE32_S) 2813c3168cabSGanesh Goudar #define FW_PORT_CMD_PORTTYPE32_G(x) \ 2814c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M) 2815c3168cabSGanesh Goudar 2816c3168cabSGanesh Goudar #define FW_PORT_CMD_MODTYPE32_S 8 2817c3168cabSGanesh Goudar #define FW_PORT_CMD_MODTYPE32_M 0x1f 2818c3168cabSGanesh Goudar #define FW_PORT_CMD_MODTYPE32_V(x) ((x) << FW_PORT_CMD_MODTYPE32_S) 2819c3168cabSGanesh Goudar #define FW_PORT_CMD_MODTYPE32_G(x) \ 2820c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M) 2821c3168cabSGanesh Goudar 2822c3168cabSGanesh Goudar #define FW_PORT_CMD_CBLLEN32_S 0 2823c3168cabSGanesh Goudar #define FW_PORT_CMD_CBLLEN32_M 0xff 2824c3168cabSGanesh Goudar #define FW_PORT_CMD_CBLLEN32_V(x) ((x) << FW_PORT_CMD_CBLLEN32_S) 2825c3168cabSGanesh Goudar #define FW_PORT_CMD_CBLLEN32_G(x) \ 2826c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M) 2827c3168cabSGanesh Goudar 2828c3168cabSGanesh Goudar #define FW_PORT_CMD_AUXLINFO32_S 24 2829c3168cabSGanesh Goudar #define FW_PORT_CMD_AUXLINFO32_M 0xff 2830c3168cabSGanesh Goudar #define FW_PORT_CMD_AUXLINFO32_V(x) ((x) << FW_PORT_CMD_AUXLINFO32_S) 2831c3168cabSGanesh Goudar #define FW_PORT_CMD_AUXLINFO32_G(x) \ 2832c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M) 2833c3168cabSGanesh Goudar 2834c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KX4_S 2 2835c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KX4_M 0x1 2836c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KX4_V(x) \ 2837c3168cabSGanesh Goudar ((x) << FW_PORT_AUXLINFO32_KX4_S) 2838c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KX4_G(x) \ 2839c3168cabSGanesh Goudar (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M) 2840c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KX4_F FW_PORT_AUXLINFO32_KX4_V(1U) 2841c3168cabSGanesh Goudar 2842c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KR_S 1 2843c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KR_M 0x1 2844c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KR_V(x) \ 2845c3168cabSGanesh Goudar ((x) << FW_PORT_AUXLINFO32_KR_S) 2846c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KR_G(x) \ 2847c3168cabSGanesh Goudar (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M) 2848c3168cabSGanesh Goudar #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U) 2849c3168cabSGanesh Goudar 2850c3168cabSGanesh Goudar #define FW_PORT_CMD_MTU32_S 0 2851c3168cabSGanesh Goudar #define FW_PORT_CMD_MTU32_M 0xffff 2852c3168cabSGanesh Goudar #define FW_PORT_CMD_MTU32_V(x) ((x) << FW_PORT_CMD_MTU32_S) 2853c3168cabSGanesh Goudar #define FW_PORT_CMD_MTU32_G(x) \ 2854c3168cabSGanesh Goudar (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M) 2855c3168cabSGanesh Goudar 2856f7917c00SJeff Kirsher enum fw_port_type { 2857f7917c00SJeff Kirsher FW_PORT_TYPE_FIBER_XFI, 2858f7917c00SJeff Kirsher FW_PORT_TYPE_FIBER_XAUI, 2859f7917c00SJeff Kirsher FW_PORT_TYPE_BT_SGMII, 2860f7917c00SJeff Kirsher FW_PORT_TYPE_BT_XFI, 2861f7917c00SJeff Kirsher FW_PORT_TYPE_BT_XAUI, 2862f7917c00SJeff Kirsher FW_PORT_TYPE_KX4, 2863f7917c00SJeff Kirsher FW_PORT_TYPE_CX4, 2864f7917c00SJeff Kirsher FW_PORT_TYPE_KX, 2865f7917c00SJeff Kirsher FW_PORT_TYPE_KR, 2866f7917c00SJeff Kirsher FW_PORT_TYPE_SFP, 2867f7917c00SJeff Kirsher FW_PORT_TYPE_BP_AP, 2868f7917c00SJeff Kirsher FW_PORT_TYPE_BP4_AP, 286972aca4bfSKumar Sanghvi FW_PORT_TYPE_QSFP_10G, 287040e9de4bSHariprasad Shenai FW_PORT_TYPE_QSA, 28715aa80e51SHariprasad Shenai FW_PORT_TYPE_QSFP, 287272aca4bfSKumar Sanghvi FW_PORT_TYPE_BP40_BA, 2873eb97ad99SGanesh Goudar FW_PORT_TYPE_KR4_100G, 2874eb97ad99SGanesh Goudar FW_PORT_TYPE_CR4_QSFP, 2875eb97ad99SGanesh Goudar FW_PORT_TYPE_CR_QSFP, 2876eb97ad99SGanesh Goudar FW_PORT_TYPE_CR2_QSFP, 2877eb97ad99SGanesh Goudar FW_PORT_TYPE_SFP28, 28782061ec3fSGanesh Goudar FW_PORT_TYPE_KR_SFP28, 2879b39ab140SGanesh Goudar FW_PORT_TYPE_KR_XLAUI, 2880f7917c00SJeff Kirsher 28812b5fb1f2SHariprasad Shenai FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M 2882f7917c00SJeff Kirsher }; 2883f7917c00SJeff Kirsher 2884f7917c00SJeff Kirsher enum fw_port_module_type { 2885f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_NA, 2886f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_LR, 2887f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_SR, 2888f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_ER, 2889f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_TWINAX_PASSIVE, 2890f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_TWINAX_ACTIVE, 2891f7917c00SJeff Kirsher FW_PORT_MOD_TYPE_LRM, 28922b5fb1f2SHariprasad Shenai FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3, 28932b5fb1f2SHariprasad Shenai FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2, 28942b5fb1f2SHariprasad Shenai FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1, 2895f7917c00SJeff Kirsher 28962b5fb1f2SHariprasad Shenai FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M 2897f7917c00SJeff Kirsher }; 2898f7917c00SJeff Kirsher 2899b407a4a9SVipul Pandya enum fw_port_mod_sub_type { 2900b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_NA, 2901b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 2902b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 2903b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 2904b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 2905b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 2906b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 2907b407a4a9SVipul Pandya 2908b407a4a9SVipul Pandya /* The following will never been in the VPD. They are TWINAX cable 2909b407a4a9SVipul Pandya * lengths decoded from SFP+ module i2c PROMs. These should 2910b407a4a9SVipul Pandya * almost certainly go somewhere else ... 2911b407a4a9SVipul Pandya */ 2912b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 2913b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 2914b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 2915b407a4a9SVipul Pandya FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 2916b407a4a9SVipul Pandya }; 2917b407a4a9SVipul Pandya 2918f7917c00SJeff Kirsher enum fw_port_stats_tx_index { 29193ccc6cf7SHariprasad Shenai FW_STAT_TX_PORT_BYTES_IX = 0, 2920f7917c00SJeff Kirsher FW_STAT_TX_PORT_FRAMES_IX, 2921f7917c00SJeff Kirsher FW_STAT_TX_PORT_BCAST_IX, 2922f7917c00SJeff Kirsher FW_STAT_TX_PORT_MCAST_IX, 2923f7917c00SJeff Kirsher FW_STAT_TX_PORT_UCAST_IX, 2924f7917c00SJeff Kirsher FW_STAT_TX_PORT_ERROR_IX, 2925f7917c00SJeff Kirsher FW_STAT_TX_PORT_64B_IX, 2926f7917c00SJeff Kirsher FW_STAT_TX_PORT_65B_127B_IX, 2927f7917c00SJeff Kirsher FW_STAT_TX_PORT_128B_255B_IX, 2928f7917c00SJeff Kirsher FW_STAT_TX_PORT_256B_511B_IX, 2929f7917c00SJeff Kirsher FW_STAT_TX_PORT_512B_1023B_IX, 2930f7917c00SJeff Kirsher FW_STAT_TX_PORT_1024B_1518B_IX, 2931f7917c00SJeff Kirsher FW_STAT_TX_PORT_1519B_MAX_IX, 2932f7917c00SJeff Kirsher FW_STAT_TX_PORT_DROP_IX, 2933f7917c00SJeff Kirsher FW_STAT_TX_PORT_PAUSE_IX, 2934f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP0_IX, 2935f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP1_IX, 2936f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP2_IX, 2937f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP3_IX, 2938f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP4_IX, 2939f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP5_IX, 2940f7917c00SJeff Kirsher FW_STAT_TX_PORT_PPP6_IX, 29413ccc6cf7SHariprasad Shenai FW_STAT_TX_PORT_PPP7_IX, 29423ccc6cf7SHariprasad Shenai FW_NUM_PORT_TX_STATS 2943f7917c00SJeff Kirsher }; 2944f7917c00SJeff Kirsher 2945f7917c00SJeff Kirsher enum fw_port_stat_rx_index { 29463ccc6cf7SHariprasad Shenai FW_STAT_RX_PORT_BYTES_IX = 0, 2947f7917c00SJeff Kirsher FW_STAT_RX_PORT_FRAMES_IX, 2948f7917c00SJeff Kirsher FW_STAT_RX_PORT_BCAST_IX, 2949f7917c00SJeff Kirsher FW_STAT_RX_PORT_MCAST_IX, 2950f7917c00SJeff Kirsher FW_STAT_RX_PORT_UCAST_IX, 2951f7917c00SJeff Kirsher FW_STAT_RX_PORT_MTU_ERROR_IX, 2952f7917c00SJeff Kirsher FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2953f7917c00SJeff Kirsher FW_STAT_RX_PORT_CRC_ERROR_IX, 2954f7917c00SJeff Kirsher FW_STAT_RX_PORT_LEN_ERROR_IX, 2955f7917c00SJeff Kirsher FW_STAT_RX_PORT_SYM_ERROR_IX, 2956f7917c00SJeff Kirsher FW_STAT_RX_PORT_64B_IX, 2957f7917c00SJeff Kirsher FW_STAT_RX_PORT_65B_127B_IX, 2958f7917c00SJeff Kirsher FW_STAT_RX_PORT_128B_255B_IX, 2959f7917c00SJeff Kirsher FW_STAT_RX_PORT_256B_511B_IX, 2960f7917c00SJeff Kirsher FW_STAT_RX_PORT_512B_1023B_IX, 2961f7917c00SJeff Kirsher FW_STAT_RX_PORT_1024B_1518B_IX, 2962f7917c00SJeff Kirsher FW_STAT_RX_PORT_1519B_MAX_IX, 2963f7917c00SJeff Kirsher FW_STAT_RX_PORT_PAUSE_IX, 2964f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP0_IX, 2965f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP1_IX, 2966f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP2_IX, 2967f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP3_IX, 2968f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP4_IX, 2969f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP5_IX, 2970f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP6_IX, 2971f7917c00SJeff Kirsher FW_STAT_RX_PORT_PPP7_IX, 29723ccc6cf7SHariprasad Shenai FW_STAT_RX_PORT_LESS_64B_IX, 29733ccc6cf7SHariprasad Shenai FW_STAT_RX_PORT_MAC_ERROR_IX, 29743ccc6cf7SHariprasad Shenai FW_NUM_PORT_RX_STATS 2975f7917c00SJeff Kirsher }; 2976f7917c00SJeff Kirsher 29773ccc6cf7SHariprasad Shenai /* port stats */ 29783ccc6cf7SHariprasad Shenai #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS) 29793ccc6cf7SHariprasad Shenai 2980f7917c00SJeff Kirsher struct fw_port_stats_cmd { 2981f7917c00SJeff Kirsher __be32 op_to_portid; 2982f7917c00SJeff Kirsher __be32 retval_len16; 2983f7917c00SJeff Kirsher union fw_port_stats { 2984f7917c00SJeff Kirsher struct fw_port_stats_ctl { 2985f7917c00SJeff Kirsher u8 nstats_bg_bm; 2986f7917c00SJeff Kirsher u8 tx_ix; 2987f7917c00SJeff Kirsher __be16 r6; 2988f7917c00SJeff Kirsher __be32 r7; 2989f7917c00SJeff Kirsher __be64 stat0; 2990f7917c00SJeff Kirsher __be64 stat1; 2991f7917c00SJeff Kirsher __be64 stat2; 2992f7917c00SJeff Kirsher __be64 stat3; 2993f7917c00SJeff Kirsher __be64 stat4; 2994f7917c00SJeff Kirsher __be64 stat5; 2995f7917c00SJeff Kirsher } ctl; 2996f7917c00SJeff Kirsher struct fw_port_stats_all { 2997f7917c00SJeff Kirsher __be64 tx_bytes; 2998f7917c00SJeff Kirsher __be64 tx_frames; 2999f7917c00SJeff Kirsher __be64 tx_bcast; 3000f7917c00SJeff Kirsher __be64 tx_mcast; 3001f7917c00SJeff Kirsher __be64 tx_ucast; 3002f7917c00SJeff Kirsher __be64 tx_error; 3003f7917c00SJeff Kirsher __be64 tx_64b; 3004f7917c00SJeff Kirsher __be64 tx_65b_127b; 3005f7917c00SJeff Kirsher __be64 tx_128b_255b; 3006f7917c00SJeff Kirsher __be64 tx_256b_511b; 3007f7917c00SJeff Kirsher __be64 tx_512b_1023b; 3008f7917c00SJeff Kirsher __be64 tx_1024b_1518b; 3009f7917c00SJeff Kirsher __be64 tx_1519b_max; 3010f7917c00SJeff Kirsher __be64 tx_drop; 3011f7917c00SJeff Kirsher __be64 tx_pause; 3012f7917c00SJeff Kirsher __be64 tx_ppp0; 3013f7917c00SJeff Kirsher __be64 tx_ppp1; 3014f7917c00SJeff Kirsher __be64 tx_ppp2; 3015f7917c00SJeff Kirsher __be64 tx_ppp3; 3016f7917c00SJeff Kirsher __be64 tx_ppp4; 3017f7917c00SJeff Kirsher __be64 tx_ppp5; 3018f7917c00SJeff Kirsher __be64 tx_ppp6; 3019f7917c00SJeff Kirsher __be64 tx_ppp7; 3020f7917c00SJeff Kirsher __be64 rx_bytes; 3021f7917c00SJeff Kirsher __be64 rx_frames; 3022f7917c00SJeff Kirsher __be64 rx_bcast; 3023f7917c00SJeff Kirsher __be64 rx_mcast; 3024f7917c00SJeff Kirsher __be64 rx_ucast; 3025f7917c00SJeff Kirsher __be64 rx_mtu_error; 3026f7917c00SJeff Kirsher __be64 rx_mtu_crc_error; 3027f7917c00SJeff Kirsher __be64 rx_crc_error; 3028f7917c00SJeff Kirsher __be64 rx_len_error; 3029f7917c00SJeff Kirsher __be64 rx_sym_error; 3030f7917c00SJeff Kirsher __be64 rx_64b; 3031f7917c00SJeff Kirsher __be64 rx_65b_127b; 3032f7917c00SJeff Kirsher __be64 rx_128b_255b; 3033f7917c00SJeff Kirsher __be64 rx_256b_511b; 3034f7917c00SJeff Kirsher __be64 rx_512b_1023b; 3035f7917c00SJeff Kirsher __be64 rx_1024b_1518b; 3036f7917c00SJeff Kirsher __be64 rx_1519b_max; 3037f7917c00SJeff Kirsher __be64 rx_pause; 3038f7917c00SJeff Kirsher __be64 rx_ppp0; 3039f7917c00SJeff Kirsher __be64 rx_ppp1; 3040f7917c00SJeff Kirsher __be64 rx_ppp2; 3041f7917c00SJeff Kirsher __be64 rx_ppp3; 3042f7917c00SJeff Kirsher __be64 rx_ppp4; 3043f7917c00SJeff Kirsher __be64 rx_ppp5; 3044f7917c00SJeff Kirsher __be64 rx_ppp6; 3045f7917c00SJeff Kirsher __be64 rx_ppp7; 3046f7917c00SJeff Kirsher __be64 rx_less_64b; 3047f7917c00SJeff Kirsher __be64 rx_bg_drop; 3048f7917c00SJeff Kirsher __be64 rx_bg_trunc; 3049f7917c00SJeff Kirsher } all; 3050f7917c00SJeff Kirsher } u; 3051f7917c00SJeff Kirsher }; 3052f7917c00SJeff Kirsher 3053f7917c00SJeff Kirsher /* port loopback stats */ 3054f7917c00SJeff Kirsher #define FW_NUM_LB_STATS 16 3055f7917c00SJeff Kirsher enum fw_port_lb_stats_index { 3056f7917c00SJeff Kirsher FW_STAT_LB_PORT_BYTES_IX, 3057f7917c00SJeff Kirsher FW_STAT_LB_PORT_FRAMES_IX, 3058f7917c00SJeff Kirsher FW_STAT_LB_PORT_BCAST_IX, 3059f7917c00SJeff Kirsher FW_STAT_LB_PORT_MCAST_IX, 3060f7917c00SJeff Kirsher FW_STAT_LB_PORT_UCAST_IX, 3061f7917c00SJeff Kirsher FW_STAT_LB_PORT_ERROR_IX, 3062f7917c00SJeff Kirsher FW_STAT_LB_PORT_64B_IX, 3063f7917c00SJeff Kirsher FW_STAT_LB_PORT_65B_127B_IX, 3064f7917c00SJeff Kirsher FW_STAT_LB_PORT_128B_255B_IX, 3065f7917c00SJeff Kirsher FW_STAT_LB_PORT_256B_511B_IX, 3066f7917c00SJeff Kirsher FW_STAT_LB_PORT_512B_1023B_IX, 3067f7917c00SJeff Kirsher FW_STAT_LB_PORT_1024B_1518B_IX, 3068f7917c00SJeff Kirsher FW_STAT_LB_PORT_1519B_MAX_IX, 3069f7917c00SJeff Kirsher FW_STAT_LB_PORT_DROP_FRAMES_IX 3070f7917c00SJeff Kirsher }; 3071f7917c00SJeff Kirsher 3072f7917c00SJeff Kirsher struct fw_port_lb_stats_cmd { 3073f7917c00SJeff Kirsher __be32 op_to_lbport; 3074f7917c00SJeff Kirsher __be32 retval_len16; 3075f7917c00SJeff Kirsher union fw_port_lb_stats { 3076f7917c00SJeff Kirsher struct fw_port_lb_stats_ctl { 3077f7917c00SJeff Kirsher u8 nstats_bg_bm; 3078f7917c00SJeff Kirsher u8 ix_pkd; 3079f7917c00SJeff Kirsher __be16 r6; 3080f7917c00SJeff Kirsher __be32 r7; 3081f7917c00SJeff Kirsher __be64 stat0; 3082f7917c00SJeff Kirsher __be64 stat1; 3083f7917c00SJeff Kirsher __be64 stat2; 3084f7917c00SJeff Kirsher __be64 stat3; 3085f7917c00SJeff Kirsher __be64 stat4; 3086f7917c00SJeff Kirsher __be64 stat5; 3087f7917c00SJeff Kirsher } ctl; 3088f7917c00SJeff Kirsher struct fw_port_lb_stats_all { 3089f7917c00SJeff Kirsher __be64 tx_bytes; 3090f7917c00SJeff Kirsher __be64 tx_frames; 3091f7917c00SJeff Kirsher __be64 tx_bcast; 3092f7917c00SJeff Kirsher __be64 tx_mcast; 3093f7917c00SJeff Kirsher __be64 tx_ucast; 3094f7917c00SJeff Kirsher __be64 tx_error; 3095f7917c00SJeff Kirsher __be64 tx_64b; 3096f7917c00SJeff Kirsher __be64 tx_65b_127b; 3097f7917c00SJeff Kirsher __be64 tx_128b_255b; 3098f7917c00SJeff Kirsher __be64 tx_256b_511b; 3099f7917c00SJeff Kirsher __be64 tx_512b_1023b; 3100f7917c00SJeff Kirsher __be64 tx_1024b_1518b; 3101f7917c00SJeff Kirsher __be64 tx_1519b_max; 3102f7917c00SJeff Kirsher __be64 rx_lb_drop; 3103f7917c00SJeff Kirsher __be64 rx_lb_trunc; 3104f7917c00SJeff Kirsher } all; 3105f7917c00SJeff Kirsher } u; 3106f7917c00SJeff Kirsher }; 3107f7917c00SJeff Kirsher 3108a4569504SAtul Gupta enum fw_ptp_subop { 3109a4569504SAtul Gupta /* none */ 3110a4569504SAtul Gupta FW_PTP_SC_INIT_TIMER = 0x00, 3111a4569504SAtul Gupta FW_PTP_SC_TX_TYPE = 0x01, 3112a4569504SAtul Gupta /* init */ 3113a4569504SAtul Gupta FW_PTP_SC_RXTIME_STAMP = 0x08, 3114a4569504SAtul Gupta FW_PTP_SC_RDRX_TYPE = 0x09, 3115a4569504SAtul Gupta /* ts */ 3116a4569504SAtul Gupta FW_PTP_SC_ADJ_FREQ = 0x10, 3117a4569504SAtul Gupta FW_PTP_SC_ADJ_TIME = 0x11, 3118a4569504SAtul Gupta FW_PTP_SC_ADJ_FTIME = 0x12, 3119a4569504SAtul Gupta FW_PTP_SC_WALL_CLOCK = 0x13, 3120a4569504SAtul Gupta FW_PTP_SC_GET_TIME = 0x14, 3121a4569504SAtul Gupta FW_PTP_SC_SET_TIME = 0x15, 3122a4569504SAtul Gupta }; 3123a4569504SAtul Gupta 3124a4569504SAtul Gupta struct fw_ptp_cmd { 3125a4569504SAtul Gupta __be32 op_to_portid; 3126a4569504SAtul Gupta __be32 retval_len16; 3127a4569504SAtul Gupta union fw_ptp { 3128a4569504SAtul Gupta struct fw_ptp_sc { 3129a4569504SAtul Gupta __u8 sc; 3130a4569504SAtul Gupta __u8 r3[7]; 3131a4569504SAtul Gupta } scmd; 3132a4569504SAtul Gupta struct fw_ptp_init { 3133a4569504SAtul Gupta __u8 sc; 3134a4569504SAtul Gupta __u8 txchan; 3135a4569504SAtul Gupta __be16 absid; 3136a4569504SAtul Gupta __be16 mode; 3137a4569504SAtul Gupta __be16 r3; 3138a4569504SAtul Gupta } init; 3139a4569504SAtul Gupta struct fw_ptp_ts { 3140a4569504SAtul Gupta __u8 sc; 3141a4569504SAtul Gupta __u8 sign; 3142a4569504SAtul Gupta __be16 r3; 3143a4569504SAtul Gupta __be32 ppb; 3144a4569504SAtul Gupta __be64 tm; 3145a4569504SAtul Gupta } ts; 3146a4569504SAtul Gupta } u; 3147a4569504SAtul Gupta __be64 r3; 3148a4569504SAtul Gupta }; 3149a4569504SAtul Gupta 3150a4569504SAtul Gupta #define FW_PTP_CMD_PORTID_S 0 3151a4569504SAtul Gupta #define FW_PTP_CMD_PORTID_M 0xf 3152a4569504SAtul Gupta #define FW_PTP_CMD_PORTID_V(x) ((x) << FW_PTP_CMD_PORTID_S) 3153a4569504SAtul Gupta #define FW_PTP_CMD_PORTID_G(x) \ 3154a4569504SAtul Gupta (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M) 3155a4569504SAtul Gupta 3156f7917c00SJeff Kirsher struct fw_rss_ind_tbl_cmd { 3157f7917c00SJeff Kirsher __be32 op_to_viid; 3158f7917c00SJeff Kirsher __be32 retval_len16; 3159f7917c00SJeff Kirsher __be16 niqid; 3160f7917c00SJeff Kirsher __be16 startidx; 3161f7917c00SJeff Kirsher __be32 r3; 3162f7917c00SJeff Kirsher __be32 iq0_to_iq2; 3163f7917c00SJeff Kirsher __be32 iq3_to_iq5; 3164f7917c00SJeff Kirsher __be32 iq6_to_iq8; 3165f7917c00SJeff Kirsher __be32 iq9_to_iq11; 3166f7917c00SJeff Kirsher __be32 iq12_to_iq14; 3167f7917c00SJeff Kirsher __be32 iq15_to_iq17; 3168f7917c00SJeff Kirsher __be32 iq18_to_iq20; 3169f7917c00SJeff Kirsher __be32 iq21_to_iq23; 3170f7917c00SJeff Kirsher __be32 iq24_to_iq26; 3171f7917c00SJeff Kirsher __be32 iq27_to_iq29; 3172f7917c00SJeff Kirsher __be32 iq30_iq31; 3173f7917c00SJeff Kirsher __be32 r15_lo; 3174f7917c00SJeff Kirsher }; 3175f7917c00SJeff Kirsher 3176b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_VIID_S 0 3177b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S) 3178b2e1a3f0SHariprasad Shenai 3179b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ0_S 20 3180b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S) 3181b2e1a3f0SHariprasad Shenai 3182b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ1_S 10 3183b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S) 3184b2e1a3f0SHariprasad Shenai 3185b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ2_S 0 3186b2e1a3f0SHariprasad Shenai #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S) 3187b2e1a3f0SHariprasad Shenai 3188f7917c00SJeff Kirsher struct fw_rss_glb_config_cmd { 3189f7917c00SJeff Kirsher __be32 op_to_write; 3190f7917c00SJeff Kirsher __be32 retval_len16; 3191f7917c00SJeff Kirsher union fw_rss_glb_config { 3192f7917c00SJeff Kirsher struct fw_rss_glb_config_manual { 3193f7917c00SJeff Kirsher __be32 mode_pkd; 3194f7917c00SJeff Kirsher __be32 r3; 3195f7917c00SJeff Kirsher __be64 r4; 3196f7917c00SJeff Kirsher __be64 r5; 3197f7917c00SJeff Kirsher } manual; 3198f7917c00SJeff Kirsher struct fw_rss_glb_config_basicvirtual { 3199f7917c00SJeff Kirsher __be32 mode_pkd; 3200f7917c00SJeff Kirsher __be32 synmapen_to_hashtoeplitz; 3201f7917c00SJeff Kirsher __be64 r8; 3202f7917c00SJeff Kirsher __be64 r9; 3203f7917c00SJeff Kirsher } basicvirtual; 3204f7917c00SJeff Kirsher } u; 3205f7917c00SJeff Kirsher }; 3206f7917c00SJeff Kirsher 3207b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28 3208b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf 3209b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S) 3210b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \ 3211b2e1a3f0SHariprasad Shenai (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M) 3212f7917c00SJeff Kirsher 3213f7917c00SJeff Kirsher #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 3214f7917c00SJeff Kirsher #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 3215f7917c00SJeff Kirsher 3216b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8 3217b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \ 3218b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S) 3219b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \ 3220b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U) 3221b2e1a3f0SHariprasad Shenai 3222b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7 3223b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \ 3224b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S) 3225b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \ 3226b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U) 3227b2e1a3f0SHariprasad Shenai 3228b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6 3229b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \ 3230b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S) 3231b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \ 3232b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U) 3233b2e1a3f0SHariprasad Shenai 3234b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5 3235b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \ 3236b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S) 3237b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \ 3238b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U) 3239b2e1a3f0SHariprasad Shenai 3240b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4 3241b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \ 3242b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S) 3243b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \ 3244b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U) 3245b2e1a3f0SHariprasad Shenai 3246b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3 3247b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \ 3248b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S) 3249b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \ 3250b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U) 3251b2e1a3f0SHariprasad Shenai 3252b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2 3253b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \ 3254b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S) 3255b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \ 3256b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U) 3257b2e1a3f0SHariprasad Shenai 3258b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1 3259b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \ 3260b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S) 3261b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \ 3262b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U) 3263b2e1a3f0SHariprasad Shenai 3264b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0 3265b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \ 3266b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S) 3267b2e1a3f0SHariprasad Shenai #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \ 3268b2e1a3f0SHariprasad Shenai FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U) 3269b2e1a3f0SHariprasad Shenai 3270f7917c00SJeff Kirsher struct fw_rss_vi_config_cmd { 3271f7917c00SJeff Kirsher __be32 op_to_viid; 3272f7917c00SJeff Kirsher #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0) 3273f7917c00SJeff Kirsher __be32 retval_len16; 3274f7917c00SJeff Kirsher union fw_rss_vi_config { 3275f7917c00SJeff Kirsher struct fw_rss_vi_config_manual { 3276f7917c00SJeff Kirsher __be64 r3; 3277f7917c00SJeff Kirsher __be64 r4; 3278f7917c00SJeff Kirsher __be64 r5; 3279f7917c00SJeff Kirsher } manual; 3280f7917c00SJeff Kirsher struct fw_rss_vi_config_basicvirtual { 3281f7917c00SJeff Kirsher __be32 r6; 3282f7917c00SJeff Kirsher __be32 defaultq_to_udpen; 3283f7917c00SJeff Kirsher __be64 r9; 3284f7917c00SJeff Kirsher __be64 r10; 3285f7917c00SJeff Kirsher } basicvirtual; 3286f7917c00SJeff Kirsher } u; 3287f7917c00SJeff Kirsher }; 3288f7917c00SJeff Kirsher 3289b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_VIID_S 0 3290b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S) 3291b2e1a3f0SHariprasad Shenai 3292b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16 3293b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff 3294b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \ 3295b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) 3296b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \ 3297b2e1a3f0SHariprasad Shenai (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \ 3298b2e1a3f0SHariprasad Shenai FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M) 3299b2e1a3f0SHariprasad Shenai 3300b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4 3301b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \ 3302b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S) 3303b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \ 3304b2e1a3f0SHariprasad Shenai FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U) 3305b2e1a3f0SHariprasad Shenai 3306b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3 3307b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \ 3308b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S) 3309b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \ 3310b2e1a3f0SHariprasad Shenai FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U) 3311b2e1a3f0SHariprasad Shenai 3312b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2 3313b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \ 3314b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S) 3315b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \ 3316b2e1a3f0SHariprasad Shenai FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U) 3317b2e1a3f0SHariprasad Shenai 3318b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1 3319b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \ 3320b2e1a3f0SHariprasad Shenai ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S) 3321b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \ 3322b2e1a3f0SHariprasad Shenai FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U) 3323b2e1a3f0SHariprasad Shenai 3324b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0 3325b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S) 3326b2e1a3f0SHariprasad Shenai #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U) 3327b2e1a3f0SHariprasad Shenai 3328b72a32daSRahul Lakkireddy enum fw_sched_sc { 3329b72a32daSRahul Lakkireddy FW_SCHED_SC_PARAMS = 1, 3330b72a32daSRahul Lakkireddy }; 3331b72a32daSRahul Lakkireddy 3332b72a32daSRahul Lakkireddy struct fw_sched_cmd { 3333b72a32daSRahul Lakkireddy __be32 op_to_write; 3334b72a32daSRahul Lakkireddy __be32 retval_len16; 3335b72a32daSRahul Lakkireddy union fw_sched { 3336b72a32daSRahul Lakkireddy struct fw_sched_config { 3337b72a32daSRahul Lakkireddy __u8 sc; 3338b72a32daSRahul Lakkireddy __u8 type; 3339b72a32daSRahul Lakkireddy __u8 minmaxen; 3340b72a32daSRahul Lakkireddy __u8 r3[5]; 3341b72a32daSRahul Lakkireddy __u8 nclasses[4]; 3342b72a32daSRahul Lakkireddy __be32 r4; 3343b72a32daSRahul Lakkireddy } config; 3344b72a32daSRahul Lakkireddy struct fw_sched_params { 3345b72a32daSRahul Lakkireddy __u8 sc; 3346b72a32daSRahul Lakkireddy __u8 type; 3347b72a32daSRahul Lakkireddy __u8 level; 3348b72a32daSRahul Lakkireddy __u8 mode; 3349b72a32daSRahul Lakkireddy __u8 unit; 3350b72a32daSRahul Lakkireddy __u8 rate; 3351b72a32daSRahul Lakkireddy __u8 ch; 3352b72a32daSRahul Lakkireddy __u8 cl; 3353b72a32daSRahul Lakkireddy __be32 min; 3354b72a32daSRahul Lakkireddy __be32 max; 3355b72a32daSRahul Lakkireddy __be16 weight; 3356b72a32daSRahul Lakkireddy __be16 pktsize; 3357b72a32daSRahul Lakkireddy __be16 burstsize; 3358b72a32daSRahul Lakkireddy __be16 r4; 3359b72a32daSRahul Lakkireddy } params; 3360b72a32daSRahul Lakkireddy } u; 3361b72a32daSRahul Lakkireddy }; 3362b72a32daSRahul Lakkireddy 336301bcca68SVipul Pandya struct fw_clip_cmd { 336401bcca68SVipul Pandya __be32 op_to_write; 336501bcca68SVipul Pandya __be32 alloc_to_len16; 336601bcca68SVipul Pandya __be64 ip_hi; 336701bcca68SVipul Pandya __be64 ip_lo; 336801bcca68SVipul Pandya __be32 r4[2]; 336901bcca68SVipul Pandya }; 337001bcca68SVipul Pandya 3371b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_ALLOC_S 31 3372b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S) 3373b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U) 337401bcca68SVipul Pandya 3375b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_FREE_S 30 3376b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S) 3377b2e1a3f0SHariprasad Shenai #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U) 337801bcca68SVipul Pandya 3379f7917c00SJeff Kirsher enum fw_error_type { 3380f7917c00SJeff Kirsher FW_ERROR_TYPE_EXCEPTION = 0x0, 3381f7917c00SJeff Kirsher FW_ERROR_TYPE_HWMODULE = 0x1, 3382f7917c00SJeff Kirsher FW_ERROR_TYPE_WR = 0x2, 3383f7917c00SJeff Kirsher FW_ERROR_TYPE_ACL = 0x3, 3384f7917c00SJeff Kirsher }; 3385f7917c00SJeff Kirsher 3386f7917c00SJeff Kirsher struct fw_error_cmd { 3387f7917c00SJeff Kirsher __be32 op_to_type; 3388f7917c00SJeff Kirsher __be32 len16_pkd; 3389f7917c00SJeff Kirsher union fw_error { 3390f7917c00SJeff Kirsher struct fw_error_exception { 3391f7917c00SJeff Kirsher __be32 info[6]; 3392f7917c00SJeff Kirsher } exception; 3393f7917c00SJeff Kirsher struct fw_error_hwmodule { 3394f7917c00SJeff Kirsher __be32 regaddr; 3395f7917c00SJeff Kirsher __be32 regval; 3396f7917c00SJeff Kirsher } hwmodule; 3397f7917c00SJeff Kirsher struct fw_error_wr { 3398f7917c00SJeff Kirsher __be16 cidx; 3399f7917c00SJeff Kirsher __be16 pfn_vfn; 3400f7917c00SJeff Kirsher __be32 eqid; 3401f7917c00SJeff Kirsher u8 wrhdr[16]; 3402f7917c00SJeff Kirsher } wr; 3403f7917c00SJeff Kirsher struct fw_error_acl { 3404f7917c00SJeff Kirsher __be16 cidx; 3405f7917c00SJeff Kirsher __be16 pfn_vfn; 3406f7917c00SJeff Kirsher __be32 eqid; 3407f7917c00SJeff Kirsher __be16 mv_pkd; 3408f7917c00SJeff Kirsher u8 val[6]; 3409f7917c00SJeff Kirsher __be64 r4; 3410f7917c00SJeff Kirsher } acl; 3411f7917c00SJeff Kirsher } u; 3412f7917c00SJeff Kirsher }; 3413f7917c00SJeff Kirsher 3414f7917c00SJeff Kirsher struct fw_debug_cmd { 3415f7917c00SJeff Kirsher __be32 op_type; 3416f7917c00SJeff Kirsher __be32 len16_pkd; 3417f7917c00SJeff Kirsher union fw_debug { 3418f7917c00SJeff Kirsher struct fw_debug_assert { 3419f7917c00SJeff Kirsher __be32 fcid; 3420f7917c00SJeff Kirsher __be32 line; 3421f7917c00SJeff Kirsher __be32 x; 3422f7917c00SJeff Kirsher __be32 y; 3423f7917c00SJeff Kirsher u8 filename_0_7[8]; 3424f7917c00SJeff Kirsher u8 filename_8_15[8]; 3425f7917c00SJeff Kirsher __be64 r3; 3426f7917c00SJeff Kirsher } assert; 3427f7917c00SJeff Kirsher struct fw_debug_prt { 3428f7917c00SJeff Kirsher __be16 dprtstridx; 3429f7917c00SJeff Kirsher __be16 r3[3]; 3430f7917c00SJeff Kirsher __be32 dprtstrparam0; 3431f7917c00SJeff Kirsher __be32 dprtstrparam1; 3432f7917c00SJeff Kirsher __be32 dprtstrparam2; 3433f7917c00SJeff Kirsher __be32 dprtstrparam3; 3434f7917c00SJeff Kirsher } prt; 3435f7917c00SJeff Kirsher } u; 3436f7917c00SJeff Kirsher }; 3437f7917c00SJeff Kirsher 3438b2e1a3f0SHariprasad Shenai #define FW_DEBUG_CMD_TYPE_S 0 3439b2e1a3f0SHariprasad Shenai #define FW_DEBUG_CMD_TYPE_M 0xff 3440b2e1a3f0SHariprasad Shenai #define FW_DEBUG_CMD_TYPE_G(x) \ 3441b2e1a3f0SHariprasad Shenai (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M) 3442b2e1a3f0SHariprasad Shenai 34438b4e6b3cSArjun Vynipadath struct fw_hma_cmd { 34448b4e6b3cSArjun Vynipadath __be32 op_pkd; 34458b4e6b3cSArjun Vynipadath __be32 retval_len16; 34468b4e6b3cSArjun Vynipadath __be32 mode_to_pcie_params; 34478b4e6b3cSArjun Vynipadath __be32 naddr_size; 34488b4e6b3cSArjun Vynipadath __be32 addr_size_pkd; 34498b4e6b3cSArjun Vynipadath __be32 r6; 34508b4e6b3cSArjun Vynipadath __be64 phy_address[5]; 34518b4e6b3cSArjun Vynipadath }; 34528b4e6b3cSArjun Vynipadath 34538b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_MODE_S 31 34548b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_MODE_M 0x1 34558b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_MODE_V(x) ((x) << FW_HMA_CMD_MODE_S) 34568b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_MODE_G(x) \ 34578b4e6b3cSArjun Vynipadath (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M) 34588b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_MODE_F FW_HMA_CMD_MODE_V(1U) 34598b4e6b3cSArjun Vynipadath 34608b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SOC_S 30 34618b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SOC_M 0x1 34628b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SOC_V(x) ((x) << FW_HMA_CMD_SOC_S) 34638b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SOC_G(x) (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M) 34648b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SOC_F FW_HMA_CMD_SOC_V(1U) 34658b4e6b3cSArjun Vynipadath 34668b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_EOC_S 29 34678b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_EOC_M 0x1 34688b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_EOC_V(x) ((x) << FW_HMA_CMD_EOC_S) 34698b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_EOC_G(x) (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M) 34708b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_EOC_F FW_HMA_CMD_EOC_V(1U) 34718b4e6b3cSArjun Vynipadath 34728b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_PCIE_PARAMS_S 0 34738b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_PCIE_PARAMS_M 0x7ffffff 34748b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_PCIE_PARAMS_V(x) ((x) << FW_HMA_CMD_PCIE_PARAMS_S) 34758b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_PCIE_PARAMS_G(x) \ 34768b4e6b3cSArjun Vynipadath (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M) 34778b4e6b3cSArjun Vynipadath 34788b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_NADDR_S 12 34798b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_NADDR_M 0x3f 34808b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_NADDR_V(x) ((x) << FW_HMA_CMD_NADDR_S) 34818b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_NADDR_G(x) \ 34828b4e6b3cSArjun Vynipadath (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M) 34838b4e6b3cSArjun Vynipadath 34848b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SIZE_S 0 34858b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SIZE_M 0xfff 34868b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SIZE_V(x) ((x) << FW_HMA_CMD_SIZE_S) 34878b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_SIZE_G(x) \ 34888b4e6b3cSArjun Vynipadath (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M) 34898b4e6b3cSArjun Vynipadath 34908b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_ADDR_SIZE_S 11 34918b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_ADDR_SIZE_M 0x1fffff 34928b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_ADDR_SIZE_V(x) ((x) << FW_HMA_CMD_ADDR_SIZE_S) 34938b4e6b3cSArjun Vynipadath #define FW_HMA_CMD_ADDR_SIZE_G(x) \ 34948b4e6b3cSArjun Vynipadath (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M) 34958b4e6b3cSArjun Vynipadath 3496d86cc04eSRahul Lakkireddy enum pcie_fw_eval { 3497d86cc04eSRahul Lakkireddy PCIE_FW_EVAL_CRASH = 0, 3498d86cc04eSRahul Lakkireddy }; 3499d86cc04eSRahul Lakkireddy 3500b2e1a3f0SHariprasad Shenai #define PCIE_FW_ERR_S 31 3501b2e1a3f0SHariprasad Shenai #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S) 3502b2e1a3f0SHariprasad Shenai #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U) 3503b2e1a3f0SHariprasad Shenai 3504b2e1a3f0SHariprasad Shenai #define PCIE_FW_INIT_S 30 3505b2e1a3f0SHariprasad Shenai #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S) 3506b2e1a3f0SHariprasad Shenai #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U) 3507b2e1a3f0SHariprasad Shenai 3508b2e1a3f0SHariprasad Shenai #define PCIE_FW_HALT_S 29 3509b2e1a3f0SHariprasad Shenai #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S) 3510b2e1a3f0SHariprasad Shenai #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U) 3511b2e1a3f0SHariprasad Shenai 3512b2e1a3f0SHariprasad Shenai #define PCIE_FW_EVAL_S 24 3513b2e1a3f0SHariprasad Shenai #define PCIE_FW_EVAL_M 0x7 3514b2e1a3f0SHariprasad Shenai #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M) 3515b2e1a3f0SHariprasad Shenai 3516b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_VLD_S 15 3517b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S) 3518b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U) 3519b2e1a3f0SHariprasad Shenai 3520b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_S 12 3521b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_M 0x7 3522b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S) 3523b2e1a3f0SHariprasad Shenai #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M) 352452367a76SVipul Pandya 3525f7917c00SJeff Kirsher struct fw_hdr { 3526f7917c00SJeff Kirsher u8 ver; 352716e47624SHariprasad Shenai u8 chip; /* terminator chip type */ 3528f7917c00SJeff Kirsher __be16 len512; /* bin length in units of 512-bytes */ 3529f7917c00SJeff Kirsher __be32 fw_ver; /* firmware version */ 3530f7917c00SJeff Kirsher __be32 tp_microcode_ver; 3531f7917c00SJeff Kirsher u8 intfver_nic; 3532f7917c00SJeff Kirsher u8 intfver_vnic; 3533f7917c00SJeff Kirsher u8 intfver_ofld; 3534f7917c00SJeff Kirsher u8 intfver_ri; 3535f7917c00SJeff Kirsher u8 intfver_iscsipdu; 3536f7917c00SJeff Kirsher u8 intfver_iscsi; 3537b407a4a9SVipul Pandya u8 intfver_fcoepdu; 3538f7917c00SJeff Kirsher u8 intfver_fcoe; 3539b407a4a9SVipul Pandya __u32 reserved2; 354026f7cbc0SVipul Pandya __u32 reserved3; 354126f7cbc0SVipul Pandya __u32 reserved4; 354226f7cbc0SVipul Pandya __be32 flags; 354326f7cbc0SVipul Pandya __be32 reserved6[23]; 3544f7917c00SJeff Kirsher }; 3545f7917c00SJeff Kirsher 354616e47624SHariprasad Shenai enum fw_hdr_chip { 354716e47624SHariprasad Shenai FW_HDR_CHIP_T4, 35483ccc6cf7SHariprasad Shenai FW_HDR_CHIP_T5, 35493ccc6cf7SHariprasad Shenai FW_HDR_CHIP_T6 355016e47624SHariprasad Shenai }; 355116e47624SHariprasad Shenai 3552b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MAJOR_S 24 3553b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MAJOR_M 0xff 3554ba3f8cd5SHariprasad Shenai #define FW_HDR_FW_VER_MAJOR_V(x) \ 3555ba3f8cd5SHariprasad Shenai ((x) << FW_HDR_FW_VER_MAJOR_S) 3556b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MAJOR_G(x) \ 3557b2e1a3f0SHariprasad Shenai (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M) 3558b2e1a3f0SHariprasad Shenai 3559b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MINOR_S 16 3560b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MINOR_M 0xff 3561ba3f8cd5SHariprasad Shenai #define FW_HDR_FW_VER_MINOR_V(x) \ 3562ba3f8cd5SHariprasad Shenai ((x) << FW_HDR_FW_VER_MINOR_S) 3563b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MINOR_G(x) \ 3564b2e1a3f0SHariprasad Shenai (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M) 3565b2e1a3f0SHariprasad Shenai 3566b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MICRO_S 8 3567b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MICRO_M 0xff 3568ba3f8cd5SHariprasad Shenai #define FW_HDR_FW_VER_MICRO_V(x) \ 3569ba3f8cd5SHariprasad Shenai ((x) << FW_HDR_FW_VER_MICRO_S) 3570b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_MICRO_G(x) \ 3571b2e1a3f0SHariprasad Shenai (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M) 3572b2e1a3f0SHariprasad Shenai 3573b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_BUILD_S 0 3574b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_BUILD_M 0xff 3575ba3f8cd5SHariprasad Shenai #define FW_HDR_FW_VER_BUILD_V(x) \ 3576ba3f8cd5SHariprasad Shenai ((x) << FW_HDR_FW_VER_BUILD_S) 3577b2e1a3f0SHariprasad Shenai #define FW_HDR_FW_VER_BUILD_G(x) \ 3578b2e1a3f0SHariprasad Shenai (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M) 35793069ee9bSVipul Pandya 3580b407a4a9SVipul Pandya enum fw_hdr_intfver { 3581b407a4a9SVipul Pandya FW_HDR_INTFVER_NIC = 0x00, 3582b407a4a9SVipul Pandya FW_HDR_INTFVER_VNIC = 0x00, 3583b407a4a9SVipul Pandya FW_HDR_INTFVER_OFLD = 0x00, 3584b407a4a9SVipul Pandya FW_HDR_INTFVER_RI = 0x00, 3585b407a4a9SVipul Pandya FW_HDR_INTFVER_ISCSIPDU = 0x00, 3586b407a4a9SVipul Pandya FW_HDR_INTFVER_ISCSI = 0x00, 3587b407a4a9SVipul Pandya FW_HDR_INTFVER_FCOEPDU = 0x00, 3588b407a4a9SVipul Pandya FW_HDR_INTFVER_FCOE = 0x00, 3589b407a4a9SVipul Pandya }; 3590b407a4a9SVipul Pandya 359126f7cbc0SVipul Pandya enum fw_hdr_flags { 359226f7cbc0SVipul Pandya FW_HDR_FLAGS_RESET_HALT = 0x00000001, 359326f7cbc0SVipul Pandya }; 359426f7cbc0SVipul Pandya 359549aa284fSHariprasad Shenai /* length of the formatting string */ 359649aa284fSHariprasad Shenai #define FW_DEVLOG_FMT_LEN 192 359749aa284fSHariprasad Shenai 359849aa284fSHariprasad Shenai /* maximum number of the formatting string parameters */ 359949aa284fSHariprasad Shenai #define FW_DEVLOG_FMT_PARAMS_NUM 8 360049aa284fSHariprasad Shenai 360149aa284fSHariprasad Shenai /* priority levels */ 360249aa284fSHariprasad Shenai enum fw_devlog_level { 360349aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_EMERG = 0x0, 360449aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_CRIT = 0x1, 360549aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_ERR = 0x2, 360649aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_NOTICE = 0x3, 360749aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_INFO = 0x4, 360849aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_DEBUG = 0x5, 360949aa284fSHariprasad Shenai FW_DEVLOG_LEVEL_MAX = 0x5, 361049aa284fSHariprasad Shenai }; 361149aa284fSHariprasad Shenai 361249aa284fSHariprasad Shenai /* facilities that may send a log message */ 361349aa284fSHariprasad Shenai enum fw_devlog_facility { 361449aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_CORE = 0x00, 361549aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_CF = 0x01, 361649aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_SCHED = 0x02, 361749aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_TIMER = 0x04, 361849aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_RES = 0x06, 361949aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_HW = 0x08, 362049aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_FLR = 0x10, 362149aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_DMAQ = 0x12, 362249aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_PHY = 0x14, 362349aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_MAC = 0x16, 362449aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_PORT = 0x18, 362549aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_VI = 0x1A, 362649aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_FILTER = 0x1C, 362749aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_ACL = 0x1E, 362849aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_TM = 0x20, 362949aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_QFC = 0x22, 363049aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_DCB = 0x24, 363149aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_ETH = 0x26, 363249aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_OFLD = 0x28, 363349aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_RI = 0x2A, 363449aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_ISCSI = 0x2C, 363549aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_FCOE = 0x2E, 363649aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_FOISCSI = 0x30, 363749aa284fSHariprasad Shenai FW_DEVLOG_FACILITY_FOFCOE = 0x32, 36387ef65a42SHariprasad Shenai FW_DEVLOG_FACILITY_CHNET = 0x34, 36397ef65a42SHariprasad Shenai FW_DEVLOG_FACILITY_MAX = 0x34, 364049aa284fSHariprasad Shenai }; 364149aa284fSHariprasad Shenai 364249aa284fSHariprasad Shenai /* log message format */ 364349aa284fSHariprasad Shenai struct fw_devlog_e { 364449aa284fSHariprasad Shenai __be64 timestamp; 364549aa284fSHariprasad Shenai __be32 seqno; 364649aa284fSHariprasad Shenai __be16 reserved1; 364749aa284fSHariprasad Shenai __u8 level; 364849aa284fSHariprasad Shenai __u8 facility; 364949aa284fSHariprasad Shenai __u8 fmt[FW_DEVLOG_FMT_LEN]; 365049aa284fSHariprasad Shenai __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 365149aa284fSHariprasad Shenai __be32 reserved3[4]; 365249aa284fSHariprasad Shenai }; 365349aa284fSHariprasad Shenai 365449aa284fSHariprasad Shenai struct fw_devlog_cmd { 365549aa284fSHariprasad Shenai __be32 op_to_write; 365649aa284fSHariprasad Shenai __be32 retval_len16; 365749aa284fSHariprasad Shenai __u8 level; 365849aa284fSHariprasad Shenai __u8 r2[7]; 365949aa284fSHariprasad Shenai __be32 memtype_devlog_memaddr16_devlog; 366049aa284fSHariprasad Shenai __be32 memsize_devlog; 366149aa284fSHariprasad Shenai __be32 r3[2]; 366249aa284fSHariprasad Shenai }; 366349aa284fSHariprasad Shenai 366449aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28 366549aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf 366649aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \ 366749aa284fSHariprasad Shenai (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \ 366849aa284fSHariprasad Shenai FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M) 366949aa284fSHariprasad Shenai 367049aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0 367149aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff 367249aa284fSHariprasad Shenai #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \ 367349aa284fSHariprasad Shenai (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \ 367449aa284fSHariprasad Shenai FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M) 367549aa284fSHariprasad Shenai 36767ef65a42SHariprasad Shenai /* P C I E F W P F 7 R E G I S T E R */ 36777ef65a42SHariprasad Shenai 36787ef65a42SHariprasad Shenai /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to 36797ef65a42SHariprasad Shenai * access the "devlog" which needing to contact firmware. The encoding is 36807ef65a42SHariprasad Shenai * mostly the same as that returned by the DEVLOG command except for the size 36817ef65a42SHariprasad Shenai * which is encoded as the number of entries in multiples-1 of 128 here rather 36827ef65a42SHariprasad Shenai * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 36837ef65a42SHariprasad Shenai * and 15 means 2048. This of course in turn constrains the allowed values 36847ef65a42SHariprasad Shenai * for the devlog size ... 36857ef65a42SHariprasad Shenai */ 36867ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG 7 36877ef65a42SHariprasad Shenai 36887ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28 36897ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf 36907ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \ 36917ef65a42SHariprasad Shenai ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S) 36927ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \ 36937ef65a42SHariprasad Shenai (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \ 36947ef65a42SHariprasad Shenai PCIE_FW_PF_DEVLOG_NENTRIES128_M) 36957ef65a42SHariprasad Shenai 36967ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_ADDR16_S 4 36977ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_ADDR16_M 0xffffff 36987ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_ADDR16_V(x) ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S) 36997ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \ 37007ef65a42SHariprasad Shenai (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M) 37017ef65a42SHariprasad Shenai 37027ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_MEMTYPE_S 0 37037ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_MEMTYPE_M 0xf 37047ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x) ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S) 37057ef65a42SHariprasad Shenai #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \ 37067ef65a42SHariprasad Shenai (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M) 37077ef65a42SHariprasad Shenai 3708d6657781SHariprasad Shenai #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr)) 3709d6657781SHariprasad Shenai 3710d6657781SHariprasad Shenai struct fw_crypto_lookaside_wr { 3711d6657781SHariprasad Shenai __be32 op_to_cctx_size; 3712d6657781SHariprasad Shenai __be32 len16_pkd; 3713d6657781SHariprasad Shenai __be32 session_id; 3714d6657781SHariprasad Shenai __be32 rx_chid_to_rx_q_id; 3715d6657781SHariprasad Shenai __be32 key_addr; 3716d6657781SHariprasad Shenai __be32 pld_size_hash_size; 3717d6657781SHariprasad Shenai __be64 cookie; 3718d6657781SHariprasad Shenai }; 3719d6657781SHariprasad Shenai 3720d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24 3721d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff 3722d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \ 3723d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) 3724d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \ 3725d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \ 3726d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_OPCODE_M) 3727d6657781SHariprasad Shenai 3728d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23 3729d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1 3730d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \ 3731d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S) 3732d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \ 3733d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \ 3734d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_COMPL_M) 3735d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U) 3736d6657781SHariprasad Shenai 3737d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15 3738d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff 3739d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \ 3740d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) 3741d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \ 3742d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \ 3743d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M) 3744d6657781SHariprasad Shenai 3745d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5 3746d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3 3747d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \ 3748d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) 3749d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \ 3750d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \ 3751d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M) 3752d6657781SHariprasad Shenai 3753d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0 3754d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f 3755d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \ 3756d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) 3757d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \ 3758d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \ 3759d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M) 3760d6657781SHariprasad Shenai 3761d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0 3762d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff 3763d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \ 3764d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S) 3765d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \ 3766d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \ 3767d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_LEN16_M) 3768d6657781SHariprasad Shenai 3769d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29 3770d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3 3771d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \ 3772d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) 3773d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \ 3774d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \ 3775d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M) 3776d6657781SHariprasad Shenai 3777d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LCB_S 27 3778d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LCB_M 0x3 3779d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \ 3780d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S) 3781d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \ 3782d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M) 3783d6657781SHariprasad Shenai 3784d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25 3785d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3 3786d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \ 3787d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S) 3788d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \ 3789d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \ 3790d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_PHASH_M) 3791d6657781SHariprasad Shenai 3792d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IV_S 23 3793d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IV_M 0x3 3794d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \ 3795d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S) 3796d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \ 3797d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M) 3798d6657781SHariprasad Shenai 37998a13449fSHarsh Jain #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S 15 38008a13449fSHarsh Jain #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M 0xff 38018a13449fSHarsh Jain #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \ 38028a13449fSHarsh Jain ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) 38038a13449fSHarsh Jain #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \ 38048a13449fSHarsh Jain (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \ 38058a13449fSHarsh Jain FW_CRYPTO_LOOKASIDE_WR_FQIDX_M) 38068a13449fSHarsh Jain 3807d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10 3808d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3 3809d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \ 3810d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) 3811d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \ 3812d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \ 3813d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_TX_CH_M) 3814d6657781SHariprasad Shenai 3815d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0 3816d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff 3817d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \ 3818d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) 3819d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \ 3820d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \ 3821d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M) 3822d6657781SHariprasad Shenai 3823d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24 3824d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff 3825d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \ 3826d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) 3827d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \ 3828d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \ 3829d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M) 3830d6657781SHariprasad Shenai 3831d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17 3832d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f 3833d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \ 3834d6657781SHariprasad Shenai ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) 3835d6657781SHariprasad Shenai #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \ 3836d6657781SHariprasad Shenai (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \ 3837d6657781SHariprasad Shenai FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M) 3838d6657781SHariprasad Shenai 3839f7917c00SJeff Kirsher #endif /* _T4FW_INTERFACE_H_ */ 3840