1 // SPDX-License-Identifier: GPL-2.0-only 2 /**************************************************************************** 3 * Driver for Solarflare network controllers and boards 4 * Copyright 2018 Solarflare Communications Inc. 5 * Copyright 2019-2022 Xilinx Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published 9 * by the Free Software Foundation, incorporated herein by reference. 10 */ 11 12 #include "ef100_nic.h" 13 #include "efx_common.h" 14 #include "efx_channels.h" 15 #include "io.h" 16 #include "selftest.h" 17 #include "ef100_regs.h" 18 #include "mcdi.h" 19 #include "mcdi_pcol.h" 20 #include "mcdi_port_common.h" 21 #include "mcdi_functions.h" 22 #include "mcdi_filters.h" 23 #include "ef100_rx.h" 24 #include "ef100_tx.h" 25 #include "ef100_sriov.h" 26 #include "ef100_netdev.h" 27 #include "tc.h" 28 #include "mae.h" 29 #include "rx_common.h" 30 31 #define EF100_MAX_VIS 4096 32 #define EF100_NUM_MCDI_BUFFERS 1 33 #define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX) 34 35 #define EF100_RESET_PORT ((ETH_RESET_MAC | ETH_RESET_PHY) << ETH_RESET_SHARED_SHIFT) 36 37 /* MCDI 38 */ 39 static u8 *ef100_mcdi_buf(struct efx_nic *efx, u8 bufid, dma_addr_t *dma_addr) 40 { 41 struct ef100_nic_data *nic_data = efx->nic_data; 42 43 if (dma_addr) 44 *dma_addr = nic_data->mcdi_buf.dma_addr + 45 bufid * ALIGN(MCDI_BUF_LEN, 256); 46 return nic_data->mcdi_buf.addr + bufid * ALIGN(MCDI_BUF_LEN, 256); 47 } 48 49 static int ef100_get_warm_boot_count(struct efx_nic *efx) 50 { 51 efx_dword_t reg; 52 53 efx_readd(efx, ®, efx_reg(efx, ER_GZ_MC_SFT_STATUS)); 54 55 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) == 0xffffffff) { 56 netif_err(efx, hw, efx->net_dev, "Hardware unavailable\n"); 57 efx->state = STATE_DISABLED; 58 return -ENETDOWN; 59 } else { 60 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 61 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 62 } 63 } 64 65 static void ef100_mcdi_request(struct efx_nic *efx, 66 const efx_dword_t *hdr, size_t hdr_len, 67 const efx_dword_t *sdu, size_t sdu_len) 68 { 69 dma_addr_t dma_addr; 70 u8 *pdu = ef100_mcdi_buf(efx, 0, &dma_addr); 71 72 memcpy(pdu, hdr, hdr_len); 73 memcpy(pdu + hdr_len, sdu, sdu_len); 74 wmb(); 75 76 /* The hardware provides 'low' and 'high' (doorbell) registers 77 * for passing the 64-bit address of an MCDI request to 78 * firmware. However the dwords are swapped by firmware. The 79 * least significant bits of the doorbell are then 0 for all 80 * MCDI requests due to alignment. 81 */ 82 _efx_writed(efx, cpu_to_le32((u64)dma_addr >> 32), efx_reg(efx, ER_GZ_MC_DB_LWRD)); 83 _efx_writed(efx, cpu_to_le32((u32)dma_addr), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 84 } 85 86 static bool ef100_mcdi_poll_response(struct efx_nic *efx) 87 { 88 const efx_dword_t hdr = 89 *(const efx_dword_t *)(ef100_mcdi_buf(efx, 0, NULL)); 90 91 rmb(); 92 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 93 } 94 95 static void ef100_mcdi_read_response(struct efx_nic *efx, 96 efx_dword_t *outbuf, size_t offset, 97 size_t outlen) 98 { 99 const u8 *pdu = ef100_mcdi_buf(efx, 0, NULL); 100 101 memcpy(outbuf, pdu + offset, outlen); 102 } 103 104 static int ef100_mcdi_poll_reboot(struct efx_nic *efx) 105 { 106 struct ef100_nic_data *nic_data = efx->nic_data; 107 int rc; 108 109 rc = ef100_get_warm_boot_count(efx); 110 if (rc < 0) { 111 /* The firmware is presumably in the process of 112 * rebooting. However, we are supposed to report each 113 * reboot just once, so we must only do that once we 114 * can read and store the updated warm boot count. 115 */ 116 return 0; 117 } 118 119 if (rc == nic_data->warm_boot_count) 120 return 0; 121 122 nic_data->warm_boot_count = rc; 123 124 return -EIO; 125 } 126 127 static void ef100_mcdi_reboot_detected(struct efx_nic *efx) 128 { 129 } 130 131 /* MCDI calls 132 */ 133 int ef100_get_mac_address(struct efx_nic *efx, u8 *mac_address, 134 int client_handle, bool empty_ok) 135 { 136 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1)); 137 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN); 138 size_t outlen; 139 int rc; 140 141 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 142 MCDI_SET_DWORD(inbuf, GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE, 143 client_handle); 144 145 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLIENT_MAC_ADDRESSES, inbuf, 146 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen); 147 if (rc) 148 return rc; 149 150 if (outlen >= MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(1)) { 151 ether_addr_copy(mac_address, 152 MCDI_PTR(outbuf, GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS)); 153 } else if (empty_ok) { 154 pci_warn(efx->pci_dev, 155 "No MAC address provisioned for client ID %#x.\n", 156 client_handle); 157 eth_zero_addr(mac_address); 158 } else { 159 return -ENOENT; 160 } 161 return 0; 162 } 163 164 int efx_ef100_init_datapath_caps(struct efx_nic *efx) 165 { 166 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_V7_OUT_LEN); 167 struct ef100_nic_data *nic_data = efx->nic_data; 168 u8 vi_window_mode; 169 size_t outlen; 170 int rc; 171 172 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 173 174 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 175 outbuf, sizeof(outbuf), &outlen); 176 if (rc) 177 return rc; 178 if (outlen < MC_CMD_GET_CAPABILITIES_V4_OUT_LEN) { 179 netif_err(efx, drv, efx->net_dev, 180 "unable to read datapath firmware capabilities\n"); 181 return -EIO; 182 } 183 184 nic_data->datapath_caps = MCDI_DWORD(outbuf, 185 GET_CAPABILITIES_OUT_FLAGS1); 186 nic_data->datapath_caps2 = MCDI_DWORD(outbuf, 187 GET_CAPABILITIES_V2_OUT_FLAGS2); 188 if (outlen < MC_CMD_GET_CAPABILITIES_V7_OUT_LEN) 189 nic_data->datapath_caps3 = 0; 190 else 191 nic_data->datapath_caps3 = MCDI_DWORD(outbuf, 192 GET_CAPABILITIES_V7_OUT_FLAGS3); 193 194 vi_window_mode = MCDI_BYTE(outbuf, 195 GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE); 196 rc = efx_mcdi_window_mode_to_stride(efx, vi_window_mode); 197 if (rc) 198 return rc; 199 200 if (efx_ef100_has_cap(nic_data->datapath_caps2, TX_TSO_V3)) { 201 struct net_device *net_dev = efx->net_dev; 202 netdev_features_t tso = NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_GSO_PARTIAL | 203 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM | 204 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM; 205 206 net_dev->features |= tso; 207 net_dev->hw_features |= tso; 208 net_dev->hw_enc_features |= tso; 209 /* EF100 HW can only offload outer checksums if they are UDP, 210 * so for GRE_CSUM we have to use GSO_PARTIAL. 211 */ 212 net_dev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; 213 } 214 efx->num_mac_stats = MCDI_WORD(outbuf, 215 GET_CAPABILITIES_V4_OUT_MAC_STATS_NUM_STATS); 216 netif_dbg(efx, probe, efx->net_dev, 217 "firmware reports num_mac_stats = %u\n", 218 efx->num_mac_stats); 219 return 0; 220 } 221 222 /* Event handling 223 */ 224 static int ef100_ev_probe(struct efx_channel *channel) 225 { 226 /* Allocate an extra descriptor for the QMDA status completion entry */ 227 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 228 (channel->eventq_mask + 2) * 229 sizeof(efx_qword_t), 230 GFP_KERNEL); 231 } 232 233 static int ef100_ev_init(struct efx_channel *channel) 234 { 235 struct ef100_nic_data *nic_data = channel->efx->nic_data; 236 237 /* initial phase is 0 */ 238 clear_bit(channel->channel, nic_data->evq_phases); 239 240 return efx_mcdi_ev_init(channel, false, false); 241 } 242 243 static void ef100_ev_read_ack(struct efx_channel *channel) 244 { 245 efx_dword_t evq_prime; 246 247 EFX_POPULATE_DWORD_2(evq_prime, 248 ERF_GZ_EVQ_ID, channel->channel, 249 ERF_GZ_IDX, channel->eventq_read_ptr & 250 channel->eventq_mask); 251 252 efx_writed(channel->efx, &evq_prime, 253 efx_reg(channel->efx, ER_GZ_EVQ_INT_PRIME)); 254 } 255 256 static int ef100_ev_process(struct efx_channel *channel, int quota) 257 { 258 struct efx_nic *efx = channel->efx; 259 struct ef100_nic_data *nic_data; 260 bool evq_phase, old_evq_phase; 261 unsigned int read_ptr; 262 efx_qword_t *p_event; 263 int spent = 0; 264 bool ev_phase; 265 int ev_type; 266 267 if (unlikely(!channel->enabled)) 268 return 0; 269 270 nic_data = efx->nic_data; 271 evq_phase = test_bit(channel->channel, nic_data->evq_phases); 272 old_evq_phase = evq_phase; 273 read_ptr = channel->eventq_read_ptr; 274 BUILD_BUG_ON(ESF_GZ_EV_RXPKTS_PHASE_LBN != ESF_GZ_EV_TXCMPL_PHASE_LBN); 275 276 while (spent < quota) { 277 p_event = efx_event(channel, read_ptr); 278 279 ev_phase = !!EFX_QWORD_FIELD(*p_event, ESF_GZ_EV_RXPKTS_PHASE); 280 if (ev_phase != evq_phase) 281 break; 282 283 netif_vdbg(efx, drv, efx->net_dev, 284 "processing event on %d " EFX_QWORD_FMT "\n", 285 channel->channel, EFX_QWORD_VAL(*p_event)); 286 287 ev_type = EFX_QWORD_FIELD(*p_event, ESF_GZ_E_TYPE); 288 289 switch (ev_type) { 290 case ESE_GZ_EF100_EV_RX_PKTS: 291 efx_ef100_ev_rx(channel, p_event); 292 ++spent; 293 break; 294 case ESE_GZ_EF100_EV_MCDI: 295 efx_mcdi_process_event(channel, p_event); 296 break; 297 case ESE_GZ_EF100_EV_TX_COMPLETION: 298 ef100_ev_tx(channel, p_event); 299 break; 300 case ESE_GZ_EF100_EV_DRIVER: 301 netif_info(efx, drv, efx->net_dev, 302 "Driver initiated event " EFX_QWORD_FMT "\n", 303 EFX_QWORD_VAL(*p_event)); 304 break; 305 default: 306 netif_info(efx, drv, efx->net_dev, 307 "Unhandled event " EFX_QWORD_FMT "\n", 308 EFX_QWORD_VAL(*p_event)); 309 } 310 311 ++read_ptr; 312 if ((read_ptr & channel->eventq_mask) == 0) 313 evq_phase = !evq_phase; 314 } 315 316 channel->eventq_read_ptr = read_ptr; 317 if (evq_phase != old_evq_phase) 318 change_bit(channel->channel, nic_data->evq_phases); 319 320 return spent; 321 } 322 323 static irqreturn_t ef100_msi_interrupt(int irq, void *dev_id) 324 { 325 struct efx_msi_context *context = dev_id; 326 struct efx_nic *efx = context->efx; 327 328 netif_vdbg(efx, intr, efx->net_dev, 329 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 330 331 if (likely(READ_ONCE(efx->irq_soft_enabled))) { 332 /* Note test interrupts */ 333 if (context->index == efx->irq_level) 334 efx->last_irq_cpu = raw_smp_processor_id(); 335 336 /* Schedule processing of the channel */ 337 efx_schedule_channel_irq(efx->channel[context->index]); 338 } 339 340 return IRQ_HANDLED; 341 } 342 343 int ef100_phy_probe(struct efx_nic *efx) 344 { 345 struct efx_mcdi_phy_data *phy_data; 346 int rc; 347 348 /* Probe for the PHY */ 349 efx->phy_data = kzalloc(sizeof(struct efx_mcdi_phy_data), GFP_KERNEL); 350 if (!efx->phy_data) 351 return -ENOMEM; 352 353 rc = efx_mcdi_get_phy_cfg(efx, efx->phy_data); 354 if (rc) 355 return rc; 356 357 /* Populate driver and ethtool settings */ 358 phy_data = efx->phy_data; 359 mcdi_to_ethtool_linkset(phy_data->media, phy_data->supported_cap, 360 efx->link_advertising); 361 efx->fec_config = mcdi_fec_caps_to_ethtool(phy_data->supported_cap, 362 false); 363 364 /* Default to Autonegotiated flow control if the PHY supports it */ 365 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; 366 if (phy_data->supported_cap & (1 << MC_CMD_PHY_CAP_AN_LBN)) 367 efx->wanted_fc |= EFX_FC_AUTO; 368 efx_link_set_wanted_fc(efx, efx->wanted_fc); 369 370 /* Push settings to the PHY. Failure is not fatal, the user can try to 371 * fix it using ethtool. 372 */ 373 rc = efx_mcdi_port_reconfigure(efx); 374 if (rc && rc != -EPERM) 375 netif_warn(efx, drv, efx->net_dev, 376 "could not initialise PHY settings\n"); 377 378 return 0; 379 } 380 381 int ef100_filter_table_probe(struct efx_nic *efx) 382 { 383 return efx_mcdi_filter_table_probe(efx, true); 384 } 385 386 static int ef100_filter_table_up(struct efx_nic *efx) 387 { 388 int rc; 389 390 down_write(&efx->filter_sem); 391 rc = efx_mcdi_filter_add_vlan(efx, EFX_FILTER_VID_UNSPEC); 392 if (rc) 393 goto fail_unspec; 394 395 rc = efx_mcdi_filter_add_vlan(efx, 0); 396 if (rc) 397 goto fail_vlan0; 398 /* Drop the lock: we've finished altering table existence, and 399 * filter insertion will need to take the lock for read. 400 */ 401 up_write(&efx->filter_sem); 402 #ifdef CONFIG_SFC_SRIOV 403 rc = efx_tc_insert_rep_filters(efx); 404 /* Rep filter failure is nonfatal */ 405 if (rc) 406 netif_warn(efx, drv, efx->net_dev, 407 "Failed to insert representor filters, rc %d\n", 408 rc); 409 #endif 410 return 0; 411 412 fail_vlan0: 413 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 414 fail_unspec: 415 efx_mcdi_filter_table_down(efx); 416 up_write(&efx->filter_sem); 417 return rc; 418 } 419 420 static void ef100_filter_table_down(struct efx_nic *efx) 421 { 422 #ifdef CONFIG_SFC_SRIOV 423 efx_tc_remove_rep_filters(efx); 424 #endif 425 down_write(&efx->filter_sem); 426 efx_mcdi_filter_del_vlan(efx, 0); 427 efx_mcdi_filter_del_vlan(efx, EFX_FILTER_VID_UNSPEC); 428 efx_mcdi_filter_table_down(efx); 429 up_write(&efx->filter_sem); 430 } 431 432 /* Other 433 */ 434 static int ef100_reconfigure_mac(struct efx_nic *efx, bool mtu_only) 435 { 436 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 437 438 efx_mcdi_filter_sync_rx_mode(efx); 439 440 if (mtu_only && efx_has_cap(efx, SET_MAC_ENHANCED)) 441 return efx_mcdi_set_mtu(efx); 442 return efx_mcdi_set_mac(efx); 443 } 444 445 static enum reset_type ef100_map_reset_reason(enum reset_type reason) 446 { 447 if (reason == RESET_TYPE_TX_WATCHDOG) 448 return reason; 449 return RESET_TYPE_DISABLE; 450 } 451 452 static int ef100_map_reset_flags(u32 *flags) 453 { 454 /* Only perform a RESET_TYPE_ALL because we don't support MC_REBOOTs */ 455 if ((*flags & EF100_RESET_PORT)) { 456 *flags &= ~EF100_RESET_PORT; 457 return RESET_TYPE_ALL; 458 } 459 if (*flags & ETH_RESET_MGMT) { 460 *flags &= ~ETH_RESET_MGMT; 461 return RESET_TYPE_DISABLE; 462 } 463 464 return -EINVAL; 465 } 466 467 static int ef100_reset(struct efx_nic *efx, enum reset_type reset_type) 468 { 469 int rc; 470 471 dev_close(efx->net_dev); 472 473 if (reset_type == RESET_TYPE_TX_WATCHDOG) { 474 netif_device_attach(efx->net_dev); 475 __clear_bit(reset_type, &efx->reset_pending); 476 rc = dev_open(efx->net_dev, NULL); 477 } else if (reset_type == RESET_TYPE_ALL) { 478 rc = efx_mcdi_reset(efx, reset_type); 479 if (rc) 480 return rc; 481 482 netif_device_attach(efx->net_dev); 483 484 rc = dev_open(efx->net_dev, NULL); 485 } else { 486 rc = 1; /* Leave the device closed */ 487 } 488 return rc; 489 } 490 491 static void ef100_common_stat_mask(unsigned long *mask) 492 { 493 __set_bit(EF100_STAT_port_rx_packets, mask); 494 __set_bit(EF100_STAT_port_tx_packets, mask); 495 __set_bit(EF100_STAT_port_rx_bytes, mask); 496 __set_bit(EF100_STAT_port_tx_bytes, mask); 497 __set_bit(EF100_STAT_port_rx_multicast, mask); 498 __set_bit(EF100_STAT_port_rx_bad, mask); 499 __set_bit(EF100_STAT_port_rx_align_error, mask); 500 __set_bit(EF100_STAT_port_rx_overflow, mask); 501 } 502 503 static void ef100_ethtool_stat_mask(unsigned long *mask) 504 { 505 __set_bit(EF100_STAT_port_tx_pause, mask); 506 __set_bit(EF100_STAT_port_tx_unicast, mask); 507 __set_bit(EF100_STAT_port_tx_multicast, mask); 508 __set_bit(EF100_STAT_port_tx_broadcast, mask); 509 __set_bit(EF100_STAT_port_tx_lt64, mask); 510 __set_bit(EF100_STAT_port_tx_64, mask); 511 __set_bit(EF100_STAT_port_tx_65_to_127, mask); 512 __set_bit(EF100_STAT_port_tx_128_to_255, mask); 513 __set_bit(EF100_STAT_port_tx_256_to_511, mask); 514 __set_bit(EF100_STAT_port_tx_512_to_1023, mask); 515 __set_bit(EF100_STAT_port_tx_1024_to_15xx, mask); 516 __set_bit(EF100_STAT_port_tx_15xx_to_jumbo, mask); 517 __set_bit(EF100_STAT_port_rx_good, mask); 518 __set_bit(EF100_STAT_port_rx_pause, mask); 519 __set_bit(EF100_STAT_port_rx_unicast, mask); 520 __set_bit(EF100_STAT_port_rx_broadcast, mask); 521 __set_bit(EF100_STAT_port_rx_lt64, mask); 522 __set_bit(EF100_STAT_port_rx_64, mask); 523 __set_bit(EF100_STAT_port_rx_65_to_127, mask); 524 __set_bit(EF100_STAT_port_rx_128_to_255, mask); 525 __set_bit(EF100_STAT_port_rx_256_to_511, mask); 526 __set_bit(EF100_STAT_port_rx_512_to_1023, mask); 527 __set_bit(EF100_STAT_port_rx_1024_to_15xx, mask); 528 __set_bit(EF100_STAT_port_rx_15xx_to_jumbo, mask); 529 __set_bit(EF100_STAT_port_rx_gtjumbo, mask); 530 __set_bit(EF100_STAT_port_rx_bad_gtjumbo, mask); 531 __set_bit(EF100_STAT_port_rx_length_error, mask); 532 __set_bit(EF100_STAT_port_rx_nodesc_drops, mask); 533 __set_bit(GENERIC_STAT_rx_nodesc_trunc, mask); 534 __set_bit(GENERIC_STAT_rx_noskb_drops, mask); 535 } 536 537 #define EF100_DMA_STAT(ext_name, mcdi_name) \ 538 [EF100_STAT_ ## ext_name] = \ 539 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 540 541 static const struct efx_hw_stat_desc ef100_stat_desc[EF100_STAT_COUNT] = { 542 EF100_DMA_STAT(port_tx_bytes, TX_BYTES), 543 EF100_DMA_STAT(port_tx_packets, TX_PKTS), 544 EF100_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS), 545 EF100_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS), 546 EF100_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS), 547 EF100_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS), 548 EF100_DMA_STAT(port_tx_lt64, TX_LT64_PKTS), 549 EF100_DMA_STAT(port_tx_64, TX_64_PKTS), 550 EF100_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS), 551 EF100_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS), 552 EF100_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS), 553 EF100_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS), 554 EF100_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 555 EF100_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 556 EF100_DMA_STAT(port_rx_bytes, RX_BYTES), 557 EF100_DMA_STAT(port_rx_packets, RX_PKTS), 558 EF100_DMA_STAT(port_rx_good, RX_GOOD_PKTS), 559 EF100_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS), 560 EF100_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS), 561 EF100_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS), 562 EF100_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS), 563 EF100_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS), 564 EF100_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS), 565 EF100_DMA_STAT(port_rx_64, RX_64_PKTS), 566 EF100_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS), 567 EF100_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS), 568 EF100_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS), 569 EF100_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS), 570 EF100_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 571 EF100_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 572 EF100_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS), 573 EF100_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS), 574 EF100_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS), 575 EF100_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS), 576 EF100_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS), 577 EF100_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS), 578 EFX_GENERIC_SW_STAT(rx_nodesc_trunc), 579 EFX_GENERIC_SW_STAT(rx_noskb_drops), 580 }; 581 582 static size_t ef100_describe_stats(struct efx_nic *efx, u8 *names) 583 { 584 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 585 586 ef100_ethtool_stat_mask(mask); 587 return efx_nic_describe_stats(ef100_stat_desc, EF100_STAT_COUNT, 588 mask, names); 589 } 590 591 static size_t ef100_update_stats_common(struct efx_nic *efx, u64 *full_stats, 592 struct rtnl_link_stats64 *core_stats) 593 { 594 struct ef100_nic_data *nic_data = efx->nic_data; 595 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 596 size_t stats_count = 0, index; 597 u64 *stats = nic_data->stats; 598 599 ef100_ethtool_stat_mask(mask); 600 601 if (full_stats) { 602 for_each_set_bit(index, mask, EF100_STAT_COUNT) { 603 if (ef100_stat_desc[index].name) { 604 *full_stats++ = stats[index]; 605 ++stats_count; 606 } 607 } 608 } 609 610 if (!core_stats) 611 return stats_count; 612 613 core_stats->rx_packets = stats[EF100_STAT_port_rx_packets]; 614 core_stats->tx_packets = stats[EF100_STAT_port_tx_packets]; 615 core_stats->rx_bytes = stats[EF100_STAT_port_rx_bytes]; 616 core_stats->tx_bytes = stats[EF100_STAT_port_tx_bytes]; 617 core_stats->rx_dropped = stats[EF100_STAT_port_rx_nodesc_drops] + 618 stats[GENERIC_STAT_rx_nodesc_trunc] + 619 stats[GENERIC_STAT_rx_noskb_drops]; 620 core_stats->multicast = stats[EF100_STAT_port_rx_multicast]; 621 core_stats->rx_length_errors = 622 stats[EF100_STAT_port_rx_gtjumbo] + 623 stats[EF100_STAT_port_rx_length_error]; 624 core_stats->rx_crc_errors = stats[EF100_STAT_port_rx_bad]; 625 core_stats->rx_frame_errors = 626 stats[EF100_STAT_port_rx_align_error]; 627 core_stats->rx_fifo_errors = stats[EF100_STAT_port_rx_overflow]; 628 core_stats->rx_errors = (core_stats->rx_length_errors + 629 core_stats->rx_crc_errors + 630 core_stats->rx_frame_errors); 631 632 return stats_count; 633 } 634 635 static size_t ef100_update_stats(struct efx_nic *efx, 636 u64 *full_stats, 637 struct rtnl_link_stats64 *core_stats) 638 { 639 __le64 *mc_stats = kmalloc(array_size(efx->num_mac_stats, sizeof(__le64)), GFP_ATOMIC); 640 struct ef100_nic_data *nic_data = efx->nic_data; 641 DECLARE_BITMAP(mask, EF100_STAT_COUNT) = {}; 642 u64 *stats = nic_data->stats; 643 644 ef100_common_stat_mask(mask); 645 ef100_ethtool_stat_mask(mask); 646 647 if (!mc_stats) 648 return 0; 649 650 efx_nic_copy_stats(efx, mc_stats); 651 efx_nic_update_stats(ef100_stat_desc, EF100_STAT_COUNT, mask, 652 stats, mc_stats, false); 653 654 kfree(mc_stats); 655 656 return ef100_update_stats_common(efx, full_stats, core_stats); 657 } 658 659 static int efx_ef100_get_phys_port_id(struct efx_nic *efx, 660 struct netdev_phys_item_id *ppid) 661 { 662 struct ef100_nic_data *nic_data = efx->nic_data; 663 664 if (!is_valid_ether_addr(nic_data->port_id)) 665 return -EOPNOTSUPP; 666 667 ppid->id_len = ETH_ALEN; 668 memcpy(ppid->id, nic_data->port_id, ppid->id_len); 669 670 return 0; 671 } 672 673 static int efx_ef100_irq_test_generate(struct efx_nic *efx) 674 { 675 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 676 677 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 678 679 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 680 return efx_mcdi_rpc_quiet(efx, MC_CMD_TRIGGER_INTERRUPT, 681 inbuf, sizeof(inbuf), NULL, 0, NULL); 682 } 683 684 #define EFX_EF100_TEST 1 685 686 static void efx_ef100_ev_test_generate(struct efx_channel *channel) 687 { 688 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 689 struct efx_nic *efx = channel->efx; 690 efx_qword_t event; 691 int rc; 692 693 EFX_POPULATE_QWORD_2(event, 694 ESF_GZ_E_TYPE, ESE_GZ_EF100_EV_DRIVER, 695 ESF_GZ_DRIVER_DATA, EFX_EF100_TEST); 696 697 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 698 699 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 700 * already swapped the data to little-endian order. 701 */ 702 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 703 sizeof(efx_qword_t)); 704 705 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 706 NULL, 0, NULL); 707 if (rc && (rc != -ENETDOWN)) 708 goto fail; 709 710 return; 711 712 fail: 713 WARN_ON(true); 714 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 715 } 716 717 static unsigned int ef100_check_caps(const struct efx_nic *efx, 718 u8 flag, u32 offset) 719 { 720 const struct ef100_nic_data *nic_data = efx->nic_data; 721 722 switch (offset) { 723 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST: 724 return nic_data->datapath_caps & BIT_ULL(flag); 725 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_OFST: 726 return nic_data->datapath_caps2 & BIT_ULL(flag); 727 case MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_OFST: 728 return nic_data->datapath_caps3 & BIT_ULL(flag); 729 default: 730 return 0; 731 } 732 } 733 734 static unsigned int efx_ef100_recycle_ring_size(const struct efx_nic *efx) 735 { 736 /* Maximum link speed for Riverhead is 100G */ 737 return 10 * EFX_RECYCLE_RING_SIZE_10G; 738 } 739 740 #ifdef CONFIG_SFC_SRIOV 741 static int efx_ef100_get_base_mport(struct efx_nic *efx) 742 { 743 struct ef100_nic_data *nic_data = efx->nic_data; 744 u32 selector, id; 745 int rc; 746 747 /* Construct mport selector for "physical network port" */ 748 efx_mae_mport_wire(efx, &selector); 749 /* Look up actual mport ID */ 750 rc = efx_mae_fw_lookup_mport(efx, selector, &id); 751 if (rc) 752 return rc; 753 /* The ID should always fit in 16 bits, because that's how wide the 754 * corresponding fields in the RX prefix & TX override descriptor are 755 */ 756 if (id >> 16) 757 netif_warn(efx, probe, efx->net_dev, "Bad base m-port id %#x\n", 758 id); 759 nic_data->base_mport = id; 760 nic_data->have_mport = true; 761 762 /* Construct mport selector for "calling PF" */ 763 efx_mae_mport_uplink(efx, &selector); 764 /* Look up actual mport ID */ 765 rc = efx_mae_fw_lookup_mport(efx, selector, &id); 766 if (rc) 767 return rc; 768 if (id >> 16) 769 netif_warn(efx, probe, efx->net_dev, "Bad own m-port id %#x\n", 770 id); 771 nic_data->own_mport = id; 772 nic_data->have_own_mport = true; 773 774 return 0; 775 } 776 #endif 777 778 static int compare_versions(const char *a, const char *b) 779 { 780 int a_major, a_minor, a_point, a_patch; 781 int b_major, b_minor, b_point, b_patch; 782 int a_matched, b_matched; 783 784 a_matched = sscanf(a, "%d.%d.%d.%d", &a_major, &a_minor, &a_point, &a_patch); 785 b_matched = sscanf(b, "%d.%d.%d.%d", &b_major, &b_minor, &b_point, &b_patch); 786 787 if (a_matched == 4 && b_matched != 4) 788 return +1; 789 790 if (a_matched != 4 && b_matched == 4) 791 return -1; 792 793 if (a_matched != 4 && b_matched != 4) 794 return 0; 795 796 if (a_major != b_major) 797 return a_major - b_major; 798 799 if (a_minor != b_minor) 800 return a_minor - b_minor; 801 802 if (a_point != b_point) 803 return a_point - b_point; 804 805 return a_patch - b_patch; 806 } 807 808 enum ef100_tlv_state_machine { 809 EF100_TLV_TYPE, 810 EF100_TLV_TYPE_CONT, 811 EF100_TLV_LENGTH, 812 EF100_TLV_VALUE 813 }; 814 815 struct ef100_tlv_state { 816 enum ef100_tlv_state_machine state; 817 u64 value; 818 u32 value_offset; 819 u16 type; 820 u8 len; 821 }; 822 823 static int ef100_tlv_feed(struct ef100_tlv_state *state, u8 byte) 824 { 825 switch (state->state) { 826 case EF100_TLV_TYPE: 827 state->type = byte & 0x7f; 828 state->state = (byte & 0x80) ? EF100_TLV_TYPE_CONT 829 : EF100_TLV_LENGTH; 830 /* Clear ready to read in a new entry */ 831 state->value = 0; 832 state->value_offset = 0; 833 return 0; 834 case EF100_TLV_TYPE_CONT: 835 state->type |= byte << 7; 836 state->state = EF100_TLV_LENGTH; 837 return 0; 838 case EF100_TLV_LENGTH: 839 state->len = byte; 840 /* We only handle TLVs that fit in a u64 */ 841 if (state->len > sizeof(state->value)) 842 return -EOPNOTSUPP; 843 /* len may be zero, implying a value of zero */ 844 state->state = state->len ? EF100_TLV_VALUE : EF100_TLV_TYPE; 845 return 0; 846 case EF100_TLV_VALUE: 847 state->value |= ((u64)byte) << (state->value_offset * 8); 848 state->value_offset++; 849 if (state->value_offset >= state->len) 850 state->state = EF100_TLV_TYPE; 851 return 0; 852 default: /* state machine error, can't happen */ 853 WARN_ON_ONCE(1); 854 return -EIO; 855 } 856 } 857 858 static int ef100_process_design_param(struct efx_nic *efx, 859 const struct ef100_tlv_state *reader) 860 { 861 struct ef100_nic_data *nic_data = efx->nic_data; 862 863 switch (reader->type) { 864 case ESE_EF100_DP_GZ_PAD: /* padding, skip it */ 865 return 0; 866 case ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS: 867 /* Driver doesn't support timestamping yet, so we don't care */ 868 return 0; 869 case ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS: 870 /* Driver doesn't support unsolicited-event credits yet, so 871 * we don't care 872 */ 873 return 0; 874 case ESE_EF100_DP_GZ_NMMU_GROUP_SIZE: 875 /* Driver doesn't manage the NMMU (so we don't care) */ 876 return 0; 877 case ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS: 878 /* Driver uses CHECKSUM_COMPLETE, so we don't care about 879 * protocol checksum validation 880 */ 881 return 0; 882 case ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN: 883 nic_data->tso_max_hdr_len = min_t(u64, reader->value, 0xffff); 884 return 0; 885 case ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS: 886 /* We always put HDR_NUM_SEGS=1 in our TSO descriptors */ 887 if (!reader->value) { 888 netif_err(efx, probe, efx->net_dev, 889 "TSO_MAX_HDR_NUM_SEGS < 1\n"); 890 return -EOPNOTSUPP; 891 } 892 return 0; 893 case ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY: 894 case ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY: 895 /* Our TXQ and RXQ sizes are always power-of-two and thus divisible by 896 * EFX_MIN_DMAQ_SIZE, so we just need to check that 897 * EFX_MIN_DMAQ_SIZE is divisible by GRANULARITY. 898 * This is very unlikely to fail. 899 */ 900 if (!reader->value || reader->value > EFX_MIN_DMAQ_SIZE || 901 EFX_MIN_DMAQ_SIZE % (u32)reader->value) { 902 netif_err(efx, probe, efx->net_dev, 903 "%s size granularity is %llu, can't guarantee safety\n", 904 reader->type == ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY ? "RXQ" : "TXQ", 905 reader->value); 906 return -EOPNOTSUPP; 907 } 908 return 0; 909 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN: 910 nic_data->tso_max_payload_len = min_t(u64, reader->value, 911 GSO_LEGACY_MAX_SIZE); 912 netif_set_tso_max_size(efx->net_dev, 913 nic_data->tso_max_payload_len); 914 return 0; 915 case ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS: 916 nic_data->tso_max_payload_num_segs = min_t(u64, reader->value, 0xffff); 917 netif_set_tso_max_segs(efx->net_dev, 918 nic_data->tso_max_payload_num_segs); 919 return 0; 920 case ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES: 921 nic_data->tso_max_frames = min_t(u64, reader->value, 0xffff); 922 return 0; 923 case ESE_EF100_DP_GZ_COMPAT: 924 if (reader->value) { 925 netif_err(efx, probe, efx->net_dev, 926 "DP_COMPAT has unknown bits %#llx, driver not compatible with this hw\n", 927 reader->value); 928 return -EOPNOTSUPP; 929 } 930 return 0; 931 case ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN: 932 /* Driver doesn't use mem2mem transfers */ 933 return 0; 934 case ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS: 935 /* Driver doesn't currently use EVQ_TIMER */ 936 return 0; 937 case ESE_EF100_DP_GZ_NMMU_PAGE_SIZES: 938 /* Driver doesn't manage the NMMU (so we don't care) */ 939 return 0; 940 case ESE_EF100_DP_GZ_VI_STRIDES: 941 /* We never try to set the VI stride, and we don't rely on 942 * being able to find VIs past VI 0 until after we've learned 943 * the current stride from MC_CMD_GET_CAPABILITIES. 944 * So the value of this shouldn't matter. 945 */ 946 if (reader->value != ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT) 947 netif_dbg(efx, probe, efx->net_dev, 948 "NIC has other than default VI_STRIDES (mask " 949 "%#llx), early probing might use wrong one\n", 950 reader->value); 951 return 0; 952 case ESE_EF100_DP_GZ_RX_MAX_RUNT: 953 /* Driver doesn't look at L2_STATUS:LEN_ERR bit, so we don't 954 * care whether it indicates runt or overlength for any given 955 * packet, so we don't care about this parameter. 956 */ 957 return 0; 958 default: 959 /* Host interface says "Drivers should ignore design parameters 960 * that they do not recognise." 961 */ 962 netif_dbg(efx, probe, efx->net_dev, 963 "Ignoring unrecognised design parameter %u\n", 964 reader->type); 965 return 0; 966 } 967 } 968 969 static int ef100_check_design_params(struct efx_nic *efx) 970 { 971 struct ef100_tlv_state reader = {}; 972 u32 total_len, offset = 0; 973 efx_dword_t reg; 974 int rc = 0, i; 975 u32 data; 976 977 efx_readd(efx, ®, ER_GZ_PARAMS_TLV_LEN); 978 total_len = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 979 pci_dbg(efx->pci_dev, "%u bytes of design parameters\n", total_len); 980 while (offset < total_len) { 981 efx_readd(efx, ®, ER_GZ_PARAMS_TLV + offset); 982 data = EFX_DWORD_FIELD(reg, EFX_DWORD_0); 983 for (i = 0; i < sizeof(data); i++) { 984 rc = ef100_tlv_feed(&reader, data); 985 /* Got a complete value? */ 986 if (!rc && reader.state == EF100_TLV_TYPE) 987 rc = ef100_process_design_param(efx, &reader); 988 if (rc) 989 goto out; 990 data >>= 8; 991 offset++; 992 } 993 } 994 /* Check we didn't end halfway through a TLV entry, which could either 995 * mean that the TLV stream is truncated or just that it's corrupted 996 * and our state machine is out of sync. 997 */ 998 if (reader.state != EF100_TLV_TYPE) { 999 if (reader.state == EF100_TLV_TYPE_CONT) 1000 netif_err(efx, probe, efx->net_dev, 1001 "truncated design parameter (incomplete type %u)\n", 1002 reader.type); 1003 else 1004 netif_err(efx, probe, efx->net_dev, 1005 "truncated design parameter %u\n", 1006 reader.type); 1007 rc = -EIO; 1008 } 1009 out: 1010 return rc; 1011 } 1012 1013 /* NIC probe and remove 1014 */ 1015 static int ef100_probe_main(struct efx_nic *efx) 1016 { 1017 unsigned int bar_size = resource_size(&efx->pci_dev->resource[efx->mem_bar]); 1018 struct ef100_nic_data *nic_data; 1019 char fw_version[32]; 1020 u32 priv_mask = 0; 1021 int i, rc; 1022 1023 if (WARN_ON(bar_size == 0)) 1024 return -EIO; 1025 1026 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 1027 if (!nic_data) 1028 return -ENOMEM; 1029 efx->nic_data = nic_data; 1030 nic_data->efx = efx; 1031 efx->max_vis = EF100_MAX_VIS; 1032 1033 /* Populate design-parameter defaults */ 1034 nic_data->tso_max_hdr_len = ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT; 1035 nic_data->tso_max_frames = ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT; 1036 nic_data->tso_max_payload_num_segs = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT; 1037 nic_data->tso_max_payload_len = ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT; 1038 1039 /* Read design parameters */ 1040 rc = ef100_check_design_params(efx); 1041 if (rc) { 1042 pci_err(efx->pci_dev, "Unsupported design parameters\n"); 1043 goto fail; 1044 } 1045 1046 /* we assume later that we can copy from this buffer in dwords */ 1047 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4); 1048 1049 /* MCDI buffers must be 256 byte aligned. */ 1050 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, MCDI_BUF_LEN, 1051 GFP_KERNEL); 1052 if (rc) 1053 goto fail; 1054 1055 /* Get the MC's warm boot count. In case it's rebooting right 1056 * now, be prepared to retry. 1057 */ 1058 i = 0; 1059 for (;;) { 1060 rc = ef100_get_warm_boot_count(efx); 1061 if (rc >= 0) 1062 break; 1063 if (++i == 5) 1064 goto fail; 1065 ssleep(1); 1066 } 1067 nic_data->warm_boot_count = rc; 1068 1069 /* In case we're recovering from a crash (kexec), we want to 1070 * cancel any outstanding request by the previous user of this 1071 * function. We send a special message using the least 1072 * significant bits of the 'high' (doorbell) register. 1073 */ 1074 _efx_writed(efx, cpu_to_le32(1), efx_reg(efx, ER_GZ_MC_DB_HWRD)); 1075 1076 /* Post-IO section. */ 1077 1078 rc = efx_mcdi_init(efx); 1079 if (rc) 1080 goto fail; 1081 /* Reset (most) configuration for this function */ 1082 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 1083 if (rc) 1084 goto fail; 1085 /* Enable event logging */ 1086 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 1087 if (rc) 1088 goto fail; 1089 1090 rc = efx_get_pf_index(efx, &nic_data->pf_index); 1091 if (rc) 1092 goto fail; 1093 1094 rc = efx_mcdi_port_get_number(efx); 1095 if (rc < 0) 1096 goto fail; 1097 efx->port_num = rc; 1098 1099 efx_mcdi_print_fwver(efx, fw_version, sizeof(fw_version)); 1100 pci_dbg(efx->pci_dev, "Firmware version %s\n", fw_version); 1101 1102 rc = efx_mcdi_get_privilege_mask(efx, &priv_mask); 1103 if (rc) /* non-fatal, and priv_mask will still be 0 */ 1104 pci_info(efx->pci_dev, 1105 "Failed to get privilege mask from FW, rc %d\n", rc); 1106 nic_data->grp_mae = !!(priv_mask & MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE); 1107 1108 if (compare_versions(fw_version, "1.1.0.1000") < 0) { 1109 pci_info(efx->pci_dev, "Firmware uses old event descriptors\n"); 1110 rc = -EINVAL; 1111 goto fail; 1112 } 1113 1114 if (efx_has_cap(efx, UNSOL_EV_CREDIT_SUPPORTED)) { 1115 pci_info(efx->pci_dev, "Firmware uses unsolicited-event credits\n"); 1116 rc = -EINVAL; 1117 goto fail; 1118 } 1119 1120 return 0; 1121 fail: 1122 return rc; 1123 } 1124 1125 int ef100_probe_netdev_pf(struct efx_nic *efx) 1126 { 1127 struct ef100_nic_data *nic_data = efx->nic_data; 1128 struct net_device *net_dev = efx->net_dev; 1129 int rc; 1130 1131 if (!nic_data->grp_mae) 1132 return 0; 1133 1134 #ifdef CONFIG_SFC_SRIOV 1135 rc = efx_init_struct_tc(efx); 1136 if (rc) 1137 return rc; 1138 1139 rc = efx_ef100_get_base_mport(efx); 1140 if (rc) { 1141 netif_warn(efx, probe, net_dev, 1142 "Failed to probe base mport rc %d; representors will not function\n", 1143 rc); 1144 } 1145 1146 rc = efx_init_mae(efx); 1147 if (rc) 1148 netif_warn(efx, probe, net_dev, 1149 "Failed to init MAE rc %d; representors will not function\n", 1150 rc); 1151 else 1152 efx_ef100_init_reps(efx); 1153 1154 rc = efx_init_tc(efx); 1155 if (rc) { 1156 /* Either we don't have an MAE at all (i.e. legacy v-switching), 1157 * or we do but we failed to probe it. In the latter case, we 1158 * may not have set up default rules, in which case we won't be 1159 * able to pass any traffic. However, we don't fail the probe, 1160 * because the user might need to use the netdevice to apply 1161 * configuration changes to fix whatever's wrong with the MAE. 1162 */ 1163 netif_warn(efx, probe, net_dev, "Failed to probe MAE rc %d\n", 1164 rc); 1165 } else { 1166 net_dev->features |= NETIF_F_HW_TC; 1167 efx->fixed_features |= NETIF_F_HW_TC; 1168 } 1169 #endif 1170 return rc; 1171 } 1172 1173 int ef100_probe_vf(struct efx_nic *efx) 1174 { 1175 return ef100_probe_main(efx); 1176 } 1177 1178 void ef100_remove(struct efx_nic *efx) 1179 { 1180 struct ef100_nic_data *nic_data = efx->nic_data; 1181 1182 #ifdef CONFIG_SFC_SRIOV 1183 if (efx->mae) { 1184 efx_ef100_fini_reps(efx); 1185 efx_fini_mae(efx); 1186 } 1187 #endif 1188 efx_mcdi_detach(efx); 1189 efx_mcdi_fini(efx); 1190 if (nic_data) 1191 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 1192 kfree(nic_data); 1193 efx->nic_data = NULL; 1194 } 1195 1196 /* NIC level access functions 1197 */ 1198 #define EF100_OFFLOAD_FEATURES (NETIF_F_HW_CSUM | NETIF_F_RXCSUM | \ 1199 NETIF_F_HIGHDMA | NETIF_F_SG | NETIF_F_FRAGLIST | NETIF_F_NTUPLE | \ 1200 NETIF_F_RXHASH | NETIF_F_RXFCS | NETIF_F_TSO_ECN | NETIF_F_RXALL | \ 1201 NETIF_F_HW_VLAN_CTAG_TX) 1202 1203 const struct efx_nic_type ef100_pf_nic_type = { 1204 .revision = EFX_REV_EF100, 1205 .is_vf = false, 1206 .probe = ef100_probe_main, 1207 .offload_features = EF100_OFFLOAD_FEATURES, 1208 .mcdi_max_ver = 2, 1209 .mcdi_request = ef100_mcdi_request, 1210 .mcdi_poll_response = ef100_mcdi_poll_response, 1211 .mcdi_read_response = ef100_mcdi_read_response, 1212 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 1213 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 1214 .irq_enable_master = efx_port_dummy_op_void, 1215 .irq_test_generate = efx_ef100_irq_test_generate, 1216 .irq_disable_non_ev = efx_port_dummy_op_void, 1217 .push_irq_moderation = efx_channel_dummy_op_void, 1218 .min_interrupt_mode = EFX_INT_MODE_MSIX, 1219 .map_reset_reason = ef100_map_reset_reason, 1220 .map_reset_flags = ef100_map_reset_flags, 1221 .reset = ef100_reset, 1222 1223 .check_caps = ef100_check_caps, 1224 1225 .ev_probe = ef100_ev_probe, 1226 .ev_init = ef100_ev_init, 1227 .ev_fini = efx_mcdi_ev_fini, 1228 .ev_remove = efx_mcdi_ev_remove, 1229 .irq_handle_msi = ef100_msi_interrupt, 1230 .ev_process = ef100_ev_process, 1231 .ev_read_ack = ef100_ev_read_ack, 1232 .ev_test_generate = efx_ef100_ev_test_generate, 1233 .tx_probe = ef100_tx_probe, 1234 .tx_init = ef100_tx_init, 1235 .tx_write = ef100_tx_write, 1236 .tx_enqueue = ef100_enqueue_skb, 1237 .rx_probe = efx_mcdi_rx_probe, 1238 .rx_init = efx_mcdi_rx_init, 1239 .rx_remove = efx_mcdi_rx_remove, 1240 .rx_write = ef100_rx_write, 1241 .rx_packet = __ef100_rx_packet, 1242 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 1243 .fini_dmaq = efx_fini_dmaq, 1244 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 1245 .filter_table_probe = ef100_filter_table_up, 1246 .filter_table_restore = efx_mcdi_filter_table_restore, 1247 .filter_table_remove = ef100_filter_table_down, 1248 .filter_insert = efx_mcdi_filter_insert, 1249 .filter_remove_safe = efx_mcdi_filter_remove_safe, 1250 .filter_get_safe = efx_mcdi_filter_get_safe, 1251 .filter_clear_rx = efx_mcdi_filter_clear_rx, 1252 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 1253 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 1254 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 1255 #ifdef CONFIG_RFS_ACCEL 1256 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 1257 #endif 1258 1259 .get_phys_port_id = efx_ef100_get_phys_port_id, 1260 1261 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 1262 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 1263 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 1264 .rx_hash_key_size = 40, 1265 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 1266 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 1267 .rx_push_rss_context_config = efx_mcdi_rx_push_rss_context_config, 1268 .rx_pull_rss_context_config = efx_mcdi_rx_pull_rss_context_config, 1269 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 1270 .rx_recycle_ring_size = efx_ef100_recycle_ring_size, 1271 1272 .reconfigure_mac = ef100_reconfigure_mac, 1273 .reconfigure_port = efx_mcdi_port_reconfigure, 1274 .test_nvram = efx_new_mcdi_nvram_test_all, 1275 .describe_stats = ef100_describe_stats, 1276 .start_stats = efx_mcdi_mac_start_stats, 1277 .update_stats = ef100_update_stats, 1278 .pull_stats = efx_mcdi_mac_pull_stats, 1279 .stop_stats = efx_mcdi_mac_stop_stats, 1280 #ifdef CONFIG_SFC_SRIOV 1281 .sriov_configure = efx_ef100_sriov_configure, 1282 #endif 1283 1284 /* Per-type bar/size configuration not used on ef100. Location of 1285 * registers is defined by extended capabilities. 1286 */ 1287 .mem_bar = NULL, 1288 .mem_map_size = NULL, 1289 1290 }; 1291 1292 const struct efx_nic_type ef100_vf_nic_type = { 1293 .revision = EFX_REV_EF100, 1294 .is_vf = true, 1295 .probe = ef100_probe_vf, 1296 .offload_features = EF100_OFFLOAD_FEATURES, 1297 .mcdi_max_ver = 2, 1298 .mcdi_request = ef100_mcdi_request, 1299 .mcdi_poll_response = ef100_mcdi_poll_response, 1300 .mcdi_read_response = ef100_mcdi_read_response, 1301 .mcdi_poll_reboot = ef100_mcdi_poll_reboot, 1302 .mcdi_reboot_detected = ef100_mcdi_reboot_detected, 1303 .irq_enable_master = efx_port_dummy_op_void, 1304 .irq_test_generate = efx_ef100_irq_test_generate, 1305 .irq_disable_non_ev = efx_port_dummy_op_void, 1306 .push_irq_moderation = efx_channel_dummy_op_void, 1307 .min_interrupt_mode = EFX_INT_MODE_MSIX, 1308 .map_reset_reason = ef100_map_reset_reason, 1309 .map_reset_flags = ef100_map_reset_flags, 1310 .reset = ef100_reset, 1311 .check_caps = ef100_check_caps, 1312 .ev_probe = ef100_ev_probe, 1313 .ev_init = ef100_ev_init, 1314 .ev_fini = efx_mcdi_ev_fini, 1315 .ev_remove = efx_mcdi_ev_remove, 1316 .irq_handle_msi = ef100_msi_interrupt, 1317 .ev_process = ef100_ev_process, 1318 .ev_read_ack = ef100_ev_read_ack, 1319 .ev_test_generate = efx_ef100_ev_test_generate, 1320 .tx_probe = ef100_tx_probe, 1321 .tx_init = ef100_tx_init, 1322 .tx_write = ef100_tx_write, 1323 .tx_enqueue = ef100_enqueue_skb, 1324 .rx_probe = efx_mcdi_rx_probe, 1325 .rx_init = efx_mcdi_rx_init, 1326 .rx_remove = efx_mcdi_rx_remove, 1327 .rx_write = ef100_rx_write, 1328 .rx_packet = __ef100_rx_packet, 1329 .rx_buf_hash_valid = ef100_rx_buf_hash_valid, 1330 .fini_dmaq = efx_fini_dmaq, 1331 .max_rx_ip_filters = EFX_MCDI_FILTER_TBL_ROWS, 1332 .filter_table_probe = ef100_filter_table_up, 1333 .filter_table_restore = efx_mcdi_filter_table_restore, 1334 .filter_table_remove = ef100_filter_table_down, 1335 .filter_insert = efx_mcdi_filter_insert, 1336 .filter_remove_safe = efx_mcdi_filter_remove_safe, 1337 .filter_get_safe = efx_mcdi_filter_get_safe, 1338 .filter_clear_rx = efx_mcdi_filter_clear_rx, 1339 .filter_count_rx_used = efx_mcdi_filter_count_rx_used, 1340 .filter_get_rx_id_limit = efx_mcdi_filter_get_rx_id_limit, 1341 .filter_get_rx_ids = efx_mcdi_filter_get_rx_ids, 1342 #ifdef CONFIG_RFS_ACCEL 1343 .filter_rfs_expire_one = efx_mcdi_filter_rfs_expire_one, 1344 #endif 1345 1346 .rx_prefix_size = ESE_GZ_RX_PKT_PREFIX_LEN, 1347 .rx_hash_offset = ESF_GZ_RX_PREFIX_RSS_HASH_LBN / 8, 1348 .rx_ts_offset = ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN / 8, 1349 .rx_hash_key_size = 40, 1350 .rx_pull_rss_config = efx_mcdi_rx_pull_rss_config, 1351 .rx_push_rss_config = efx_mcdi_pf_rx_push_rss_config, 1352 .rx_restore_rss_contexts = efx_mcdi_rx_restore_rss_contexts, 1353 .rx_recycle_ring_size = efx_ef100_recycle_ring_size, 1354 1355 .reconfigure_mac = ef100_reconfigure_mac, 1356 .test_nvram = efx_new_mcdi_nvram_test_all, 1357 .describe_stats = ef100_describe_stats, 1358 .start_stats = efx_mcdi_mac_start_stats, 1359 .update_stats = ef100_update_stats, 1360 .pull_stats = efx_mcdi_mac_pull_stats, 1361 .stop_stats = efx_mcdi_mac_stop_stats, 1362 1363 .mem_bar = NULL, 1364 .mem_map_size = NULL, 1365 1366 }; 1367