1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Performance Monitor Drivers 4# 5 6menu "Performance monitor support" 7 depends on PERF_EVENTS 8 9config ARM_CCI_PMU 10 tristate "ARM CCI PMU driver" 11 depends on (ARM && CPU_V7) || ARM64 12 select ARM_CCI 13 help 14 Support for PMU events monitoring on the ARM CCI (Cache Coherent 15 Interconnect) family of products. 16 17 If compiled as a module, it will be called arm-cci. 18 19config ARM_CCI400_PMU 20 bool "support CCI-400" 21 default y 22 depends on ARM_CCI_PMU 23 select ARM_CCI400_COMMON 24 help 25 CCI-400 provides 4 independent event counters counting events related 26 to the connected slave/master interfaces, plus a cycle counter. 27 28config ARM_CCI5xx_PMU 29 bool "support CCI-500/CCI-550" 30 default y 31 depends on ARM_CCI_PMU 32 help 33 CCI-500/CCI-550 both provide 8 independent event counters, which can 34 count events pertaining to the slave/master interfaces as well as the 35 internal events to the CCI. 36 37config ARM_CCN 38 tristate "ARM CCN driver support" 39 depends on ARM || ARM64 || COMPILE_TEST 40 help 41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 42 interconnect. 43 44config ARM_CMN 45 tristate "Arm CMN-600 PMU support" 46 depends on ARM64 || (COMPILE_TEST && 64BIT) 47 help 48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh 49 Network interconnect. 50 51config ARM_PMU 52 depends on ARM || ARM64 53 bool "ARM PMU framework" 54 default y 55 help 56 Say y if you want to use CPU performance monitors on ARM-based 57 systems. 58 59config ARM_PMU_ACPI 60 depends on ARM_PMU && ACPI 61 def_bool y 62 63config ARM_SMMU_V3_PMU 64 tristate "ARM SMMUv3 Performance Monitors Extension" 65 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT) 66 depends on GENERIC_MSI_IRQ_DOMAIN 67 help 68 Provides support for the ARM SMMUv3 Performance Monitor Counter 69 Groups (PMCG), which provide monitoring of transactions passing 70 through the SMMU and allow the resulting information to be filtered 71 based on the Stream ID of the corresponding master. 72 73config ARM_DSU_PMU 74 tristate "ARM DynamIQ Shared Unit (DSU) PMU" 75 depends on ARM64 76 help 77 Provides support for performance monitor unit in ARM DynamIQ Shared 78 Unit (DSU). The DSU integrates one or more cores with an L3 memory 79 system, control logic. The PMU allows counting various events related 80 to DSU. 81 82config FSL_IMX8_DDR_PMU 83 tristate "Freescale i.MX8 DDR perf monitor" 84 depends on ARCH_MXC || COMPILE_TEST 85 help 86 Provides support for the DDR performance monitor in i.MX8, which 87 can give information about memory throughput and other related 88 events. 89 90config QCOM_L2_PMU 91 bool "Qualcomm Technologies L2-cache PMU" 92 depends on ARCH_QCOM && ARM64 && ACPI 93 select QCOM_KRYO_L2_ACCESSORS 94 help 95 Provides support for the L2 cache performance monitor unit (PMU) 96 in Qualcomm Technologies processors. 97 Adds the L2 cache PMU into the perf events subsystem for 98 monitoring L2 cache events. 99 100config QCOM_L3_PMU 101 bool "Qualcomm Technologies L3-cache PMU" 102 depends on ARCH_QCOM && ARM64 && ACPI 103 select QCOM_IRQ_COMBINER 104 help 105 Provides support for the L3 cache performance monitor unit (PMU) 106 in Qualcomm Technologies processors. 107 Adds the L3 cache PMU into the perf events subsystem for 108 monitoring L3 cache events. 109 110config THUNDERX2_PMU 111 tristate "Cavium ThunderX2 SoC PMU UNCORE" 112 depends on ARCH_THUNDER2 || COMPILE_TEST 113 depends on NUMA && ACPI 114 default m 115 help 116 Provides support for ThunderX2 UNCORE events. 117 The SoC has PMU support in its L3 cache controller (L3C) and 118 in the DDR4 Memory Controller (DMC). 119 120config XGENE_PMU 121 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT) 122 bool "APM X-Gene SoC PMU" 123 default n 124 help 125 Say y if you want to use APM X-Gene SoC performance monitors. 126 127config ARM_SPE_PMU 128 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension" 129 depends on ARM64 130 help 131 Enable perf support for the ARMv8.2 Statistical Profiling 132 Extension, which provides periodic sampling of operations in 133 the CPU pipeline and reports this via the perf AUX interface. 134 135config ARM_DMC620_PMU 136 tristate "Enable PMU support for the ARM DMC-620 memory controller" 137 depends on (ARM64 && ACPI) || COMPILE_TEST 138 help 139 Support for PMU events monitoring on the ARM DMC-620 memory 140 controller. 141 142config MARVELL_CN10K_TAD_PMU 143 tristate "Marvell CN10K LLC-TAD PMU" 144 depends on ARM64 || (COMPILE_TEST && 64BIT) 145 help 146 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD) 147 performance monitors on CN10K family silicons. 148 149source "drivers/perf/hisilicon/Kconfig" 150 151endmenu 152